diff options
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/microchip.yaml | 1 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/starfive.yaml | 6 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 | ||||
| -rw-r--r-- | arch/riscv/Kconfig.socs | 39 | ||||
| -rw-r--r-- | arch/riscv/Makefile | 2 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/Makefile | 2 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/canaan/Makefile | 14 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/microchip/Makefile | 9 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi | 18 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts | 165 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/sifive/Makefile | 4 | ||||
| -rw-r--r-- | arch/riscv/boot/dts/starfive/Makefile | 2 |
12 files changed, 235 insertions, 29 deletions
diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 714d0fcab399..4a29c890619a 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: + - aldec,tysom-m-mpfs250t-rev2 - aries,m100pfsevp - microchip,mpfs-sev-kit - sundance,polarberry diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 5d3fcee52d59..60c7c03fcdce 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -24,6 +24,12 @@ properties: - starfive,visionfive-v1 - const: starfive,jh7100 + - items: + - enum: + - starfive,visionfive-2-va + - starfive,visionfive-2-vb + - const: starfive,jh7110 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 5977d978fa67..d483252654b6 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -69,6 +69,8 @@ patternProperties: description: Annapurna Labs "^alcatel,.*": description: Alcatel + "^aldec,.*": + description: Aldec, Inc. "^alfa-network,.*": description: ALFA Network Inc. "^allegro,.*": diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 4b6deb2715f1..34a54e5310a1 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,8 +1,10 @@ menu "SoC selection" +config ARCH_MICROCHIP_POLARFIRE + def_bool SOC_MICROCHIP_POLARFIRE + config SOC_MICROCHIP_POLARFIRE bool "Microchip PolarFire SoCs" - select MCHP_CLK_MPFS help This enables support for Microchip PolarFire SoC platforms. @@ -11,16 +13,18 @@ config ARCH_RENESAS help This enables support for the RISC-V based Renesas SoCs. +config ARCH_SIFIVE + def_bool SOC_SIFIVE + config SOC_SIFIVE bool "SiFive SoCs" - select SERIAL_SIFIVE if TTY - select SERIAL_SIFIVE_CONSOLE if TTY - select CLK_SIFIVE - select CLK_SIFIVE_PRCI select ERRATA_SIFIVE if !XIP_KERNEL help This enables support for SiFive SoC platform hardware. +config ARCH_STARFIVE + def_bool SOC_STARFIVE + config SOC_STARFIVE bool "StarFive SoCs" select PINCTRL @@ -28,6 +32,9 @@ config SOC_STARFIVE help This enables support for StarFive SoC platform hardware. +config ARCH_VIRT + def_bool SOC_VIRT + config SOC_VIRT bool "QEMU Virt Machine" select CLINT_TIMER if RISCV_M_MODE @@ -42,24 +49,27 @@ config SOC_VIRT help This enables support for QEMU Virt Machine. +config ARCH_CANAAN + def_bool SOC_CANAAN + config SOC_CANAAN bool "Canaan Kendryte K210 SoC" depends on !MMU select CLINT_TIMER if RISCV_M_MODE - select SERIAL_SIFIVE if TTY - select SERIAL_SIFIVE_CONSOLE if TTY select ARCH_HAS_RESET_CONTROLLER select PINCTRL select COMMON_CLK - select COMMON_CLK_K210 help This enables support for Canaan Kendryte K210 SoC platform hardware. -if SOC_CANAAN +if ARCH_CANAAN + +config ARCH_CANAAN_K210_DTB_BUILTIN + def_bool SOC_CANAAN_K210_DTB_BUILTIN config SOC_CANAAN_K210_DTB_BUILTIN bool "Builtin device tree for the Canaan Kendryte K210" - depends on SOC_CANAAN + depends on ARCH_CANAAN default y select OF select BUILTIN_DTB @@ -68,16 +78,19 @@ config SOC_CANAAN_K210_DTB_BUILTIN This option should be selected if no bootloader is being used. If unsure, say Y. +config ARCH_CANAAN_K210_DTB_SOURCE + def_bool SOC_CANAAN_K210_DTB_SOURCE + config SOC_CANAAN_K210_DTB_SOURCE string "Source file for the Canaan Kendryte K210 builtin DTB" - depends on SOC_CANAAN - depends on SOC_CANAAN_K210_DTB_BUILTIN + depends on ARCH_CANAAN + depends on ARCH_CANAAN_K210_DTB_BUILTIN default "k210_generic" help Base name (without suffix, relative to arch/riscv/boot/dts/canaan) for the DTS file that will be used to produce the DTB linked into the kernel. -endif # SOC_CANAAN +endif # ARCH_CANAAN endmenu # "SoC selection" diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index faf2c2177094..12d91b0a73d8 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -131,7 +131,7 @@ endif endif ifneq ($(CONFIG_XIP_KERNEL),y) -ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_SOC_CANAAN),yy) +ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy) KBUILD_IMAGE := $(boot)/loader.bin else ifeq ($(CONFIG_EFI_ZBOOT),) diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index b0ff5fbabb0c..0c97d673b775 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += sifive subdir-y += starfive -subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan +subdir-y += canaan subdir-y += microchip subdir-y += renesas diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile index befe4eb7527b..520623264c87 100644 --- a/arch/riscv/boot/dts/canaan/Makefile +++ b/arch/riscv/boot/dts/canaan/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_CANAAN) += canaan_kd233.dtb -dtb-$(CONFIG_SOC_CANAAN) += k210_generic.dtb -dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_bit.dtb -dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_dock.dtb -dtb-$(CONFIG_SOC_CANAAN) += sipeed_maix_go.dtb -dtb-$(CONFIG_SOC_CANAAN) += sipeed_maixduino.dtb +dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb +dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb +dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb +dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb +dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb +dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maixduino.dtb -obj-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_SOC_CANAAN_K210_DTB_SOURCE)) +obj-$(CONFIG_ARCH_CANAAN_K210_DTB_BUILTIN) += $(addsuffix .dtb.o, $(CONFIG_ARCH_CANAAN_K210_DTB_SOURCE)) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 7427a20934f3..45adc4926e79 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi new file mode 100644 index 000000000000..98f642e83ad4 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +// #include "dt-bindings/mailbox/miv-ihc.h" + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts new file mode 100644 index 000000000000..e0797c7e1b35 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2020-2022 - Aldec + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com> + */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-tysom-m-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Aldec TySOM-M-MPFS250T-REV2"; + compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; + + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + gpio0 = &gpio0; + gpio1 = &gpio2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = <MTIMER_FREQ>; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x30000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0x40000000>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led0 { + gpios = <&gpio1 23 1>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + hwmon: hwmon@45 { + status = "okay"; + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <2000>; + }; +}; + +&gpio1 { + interrupts = <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <47>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + status = "okay"; +}; + +&mac0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + +}; + +&mac1 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + max-frequency = <200000000>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + disable-wp; + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <10000000>; + }; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/riscv/boot/dts/sifive/Makefile b/arch/riscv/boot/dts/sifive/Makefile index d90e4eb0ade8..6a5fbd4ed96a 100644 --- a/arch/riscv/boot/dts/sifive/Makefile +++ b/arch/riscv/boot/dts/sifive/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_SIFIVE) += hifive-unleashed-a00.dtb \ - hifive-unmatched-a00.dtb +dtb-$(CONFIG_ARCH_SIFIVE) += hifive-unleashed-a00.dtb \ + hifive-unmatched-a00.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 039c143cba33..7b00a48580ca 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb +dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb |