diff options
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm6350.dtsi | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 6001abaa0f48..d882c29d53aa 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/qcom,gcc-sm6350.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interconnect/qcom,sm6350.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -519,6 +520,26 @@ }; }; + gpi_dma0: dma-controller@800000 { + compatible = "qcom,sm6350-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x56 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x8c0000 0x0 0x2000>; @@ -539,6 +560,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, @@ -556,6 +580,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, @@ -566,6 +593,26 @@ }; }; + gpi_dma1: dma-controller@900000 { + compatible = "qcom,sm6350-gpi-dma"; + reg = <0 0x00900000 0 0x60000>; + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; + dma-channels = <10>; + dma-channel-mask = <0x3f>; + iommus = <&apps_smmu 0x4d6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x9c0000 0x0 0x2000>; @@ -586,6 +633,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, @@ -603,6 +653,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, @@ -620,6 +673,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, @@ -651,6 +707,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |