diff options
52 files changed, 2145 insertions, 782 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 7a9c3ce2dbef..f61a5a13fb42 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -123,11 +123,18 @@ properties: - arm,cortex-a12 - arm,cortex-a15 - arm,cortex-a17 + - arm,cortex-a32 + - arm,cortex-a34 + - arm,cortex-a35 - arm,cortex-a53 - arm,cortex-a55 - arm,cortex-a57 + - arm,cortex-a65 - arm,cortex-a72 - arm,cortex-a73 + - arm,cortex-a75 + - arm,cortex-a76 + - arm,cortex-a77 - arm,cortex-m0 - arm,cortex-m0+ - arm,cortex-m1 @@ -136,6 +143,8 @@ properties: - arm,cortex-r4 - arm,cortex-r5 - arm,cortex-r7 + - arm,neoverse-e1 + - arm,neoverse-n1 - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan @@ -155,6 +164,7 @@ properties: - nvidia,tegra194-carmel - qcom,krait - qcom,kryo + - qcom,kryo260 - qcom,kryo385 - qcom,kryo485 - qcom,scorpion diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 52ae094ce330..97df36d301c9 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -20,27 +20,36 @@ properties: items: - enum: - apm,potenza-pmu - - arm,armv8-pmuv3 - - arm,cortex-a73-pmu - - arm,cortex-a72-pmu - - arm,cortex-a57-pmu - - arm,cortex-a53-pmu - - arm,cortex-a35-pmu - - arm,cortex-a17-pmu - - arm,cortex-a15-pmu - - arm,cortex-a12-pmu - - arm,cortex-a9-pmu - - arm,cortex-a8-pmu - - arm,cortex-a7-pmu - - arm,cortex-a5-pmu - - arm,arm11mpcore-pmu - - arm,arm1176-pmu + - arm,armv8-pmuv3 # Only for s/w models - arm,arm1136-pmu + - arm,arm1176-pmu + - arm,arm11mpcore-pmu + - arm,cortex-a5-pmu + - arm,cortex-a7-pmu + - arm,cortex-a8-pmu + - arm,cortex-a9-pmu + - arm,cortex-a12-pmu + - arm,cortex-a15-pmu + - arm,cortex-a17-pmu + - arm,cortex-a32-pmu + - arm,cortex-a34-pmu + - arm,cortex-a35-pmu + - arm,cortex-a53-pmu + - arm,cortex-a55-pmu + - arm,cortex-a57-pmu + - arm,cortex-a65-pmu + - arm,cortex-a72-pmu + - arm,cortex-a73-pmu + - arm,cortex-a75-pmu + - arm,cortex-a76-pmu + - arm,cortex-a77-pmu + - arm,neoverse-e1-pmu + - arm,neoverse-n1-pmu - brcm,vulcan-pmu - cavium,thunder-pmu + - qcom,krait-pmu - qcom,scorpion-pmu - qcom,scorpion-mp-pmu - - qcom,krait-pmu interrupts: # Don't know how many CPUs, so no constraints to specify diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt deleted file mode 100644 index b3ed1033740e..000000000000 --- a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt +++ /dev/null @@ -1,47 +0,0 @@ -Socionext UniPhier SoC family ------------------------------ - -Required properties in the root node: - - compatible: should contain board and SoC compatible strings - -SoC and board compatible strings: - (sorted chronologically) - - - LD4 SoC: "socionext,uniphier-ld4" - - Reference Board: "socionext,uniphier-ld4-ref" - - - Pro4 SoC: "socionext,uniphier-pro4" - - Reference Board: "socionext,uniphier-pro4-ref" - - Ace Board: "socionext,uniphier-pro4-ace" - - Sanji Board: "socionext,uniphier-pro4-sanji" - - - sLD8 SoC: "socionext,uniphier-sld8" - - Reference Board: "socionext,uniphier-sld8-ref" - - - PXs2 SoC: "socionext,uniphier-pxs2" - - Gentil Board: "socionext,uniphier-pxs2-gentil" - - Vodka Board: "socionext,uniphier-pxs2-vodka" - - - LD6b SoC: "socionext,uniphier-ld6b" - - Reference Board: "socionext,uniphier-ld6b-ref" - - - LD11 SoC: "socionext,uniphier-ld11" - - Reference Board: "socionext,uniphier-ld11-ref" - - Global Board: "socionext,uniphier-ld11-global" - - - LD20 SoC: "socionext,uniphier-ld20" - - Reference Board: "socionext,uniphier-ld20-ref" - - Global Board: "socionext,uniphier-ld20-global" - - - PXs3 SoC: "socionext,uniphier-pxs3" - - Reference Board: "socionext,uniphier-pxs3-ref" - -Example: - -/dts-v1/; - -/ { - compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; - - ... -}; diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml b/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml new file mode 100644 index 000000000000..65ad6d8a3c99 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/uniphier.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/socionext/uniphier.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier platform device tree bindings + +maintainers: + - Masahiro Yamada <[email protected]> + +properties: + $nodename: + const: / + compatible: + oneOf: + - description: LD4 SoC boards + items: + - enum: + - socionext,uniphier-ld4-ref + - const: socionext,uniphier-ld4 + - description: Pro4 SoC boards + items: + - enum: + - socionext,uniphier-pro4-ace + - socionext,uniphier-pro4-ref + - socionext,uniphier-pro4-sanji + - const: socionext,uniphier-pro4 + - description: sLD8 SoC boards + items: + - enum: + - socionext,uniphier-sld8-ref + - const: socionext,uniphier-sld8 + - description: PXs2 SoC boards + items: + - enum: + - socionext,uniphier-pxs2-gentil + - socionext,uniphier-pxs2-vodka + - const: socionext,uniphier-pxs2 + - description: LD6b SoC boards + items: + - enum: + - socionext,uniphier-ld6b-ref + - const: socionext,uniphier-ld6b + - description: LD11 SoC boards + items: + - enum: + - socionext,uniphier-ld11-global + - socionext,uniphier-ld11-ref + - const: socionext,uniphier-ld11 + - description: LD20 SoC boards + items: + - enum: + - socionext,uniphier-ld20-global + - socionext,uniphier-ld20-ref + - const: socionext,uniphier-ld20 + - description: PXs3 SoC boards + items: + - enum: + - socionext,uniphier-pxs3-ref + - const: socionext,uniphier-pxs3 diff --git a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml new file mode 100644 index 000000000000..7b69831060d8 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas R-Car Serial-ATA Interface + +maintainers: + - Geert Uytterhoeven <[email protected]> + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,sata-r8a7779 # R-Car H1 + - items: + - enum: + - renesas,sata-r8a7790-es1 # R-Car H2 ES1 + - renesas,sata-r8a7790 # R-Car H2 other than ES1 + - renesas,sata-r8a7791 # R-Car M2-W + - renesas,sata-r8a7793 # R-Car M2-N + - const: renesas,rcar-gen2-sata # generic R-Car Gen2 + - items: + - enum: + - renesas,sata-r8a774b1 # RZ/G2N + - renesas,sata-r8a7795 # R-Car H3 + - renesas,sata-r8a77965 # R-Car M3-N + - const: renesas,rcar-gen3-sata # generic R-Car Gen3 or RZ/G2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + iommus: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7791-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7791-sysc.h> + + sata@ee300000 { + compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; + reg = <0xee300000 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 815>; + }; diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt deleted file mode 100644 index a2fbdc91570d..000000000000 --- a/Documentation/devicetree/bindings/ata/sata_rcar.txt +++ /dev/null @@ -1,36 +0,0 @@ -* Renesas R-Car SATA - -Required properties: -- compatible : should contain one or more of the following: - - "renesas,sata-r8a774b1" for RZ/G2N - - "renesas,sata-r8a7779" for R-Car H1 - - "renesas,sata-r8a7790-es1" for R-Car H2 ES1 - - "renesas,sata-r8a7790" for R-Car H2 other than ES1 - - "renesas,sata-r8a7791" for R-Car M2-W - - "renesas,sata-r8a7793" for R-Car M2-N - - "renesas,sata-r8a7795" for R-Car H3 - - "renesas,sata-r8a77965" for R-Car M3-N - - "renesas,rcar-gen2-sata" for a generic R-Car Gen2 - compatible device - - "renesas,rcar-gen3-sata" for a generic R-Car Gen3 or - RZ/G2 compatible device - - "renesas,rcar-sata" is deprecated - - When compatible with the generic version nodes - must list the SoC-specific version corresponding - to the platform first followed by the generic - version. - -- reg : address and length of the SATA registers; -- interrupts : must consist of one interrupt specifier. -- clocks : must contain a reference to the functional clock. - -Example: - -sata0: sata@ee300000 { - compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; - reg = <0 0xee300000 0 0x2000>; - interrupt-parent = <&gic>; - interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp8_clks R8A7791_CLK_SATA0>; -}; diff --git a/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml b/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml new file mode 100644 index 000000000000..ff9600d6de3b --- /dev/null +++ b/Documentation/devicetree/bindings/bus/socionext,uniphier-system-bus.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier System Bus + +description: | + The UniPhier System Bus is an external bus that connects on-board devices to + the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and + some control signals. It supports up to 8 banks (chip selects). + + Before any access to the bus, the bus controller must be configured; the bus + controller registers provide the control for the translation from the offset + within each bank to the CPU-viewed address. The needed setup includes the + base address, the size of each bank. Optionally, some timing parameters can + be optimized for faster bus access. + +maintainers: + - Masahiro Yamada <[email protected]> + +properties: + compatible: + const: socionext,uniphier-system-bus + + reg: + maxItems: 1 + + "#address-cells": + description: | + The first cell is the bank number (chip select). + The second cell is the address offset within the bank. + const: 2 + + "#size-cells": + const: 1 + + ranges: + description: | + Provide address translation from the System Bus to the parent bus. + + Note: + The address region(s) that can be assigned for the System Bus is + implementation defined. Some SoCs can use 0x00000000-0x0fffffff and + 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff. + There might be additional limitations depending on SoCs and the boot mode. + The address translation is arbitrary as long as the banks are assigned in + the supported address space with the required alignment and they do not + overlap one another. + + For example, it is possible to map: + bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff + It is also possible to map: + bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff + There is no reason to stick to a particular translation mapping, but the + "ranges" property should provide a "reasonable" default that is known to + work. The software should initialize the bus controller according to it. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +examples: + - | + // In this example, + // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and + // mapped to 0x43f00000 of the parent bus. + // - the UART device is connected at the offset 0x00200000 of CS5 and + // mapped to 0x46200000 of the parent bus. + + system-bus { + compatible = "socionext,uniphier-system-bus"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0x00000000 0x42000000 0x02000000>, + <5 0x00000000 0x46000000 0x01000000>; + + ethernet@1,01f00000 { + compatible = "smsc,lan9115"; + reg = <1 0x01f00000 0x1000>; + interrupts = <0 48 4>; + phy-mode = "mii"; + }; + + uart@5,00200000 { + compatible = "ns16550a"; + reg = <5 0x00200000 0x20>; + interrupts = <0 49 4>; + clock-frequency = <12288000>; + }; + }; diff --git a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt b/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt deleted file mode 100644 index 68ef80afff16..000000000000 --- a/Documentation/devicetree/bindings/bus/uniphier-system-bus.txt +++ /dev/null @@ -1,66 +0,0 @@ -UniPhier System Bus - -The UniPhier System Bus is an external bus that connects on-board devices to -the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and -some control signals. It supports up to 8 banks (chip selects). - -Before any access to the bus, the bus controller must be configured; the bus -controller registers provide the control for the translation from the offset -within each bank to the CPU-viewed address. The needed setup includes the base -address, the size of each bank. Optionally, some timing parameters can be -optimized for faster bus access. - -Required properties: -- compatible: should be "socionext,uniphier-system-bus". -- reg: offset and length of the register set for the bus controller device. -- #address-cells: should be 2. The first cell is the bank number (chip select). - The second cell is the address offset within the bank. -- #size-cells: should be 1. -- ranges: should provide a proper address translation from the System Bus to - the parent bus. - -Note: -The address region(s) that can be assigned for the System Bus is implementation -defined. Some SoCs can use 0x00000000-0x0fffffff and 0x40000000-0x4fffffff, -while other SoCs can only use 0x40000000-0x4fffffff. There might be additional -limitations depending on SoCs and the boot mode. The address translation is -arbitrary as long as the banks are assigned in the supported address space with -the required alignment and they do not overlap one another. -For example, it is possible to map: - bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff -It is also possible to map: - bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff -There is no reason to stick to a particular translation mapping, but the -"ranges" property should provide a "reasonable" default that is known to work. -The software should initialize the bus controller according to it. - -Example: - - system-bus { - compatible = "socionext,uniphier-system-bus"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - ranges = <1 0x00000000 0x42000000 0x02000000 - 5 0x00000000 0x46000000 0x01000000>; - - ethernet@1,01f00000 { - compatible = "smsc,lan9115"; - reg = <1 0x01f00000 0x1000>; - interrupts = <0 48 4> - phy-mode = "mii"; - }; - - uart@5,00200000 { - compatible = "ns16550a"; - reg = <5 0x00200000 0x20>; - interrupts = <0 49 4> - clock-frequency = <12288000>; - }; - }; - -In this example, - - the Ethernet device is connected at the offset 0x01f00000 of CS1 and - mapped to 0x43f00000 of the parent bus. - - the UART device is connected at the offset 0x00200000 of CS5 and - mapped to 0x46200000 of the parent bus. diff --git a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt deleted file mode 100644 index 8def11b16a24..000000000000 --- a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt +++ /dev/null @@ -1,36 +0,0 @@ -Vivante GPU core devices -======================== - -Required properties: -- compatible: Should be "vivante,gc" - A more specific compatible is not needed, as the cores contain chip - identification registers at fixed locations, which provide all the - necessary information to the driver. -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain the cores interrupt line -- clocks: should contain one clock for entry in clock-names - see Documentation/devicetree/bindings/clock/clock-bindings.txt -- clock-names: - - "bus": AXI/master interface clock - - "reg": AHB/slave interface clock - (only required if GPU can gate slave interface independently) - - "core": GPU core clock - - "shader": Shader clock (only required if GPU has feature PIPE_3D) - -Optional properties: -- power-domains: a power domain consumer specifier according to - Documentation/devicetree/bindings/power/power_domain.txt - -example: - -gpu_3d: gpu@130000 { - compatible = "vivante,gc"; - reg = <0x00130000 0x4000>; - interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, - <&clks IMX6QDL_CLK_GPU3D_CORE>, - <&clks IMX6QDL_CLK_GPU3D_SHADER>; - clock-names = "bus", "core", "shader"; - power-domains = <&gpc 1>; -}; diff --git a/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml b/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml new file mode 100644 index 000000000000..e7bf6dd7da29 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/socionext,uniphier-mio-dmac.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier Media IO DMA controller + +description: | + This works as an external DMA engine for SD/eMMC controllers etc. + found in UniPhier LD4, Pro4, sLD8 SoCs. + +maintainers: + - Masahiro Yamada <[email protected]> + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + const: socionext,uniphier-mio-dmac + + reg: + maxItems: 1 + + interrupts: + description: | + A list of interrupt specifiers associated with the DMA channels. + The number of interrupt lines is SoC-dependent. + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + '#dma-cells': + description: The single cell represents the channel index. + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - '#dma-cells' + +additionalProperties: false + +examples: + - | + // In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a + // typo. The first two channels share a single interrupt line. + + dmac: dma-controller@5a000000 { + compatible = "socionext,uniphier-mio-dmac"; + reg = <0x5a000000 0x1000>; + interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, + <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; + clocks = <&mio_clk 7>; + resets = <&mio_rst 7>; + #dma-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt b/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt deleted file mode 100644 index b12388dc7eac..000000000000 --- a/Documentation/devicetree/bindings/dma/uniphier-mio-dmac.txt +++ /dev/null @@ -1,25 +0,0 @@ -UniPhier Media IO DMA controller - -This works as an external DMA engine for SD/eMMC controllers etc. -found in UniPhier LD4, Pro4, sLD8 SoCs. - -Required properties: -- compatible: should be "socionext,uniphier-mio-dmac". -- reg: offset and length of the register set for the device. -- interrupts: a list of interrupt specifiers associated with the DMA channels. -- clocks: a single clock specifier. -- #dma-cells: should be <1>. The single cell represents the channel index. - -Example: - dmac: dma-controller@5a000000 { - compatible = "socionext,uniphier-mio-dmac"; - reg = <0x5a000000 0x1000>; - interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, - <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; - clocks = <&mio_clk 7>; - #dma-cells = <1>; - }; - -Note: -In the example above, "interrupts = <0 68 4>, <0 68 4>, ..." is not a typo. -The first two channels share a single interrupt line. diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index 4ddcf709cc3c..62811a1b5058 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -7,9 +7,9 @@ # $id is a unique identifier based on the filename. There may or may not be a # file present at the URL. -$id: "http://devicetree.org/schemas/example-schema.yaml#" +$id: http://devicetree.org/schemas/example-schema.yaml# # $schema is the meta-schema this schema should be validated with. -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$schema: http://devicetree.org/meta-schemas/core.yaml# title: An example schema annotated with jsonschema details diff --git a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt b/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt deleted file mode 100644 index f281f12dac18..000000000000 --- a/Documentation/devicetree/bindings/gpio/gpio-uniphier.txt +++ /dev/null @@ -1,51 +0,0 @@ -UniPhier GPIO controller - -Required properties: -- compatible: Should be "socionext,uniphier-gpio". -- reg: Specifies offset and length of the register set for the device. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells: Should be 2. The first cell is the pin number and the second - cell is used to specify optional parameters. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells: Should be 2. The first cell defines the interrupt number. - The second cell bits[3:0] is used to specify trigger type as follows: - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - Valid combinations are 1, 2, 3, 4, 8. -- ngpios: Specifies the number of GPIO lines. -- gpio-ranges: Mapping to pin controller pins (as described in gpio.txt) -- socionext,interrupt-ranges: Specifies an interrupt number mapping between - this GPIO controller and its interrupt parent, in the form of arbitrary - number of <child-interrupt-base parent-interrupt-base length> triplets. - -Optional properties: -- gpio-ranges-group-names: Used for named gpio ranges (as described in gpio.txt) - -Example: - gpio: gpio@55000000 { - compatible = "socionext,uniphier-gpio"; - reg = <0x55000000 0x200>; - interrupt-parent = <&aidet>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 0 0>; - gpio-ranges-group-names = "gpio_range"; - ngpios = <248>; - socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>; - }; - -Consumer Example: - - sdhci0_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>; - }; - -Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC document. -Unfortunately, only the one's place is octal in the port numbering. (That is, -PORT 8, 9, 18, 19, 28, 29, ... are missing.) UNIPHIER_GPIO_PORT() is a helper -macro to calculate 29 * 8 + 4. diff --git a/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml b/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml new file mode 100644 index 000000000000..580a39e09d39 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier GPIO controller + +maintainers: + - Masahiro Yamada <[email protected]> + +properties: + $nodename: + pattern: "^gpio@[0-9a-f]+$" + + compatible: + const: socionext,uniphier-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + description: | + The first cell defines the interrupt number. + The second cell bits[3:0] is used to specify trigger type as follows: + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Valid combinations are 1, 2, 3, 4, 8. + const: 2 + + ngpios: + minimum: 0 + maximum: 512 + + gpio-ranges-group-names: + $ref: /schemas/types.yaml#/definitions/string-array + + socionext,interrupt-ranges: + description: | + Specifies an interrupt number mapping between this GPIO controller and + its interrupt parent, in the form of arbitrary number of + <child-interrupt-base parent-interrupt-base length> triplets. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + - ngpios + - gpio-ranges + - socionext,interrupt-ranges + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/gpio/uniphier-gpio.h> + + gpio: gpio@55000000 { + compatible = "socionext,uniphier-gpio"; + reg = <0x55000000 0x200>; + interrupt-parent = <&aidet>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 0>; + gpio-ranges-group-names = "gpio_range"; + ngpios = <248>; + socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>; + }; + + // Consumer: + // Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC + // document. Unfortunately, only the one's place is octal in the port + // numbering. (That is, PORT 8, 9, 18, 19, 28, 29, ... do not exist.) + // UNIPHIER_GPIO_PORT() is a helper macro to calculate 29 * 8 + 4. + sdhci0_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>; + }; diff --git a/Documentation/devicetree/bindings/gpu/vivante,gc.yaml b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml new file mode 100644 index 000000000000..0bc4b38d5cbb --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/vivante,gc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Vivante GPU Bindings + +description: Vivante GPU core devices + +maintainers: + - Lucas Stach <[email protected]> + +properties: + compatible: + const: vivante,gc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: AXI/master interface clock + - description: GPU core clock + - description: Shader clock (only required if GPU has feature PIPE_3D) + - description: AHB/slave interface clock (only required if GPU can gate slave interface independently) + minItems: 1 + maxItems: 4 + + clock-names: + items: + enum: [ bus, core, shader, reg ] + minItems: 1 + maxItems: 4 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6qdl-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + gpu@130000 { + compatible = "vivante,gc"; + reg = <0x00130000 0x4000>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "bus", "core", "shader"; + power-domains = <&gpc 1>; + }; + +... diff --git a/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt b/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt deleted file mode 100644 index 27fc6f8c798b..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-uniphier-f.txt +++ /dev/null @@ -1,25 +0,0 @@ -UniPhier I2C controller (FIFO-builtin) - -Required properties: -- compatible: should be "socionext,uniphier-fi2c". -- #address-cells: should be 1. -- #size-cells: should be 0. -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -- clock-frequency: desired I2C bus frequency in Hz. The maximum supported - value is 400000. Defaults to 100000 if not specified. - -Examples: - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt b/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt deleted file mode 100644 index 26f9d95b3436..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-uniphier.txt +++ /dev/null @@ -1,25 +0,0 @@ -UniPhier I2C controller (FIFO-less) - -Required properties: -- compatible: should be "socionext,uniphier-i2c". -- #address-cells: should be 1. -- #size-cells: should be 0. -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -- clock-frequency: desired I2C bus frequency in Hz. The maximum supported - value is 400000. Defaults to 100000 if not specified. - -Examples: - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml new file mode 100644 index 000000000000..15abc022968e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-fi2c.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/socionext,uniphier-fi2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier I2C controller (FIFO-builtin) + +maintainers: + - Masahiro Yamada <[email protected]> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: socionext,uniphier-fi2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + minimum: 100000 + maximum: 400000 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - interrupts + - clocks + +examples: + - | + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; diff --git a/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml new file mode 100644 index 000000000000..ef998def554e --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/socionext,uniphier-i2c.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/socionext,uniphier-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier I2C controller (FIFO-less) + +maintainers: + - Masahiro Yamada <[email protected]> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: socionext,uniphier-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + minimum: 100000 + maximum: 400000 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - interrupts + - clocks + +examples: + - | + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt deleted file mode 100644 index 48e71d3ac2ad..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt +++ /dev/null @@ -1,32 +0,0 @@ -UniPhier AIDET - -UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic -Interrupt Controller). GIC itself can handle only high level and rising edge -interrupts. The AIDET provides logic inverter to support low level and falling -edge interrupts. - -Required properties: -- compatible: Should be one of the following: - "socionext,uniphier-ld4-aidet" - for LD4 SoC - "socionext,uniphier-pro4-aidet" - for Pro4 SoC - "socionext,uniphier-sld8-aidet" - for sLD8 SoC - "socionext,uniphier-pro5-aidet" - for Pro5 SoC - "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC - "socionext,uniphier-ld11-aidet" - for LD11 SoC - "socionext,uniphier-ld20-aidet" - for LD20 SoC - "socionext,uniphier-pxs3-aidet" - for PXs3 SoC -- reg: Specifies offset and length of the register set for the device. -- interrupt-controller: Identifies the node as an interrupt controller -- #interrupt-cells : Specifies the number of cells needed to encode an interrupt - source. The value should be 2. The first cell defines the interrupt number - (corresponds to the SPI interrupt number of GIC). The second cell specifies - the trigger type as defined in interrupts.txt in this directory. - -Example: - - aidet: aidet@5fc20000 { - compatible = "socionext,uniphier-pro4-aidet"; - reg = <0x5fc20000 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml new file mode 100644 index 000000000000..f89ebde76dab --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/socionext,uniphier-aidet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier AIDET + +description: | + UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC + (Generic Interrupt Controller). GIC itself can handle only high level and + rising edge interrupts. The AIDET provides logic inverter to support low + level and falling edge interrupts. + +maintainers: + - Masahiro Yamada <[email protected]> + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + enum: + - socionext,uniphier-ld4-aidet + - socionext,uniphier-pro4-aidet + - socionext,uniphier-sld8-aidet + - socionext,uniphier-pro5-aidet + - socionext,uniphier-pxs2-aidet + - socionext,uniphier-ld6b-aidet + - socionext,uniphier-ld11-aidet + - socionext,uniphier-ld20-aidet + - socionext,uniphier-pxs3-aidet + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: | + The first cell defines the interrupt number (corresponds to the SPI + interrupt number of GIC). The second cell specifies the trigger type as + defined in interrupts.txt in this directory. + const: 2 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +additionalProperties: false + +examples: + - | + interrupt-controller@5fc20000 { + compatible = "socionext,uniphier-pro4-aidet"; + reg = <0x5fc20000 0x200>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml new file mode 100644 index 000000000000..2f45dd0d04db --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml @@ -0,0 +1,143 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence SD/SDIO/eMMC Host Controller (SD4HC) + +maintainers: + - Masahiro Yamada <[email protected]> + - Piotr Sroka <[email protected]> + +allOf: + - $ref: mmc-controller.yaml + +properties: + compatible: + items: + - enum: + - socionext,uniphier-sd4hc + - const: cdns,sd4hc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + # PHY DLL input delays: + # They are used to delay the data valid window, and align the window to + # sampling clock. The delay starts from 5ns (for delay parameter equal to 0) + # and it is increased by 2.5ns in each step. + + cdns,phy-input-delay-sd-highspeed: + description: Value of the delay in the input path for SD high-speed timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-legacy: + description: Value of the delay in the input path for legacy timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-sd-uhs-sdr12: + description: Value of the delay in the input path for SD UHS SDR12 timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-sd-uhs-sdr25: + description: Value of the delay in the input path for SD UHS SDR25 timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-sd-uhs-sdr50: + description: Value of the delay in the input path for SD UHS SDR50 timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-sd-uhs-ddr50: + description: Value of the delay in the input path for SD UHS DDR50 timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-mmc-highspeed: + description: Value of the delay in the input path for MMC high-speed timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + cdns,phy-input-delay-mmc-ddr: + description: Value of the delay in the input path for eMMC high-speed DDR timing + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x1f + + # PHY DLL clock delays: + # Each delay property represents the fraction of the clock period. + # The approximate delay value will be + # (<delay property value>/128)*sdmclk_clock_period. + + cdns,phy-dll-delay-sdclk: + description: | + Value of the delay introduced on the sdclk output for all modes except + HS200, HS400 and HS400_ES. + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x7f + + cdns,phy-dll-delay-sdclk-hsmmc: + description: | + Value of the delay introduced on the sdclk output for HS200, HS400 and + HS400_ES speed modes. + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x7f + + cdns,phy-dll-delay-strobe: + description: | + Value of the delay introduced on the dat_strobe input used in + HS400 / HS400_ES speed modes. + allOf: + - $ref: "/schemas/types.yaml#/definitions/uint32" + - minimum: 0 + - maximum: 0x7f + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + emmc: mmc@5a000000 { + compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; + reg = <0x5a000000 0x400>; + interrupts = <0 78 4>; + clocks = <&clk 4>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cdns,phy-dll-delay-sdclk = <0>; + }; diff --git a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt b/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt deleted file mode 100644 index fa423c277853..000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-cadence.txt +++ /dev/null @@ -1,80 +0,0 @@ -* Cadence SD/SDIO/eMMC Host Controller - -Required properties: -- compatible: should be one of the following: - "cdns,sd4hc" - default of the IP - "socionext,uniphier-sd4hc" - for Socionext UniPhier SoCs -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: -For eMMC configuration, supported speed modes are not indicated by the SDHCI -Capabilities Register. Instead, the following properties should be specified -if supported. See mmc.txt for details. -- mmc-ddr-1_8v -- mmc-ddr-1_2v -- mmc-hs200-1_8v -- mmc-hs200-1_2v -- mmc-hs400-1_8v -- mmc-hs400-1_2v - -Some PHY delays can be configured by following properties. -PHY DLL input delays: -They are used to delay the data valid window, and align the window -to sampling clock. The delay starts from 5ns (for delay parameter equal to 0) -and it is increased by 2.5ns in each step. -- cdns,phy-input-delay-sd-highspeed: - Value of the delay in the input path for SD high-speed timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-legacy: - Value of the delay in the input path for legacy timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-sdr12: - Value of the delay in the input path for SD UHS SDR12 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-sdr25: - Value of the delay in the input path for SD UHS SDR25 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-sdr50: - Value of the delay in the input path for SD UHS SDR50 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-sd-uhs-ddr50: - Value of the delay in the input path for SD UHS DDR50 timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-mmc-highspeed: - Value of the delay in the input path for MMC high-speed timing - Valid range = [0:0x1F]. -- cdns,phy-input-delay-mmc-ddr: - Value of the delay in the input path for eMMC high-speed DDR timing - Valid range = [0:0x1F]. - -PHY DLL clock delays: -Each delay property represents the fraction of the clock period. -The approximate delay value will be -(<delay property value>/128)*sdmclk_clock_period. -- cdns,phy-dll-delay-sdclk: - Value of the delay introduced on the sdclk output - for all modes except HS200, HS400 and HS400_ES. - Valid range = [0:0x7F]. -- cdns,phy-dll-delay-sdclk-hsmmc: - Value of the delay introduced on the sdclk output - for HS200, HS400 and HS400_ES speed modes. - Valid range = [0:0x7F]. -- cdns,phy-dll-delay-strobe: - Value of the delay introduced on the dat_strobe input - used in HS400 / HS400_ES speed modes. - Valid range = [0:0x7F]. - -Example: - emmc: sdhci@5a000000 { - compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; - reg = <0x5a000000 0x400>; - interrupts = <0 78 4>; - clocks = <&clk 4>; - bus-width = <8>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - cdns,phy-dll-delay-sdclk = <0>; - }; diff --git a/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml new file mode 100644 index 000000000000..cdfac9b4411b --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/socionext,uniphier-sd.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/socionext,uniphier-sd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier SD/SDIO/eMMC controller + +maintainers: + - Masahiro Yamada <[email protected]> + +properties: + compatible: + description: version 2.91, 3.1, 3.1.1, respectively + enum: + - socionext,uniphier-sd-v2.91 + - socionext,uniphier-sd-v3.1 + - socionext,uniphier-sd-v3.1.1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + reset-names: + description: | + There are three reset signals at maximum + host: mandatory for all variants + bridge: exist only for version 2.91 + hw: optional. exist if eMMC hw reset line is available + oneOf: + - const: host + - items: + - const: host + - const: bridge + - items: + - const: host + - const: hw + - items: + - const: host + - const: bridge + - const: hw + + resets: + minItems: 1 + maxItems: 3 + +allOf: + - $ref: mmc-controller.yaml + + - if: + properties: + compatible: + contains: + const: socionext,uniphier-sd-v2.91 + then: + properties: + reset-names: + contains: + const: bridge + else: + properties: + reset-names: + not: + contains: + const: bridge + +required: + - compatible + - reg + - interrupts + - clocks + - reset-names + - resets + +examples: + - | + sd: mmc@5a400000 { + compatible = "socionext,uniphier-sd-v2.91"; + reg = <0x5a400000 0x200>; + interrupts = <0 76 4>; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_uhs>; + clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; + dma-names = "rx-tx"; + dmas = <&dmac 4>; + bus-width = <4>; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + }; diff --git a/Documentation/devicetree/bindings/mmc/uniphier-sd.txt b/Documentation/devicetree/bindings/mmc/uniphier-sd.txt deleted file mode 100644 index e1d658755722..000000000000 --- a/Documentation/devicetree/bindings/mmc/uniphier-sd.txt +++ /dev/null @@ -1,55 +0,0 @@ -UniPhier SD/eMMC controller - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-sd-v2.91" - IP version 2.91 - "socionext,uniphier-sd-v3.1" - IP version 3.1 - "socionext,uniphier-sd-v3.1.1" - IP version 3.1.1 -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: a single clock specifier of the controller clock. -- reset-names: should contain the following: - "host" - mandatory for all versions - "bridge" - should exist only for "socionext,uniphier-sd-v2.91" - "hw" - should exist if eMMC hw reset line is available -- resets: a list of reset specifiers, corresponding to the reset-names - -Optional properties: -- pinctrl-names: if present, should contain the following: - "default" - should exist for all instances - "uhs" - should exist for SD instance with UHS support -- pinctrl-0: pin control state for the default mode -- pinctrl-1: pin control state for the UHS mode -- dma-names: should be "rx-tx" if present. - This property can exist only for "socionext,uniphier-sd-v2.91". -- dmas: a single DMA channel specifier - This property can exist only for "socionext,uniphier-sd-v2.91". -- bus-width: see mmc.txt -- cap-sd-highspeed: see mmc.txt -- cap-mmc-highspeed: see mmc.txt -- sd-uhs-sdr12: see mmc.txt -- sd-uhs-sdr25: see mmc.txt -- sd-uhs-sdr50: see mmc.txt -- cap-mmc-hw-reset: should exist if reset-names contains "hw". see mmc.txt -- non-removable: see mmc.txt - -Example: - - sd: sdhc@5a400000 { - compatible = "socionext,uniphier-sd-v2.91"; - reg = <0x5a400000 0x200>; - interrupts = <0 76 4>; - pinctrl-names = "default", "uhs"; - pinctrl-0 = <&pinctrl_sd>; - pinctrl-1 = <&pinctrl_sd_uhs>; - clocks = <&mio_clk 0>; - reset-names = "host", "bridge"; - resets = <&mio_rst 0>, <&mio_rst 3>; - dma-names = "rx-tx"; - dmas = <&dmac 4>; - bus-width = <4>; - cap-sd-highspeed; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - }; diff --git a/Documentation/devicetree/bindings/mtd/denali,nand.yaml b/Documentation/devicetree/bindings/mtd/denali,nand.yaml new file mode 100644 index 000000000000..46e6b6726bc0 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/denali,nand.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/denali,nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Denali NAND controller + +maintainers: + - Masahiro Yamada <[email protected]> + +properties: + compatible: + enum: + - altr,socfpga-denali-nand + - socionext,uniphier-denali-nand-v5a + - socionext,uniphier-denali-nand-v5b + + reg-names: + description: | + There are two register regions: + nand_data: host data/command interface + denali_reg: register interface + items: + - const: nand_data + - const: denali_reg + + reg: + minItems: 2 + maxItems: 2 + + interrupts: + maxItems: 1 + + clock-names: + description: | + There are three clocks: + nand: controller core clock + nand_x: bus interface clock + ecc: ECC circuit clock + items: + - const: nand + - const: nand_x + - const: ecc + + clocks: + minItems: 3 + maxItems: 3 + + reset-names: + description: | + There are two optional resets: + nand: controller core reset + reg: register reset + oneOf: + - items: + - const: nand + - const: reg + - const: nand + - const: reg + + resets: + minItems: 1 + maxItems: 2 + +allOf: + - $ref: nand-controller.yaml + + - if: + properties: + compatible: + contains: + const: altr,socfpga-denali-nand + then: + patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + nand-ecc-strength: + enum: + - 8 + - 15 + nand-ecc-step-size: + enum: + - 512 + + - if: + properties: + compatible: + contains: + const: socionext,uniphier-denali-nand-v5a + then: + patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + nand-ecc-strength: + enum: + - 8 + - 16 + - 24 + nand-ecc-step-size: + enum: + - 1024 + + - if: + properties: + compatible: + contains: + const: socionext,uniphier-denali-nand-v5b + then: + patternProperties: + "^nand@[a-f0-9]$": + type: object + properties: + nand-ecc-strength: + enum: + - 8 + - 16 + nand-ecc-step-size: + enum: + - 1024 + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +examples: + - | + nand-controller@ff900000 { + compatible = "altr,socfpga-denali-nand"; + reg-names = "nand_data", "denali_reg"; + reg = <0xff900000 0x20>, <0xffb80000 0x1000>; + interrupts = <0 144 4>; + clock-names = "nand", "nand_x", "ecc"; + clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; + reset-names = "nand", "reg"; + resets = <&nand_rst>, <&nand_reg_rst>; + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt deleted file mode 100644 index 98916a84bbf6..000000000000 --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt +++ /dev/null @@ -1,61 +0,0 @@ -* Denali NAND controller - -Required properties: - - compatible : should be one of the following: - "altr,socfpga-denali-nand" - for Altera SOCFPGA - "socionext,uniphier-denali-nand-v5a" - for Socionext UniPhier (v5a) - "socionext,uniphier-denali-nand-v5b" - for Socionext UniPhier (v5b) - - reg : should contain registers location and length for data and reg. - - reg-names: Should contain the reg names "nand_data" and "denali_reg" - - #address-cells: should be 1. The cell encodes the chip select connection. - - #size-cells : should be 0. - - interrupts : The interrupt number. - - clocks: should contain phandle of the controller core clock, the bus - interface clock, and the ECC circuit clock. - - clock-names: should contain "nand", "nand_x", "ecc" - -Optional properties: - - resets: may contain phandles to the controller core reset, the register - reset - - reset-names: may contain "nand", "reg" - -Sub-nodes: - Sub-nodes represent available NAND chips. - - Required properties: - - reg: should contain the bank ID of the controller to which each chip - select is connected. - - Optional properties: - - nand-ecc-step-size: see nand-controller.yaml for details. - If present, the value must be - 512 for "altr,socfpga-denali-nand" - 1024 for "socionext,uniphier-denali-nand-v5a" - 1024 for "socionext,uniphier-denali-nand-v5b" - - nand-ecc-strength: see nand-controller.yaml for details. Valid values are: - 8, 15 for "altr,socfpga-denali-nand" - 8, 16, 24 for "socionext,uniphier-denali-nand-v5a" - 8, 16 for "socionext,uniphier-denali-nand-v5b" - - nand-ecc-maximize: see nand-controller.yaml for details - -The chip nodes may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Examples: - -nand: nand@ff900000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "altr,socfpga-denali-nand"; - reg = <0xff900000 0x20>, <0xffb80000 0x1000>; - reg-names = "nand_data", "denali_reg"; - clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>; - clock-names = "nand", "nand_x", "ecc"; - resets = <&nand_rst>, <&nand_reg_rst>; - reset-names = "nand", "reg"; - interrupts = <0 144 4>; - - nand@0 { - reg = <0>; - } -}; diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml new file mode 100644 index 000000000000..cccf8202c8f7 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/bosch,m_can.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bosch MCAN controller Bindings + +description: Bosch MCAN controller for CAN bus + +maintainers: + - Sriram Dash <[email protected]> + +properties: + compatible: + const: bosch,m_can + + reg: + items: + - description: M_CAN registers map + - description: message RAM + + reg-names: + items: + - const: m_can + - const: message_ram + + interrupts: + items: + - description: interrupt line0 + - description: interrupt line1 + minItems: 1 + maxItems: 2 + + interrupt-names: + items: + - const: int0 + - const: int1 + minItems: 1 + maxItems: 2 + + clocks: + items: + - description: peripheral clock + - description: bus clock + + clock-names: + items: + - const: hclk + - const: cclk + + bosch,mram-cfg: + description: | + Message RAM configuration data. + Multiple M_CAN instances can share the same Message RAM + and each element(e.g Rx FIFO or Tx Buffer and etc) number + in Message RAM is also configurable, so this property is + telling driver how the shared or private Message RAM are + used by this M_CAN controller. + + The format should be as follows: + <offset sidf_elems xidf_elems rxf0_elems rxf1_elems rxb_elems txe_elems txb_elems> + The 'offset' is an address offset of the Message RAM where + the following elements start from. This is usually set to + 0x0 if you're using a private Message RAM. The remain cells + are used to specify how many elements are used for each FIFO/Buffer. + + M_CAN includes the following elements according to user manual: + 11-bit Filter 0-128 elements / 0-128 words + 29-bit Filter 0-64 elements / 0-128 words + Rx FIFO 0 0-64 elements / 0-1152 words + Rx FIFO 1 0-64 elements / 0-1152 words + Rx Buffers 0-64 elements / 0-1152 words + Tx Event FIFO 0-32 elements / 0-64 words + Tx Buffers 0-32 elements / 0-576 words + + Please refer to 2.4.1 Message RAM Configuration in Bosch + M_CAN user manual for details. + allOf: + - $ref: /schemas/types.yaml#/definitions/int32-array + - items: + items: + - description: The 'offset' is an address offset of the Message RAM + where the following elements start from. This is usually + set to 0x0 if you're using a private Message RAM. + default: 0 + - description: 11-bit Filter 0-128 elements / 0-128 words + minimum: 0 + maximum: 128 + - description: 29-bit Filter 0-64 elements / 0-128 words + minimum: 0 + maximum: 64 + - description: Rx FIFO 0 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Rx FIFO 1 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Rx Buffers 0-64 elements / 0-1152 words + minimum: 0 + maximum: 64 + - description: Tx Event FIFO 0-32 elements / 0-64 words + minimum: 0 + maximum: 32 + - description: Tx Buffers 0-32 elements / 0-576 words + minimum: 0 + maximum: 32 + maxItems: 1 + + can-transceiver: + $ref: can-transceiver.yaml# + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - bosch,mram-cfg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6sx-clock.h> + can@20e8000 { + compatible = "bosch,m_can"; + reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; + reg-names = "m_can", "message_ram"; + interrupts = <0 114 0x04>, <0 114 0x04>; + interrupt-names = "int0", "int1"; + clocks = <&clks IMX6SX_CLK_CANFD>, + <&clks IMX6SX_CLK_CANFD>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; + + can-transceiver { + max-bitrate = <5000000>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/net/can/can-transceiver.txt b/Documentation/devicetree/bindings/net/can/can-transceiver.txt deleted file mode 100644 index 0011f53ff159..000000000000 --- a/Documentation/devicetree/bindings/net/can/can-transceiver.txt +++ /dev/null @@ -1,24 +0,0 @@ -Generic CAN transceiver Device Tree binding ------------------------------- - -CAN transceiver typically limits the max speed in standard CAN and CAN FD -modes. Typically these limitations are static and the transceivers themselves -provide no way to detect this limitation at runtime. For this situation, -the "can-transceiver" node can be used. - -Required Properties: - max-bitrate: a positive non 0 value that determines the max - speed that CAN/CAN-FD can run. Any other value - will be ignored. - -Examples: - -Based on Texas Instrument's TCAN1042HGV CAN Transceiver - -m_can0 { - .... - can-transceiver { - max-bitrate = <5000000>; - }; - ... -}; diff --git a/Documentation/devicetree/bindings/net/can/can-transceiver.yaml b/Documentation/devicetree/bindings/net/can/can-transceiver.yaml new file mode 100644 index 000000000000..6396977d29e5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/can-transceiver.yaml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/can-transceiver.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CAN transceiver Bindings + +description: CAN transceiver generic properties bindings + +maintainers: + - Rob Herring <[email protected]> + +properties: + max-bitrate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: a positive non 0 value that determines the max speed that CAN/CAN-FD can run. + minimum: 1 diff --git a/Documentation/devicetree/bindings/net/can/m_can.txt b/Documentation/devicetree/bindings/net/can/m_can.txt deleted file mode 100644 index ed614383af9c..000000000000 --- a/Documentation/devicetree/bindings/net/can/m_can.txt +++ /dev/null @@ -1,75 +0,0 @@ -Bosch MCAN controller Device Tree Bindings -------------------------------------------------- - -Required properties: -- compatible : Should be "bosch,m_can" for M_CAN controllers -- reg : physical base address and size of the M_CAN - registers map and Message RAM -- reg-names : Should be "m_can" and "message_ram" -- interrupts : Should be the interrupt number of M_CAN interrupt - line 0 and line 1, could be same if sharing - the same interrupt. -- interrupt-names : Should contain "int0" and "int1" -- clocks : Clocks used by controller, should be host clock - and CAN clock. -- clock-names : Should contain "hclk" and "cclk" -- pinctrl-<n> : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt -- pinctrl-names : Names corresponding to the numbered pinctrl states -- bosch,mram-cfg : Message RAM configuration data. - Multiple M_CAN instances can share the same Message - RAM and each element(e.g Rx FIFO or Tx Buffer and etc) - number in Message RAM is also configurable, - so this property is telling driver how the shared or - private Message RAM are used by this M_CAN controller. - - The format should be as follows: - <offset sidf_elems xidf_elems rxf0_elems rxf1_elems - rxb_elems txe_elems txb_elems> - The 'offset' is an address offset of the Message RAM - where the following elements start from. This is - usually set to 0x0 if you're using a private Message - RAM. The remain cells are used to specify how many - elements are used for each FIFO/Buffer. - - M_CAN includes the following elements according to user manual: - 11-bit Filter 0-128 elements / 0-128 words - 29-bit Filter 0-64 elements / 0-128 words - Rx FIFO 0 0-64 elements / 0-1152 words - Rx FIFO 1 0-64 elements / 0-1152 words - Rx Buffers 0-64 elements / 0-1152 words - Tx Event FIFO 0-32 elements / 0-64 words - Tx Buffers 0-32 elements / 0-576 words - - Please refer to 2.4.1 Message RAM Configuration in - Bosch M_CAN user manual for details. - -Optional Subnode: -- can-transceiver : Can-transceiver subnode describing maximum speed - that can be used for CAN/CAN-FD modes. See - Documentation/devicetree/bindings/net/can/can-transceiver.txt - for details. -Example: -SoC dtsi: -m_can1: can@20e8000 { - compatible = "bosch,m_can"; - reg = <0x020e8000 0x4000>, <0x02298000 0x4000>; - reg-names = "m_can", "message_ram"; - interrupts = <0 114 0x04>, - <0 114 0x04>; - interrupt-names = "int0", "int1"; - clocks = <&clks IMX6SX_CLK_CANFD>, - <&clks IMX6SX_CLK_CANFD>; - clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>; -}; - -Board dts: -&m_can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_m_can1>; - status = "enabled"; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt deleted file mode 100644 index 8173b12138ad..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt +++ /dev/null @@ -1,27 +0,0 @@ -UniPhier SoCs pin controller - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-pinctrl" - for LD4 SoC - "socionext,uniphier-pro4-pinctrl" - for Pro4 SoC - "socionext,uniphier-sld8-pinctrl" - for sLD8 SoC - "socionext,uniphier-pro5-pinctrl" - for Pro5 SoC - "socionext,uniphier-pxs2-pinctrl" - for PXs2 SoC - "socionext,uniphier-ld6b-pinctrl" - for LD6b SoC - "socionext,uniphier-ld11-pinctrl" - for LD11 SoC - "socionext,uniphier-ld20-pinctrl" - for LD20 SoC - "socionext,uniphier-pxs3-pinctrl" - for PXs3 SoC - -Note: -The UniPhier pinctrl should be a subnode of a "syscon" compatible node. - -Example: - soc-glue@5f800000 { - compatible = "socionext,uniphier-pro4-soc-glue", - "simple-mfd", "syscon"; - reg = <0x5f800000 0x2000>; - - pinctrl: pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml new file mode 100644 index 000000000000..f8a93d8680f9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier SoCs pin controller + +maintainers: + - Masahiro Yamada <[email protected]> + +properties: + $nodename: + pattern: "pinctrl" + + compatible: + enum: + - socionext,uniphier-ld4-pinctrl + - socionext,uniphier-pro4-pinctrl + - socionext,uniphier-sld8-pinctrl + - socionext,uniphier-pro5-pinctrl + - socionext,uniphier-pxs2-pinctrl + - socionext,uniphier-ld6b-pinctrl + - socionext,uniphier-ld11-pinctrl + - socionext,uniphier-ld20-pinctrl + - socionext,uniphier-pxs3-pinctrl + +required: + - compatible + +examples: + - | + // The UniPhier pinctrl should be a subnode of a "syscon" compatible node. + + soc-glue@5f800000 { + compatible = "socionext,uniphier-pro4-soc-glue", "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-pro4-pinctrl"; + }; + }; diff --git a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt b/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt deleted file mode 100644 index aaac7975f61c..000000000000 --- a/Documentation/devicetree/bindings/rng/brcm,bcm2835.txt +++ /dev/null @@ -1,40 +0,0 @@ -BCM2835/6368 Random number generator - -Required properties: - -- compatible : should be one of - "brcm,bcm2835-rng" - "brcm,bcm-nsp-rng" - "brcm,bcm5301x-rng" or - "brcm,bcm6368-rng" -- reg : Specifies base physical address and size of the registers. - -Optional properties: - -- clocks : phandle to clock-controller plus clock-specifier pair -- clock-names : "ipsec" as a clock name - -Optional properties: - -- interrupts: specify the interrupt for the RNG block - -Example: - -rng { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - interrupts = <2 29>; -}; - -rng@18033000 { - compatible = "brcm,bcm-nsp-rng"; - reg = <0x18033000 0x14>; -}; - -random: rng@10004180 { - compatible = "brcm,bcm6368-rng"; - reg = <0x10004180 0x14>; - - clocks = <&periph_clk 18>; - clock-names = "ipsec"; -}; diff --git a/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml new file mode 100644 index 000000000000..42d9a38e4e1a --- /dev/null +++ b/Documentation/devicetree/bindings/rng/brcm,bcm2835.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/brcm,bcm2835.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BCM2835/6368 Random number generator + +maintainers: + - Stefan Wahren <[email protected]> + - Florian Fainelli <[email protected]> + - Herbert Xu <[email protected]> + +properties: + compatible: + enum: + - brcm,bcm2835-rng + - brcm,bcm-nsp-rng + - brcm,bcm5301x-rng + - brcm,bcm6368-rng + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: ipsec + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + rng { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; + interrupts = <2 29>; + }; + + - | + rng@18033000 { + compatible = "brcm,bcm-nsp-rng"; + reg = <0x18033000 0x14>; + }; + + - | + rng@10004180 { + compatible = "brcm,bcm6368-rng"; + reg = <0x10004180 0x14>; + + clocks = <&periph_clk 18>; + clock-names = "ipsec"; + }; diff --git a/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml new file mode 100644 index 000000000000..09a30300850c --- /dev/null +++ b/Documentation/devicetree/bindings/serial/socionext,uniphier-uart.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/socionext,uniphier-uart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier UART controller + +maintainers: + - Masahiro Yamada <[email protected]> + +properties: + compatible: + const: socionext,uniphier-uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + + auto-flow-control: + description: enable automatic flow control support. + $ref: /schemas/types.yaml#/definitions/flag + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + aliases { + serial0 = &serial0; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + }; diff --git a/Documentation/devicetree/bindings/serial/uniphier-uart.txt b/Documentation/devicetree/bindings/serial/uniphier-uart.txt deleted file mode 100644 index 7a1bf02bb869..000000000000 --- a/Documentation/devicetree/bindings/serial/uniphier-uart.txt +++ /dev/null @@ -1,22 +0,0 @@ -UniPhier UART controller - -Required properties: -- compatible: should be "socionext,uniphier-uart". -- reg: offset and length of the register set for the device. -- interrupts: a single interrupt specifier. -- clocks: phandle to the input clock. - -Optional properties: --auto-flow-control: enable automatic flow control support. - -Example: - aliases { - serial0 = &serial0; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - }; diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml new file mode 100644 index 000000000000..3cbf2d28a188 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,aips-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX AHB to IP Bridge + +maintainers: + - Peng Fan <[email protected]> + +description: | + This particular peripheral is designed as the bridge between + AHB bus and peripherals with the lower bandwidth IP Slave (IPS) + buses. + +select: + properties: + compatible: + contains: + const: fsl,aips-bus + required: + - compatible + +properties: + compatible: + items: + - const: fsl,aips-bus + - const: simple-bus + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x30000000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; +... diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index 71cf7ba32237..e95ba9373023 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -58,6 +58,8 @@ properties: - const: st,stm32f4x9-fsotg - const: st,stm32f4x9-hsotg - const: st,stm32f7-hsotg + - const: st,stm32mp15-fsotg + - const: st,stm32mp15-hsotg - const: samsung,s3c6400-hsotg reg: @@ -103,6 +105,10 @@ properties: vusb_a-supply: description: phandle to voltage regulator of analog section. + vusb33d-supply: + description: reference to the VBUS and ID sensing comparators supply, in + order to perform OTG operation, used on STM32MP15 SoCs. + dr_mode: enum: [host, peripheral, otg] diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt index 66c394f9e11f..6aae1544f240 100644 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt @@ -78,7 +78,14 @@ Required properties: - ranges: allows valid 1:1 translation between child's address space and parent's address space - clocks: Clock IDs array as required by the controller. - - clock-names: names of clocks correseponding to IDs in the clock property + - clock-names: Names of clocks corresponding to IDs in the clock property. + Following clock names shall be provided for different + compatibles: + - samsung,exynos5250-dwusb3: "usbdrd30", + - samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk", + "phyclk", + - samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk", + "usbdrd30_axius_clk" - vdd10-supply: 1.0V powr supply - vdd33-supply: 3.0V/3.3V power supply diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 9e67944bec9c..fcdda587def5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -469,6 +469,8 @@ patternProperties: description: Intersil "^issi,.*": description: Integrated Silicon Solutions Inc. + "^ite,.*": + description: ITE Tech, Inc. "^itead,.*": description: ITEAD Intelligent Systems Co.Ltd "^iwave,.*": @@ -545,6 +547,8 @@ patternProperties: description: LinkSprite Technologies, Inc. "^linksys,.*": description: Belkin International, Inc. (Linksys) + "^linutronix,.*": + description: Linutronix GmbH "^linux,.*": description: Linux-specific binding "^linx,.*": @@ -727,6 +731,8 @@ patternProperties: description: OmniVision Technologies "^oxsemi,.*": description: Oxford Semiconductor, Ltd. + "^ozzmaker,.*": + description: OzzMaker "^panasonic,.*": description: Panasonic Corporation "^parade,.*": @@ -761,6 +767,8 @@ patternProperties: description: Broadcom Corporation (formerly PLX Technology) "^pni,.*": description: PNI Sensor Corporation + "^pocketbook,.*": + description: PocketBook International SA "^polaroid,.*": description: Polaroid Corporation "^portwell,.*": @@ -1052,6 +1060,8 @@ patternProperties: description: Vision Optical Technology Co., Ltd. "^vxt,.*": description: VXT Ltd + "^waveshare,.*": + description: Waveshare Electronics "^wd,.*": description: Western Digital Corp. "^wetek,.*": @@ -1078,6 +1088,8 @@ patternProperties: description: X-Powers "^xes,.*": description: Extreme Engineering Solutions (X-ES) + "^xiaomi,.*": + description: Xiaomi Technology Co., Ltd. "^xillybus,.*": description: Xillybus Ltd. "^xinpeng,.*": diff --git a/MAINTAINERS b/MAINTAINERS index 38fe2f3f7b6f..c3800f3b5e6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2546,9 +2546,9 @@ M: Masahiro Yamada <[email protected]> L: [email protected] (moderated for non-subscribers) T: git git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git S: Maintained -F: Documentation/devicetree/bindings/arm/socionext/uniphier.txt -F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt -F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt +F: Documentation/devicetree/bindings/arm/socionext/uniphier.yaml +F: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml +F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml F: arch/arm/boot/dts/uniphier* F: arch/arm/include/asm/hardware/cache-uniphier.h F: arch/arm/mach-uniphier/ @@ -12418,7 +12418,6 @@ F: Documentation/ABI/testing/sysfs-firmware-ofw OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS M: Rob Herring <[email protected]> -M: Mark Rutland <[email protected]> T: git git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git Q: http://patchwork.ozlabs.org/project/devicetree-bindings/list/ diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c index 6bd610ee2cd7..1a84bc0d5fa8 100644 --- a/drivers/of/of_reserved_mem.c +++ b/drivers/of/of_reserved_mem.c @@ -22,7 +22,7 @@ #include <linux/slab.h> #include <linux/memblock.h> -#define MAX_RESERVED_REGIONS 32 +#define MAX_RESERVED_REGIONS 64 static struct reserved_mem reserved_mem[MAX_RESERVED_REGIONS]; static int reserved_mem_count; diff --git a/drivers/of/property.c b/drivers/of/property.c index e851c57a15b0..d977c11decda 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1204,6 +1204,8 @@ DEFINE_SIMPLE_PROP(mboxes, "mboxes", "#mbox-cells") DEFINE_SIMPLE_PROP(io_channels, "io-channel", "#io-channel-cells") DEFINE_SIMPLE_PROP(interrupt_parent, "interrupt-parent", NULL) DEFINE_SIMPLE_PROP(dmas, "dmas", "#dma-cells") +DEFINE_SIMPLE_PROP(power_domains, "power-domains", "#power-domain-cells") +DEFINE_SIMPLE_PROP(hwlocks, "hwlocks", "#hwlock-cells") DEFINE_SUFFIX_PROP(regulators, "-supply", NULL) DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells") DEFINE_SUFFIX_PROP(gpios, "-gpios", "#gpio-cells") @@ -1226,6 +1228,8 @@ static const struct supplier_bindings of_supplier_bindings[] = { { .parse_prop = parse_io_channels, }, { .parse_prop = parse_interrupt_parent, }, { .parse_prop = parse_dmas, }, + { .parse_prop = parse_power_domains, }, + { .parse_prop = parse_hwlocks, }, { .parse_prop = parse_regulators, }, { .parse_prop = parse_gpio, }, { .parse_prop = parse_gpios, }, diff --git a/drivers/of/unittest-data/Makefile b/drivers/of/unittest-data/Makefile index 9b6807065827..009f4045c8e4 100644 --- a/drivers/of/unittest-data/Makefile +++ b/drivers/of/unittest-data/Makefile @@ -21,7 +21,13 @@ obj-$(CONFIG_OF_OVERLAY) += overlay.dtb.o \ overlay_bad_add_dup_prop.dtb.o \ overlay_bad_phandle.dtb.o \ overlay_bad_symbol.dtb.o \ - overlay_base.dtb.o + overlay_base.dtb.o \ + overlay_gpio_01.dtb.o \ + overlay_gpio_02a.dtb.o \ + overlay_gpio_02b.dtb.o \ + overlay_gpio_03.dtb.o \ + overlay_gpio_04a.dtb.o \ + overlay_gpio_04b.dtb.o # enable creation of __symbols__ node DTC_FLAGS_overlay += -@ diff --git a/drivers/of/unittest-data/overlay_gpio_01.dts b/drivers/of/unittest-data/overlay_gpio_01.dts new file mode 100644 index 000000000000..699ff104ae10 --- /dev/null +++ b/drivers/of/unittest-data/overlay_gpio_01.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +&unittest_test_bus { + #address-cells = <1>; + #size-cells = <0>; + gpio@0 { + compatible = "unittest-gpio"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <2>; + gpio-line-names = "line-A", "line-B"; + + line-b { + gpio-hog; + gpios = <2 0>; + input; + line-name = "line-B-input"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_gpio_02a.dts b/drivers/of/unittest-data/overlay_gpio_02a.dts new file mode 100644 index 000000000000..ec59aff6ed47 --- /dev/null +++ b/drivers/of/unittest-data/overlay_gpio_02a.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +&unittest_test_bus { + #address-cells = <1>; + #size-cells = <0>; + gpio@2 { + compatible = "unittest-gpio"; + reg = <2>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <2>; + gpio-line-names = "line-A", "line-B"; + }; +}; diff --git a/drivers/of/unittest-data/overlay_gpio_02b.dts b/drivers/of/unittest-data/overlay_gpio_02b.dts new file mode 100644 index 000000000000..43ce111d41ce --- /dev/null +++ b/drivers/of/unittest-data/overlay_gpio_02b.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +&unittest_test_bus { + #address-cells = <1>; + #size-cells = <0>; + gpio@2 { + line-a { + gpio-hog; + gpios = <1 0>; + input; + line-name = "line-A-input"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_gpio_03.dts b/drivers/of/unittest-data/overlay_gpio_03.dts new file mode 100644 index 000000000000..6e0312340a1b --- /dev/null +++ b/drivers/of/unittest-data/overlay_gpio_03.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +&unittest_test_bus { + #address-cells = <1>; + #size-cells = <0>; + gpio@3 { + compatible = "unittest-gpio"; + reg = <3>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <2>; + gpio-line-names = "line-A", "line-B", "line-C", "line-D"; + + line-d { + gpio-hog; + gpios = <4 0>; + input; + line-name = "line-D-input"; + }; + }; +}; diff --git a/drivers/of/unittest-data/overlay_gpio_04a.dts b/drivers/of/unittest-data/overlay_gpio_04a.dts new file mode 100644 index 000000000000..7b1e04ebfa7a --- /dev/null +++ b/drivers/of/unittest-data/overlay_gpio_04a.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +&unittest_test_bus { + #address-cells = <1>; + #size-cells = <0>; + gpio@4 { + compatible = "unittest-gpio"; + reg = <4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <2>; + gpio-line-names = "line-A", "line-B", "line-C", "line-D"; + }; +}; diff --git a/drivers/of/unittest-data/overlay_gpio_04b.dts b/drivers/of/unittest-data/overlay_gpio_04b.dts new file mode 100644 index 000000000000..a14e95c6699a --- /dev/null +++ b/drivers/of/unittest-data/overlay_gpio_04b.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +&unittest_test_bus { + #address-cells = <1>; + #size-cells = <0>; + gpio@4 { + line-c { + gpio-hog; + gpios = <3 0>; + input; + line-name = "line-C-input"; + }; + }; +}; diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 68b87587b2ef..96ae8a762a9e 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -24,6 +24,7 @@ #include <linux/i2c.h> #include <linux/i2c-mux.h> +#include <linux/gpio/driver.h> #include <linux/bitops.h> @@ -46,6 +47,100 @@ static struct unittest_results { failed; \ }) +/* + * Expected message may have a message level other than KERN_INFO. + * Print the expected message only if the current loglevel will allow + * the actual message to print. + * + * Do not use EXPECT_BEGIN() or EXPECT_END() for messages generated by + * pr_debug(). + */ +#define EXPECT_BEGIN(level, fmt, ...) \ + printk(level pr_fmt("EXPECT \\ : ") fmt, ##__VA_ARGS__) + +#define EXPECT_END(level, fmt, ...) \ + printk(level pr_fmt("EXPECT / : ") fmt, ##__VA_ARGS__) + +struct unittest_gpio_dev { + struct gpio_chip chip; +}; + +static int unittest_gpio_chip_request_count; +static int unittest_gpio_probe_count; +static int unittest_gpio_probe_pass_count; + +static int unittest_gpio_chip_request(struct gpio_chip *chip, unsigned int offset) +{ + unittest_gpio_chip_request_count++; + + pr_debug("%s(): %s %d %d\n", __func__, chip->label, offset, + unittest_gpio_chip_request_count); + return 0; +} + +static int unittest_gpio_probe(struct platform_device *pdev) +{ + struct unittest_gpio_dev *devptr; + int ret; + + unittest_gpio_probe_count++; + + devptr = kzalloc(sizeof(*devptr), GFP_KERNEL); + if (!devptr) + return -ENOMEM; + + platform_set_drvdata(pdev, devptr); + + devptr->chip.of_node = pdev->dev.of_node; + devptr->chip.label = "of-unittest-gpio"; + devptr->chip.base = -1; /* dynamic allocation */ + devptr->chip.ngpio = 5; + devptr->chip.request = unittest_gpio_chip_request; + + ret = gpiochip_add_data(&devptr->chip, NULL); + + unittest(!ret, + "gpiochip_add_data() for node @%pOF failed, ret = %d\n", devptr->chip.of_node, ret); + + if (!ret) + unittest_gpio_probe_pass_count++; + return ret; +} + +static int unittest_gpio_remove(struct platform_device *pdev) +{ + struct unittest_gpio_dev *gdev = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + + dev_dbg(dev, "%s for node @%pOF\n", __func__, np); + + if (!gdev) + return -EINVAL; + + if (gdev->chip.base != -1) + gpiochip_remove(&gdev->chip); + + platform_set_drvdata(pdev, NULL); + kfree(pdev); + + return 0; +} + +static const struct of_device_id unittest_gpio_id[] = { + { .compatible = "unittest-gpio", }, + {} +}; + +static struct platform_driver unittest_gpio_driver = { + .probe = unittest_gpio_probe, + .remove = unittest_gpio_remove, + .driver = { + .name = "unittest-gpio", + .of_match_table = of_match_ptr(unittest_gpio_id), + }, +}; + static void __init of_unittest_find_node_by_name(void) { struct device_node *np; @@ -444,29 +539,77 @@ static void __init of_unittest_parse_phandle_with_args(void) /* Check for missing cells property */ memset(&args, 0, sizeof(args)); + + EXPECT_BEGIN(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: could not get #phandle-cells-missing for /testcase-data/phandle-tests/provider1"); + rc = of_parse_phandle_with_args(np, "phandle-list", "#phandle-cells-missing", 0, &args); + + EXPECT_END(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: could not get #phandle-cells-missing for /testcase-data/phandle-tests/provider1"); + unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc); + + EXPECT_BEGIN(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: could not get #phandle-cells-missing for /testcase-data/phandle-tests/provider1"); + rc = of_count_phandle_with_args(np, "phandle-list", "#phandle-cells-missing"); + + EXPECT_END(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: could not get #phandle-cells-missing for /testcase-data/phandle-tests/provider1"); + unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc); /* Check for bad phandle in list */ memset(&args, 0, sizeof(args)); + + EXPECT_BEGIN(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: could not find phandle"); + rc = of_parse_phandle_with_args(np, "phandle-list-bad-phandle", "#phandle-cells", 0, &args); + + EXPECT_END(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: could not find phandle"); + unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc); + + EXPECT_BEGIN(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: could not find phandle"); + rc = of_count_phandle_with_args(np, "phandle-list-bad-phandle", "#phandle-cells"); + + EXPECT_END(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: could not find phandle"); + unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc); /* Check for incorrectly formed argument list */ memset(&args, 0, sizeof(args)); + + EXPECT_BEGIN(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: #phandle-cells = 3 found -1"); + rc = of_parse_phandle_with_args(np, "phandle-list-bad-args", "#phandle-cells", 1, &args); + + EXPECT_END(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: #phandle-cells = 3 found -1"); + unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc); + + EXPECT_BEGIN(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: #phandle-cells = 3 found -1"); + rc = of_count_phandle_with_args(np, "phandle-list-bad-args", "#phandle-cells"); + + EXPECT_END(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-a: #phandle-cells = 3 found -1"); + unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc); } @@ -577,20 +720,41 @@ static void __init of_unittest_parse_phandle_with_args_map(void) /* Check for missing cells,map,mask property */ memset(&args, 0, sizeof(args)); + + EXPECT_BEGIN(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-b: could not get #phandle-missing-cells for /testcase-data/phandle-tests/provider1"); + rc = of_parse_phandle_with_args_map(np, "phandle-list", "phandle-missing", 0, &args); + EXPECT_END(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-b: could not get #phandle-missing-cells for /testcase-data/phandle-tests/provider1"); + unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc); /* Check for bad phandle in list */ memset(&args, 0, sizeof(args)); + + EXPECT_BEGIN(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-b: could not find phandle"); + rc = of_parse_phandle_with_args_map(np, "phandle-list-bad-phandle", "phandle", 0, &args); + EXPECT_END(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-b: could not find phandle"); + unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc); /* Check for incorrectly formed argument list */ memset(&args, 0, sizeof(args)); + + EXPECT_BEGIN(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-b: #phandle-cells = 2 found -1"); + rc = of_parse_phandle_with_args_map(np, "phandle-list-bad-args", "phandle", 1, &args); + EXPECT_END(KERN_INFO, + "OF: /testcase-data/phandle-tests/consumer-b: #phandle-cells = 2 found -1"); + unittest(rc == -EINVAL, "expected:%i got:%i\n", -EINVAL, rc); } @@ -1121,7 +1285,15 @@ static void __init of_unittest_platform_populate(void) np = of_find_node_by_path("/testcase-data/testcase-device2"); pdev = of_find_device_by_node(np); unittest(pdev, "device 2 creation failed\n"); + + EXPECT_BEGIN(KERN_INFO, + "platform testcase-data:testcase-device2: IRQ index 0 not found"); + irq = platform_get_irq(pdev, 0); + + EXPECT_END(KERN_INFO, + "platform testcase-data:testcase-device2: IRQ index 0 not found"); + unittest(irq < 0 && irq != -EPROBE_DEFER, "device parsing error failed - %d\n", irq); } @@ -1325,6 +1497,9 @@ static int __init unittest_data_add(void) return 0; } + EXPECT_BEGIN(KERN_INFO, + "Duplicate name in testcase-data, renamed to \"duplicate-name#1\""); + /* attach the sub-tree to live tree */ np = unittest_data_node->child; while (np) { @@ -1335,6 +1510,9 @@ static int __init unittest_data_add(void) np = next; } + EXPECT_END(KERN_INFO, + "Duplicate name in testcase-data, renamed to \"duplicate-name#1\""); + of_overlay_mutex_unlock(); return 0; @@ -1677,8 +1855,18 @@ static int __init of_unittest_apply_revert_overlay_check(int overlay_nr, /* test activation of device */ static void __init of_unittest_overlay_0(void) { + int ret; + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest0/status"); + /* device should enable */ - if (of_unittest_apply_overlay_check(0, 0, 0, 1, PDEV_OVERLAY)) + ret = of_unittest_apply_overlay_check(0, 0, 0, 1, PDEV_OVERLAY); + + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest0/status"); + + if (ret) return; unittest(1, "overlay test %d passed\n", 0); @@ -1687,28 +1875,58 @@ static void __init of_unittest_overlay_0(void) /* test deactivation of device */ static void __init of_unittest_overlay_1(void) { + int ret; + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest1/status"); + /* device should disable */ - if (of_unittest_apply_overlay_check(1, 1, 1, 0, PDEV_OVERLAY)) + ret = of_unittest_apply_overlay_check(1, 1, 1, 0, PDEV_OVERLAY); + + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest1/status"); + + if (ret) return; unittest(1, "overlay test %d passed\n", 1); + } /* test activation of device */ static void __init of_unittest_overlay_2(void) { + int ret; + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest2/status"); + /* device should enable */ - if (of_unittest_apply_overlay_check(2, 2, 0, 1, PDEV_OVERLAY)) - return; + ret = of_unittest_apply_overlay_check(2, 2, 0, 1, PDEV_OVERLAY); + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest2/status"); + + if (ret) + return; unittest(1, "overlay test %d passed\n", 2); } /* test deactivation of device */ static void __init of_unittest_overlay_3(void) { + int ret; + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest3/status"); + /* device should disable */ - if (of_unittest_apply_overlay_check(3, 3, 1, 0, PDEV_OVERLAY)) + ret = of_unittest_apply_overlay_check(3, 3, 1, 0, PDEV_OVERLAY); + + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest3/status"); + + if (ret) return; unittest(1, "overlay test %d passed\n", 3); @@ -1727,8 +1945,18 @@ static void __init of_unittest_overlay_4(void) /* test overlay apply/revert sequence */ static void __init of_unittest_overlay_5(void) { + int ret; + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest5/status"); + /* device should disable */ - if (of_unittest_apply_revert_overlay_check(5, 5, 0, 1, PDEV_OVERLAY)) + ret = of_unittest_apply_revert_overlay_check(5, 5, 0, 1, PDEV_OVERLAY); + + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest5/status"); + + if (ret) return; unittest(1, "overlay test %d passed\n", 5); @@ -1742,6 +1970,8 @@ static void __init of_unittest_overlay_6(void) int before = 0, after = 1; const char *overlay_name; + int ret; + /* unittest device must be in before state */ for (i = 0; i < 2; i++) { if (of_unittest_device_exists(unittest_nr + i, PDEV_OVERLAY) @@ -1756,18 +1986,41 @@ static void __init of_unittest_overlay_6(void) } /* apply the overlays */ - for (i = 0; i < 2; i++) { - overlay_name = overlay_name_from_nr(overlay_nr + i); + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest6/status"); + + overlay_name = overlay_name_from_nr(overlay_nr + 0); - if (!overlay_data_apply(overlay_name, &ovcs_id)) { - unittest(0, "could not apply overlay \"%s\"\n", - overlay_name); + ret = overlay_data_apply(overlay_name, &ovcs_id); + + if (!ret) { + unittest(0, "could not apply overlay \"%s\"\n", overlay_name); + return; + } + ov_id[0] = ovcs_id; + of_unittest_track_overlay(ov_id[0]); + + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest6/status"); + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest7/status"); + + overlay_name = overlay_name_from_nr(overlay_nr + 1); + + ret = overlay_data_apply(overlay_name, &ovcs_id); + + if (!ret) { + unittest(0, "could not apply overlay \"%s\"\n", overlay_name); return; - } - ov_id[i] = ovcs_id; - of_unittest_track_overlay(ov_id[i]); } + ov_id[1] = ovcs_id; + of_unittest_track_overlay(ov_id[1]); + + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest7/status"); + for (i = 0; i < 2; i++) { /* unittest device must be in after state */ @@ -1808,6 +2061,7 @@ static void __init of_unittest_overlay_6(void) } unittest(1, "overlay test %d passed\n", 6); + } /* test overlay application in sequence */ @@ -1816,26 +2070,65 @@ static void __init of_unittest_overlay_8(void) int i, ov_id[2], ovcs_id; int overlay_nr = 8, unittest_nr = 8; const char *overlay_name; + int ret; /* we don't care about device state in this test */ + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest8/status"); + + overlay_name = overlay_name_from_nr(overlay_nr + 0); + + ret = overlay_data_apply(overlay_name, &ovcs_id); + if (!ret) + unittest(0, "could not apply overlay \"%s\"\n", overlay_name); + + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest8/status"); + + if (!ret) + return; + + ov_id[0] = ovcs_id; + of_unittest_track_overlay(ov_id[0]); + + overlay_name = overlay_name_from_nr(overlay_nr + 1); + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest8/property-foo"); + /* apply the overlays */ - for (i = 0; i < 2; i++) { + ret = overlay_data_apply(overlay_name, &ovcs_id); - overlay_name = overlay_name_from_nr(overlay_nr + i); + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/test-unittest8/property-foo"); - if (!overlay_data_apply(overlay_name, &ovcs_id)) { - unittest(0, "could not apply overlay \"%s\"\n", - overlay_name); - return; - } - ov_id[i] = ovcs_id; - of_unittest_track_overlay(ov_id[i]); + if (!ret) { + unittest(0, "could not apply overlay \"%s\"\n", overlay_name); + return; } + ov_id[1] = ovcs_id; + of_unittest_track_overlay(ov_id[1]); + /* now try to remove first overlay (it should fail) */ ovcs_id = ov_id[0]; - if (!of_overlay_remove(&ovcs_id)) { + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: node_overlaps_later_cs: #6 overlaps with #7 @/testcase-data/overlay-node/test-bus/test-unittest8"); + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: overlay #6 is not topmost"); + + ret = of_overlay_remove(&ovcs_id); + + EXPECT_END(KERN_INFO, + "OF: overlay: overlay #6 is not topmost"); + + EXPECT_END(KERN_INFO, + "OF: overlay: node_overlaps_later_cs: #6 overlaps with #7 @/testcase-data/overlay-node/test-bus/test-unittest8"); + + if (!ret) { unittest(0, "%s was destroyed @\"%s\"\n", overlay_name_from_nr(overlay_nr + 0), unittest_path(unittest_nr, @@ -1867,6 +2160,7 @@ static void __init of_unittest_overlay_10(void) /* device should disable */ ret = of_unittest_apply_overlay_check(10, 10, 0, 1, PDEV_OVERLAY); + if (unittest(ret == 0, "overlay test %d failed; overlay application\n", 10)) return; @@ -1890,6 +2184,7 @@ static void __init of_unittest_overlay_11(void) /* device should disable */ ret = of_unittest_apply_revert_overlay_check(11, 11, 0, 1, PDEV_OVERLAY); + unittest(ret == 0, "overlay test %d failed; overlay apply\n", 11); } @@ -2120,12 +2415,21 @@ static int of_unittest_overlay_i2c_init(void) return ret; ret = platform_driver_register(&unittest_i2c_bus_driver); + if (unittest(ret == 0, "could not register unittest i2c bus driver\n")) return ret; #if IS_BUILTIN(CONFIG_I2C_MUX) + + EXPECT_BEGIN(KERN_INFO, + "i2c i2c-1: Added multiplexed i2c bus 2"); + ret = i2c_add_driver(&unittest_i2c_mux_driver); + + EXPECT_END(KERN_INFO, + "i2c i2c-1: Added multiplexed i2c bus 2"); + if (unittest(ret == 0, "could not register unittest i2c mux driver\n")) return ret; @@ -2145,8 +2449,18 @@ static void of_unittest_overlay_i2c_cleanup(void) static void __init of_unittest_overlay_i2c_12(void) { + int ret; + /* device should enable */ - if (of_unittest_apply_overlay_check(12, 12, 0, 1, I2C_OVERLAY)) + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest12/status"); + + ret = of_unittest_apply_overlay_check(12, 12, 0, 1, I2C_OVERLAY); + + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest12/status"); + + if (ret) return; unittest(1, "overlay test %d passed\n", 12); @@ -2155,8 +2469,18 @@ static void __init of_unittest_overlay_i2c_12(void) /* test deactivation of device */ static void __init of_unittest_overlay_i2c_13(void) { + int ret; + + EXPECT_BEGIN(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest13/status"); + /* device should disable */ - if (of_unittest_apply_overlay_check(13, 13, 1, 0, I2C_OVERLAY)) + ret = of_unittest_apply_overlay_check(13, 13, 1, 0, I2C_OVERLAY); + + EXPECT_END(KERN_INFO, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data/overlay-node/test-bus/i2c-test-bus/test-unittest13/status"); + + if (ret) return; unittest(1, "overlay test %d passed\n", 13); @@ -2169,8 +2493,18 @@ static void of_unittest_overlay_i2c_14(void) static void __init of_unittest_overlay_i2c_15(void) { + int ret; + /* device should enable */ - if (of_unittest_apply_overlay_check(15, 15, 0, 1, I2C_OVERLAY)) + EXPECT_BEGIN(KERN_INFO, + "i2c i2c-1: Added multiplexed i2c bus 3"); + + ret = of_unittest_apply_overlay_check(15, 15, 0, 1, I2C_OVERLAY); + + EXPECT_END(KERN_INFO, + "i2c i2c-1: Added multiplexed i2c bus 3"); + + if (ret) return; unittest(1, "overlay test %d passed\n", 15); @@ -2183,6 +2517,153 @@ static inline void of_unittest_overlay_i2c_15(void) { } #endif +static void __init of_unittest_overlay_gpio(void) +{ + int chip_request_count; + int probe_pass_count; + int ret; + + /* + * tests: apply overlays before registering driver + * Similar to installing a driver as a module, the + * driver is registered after applying the overlays. + * + * - apply overlay_gpio_01 + * - apply overlay_gpio_02a + * - apply overlay_gpio_02b + * - register driver + * + * register driver will result in + * - probe and processing gpio hog for overlay_gpio_01 + * - probe for overlay_gpio_02a + * - processing gpio for overlay_gpio_02b + */ + + probe_pass_count = unittest_gpio_probe_pass_count; + chip_request_count = unittest_gpio_chip_request_count; + + /* + * overlay_gpio_01 contains gpio node and child gpio hog node + * overlay_gpio_02a contains gpio node + * overlay_gpio_02b contains child gpio hog node + */ + + unittest(overlay_data_apply("overlay_gpio_01", NULL), + "Adding overlay 'overlay_gpio_01' failed\n"); + + unittest(overlay_data_apply("overlay_gpio_02a", NULL), + "Adding overlay 'overlay_gpio_02a' failed\n"); + + unittest(overlay_data_apply("overlay_gpio_02b", NULL), + "Adding overlay 'overlay_gpio_02b' failed\n"); + + /* + * messages are the result of the probes, after the + * driver is registered + */ + + EXPECT_BEGIN(KERN_INFO, + "GPIO line <<int>> (line-B-input) hogged as input\n"); + + EXPECT_BEGIN(KERN_INFO, + "GPIO line <<int>> (line-A-input) hogged as input\n"); + + ret = platform_driver_register(&unittest_gpio_driver); + if (unittest(ret == 0, "could not register unittest gpio driver\n")) + return; + + EXPECT_END(KERN_INFO, + "GPIO line <<int>> (line-A-input) hogged as input\n"); + EXPECT_END(KERN_INFO, + "GPIO line <<int>> (line-B-input) hogged as input\n"); + + unittest(probe_pass_count + 2 == unittest_gpio_probe_pass_count, + "unittest_gpio_probe() failed or not called\n"); + + unittest(chip_request_count + 2 == unittest_gpio_chip_request_count, + "unittest_gpio_chip_request() called %d times (expected 1 time)\n", + unittest_gpio_chip_request_count - chip_request_count); + + /* + * tests: apply overlays after registering driver + * + * Similar to a driver built-in to the kernel, the + * driver is registered before applying the overlays. + * + * overlay_gpio_03 contains gpio node and child gpio hog node + * + * - apply overlay_gpio_03 + * + * apply overlay will result in + * - probe and processing gpio hog. + */ + + probe_pass_count = unittest_gpio_probe_pass_count; + chip_request_count = unittest_gpio_chip_request_count; + + EXPECT_BEGIN(KERN_INFO, + "GPIO line <<int>> (line-D-input) hogged as input\n"); + + /* overlay_gpio_03 contains gpio node and child gpio hog node */ + + unittest(overlay_data_apply("overlay_gpio_03", NULL), + "Adding overlay 'overlay_gpio_03' failed\n"); + + EXPECT_END(KERN_INFO, + "GPIO line <<int>> (line-D-input) hogged as input\n"); + + unittest(probe_pass_count + 1 == unittest_gpio_probe_pass_count, + "unittest_gpio_probe() failed or not called\n"); + + unittest(chip_request_count + 1 == unittest_gpio_chip_request_count, + "unittest_gpio_chip_request() called %d times (expected 1 time)\n", + unittest_gpio_chip_request_count - chip_request_count); + + /* + * overlay_gpio_04a contains gpio node + * + * - apply overlay_gpio_04a + * + * apply the overlay will result in + * - probe for overlay_gpio_04a + */ + + probe_pass_count = unittest_gpio_probe_pass_count; + chip_request_count = unittest_gpio_chip_request_count; + + /* overlay_gpio_04a contains gpio node */ + + unittest(overlay_data_apply("overlay_gpio_04a", NULL), + "Adding overlay 'overlay_gpio_04a' failed\n"); + + unittest(probe_pass_count + 1 == unittest_gpio_probe_pass_count, + "unittest_gpio_probe() failed or not called\n"); + + /* + * overlay_gpio_04b contains child gpio hog node + * + * - apply overlay_gpio_04b + * + * apply the overlay will result in + * - processing gpio for overlay_gpio_04b + */ + + EXPECT_BEGIN(KERN_INFO, + "GPIO line <<int>> (line-C-input) hogged as input\n"); + + /* overlay_gpio_04b contains child gpio hog node */ + + unittest(overlay_data_apply("overlay_gpio_04b", NULL), + "Adding overlay 'overlay_gpio_04b' failed\n"); + + EXPECT_END(KERN_INFO, + "GPIO line <<int>> (line-C-input) hogged as input\n"); + + unittest(chip_request_count + 1 == unittest_gpio_chip_request_count, + "unittest_gpio_chip_request() called %d times (expected 1 time)\n", + unittest_gpio_chip_request_count - chip_request_count); +} + static void __init of_unittest_overlay(void) { struct device_node *bus_np = NULL; @@ -2242,6 +2723,8 @@ static void __init of_unittest_overlay(void) of_unittest_overlay_i2c_cleanup(); #endif + of_unittest_overlay_gpio(); + of_unittest_destroy_tracked_overlays(); out: @@ -2295,6 +2778,12 @@ OVERLAY_INFO_EXTERN(overlay_11); OVERLAY_INFO_EXTERN(overlay_12); OVERLAY_INFO_EXTERN(overlay_13); OVERLAY_INFO_EXTERN(overlay_15); +OVERLAY_INFO_EXTERN(overlay_gpio_01); +OVERLAY_INFO_EXTERN(overlay_gpio_02a); +OVERLAY_INFO_EXTERN(overlay_gpio_02b); +OVERLAY_INFO_EXTERN(overlay_gpio_03); +OVERLAY_INFO_EXTERN(overlay_gpio_04a); +OVERLAY_INFO_EXTERN(overlay_gpio_04b); OVERLAY_INFO_EXTERN(overlay_bad_add_dup_node); OVERLAY_INFO_EXTERN(overlay_bad_add_dup_prop); OVERLAY_INFO_EXTERN(overlay_bad_phandle); @@ -2319,6 +2808,12 @@ static struct overlay_info overlays[] = { OVERLAY_INFO(overlay_12, 0), OVERLAY_INFO(overlay_13, 0), OVERLAY_INFO(overlay_15, 0), + OVERLAY_INFO(overlay_gpio_01, 0), + OVERLAY_INFO(overlay_gpio_02a, 0), + OVERLAY_INFO(overlay_gpio_02b, 0), + OVERLAY_INFO(overlay_gpio_03, 0), + OVERLAY_INFO(overlay_gpio_04a, 0), + OVERLAY_INFO(overlay_gpio_04b, 0), OVERLAY_INFO(overlay_bad_add_dup_node, -EINVAL), OVERLAY_INFO(overlay_bad_add_dup_prop, -EINVAL), OVERLAY_INFO(overlay_bad_phandle, -EINVAL), @@ -2470,6 +2965,7 @@ static __init void of_unittest_overlay_high_level(void) struct device_node *overlay_base_symbols; struct device_node **pprev; struct property *prop; + int ret; if (!overlay_base_root) { unittest(0, "overlay_base_root not initialized\n"); @@ -2584,15 +3080,86 @@ static __init void of_unittest_overlay_high_level(void) /* now do the normal overlay usage test */ - unittest(overlay_data_apply("overlay", NULL), - "Adding overlay 'overlay' failed\n"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/substation@100/status"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/fairway-1/status"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/fairway-1/ride@100/track@30/incline-up"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/fairway-1/ride@100/track@40/incline-up"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/lights@40000/status"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/lights@40000/color"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/lights@40000/rate"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/hvac_2"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ride_200"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ride_200_left"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ride_200_right"); + + ret = overlay_data_apply("overlay", NULL); + + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ride_200_right"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ride_200_left"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/ride_200"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /__symbols__/hvac_2"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/lights@40000/rate"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/lights@40000/color"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/lights@40000/status"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/fairway-1/ride@100/track@40/incline-up"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/fairway-1/ride@100/track@30/incline-up"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/fairway-1/status"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/substation@100/status"); + + unittest(ret, "Adding overlay 'overlay' failed\n"); + + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: ERROR: multiple fragments add and/or delete node /testcase-data-2/substation@100/motor-1/controller"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/controller/name"); unittest(overlay_data_apply("overlay_bad_add_dup_node", NULL), "Adding overlay 'overlay_bad_add_dup_node' failed\n"); + EXPECT_END(KERN_ERR, + "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/controller/name"); + EXPECT_END(KERN_ERR, + "OF: overlay: ERROR: multiple fragments add and/or delete node /testcase-data-2/substation@100/motor-1/controller"); + + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/substation@100/motor-1/rpm_avail"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/substation@100/motor-1/rpm_avail"); + EXPECT_BEGIN(KERN_ERR, + "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/rpm_avail"); + unittest(overlay_data_apply("overlay_bad_add_dup_prop", NULL), "Adding overlay 'overlay_bad_add_dup_prop' failed\n"); + EXPECT_END(KERN_ERR, + "OF: overlay: ERROR: multiple fragments add, update, and/or delete property /testcase-data-2/substation@100/motor-1/rpm_avail"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/substation@100/motor-1/rpm_avail"); + EXPECT_END(KERN_ERR, + "OF: overlay: WARNING: memory leak will occur if overlay removed, property: /testcase-data-2/substation@100/motor-1/rpm_avail"); + unittest(overlay_data_apply("overlay_bad_phandle", NULL), "Adding overlay 'overlay_bad_phandle' failed\n"); @@ -2616,6 +3183,8 @@ static int __init of_unittest(void) struct device_node *np; int res; + pr_info("start of unittest - you will see error messages\n"); + /* adding data for unittest */ if (IS_ENABLED(CONFIG_UML)) @@ -2634,7 +3203,6 @@ static int __init of_unittest(void) } of_node_put(np); - pr_info("start of unittest - you will see error messages\n"); of_unittest_check_tree_linkage(); of_unittest_check_phandles(); of_unittest_find_node_by_name(); |