diff options
26 files changed, 2001 insertions, 3507 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt new file mode 100644 index 000000000000..fb87c7d74f2e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt @@ -0,0 +1,178 @@ +Actions Semi S900 Pin Controller + +This binding describes the pin controller found in the S900 SoC. + +Required Properties: + +- compatible: Should be "actions,s900-pinctrl" +- reg: Should contain the register base address and size of + the pin controller. +- clocks: phandle of the clock feeding the pin controller + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Pinmux functions are available only for the pin groups while pinconf +parameters are available for both pin groups and individual pins. + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +Required Properties: + +- pins: An array of strings, each string containing the name of a pin. + These pins are used for selecting the pull control and schmitt + trigger parameters. The following are the list of pins + available: + + eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, + eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, + sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0, + i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5, + eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, + lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, + lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, + lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, + lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, + sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1, + sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, + uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, + uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx, + uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, + i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1, + csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3, + csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, + dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, + csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, + sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, + nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs, + nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1, + nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2, + nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs, + nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1, + nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3 + +- groups: An array of strings, each string containing the name of a pin + group. These pin groups are used for selecting the pinmux + functions. + + lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, + sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, + rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, + rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, + i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, + pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, + eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp, + eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp, + lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp, + spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, + uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, + sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp, + uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp, + csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp, + dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, + nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, + csi1_dn0_dp0_mfp, uart4_rx_tx_mfp + + + These pin groups are used for selecting the drive strength + parameters. + + sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, + rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv, + rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv, + sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv, + i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv, + lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, + sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, + spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, + uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv + + These pin groups are used for selecting the slew rate + parameters. + + sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, + rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, + rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, + i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, + pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, + spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, + uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, + sensor0_sr + +- function: An array of strings, each string containing the name of the + pinmux functions. These functions can only be selected by + the corresponding pin groups. The following are the list of + pinmux functions available: + + eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, + pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, + sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, + usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, + nand1, spdif, sirq0, sirq1, sirq2 + +Optional Properties: + +- bias-bus-hold: No arguments. The specified pins should retain the previous + state value. +- bias-high-impedance: No arguments. The specified pins should be configured + as high impedance. +- bias-pull-down: No arguments. The specified pins should be configured as + pull down. +- bias-pull-up: No arguments. The specified pins should be configured as + pull up. +- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified + pins +- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified + pins +- slew-rate: Integer. Sets slew rate for the specified pins. + Valid values are: + <0> - Slow + <1> - Fast +- drive-strength: Integer. Selects the drive strength for the specified + pins in mA. + Valid values are: + <2> + <4> + <8> + <12> + +Example: + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s900-pinctrl"; + reg = <0x0 0xe01b0000 0x0 0x1000>; + clocks = <&cmu CLK_GPIO>; + + uart2-default: uart2-default { + pinmux { + groups = "lvds_oep_odn_mfp"; + function = "uart2"; + }; + pinconf { + groups = "lvds_oep_odn_drv"; + drive-strength = <12>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt index 47284f85ec80..678f5097058e 100644 --- a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt @@ -19,8 +19,10 @@ Required subnode-properties: Available functions and groups (function: group0, group1...): gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0, i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0, - spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0, - uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0 + spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2, + uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2, + uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1, + uart5nocts cpuclkout: cpuclkoutgrp0 udlclkout: udlclkoutgrp0 i2c1: i2c1grp0 @@ -32,12 +34,12 @@ Required subnode-properties: spi0: spi0grp0 spi1: spi1grp0 pciedebug: pciedebuggrp0 - uart0: uart0grp0, uart0grp1 - uart1: uart1grp0 - uart2: uart2grp0, uart2grp1 + uart0: uart0grp0, uart0grp1, uart0grp2 + uart1: uart1grp0, uart1grp1 + uart2: uart2grp0, uart2grp1, uart2grp2 uart3: uart3grp0 - uart4: uart4grp0 - uart5: uart5grp0 + uart4: uart4grp0, uart4grp1 + uart5: uart5grp0, uart5grp1, uart5nocts nand: nandgrp0 sdio0: sdio0grp0 sdio1: sdio1grp0 diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt deleted file mode 100644 index cf9ccdff4455..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pdc-pinctrl.txt +++ /dev/null @@ -1,127 +0,0 @@ -ImgTec TZ1090 PDC pin controller - -Required properties: -- compatible: "img,tz1090-pdc-pinctrl" -- reg: Should contain the register physical address and length of the - SOC_GPIO_CONTROL registers in the PDC register region. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -TZ1090-PDC's pin configuration nodes act as a container for an arbitrary number -of subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. For this reason, even seemingly boolean -values are actually tristates in this binding: unspecified, off, or on. -Unspecified is represented as an absent property, and off/on are represented as -integer values 0 and 1. - -Required subnode-properties: -- tz1090,pins : An array of strings. Each string contains the name of a pin or - group. Valid values for these names are listed below. - -Optional subnode-properties: -- tz1090,function: A string containing the name of the function to mux to the - pin or group. Valid values for function names are listed below, including - which pingroups can be muxed to them. -- supported generic pinconfig properties (for further details see - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt): - - bias-disable - - bias-high-impedance - - bias-bus-hold - - bias-pull-up - - bias-pull-down - - input-schmitt-enable - - input-schmitt-disable - - drive-strength: Integer, control drive strength of pins in mA. - 2: 2mA - 4: 4mA - 8: 8mA - 12: 12mA - - low-power-enable: Flag, power-on-start weak pull-down for invalid power. - - low-power-disable: Flag, power-on-start weak pull-down disabled. - -Note that many of these properties are only valid for certain specific pins -or groups. See the TZ1090 TRM for complete details regarding which groups -support which functionality. The Linux pinctrl driver may also be a useful -reference. - -Valid values for pin and group names are: - - pins: - - These all support bias-high-impediance, bias-pull-up, bias-pull-down, and - bias-bus-hold (which can also be provided to any of the groups below to set - it for all gpio pins in that group). - - gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, ext_power. - - mux groups: - - These all support function. - - gpio0 - pins: gpio0. - function: ir_mod_stable_out. - gpio1 - pins: gpio1. - function: ir_mod_power_out. - - drive groups: - - These support input-schmitt-enable, input-schmitt-disable, - drive-strength, low-power-enable, and low-power-disable. - - pdc - pins: gpio0, gpio1, sys_wake0, sys_wake1, sys_wake2, ir_data, - ext_power. - -Example: - - pinctrl_pdc: pinctrl@2006500 { - #gpio-range-cells = <3>; - compatible = "img,tz1090-pdc-pinctrl"; - reg = <0x02006500 0x100>; - }; - -Example board file extracts: - - &pinctrl_pdc { - pinctrl-names = "default"; - pinctrl-0 = <&syswake_default>; - - syswake_default: syswakes { - syswake_cfg { - tz1090,pins = "sys_wake0", - "sys_wake1", - "sys_wake2"; - pull-up; - }; - }; - irmod_default: irmod { - gpio0_cfg { - tz1090,pins = "gpio0"; - tz1090,function = "ir_mod_stable_out"; - }; - gpio1_cfg { - tz1090,pins = "gpio1"; - tz1090,function = "ir_mod_power_out"; - }; - }; - }; - - ir: ir@2006200 { - pinctrl-names = "default"; - pinctrl-0 = <&irmod_default>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt deleted file mode 100644 index 2dfd9a3fc1e4..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/img,tz1090-pinctrl.txt +++ /dev/null @@ -1,227 +0,0 @@ -ImgTec TZ1090 pin controller - -Required properties: -- compatible: "img,tz1090-pinctrl" -- reg: Should contain the register physical address and length of the pad - configuration registers (CR_PADS_* and CR_IF_CTL0). - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -TZ1090's pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. For this reason, even seemingly boolean -values are actually tristates in this binding: unspecified, off, or on. -Unspecified is represented as an absent property, and off/on are represented as -integer values 0 and 1. - -Required subnode-properties: -- tz1090,pins : An array of strings. Each string contains the name of a pin or - group. Valid values for these names are listed below. - -Optional subnode-properties: -- tz1090,function: A string containing the name of the function to mux to the - pin or group. Valid values for function names are listed below, including - which pingroups can be muxed to them. -- supported generic pinconfig properties (for further details see - Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt): - - bias-disable - - bias-high-impedance - - bias-bus-hold - - bias-pull-up - - bias-pull-down - - input-schmitt-enable - - input-schmitt-disable - - drive-strength: Integer, control drive strength of pins in mA. - 2: 2mA - 4: 4mA - 8: 8mA - 12: 12mA - - -Note that many of these properties are only valid for certain specific pins -or groups. See the TZ1090 TRM for complete details regarding which groups -support which functionality. The Linux pinctrl driver may also be a useful -reference. - -Valid values for pin and group names are: - - gpio pins: - - These all support bias-high-impediance, bias-pull-up, bias-pull-down, and - bias-bus-hold (which can also be provided to any of the groups below to set - it for all pins in that group). - - They also all support the some form of muxing. Any pins which are contained - in one of the mux groups (see below) can be muxed only to the functions - supported by the mux group. All other pins can be muxed to the "perip" - function which enables them with their intended peripheral. - - Different pins in the same mux group cannot be muxed to different functions, - however it is possible to mux only a subset of the pins in a mux group to a - particular function and leave the remaining pins unmuxed. This is useful if - the board connects certain pins in a group to other devices to be controlled - by GPIO, and you don't want the usual peripheral to have any control of the - pin. - - ant_sel0, ant_sel1, gain0, gain1, gain2, gain3, gain4, gain5, gain6, gain7, - i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, i2s_lrclk_out, - i2s_mclk, pa_on, pdm_a, pdm_b, pdm_c, pdm_d, pll_on, rx_hp, rx_on, - scb0_sclk, scb0_sdat, scb1_sclk, scb1_sdat, scb2_sclk, scb2_sdat, sdh_cd, - sdh_clk_in, sdh_wp, sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3, - spi0_cs0, spi0_cs1, spi0_cs2, spi0_din, spi0_dout, spi0_mclk, spi1_cs0, - spi1_cs1, spi1_cs2, spi1_din, spi1_dout, spi1_mclk, tft_blank_ls, tft_blue0, - tft_blue1, tft_blue2, tft_blue3, tft_blue4, tft_blue5, tft_blue6, tft_blue7, - tft_green0, tft_green1, tft_green2, tft_green3, tft_green4, tft_green5, - tft_green6, tft_green7, tft_hsync_nr, tft_panelclk, tft_pwrsave, tft_red0, - tft_red1, tft_red2, tft_red3, tft_red4, tft_red5, tft_red6, tft_red7, - tft_vd12acb, tft_vdden_gd, tft_vsync_ns, tx_on, uart0_cts, uart0_rts, - uart0_rxd, uart0_txd, uart1_rxd, uart1_txd. - - bias-high-impediance: supported. - bias-pull-up: supported. - bias-pull-down: supported. - bias-bus-hold: supported. - function: perip or those supported by pin's mux group. - - other pins: - - These other pins are part of various pin groups below, but can't be - controlled as GPIOs. They do however support bias-high-impediance, - bias-pull-up, bias-pull-down, and bias-bus-hold (which can also be provided - to any of the groups below to set it for all pins in that group). - - clk_out0, clk_out1, tck, tdi, tdo, tms, trst. - - bias-high-impediance: supported. - bias-pull-up: supported. - bias-pull-down: supported. - bias-bus-hold: supported. - - mux groups: - - These all support function, and some support drive configs. - - afe - pins: tx_on, rx_on, pll_on, pa_on, rx_hp, ant_sel0, - ant_sel1, gain0, gain1, gain2, gain3, gain4, - gain5, gain6, gain7. - function: afe, ts_out_0. - input-schmitt-enable: supported. - input-schmitt-disable: supported. - drive-strength: supported. - pdm_d - pins: pdm_d. - function: pdm_dac, usb_vbus. - sdh - pins: sdh_cd, sdh_wp, sdh_clk_in. - function: sdh, sdio. - sdio - pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, - sdio_d3. - function: sdio, sdh. - spi1_cs2 - pins: spi1_cs2. - function: spi1_cs2, usb_vbus. - tft - pins: tft_red0, tft_red1, tft_red2, tft_red3, - tft_red4, tft_red5, tft_red6, tft_red7, - tft_green0, tft_green1, tft_green2, tft_green3, - tft_green4, tft_green5, tft_green6, tft_green7, - tft_blue0, tft_blue1, tft_blue2, tft_blue3, - tft_blue4, tft_blue5, tft_blue6, tft_blue7, - tft_vdden_gd, tft_panelclk, tft_blank_ls, - tft_vsync_ns, tft_hsync_nr, tft_vd12acb, - tft_pwrsave. - function: tft, ext_dac, not_iqadc_stb, iqdac_stb, ts_out_1, - lcd_trace, phy_ringosc. - input-schmitt-enable: supported. - input-schmitt-disable: supported. - drive-strength: supported. - - drive groups: - - These all support input-schmitt-enable, input-schmitt-disable, - and drive-strength. - - jtag - pins: tck, trst, tdi, tdo, tms. - scb1 - pins: scb1_sdat, scb1_sclk. - scb2 - pins: scb2_sdat, scb2_sclk. - spi0 - pins: spi0_mclk, spi0_cs0, spi0_cs1, spi0_cs2, spi0_dout, spi0_din. - spi1 - pins: spi1_mclk, spi1_cs0, spi1_cs1, spi1_cs2, spi1_dout, spi1_din. - uart - pins: uart0_txd, uart0_rxd, uart0_rts, uart0_cts, - uart1_txd, uart1_rxd. - drive_i2s - pins: clk_out1, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, - i2s_lrclk_out, i2s_bclk_out, i2s_mclk. - drive_pdm - pins: clk_out0, pdm_b, pdm_a. - drive_scb0 - pins: scb0_sclk, scb0_sdat, pdm_d, pdm_c. - drive_sdio - pins: sdio_clk, sdio_cmd, sdio_d0, sdio_d1, sdio_d2, sdio_d3, - sdh_wp, sdh_cd, sdh_clk_in. - - convenience groups: - - These are just convenient groupings of pins and don't support any drive - configs. - - uart0 - pins: uart0_cts, uart0_rts, uart0_rxd, uart0_txd. - uart1 - pins: uart1_rxd, uart1_txd. - scb0 - pins: scb0_sclk, scb0_sdat. - i2s - pins: i2s_bclk_out, i2s_din, i2s_dout0, i2s_dout1, i2s_dout2, - i2s_lrclk_out, i2s_mclk. - -Example: - - pinctrl: pinctrl@2005800 { - #gpio-range-cells = <3>; - compatible = "img,tz1090-pinctrl"; - reg = <0x02005800 0xe4>; - }; - -Example board file extract: - - &pinctrl { - uart0_default: uart0 { - uart0_cfg { - tz1090,pins = "uart0_rxd", - "uart0_txd"; - tz1090,function = "perip"; - }; - }; - tft_default: tft { - tft_cfg { - tz1090,pins = "tft"; - tz1090,function = "tft"; - }; - }; - }; - - uart@2004b00 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_default>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt index 9c451c20dda4..a5a8322a31bd 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt @@ -45,6 +45,8 @@ Optional properties: - first cell is the pin number - second cell is used to specify flags. - interrupt-controller: Marks the device node as a interrupt controller. +- drive-open-drain: Sets the ODR flag in the IOCON register. This configures + the IRQ output as open drain active low. Optional device specific properties: - microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index afa8a18ea11a..e7d6f81c227f 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -76,12 +76,12 @@ Examples: ... { - syscfg_pctl_a: syscfg_pctl_a@10005000 { + syscfg_pctl_a: syscfg-pctl-a@10005000 { compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon"; reg = <0 0x10005000 0 0x1000>; }; - syscfg_pctl_b: syscfg_pctl_b@1020c020 { + syscfg_pctl_b: syscfg-pctl-b@1020c020 { compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon"; reg = <0 0x1020C020 0 0x1000>; }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt new file mode 100644 index 000000000000..665aadb5ea28 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt @@ -0,0 +1,176 @@ +Qualcomm SDM845 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +SDM845 platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,sdm845-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio149 + Supports mux, bias and drive-strength + + sdc2_clk, sdc2_cmd, sdc2_data + Supports bias and drive-strength + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + gpio, adsp_ext, agera_pll, atest_char, atest_tsens, + atest_tsens2, atest_usb1, atest_usb10, atest_usb11, + atest_usb12, atest_usb13, atest_usb2, atest_usb20, + atest_usb21, atest_usb22, atest_usb23, audio_ref, + btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, + gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update, + lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator, + pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl, + pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, + qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1, + qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4, + qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, + qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd, + sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0, + tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, + tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, + tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync, + uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, + uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, + vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, + wlan2_adc1, + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@3400000 { + compatible = "qcom,sdm845-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <GIC_SPI 208 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + qup9_active: qup9-active { + mux { + pins = "gpio4", "gpio5"; + function = "qup9"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 0f254b35c378..f5ef8201c09f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -263,18 +263,6 @@ config PINCTRL_ST select PINCONF select GPIOLIB_IRQCHIP -config PINCTRL_TZ1090 - bool "Toumaz Xenif TZ1090 pin control driver" - depends on SOC_TZ1090 - select PINMUX - select GENERIC_PINCONF - -config PINCTRL_TZ1090_PDC - bool "Toumaz Xenif TZ1090 PDC pin control driver" - depends on SOC_TZ1090 - select PINMUX - select PINCONF - config PINCTRL_U300 bool "U300 pin controller driver" depends on ARCH_U300 diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index d3692633e9ed..6255546735ff 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -34,8 +34,6 @@ obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += sirf/ obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o obj-$(CONFIG_ARCH_TEGRA) += tegra/ -obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o -obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 2c0dbfcff3e6..e5a303002021 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1416,6 +1416,7 @@ int pinctrl_register_mappings(const struct pinctrl_map *maps, { return pinctrl_register_map(maps, num_maps, true); } +EXPORT_SYMBOL_GPL(pinctrl_register_mappings); void pinctrl_unregister_map(const struct pinctrl_map *map) { @@ -1586,6 +1587,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what) return 0; } +DEFINE_SHOW_ATTRIBUTE(pinctrl_pins); static int pinctrl_groups_show(struct seq_file *s, void *what) { @@ -1631,6 +1633,7 @@ static int pinctrl_groups_show(struct seq_file *s, void *what) return 0; } +DEFINE_SHOW_ATTRIBUTE(pinctrl_groups); static int pinctrl_gpioranges_show(struct seq_file *s, void *what) { @@ -1664,6 +1667,7 @@ static int pinctrl_gpioranges_show(struct seq_file *s, void *what) return 0; } +DEFINE_SHOW_ATTRIBUTE(pinctrl_gpioranges); static int pinctrl_devices_show(struct seq_file *s, void *what) { @@ -1690,6 +1694,7 @@ static int pinctrl_devices_show(struct seq_file *s, void *what) return 0; } +DEFINE_SHOW_ATTRIBUTE(pinctrl_devices); static inline const char *map_type(enum pinctrl_map_type type) { @@ -1743,6 +1748,7 @@ static int pinctrl_maps_show(struct seq_file *s, void *what) return 0; } +DEFINE_SHOW_ATTRIBUTE(pinctrl_maps); static int pinctrl_show(struct seq_file *s, void *what) { @@ -1788,87 +1794,30 @@ static int pinctrl_show(struct seq_file *s, void *what) return 0; } - -static int pinctrl_pins_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinctrl_pins_show, inode->i_private); -} - -static int pinctrl_groups_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinctrl_groups_show, inode->i_private); -} - -static int pinctrl_gpioranges_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinctrl_gpioranges_show, inode->i_private); -} - -static int pinctrl_devices_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinctrl_devices_show, NULL); -} - -static int pinctrl_maps_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinctrl_maps_show, NULL); -} - -static int pinctrl_open(struct inode *inode, struct file *file) -{ - return single_open(file, pinctrl_show, NULL); -} - -static const struct file_operations pinctrl_pins_ops = { - .open = pinctrl_pins_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static const struct file_operations pinctrl_groups_ops = { - .open = pinctrl_groups_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static const struct file_operations pinctrl_gpioranges_ops = { - .open = pinctrl_gpioranges_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static const struct file_operations pinctrl_devices_ops = { - .open = pinctrl_devices_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static const struct file_operations pinctrl_maps_ops = { - .open = pinctrl_maps_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static const struct file_operations pinctrl_ops = { - .open = pinctrl_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; +DEFINE_SHOW_ATTRIBUTE(pinctrl); static struct dentry *debugfs_root; static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev) { struct dentry *device_root; + const char *debugfs_name; + + if (pctldev->desc->name && + strcmp(dev_name(pctldev->dev), pctldev->desc->name)) { + debugfs_name = devm_kasprintf(pctldev->dev, GFP_KERNEL, + "%s-%s", dev_name(pctldev->dev), + pctldev->desc->name); + if (!debugfs_name) { + pr_warn("failed to determine debugfs dir name for %s\n", + dev_name(pctldev->dev)); + return; + } + } else { + debugfs_name = dev_name(pctldev->dev); + } - device_root = debugfs_create_dir(dev_name(pctldev->dev), - debugfs_root); + device_root = debugfs_create_dir(debugfs_name, debugfs_root); pctldev->device_root = device_root; if (IS_ERR(device_root) || !device_root) { @@ -1877,11 +1826,11 @@ static void pinctrl_init_device_debugfs(struct pinctrl_dev *pctldev) return; } debugfs_create_file("pins", S_IFREG | S_IRUGO, - device_root, pctldev, &pinctrl_pins_ops); + device_root, pctldev, &pinctrl_pins_fops); debugfs_create_file("pingroups", S_IFREG | S_IRUGO, - device_root, pctldev, &pinctrl_groups_ops); + device_root, pctldev, &pinctrl_groups_fops); debugfs_create_file("gpio-ranges", S_IFREG | S_IRUGO, - device_root, pctldev, &pinctrl_gpioranges_ops); + device_root, pctldev, &pinctrl_gpioranges_fops); if (pctldev->desc->pmxops) pinmux_init_device_debugfs(device_root, pctldev); if (pctldev->desc->confops) @@ -1903,11 +1852,11 @@ static void pinctrl_init_debugfs(void) } debugfs_create_file("pinctrl-devices", S_IFREG | S_IRUGO, - debugfs_root, NULL, &pinctrl_devices_ops); + debugfs_root, NULL, &pinctrl_devices_fops); debugfs_create_file("pinctrl-maps", S_IFREG | S_IRUGO, - debugfs_root, NULL, &pinctrl_maps_ops); + debugfs_root, NULL, &pinctrl_maps_fops); debugfs_create_file("pinctrl-handles", S_IFREG | S_IRUGO, - debugfs_root, NULL, &pinctrl_ops); + debugfs_root, NULL, &pinctrl_fops); } #else /* CONFIG_DEBUG_FS */ diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 1ff6c3573493..b601039d6c69 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -122,8 +122,10 @@ static int dt_to_map_one_config(struct pinctrl *p, /* OK let's just assume this will appear later then */ return -EPROBE_DEFER; } - if (!pctldev) - pctldev = get_pinctrl_dev_from_of_node(np_pctldev); + /* If we're creating a hog we can use the passed pctldev */ + if (pctldev && (np_pctldev == p->dev->of_node)) + break; + pctldev = get_pinctrl_dev_from_of_node(np_pctldev); if (pctldev) break; /* Do not defer probing of hogs (circular loop) */ diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index 5bd808dc81e1..bb2a30964fc6 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -884,20 +884,24 @@ static struct meson_pmx_func meson8b_aobus_functions[] = { }; static struct meson_bank meson8b_cbus_banks[] = { - /* name first last irq pullen pull dir out in */ - BANK("X", GPIOX_0, GPIOX_21, 97, 118, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), - BANK("Y", GPIOY_0, GPIOY_14, 80, 96, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), - BANK("DV", GPIODV_9, GPIODV_29, 59, 79, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), - BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), - BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), - BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), + /* name first last irq pullen pull dir out in */ + BANK("X0..11", GPIOX_0, GPIOX_11, 97, 108, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), + BANK("X16..21", GPIOX_16, GPIOX_21, 113, 118, 4, 16, 4, 16, 0, 16, 1, 16, 2, 16), + BANK("Y0..1", GPIOY_0, GPIOY_1, 80, 81, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), + BANK("Y3", GPIOY_3, GPIOY_3, 83, 83, 3, 3, 3, 3, 3, 3, 4, 3, 5, 3), + BANK("Y6..14", GPIOY_6, GPIOY_14, 86, 94, 3, 6, 3, 6, 3, 6, 4, 6, 5, 6), + BANK("DV9", GPIODV_9, GPIODV_9, 59, 59, 0, 9, 0, 9, 7, 9, 8, 9, 9, 9), + BANK("DV24..29", GPIODV_24, GPIODV_29, 74, 79, 0, 24, 0, 24, 7, 24, 8, 24, 9, 24), + BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), + BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), + BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), /* * The following bank is not mentionned in the public datasheet * There is no information whether it can be used with the gpio * interrupt controller */ - BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), + BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), }; static struct meson_bank meson8b_aobus_banks[] = { diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c index 7e814764da7d..8d944bb3a036 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-stn8815.c @@ -291,7 +291,17 @@ static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 }; static const unsigned clcd_16_23_b_1_pins[] = { STN8815_PIN_AB6, STN8815_PIN_AA6, STN8815_PIN_Y6, STN8815_PIN_Y5, STN8815_PIN_AA5, STN8815_PIN_AB5, STN8815_PIN_AB4, STN8815_PIN_Y4 }; - +/* Full-speed and high-speed USB pins */ +static const unsigned usbfs_b_1_pins[] = { STN8815_PIN_E21, STN8815_PIN_E20, + STN8815_PIN_C22, STN8815_PIN_D21, + STN8815_PIN_D20, STN8815_PIN_C21, + STN8815_PIN_C20 }; +static const unsigned usbhs_c_1_pins[] = { STN8815_PIN_E21, STN8815_PIN_E20, + STN8815_PIN_C20, STN8815_PIN_C19, + STN8815_PIN_C22, STN8815_PIN_D21, + STN8815_PIN_D20, STN8815_PIN_C21, + STN8815_PIN_C16, STN8815_PIN_A15, + STN8815_PIN_D17, STN8815_PIN_C17 }; #define STN8815_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \ .npins = ARRAY_SIZE(a##_pins), .altsetting = b } @@ -308,6 +318,8 @@ static const struct nmk_pingroup nmk_stn8815_groups[] = { STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B), STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B), STN8815_PIN_GROUP(clcd_16_23_b_1, NMK_GPIO_ALT_B), + STN8815_PIN_GROUP(usbfs_b_1, NMK_GPIO_ALT_B), + STN8815_PIN_GROUP(usbhs_c_1, NMK_GPIO_ALT_C), }; /* We use this macro to define the groups applicable to a function */ @@ -321,6 +333,7 @@ STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1"); STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1"); STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1"); STN8815_FUNC_GROUPS(clcd, "clcd_16_23_b_1"); +STN8815_FUNC_GROUPS(usb, "usbfs_b_1", "usbhs_c_1"); #define FUNCTION(fname) \ { \ @@ -337,6 +350,7 @@ static const struct nmk_function nmk_stn8815_functions[] = { FUNCTION(i2c0), FUNCTION(i2cusb), FUNCTION(clcd), + FUNCTION(usb), }; static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = { diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 61d830c2bc17..281b700fe7e9 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -40,6 +40,19 @@ #include "pinctrl-utils.h" #include "pinctrl-amd.h" +static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) +{ + unsigned long flags; + u32 pin_reg; + struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + offset * 4); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return !(pin_reg & BIT(OUTPUT_ENABLE_OFF)); +} + static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) { unsigned long flags; @@ -845,6 +858,7 @@ static int amd_gpio_probe(struct platform_device *pdev) #endif gpio_dev->pdev = pdev; + gpio_dev->gc.get_direction = amd_gpio_get_direction; gpio_dev->gc.direction_input = amd_gpio_direction_input; gpio_dev->gc.direction_output = amd_gpio_direction_output; gpio_dev->gc.get = amd_gpio_get_value; diff --git a/drivers/pinctrl/pinctrl-artpec6.c b/drivers/pinctrl/pinctrl-artpec6.c index e33781cd0a05..d89dc43c5757 100644 --- a/drivers/pinctrl/pinctrl-artpec6.c +++ b/drivers/pinctrl/pinctrl-artpec6.c @@ -277,37 +277,61 @@ static const struct artpec6_pin_group artpec6_pin_groups[] = { .config = ARTPEC6_CONFIG_3, }, { - .name = "uart0grp0", + .name = "uart0grp0", /* All pins. */ .pins = uart0_pins0, .num_pins = ARRAY_SIZE(uart0_pins0), .config = ARTPEC6_CONFIG_1, }, { - .name = "uart0grp1", + .name = "uart0grp1", /* RX/TX and RTS/CTS */ .pins = uart0_pins1, .num_pins = ARRAY_SIZE(uart0_pins1), .config = ARTPEC6_CONFIG_1, }, { - .name = "uart1grp0", + .name = "uart0grp2", /* Only RX/TX pins. */ + .pins = uart0_pins1, + .num_pins = ARRAY_SIZE(uart0_pins1) - 2, + .config = ARTPEC6_CONFIG_1, + }, + { + .name = "uart1grp0", /* RX/TX and RTS/CTS */ .pins = uart1_pins0, .num_pins = ARRAY_SIZE(uart1_pins0), .config = ARTPEC6_CONFIG_2, }, { - .name = "uart2grp0", + .name = "uart1grp1", /* Only RX/TX pins. */ + .pins = uart1_pins0, + .num_pins = 2, + .config = ARTPEC6_CONFIG_2, + }, + { + .name = "uart2grp0", /* Full pinout */ .pins = uart2_pins0, .num_pins = ARRAY_SIZE(uart2_pins0), .config = ARTPEC6_CONFIG_1, }, { - .name = "uart2grp1", + .name = "uart2grp1", /* RX/TX and RTS/CTS */ .pins = uart2_pins1, .num_pins = ARRAY_SIZE(uart2_pins1), .config = ARTPEC6_CONFIG_1, }, { - .name = "uart3grp0", + .name = "uart2grp2", /* Only RX/TX */ + .pins = uart2_pins1, + .num_pins = 2, + .config = ARTPEC6_CONFIG_1, + }, + { + .name = "uart3grp0", /* RX/TX and CTS/RTS */ + .pins = uart3_pins0, + .num_pins = ARRAY_SIZE(uart3_pins0), + .config = ARTPEC6_CONFIG_0, + }, + { + .name = "uart3grp1", /* Only RX/TX */ .pins = uart3_pins0, .num_pins = ARRAY_SIZE(uart3_pins0), .config = ARTPEC6_CONFIG_0, @@ -319,13 +343,19 @@ static const struct artpec6_pin_group artpec6_pin_groups[] = { .config = ARTPEC6_CONFIG_2, }, { - .name = "uart5grp0", + .name = "uart5grp0", /* TX/RX and RTS/CTS */ .pins = uart5_pins0, .num_pins = ARRAY_SIZE(uart5_pins0), .config = ARTPEC6_CONFIG_2, }, { - .name = "uart5nocts", + .name = "uart5grp1", /* Only TX/RX */ + .pins = uart5_pins0, + .num_pins = 2, + .config = ARTPEC6_CONFIG_2, + }, + { + .name = "uart5nocts", /* TX/RX/RTS */ .pins = uart5_pins0, .num_pins = ARRAY_SIZE(uart5_pins0) - 1, .config = ARTPEC6_CONFIG_2, @@ -457,8 +487,9 @@ static const char * const gpiogrps[] = { "cpuclkoutgrp0", "udlclkoutgrp0", "i2c1grp0", "i2c2grp0", "i2c3grp0", "i2s0grp0", "i2s1grp0", "i2srefclkgrp0", "spi0grp0", "spi1grp0", "pciedebuggrp0", "uart0grp0", - "uart0grp1", "uart1grp0", "uart2grp0", "uart2grp1", - "uart4grp0", "uart5grp0", + "uart0grp1", "uart0grp2", "uart1grp0", "uart1grp1", + "uart2grp0", "uart2grp1", "uart2grp2", "uart4grp0", "uart5grp0", + "uart5grp1", "uart5nocts", }; static const char * const cpuclkoutgrps[] = { "cpuclkoutgrp0" }; static const char * const udlclkoutgrps[] = { "udlclkoutgrp0" }; @@ -471,12 +502,15 @@ static const char * const i2srefclkgrps[] = { "i2srefclkgrp0" }; static const char * const spi0grps[] = { "spi0grp0" }; static const char * const spi1grps[] = { "spi1grp0" }; static const char * const pciedebuggrps[] = { "pciedebuggrp0" }; -static const char * const uart0grps[] = { "uart0grp0", "uart0grp1" }; -static const char * const uart1grps[] = { "uart1grp0" }; -static const char * const uart2grps[] = { "uart2grp0", "uart2grp1" }; +static const char * const uart0grps[] = { "uart0grp0", "uart0grp1", + "uart0grp2" }; +static const char * const uart1grps[] = { "uart1grp0", "uart1grp1" }; +static const char * const uart2grps[] = { "uart2grp0", "uart2grp1", + "uart2grp2" }; static const char * const uart3grps[] = { "uart3grp0" }; -static const char * const uart4grps[] = { "uart4grp0" }; -static const char * const uart5grps[] = { "uart5grp0", "uart5nocts" }; +static const char * const uart4grps[] = { "uart4grp0", "uart4grp1" }; +static const char * const uart5grps[] = { "uart5grp0", "uart5grp1", + "uart5nocts" }; static const char * const nandgrps[] = { "nandgrp0" }; static const char * const sdio0grps[] = { "sdio0grp0" }; static const char * const sdio1grps[] = { "sdio1grp0" }; @@ -601,7 +635,7 @@ static int artpec6_pmx_get_functions_count(struct pinctrl_dev *pctldev) } static const char *artpec6_pmx_get_fname(struct pinctrl_dev *pctldev, - unsigned int function) + unsigned int function) { return artpec6_pmx_functions[function].name; } diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 644c5beb05cb..022307dd4b54 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -771,6 +771,9 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, { int status, ret; bool mirror = false; + bool open_drain = false; + struct regmap_config *one_regmap_config = NULL; + int raw_chip_address = (addr & ~0x40) >> 1; mutex_init(&mcp->lock); @@ -791,19 +794,33 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, switch (type) { #ifdef CONFIG_SPI_MASTER case MCP_TYPE_S08: - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - &mcp23x08_regmap); - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = "mcp23s08"; - break; - case MCP_TYPE_S17: + switch (type) { + case MCP_TYPE_S08: + one_regmap_config = + devm_kmemdup(dev, &mcp23x08_regmap, + sizeof(struct regmap_config), GFP_KERNEL); + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, + "mcp23s08.%d", raw_chip_address); + break; + case MCP_TYPE_S17: + one_regmap_config = + devm_kmemdup(dev, &mcp23x17_regmap, + sizeof(struct regmap_config), GFP_KERNEL); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, + "mcp23s17.%d", raw_chip_address); + break; + } + if (!one_regmap_config) + return -ENOMEM; + + one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address); mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - &mcp23x17_regmap); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23s17"; + one_regmap_config); break; case MCP_TYPE_S18: @@ -867,10 +884,11 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, "microchip,irq-active-high"); mirror = device_property_read_bool(dev, "microchip,irq-mirror"); + open_drain = device_property_read_bool(dev, "drive-open-drain"); } if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || - mcp->irq_active_high) { + mcp->irq_active_high || open_drain) { /* mcp23s17 has IOCON twice, make sure they are in sync */ status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8)); status |= IOCON_HAEN | (IOCON_HAEN << 8); @@ -882,6 +900,9 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, if (mirror) status |= IOCON_MIRROR | (IOCON_MIRROR << 8); + if (open_drain) + status |= IOCON_ODR | (IOCON_ODR << 8); + if (type == MCP_TYPE_S18 || type == MCP_TYPE_018) status |= IOCON_INTCC | (IOCON_INTCC << 8); @@ -900,7 +921,14 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, if (ret < 0) goto fail; - mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; + if (one_regmap_config) { + mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, + "mcp23xxx-pinctrl.%d", raw_chip_address); + if (!mcp->pinctrl_desc.name) + return -ENOMEM; + } else { + mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; + } mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; mcp->pinctrl_desc.confops = &mcp_pinconf_ops; mcp->pinctrl_desc.npins = mcp->chip.ngpio; diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 01a50d969111..a9423238471e 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -462,7 +462,7 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = { {}, }; -int ocelot_pinctrl_probe(struct platform_device *pdev) +static int ocelot_pinctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct ocelot_pinctrl *info; diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c deleted file mode 100644 index b16d1c96b7eb..000000000000 --- a/drivers/pinctrl/pinctrl-tz1090-pdc.c +++ /dev/null @@ -1,989 +0,0 @@ -/* - * Pinctrl driver for the Toumaz Xenif TZ1090 PowerDown Controller pins - * - * Copyright (c) 2013, Imagination Technologies Ltd. - * - * Derived from Tegra code: - * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. - * - * Derived from code: - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2010 NVIDIA Corporation - * Copyright (C) 2009-2011 ST-Ericsson AB - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include <linux/bitops.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/slab.h> - -/* - * The registers may be shared with other threads/cores, so we need to use the - * metag global lock2 for atomicity. - */ -#include <asm/global_lock.h> - -#include "core.h" -#include "pinconf.h" - -/* Register offsets from bank base address */ -#define REG_GPIO_CONTROL0 0x00 -#define REG_GPIO_CONTROL2 0x08 - -/* Register field information */ -#define REG_GPIO_CONTROL2_PU_PD_S 16 -#define REG_GPIO_CONTROL2_PDC_POS_S 4 -#define REG_GPIO_CONTROL2_PDC_DR_S 2 -#define REG_GPIO_CONTROL2_PDC_SR_S 1 -#define REG_GPIO_CONTROL2_PDC_SCHMITT_S 0 - -/* PU_PD field values */ -#define REG_PU_PD_TRISTATE 0 -#define REG_PU_PD_UP 1 -#define REG_PU_PD_DOWN 2 -#define REG_PU_PD_REPEATER 3 - -/* DR field values */ -#define REG_DR_2mA 0 -#define REG_DR_4mA 1 -#define REG_DR_8mA 2 -#define REG_DR_12mA 3 - -/** - * struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function - * @name: The name of the function, exported to pinctrl core. - * @groups: An array of pin groups that may select this function. - * @ngroups: The number of entries in @groups. - */ -struct tz1090_pdc_function { - const char *name; - const char * const *groups; - unsigned int ngroups; -}; - -/** - * struct tz1090_pdc_pingroup - TZ1090 PDC pin group - * @name: Name of pin group. - * @pins: Array of pin numbers in this pin group. - * @npins: Number of pins in this pin group. - * @func: Function enabled by the mux. - * @reg: Mux register offset. - * @bit: Mux register bit. - * @drv: Drive control supported, otherwise it's a mux. - * This means Schmitt, Slew, and Drive strength. - * - * A representation of a group of pins (possibly just one pin) in the TZ1090 - * PDC pin controller. Each group allows some parameter or parameters to be - * configured. The most common is mux function selection. - */ -struct tz1090_pdc_pingroup { - const char *name; - const unsigned int *pins; - unsigned int npins; - int func; - u16 reg; - u8 bit; - bool drv; -}; - -/* - * All PDC pins can be GPIOs. Define these first to match how the GPIO driver - * names/numbers its pins. - */ - -enum tz1090_pdc_pin { - TZ1090_PDC_PIN_GPIO0, - TZ1090_PDC_PIN_GPIO1, - TZ1090_PDC_PIN_SYS_WAKE0, - TZ1090_PDC_PIN_SYS_WAKE1, - TZ1090_PDC_PIN_SYS_WAKE2, - TZ1090_PDC_PIN_IR_DATA, - TZ1090_PDC_PIN_EXT_POWER, -}; - -/* Pin names */ - -static const struct pinctrl_pin_desc tz1090_pdc_pins[] = { - /* PDC GPIOs */ - PINCTRL_PIN(TZ1090_PDC_PIN_GPIO0, "gpio0"), - PINCTRL_PIN(TZ1090_PDC_PIN_GPIO1, "gpio1"), - PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE0, "sys_wake0"), - PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE1, "sys_wake1"), - PINCTRL_PIN(TZ1090_PDC_PIN_SYS_WAKE2, "sys_wake2"), - PINCTRL_PIN(TZ1090_PDC_PIN_IR_DATA, "ir_data"), - PINCTRL_PIN(TZ1090_PDC_PIN_EXT_POWER, "ext_power"), -}; - -/* Pin group pins */ - -static const unsigned int gpio0_pins[] = { - TZ1090_PDC_PIN_GPIO0, -}; - -static const unsigned int gpio1_pins[] = { - TZ1090_PDC_PIN_GPIO1, -}; - -static const unsigned int pdc_pins[] = { - TZ1090_PDC_PIN_GPIO0, - TZ1090_PDC_PIN_GPIO1, - TZ1090_PDC_PIN_SYS_WAKE0, - TZ1090_PDC_PIN_SYS_WAKE1, - TZ1090_PDC_PIN_SYS_WAKE2, - TZ1090_PDC_PIN_IR_DATA, - TZ1090_PDC_PIN_EXT_POWER, -}; - -/* Mux functions */ - -enum tz1090_pdc_mux { - /* PDC_GPIO0 mux */ - TZ1090_PDC_MUX_IR_MOD_STABLE_OUT, - /* PDC_GPIO1 mux */ - TZ1090_PDC_MUX_IR_MOD_POWER_OUT, -}; - -/* Pin groups a function can be muxed to */ - -static const char * const gpio0_groups[] = { - "gpio0", -}; - -static const char * const gpio1_groups[] = { - "gpio1", -}; - -#define FUNCTION(mux, fname, group) \ - [(TZ1090_PDC_MUX_ ## mux)] = { \ - .name = #fname, \ - .groups = group##_groups, \ - .ngroups = ARRAY_SIZE(group##_groups), \ - } - -/* Must correlate with enum tz1090_pdc_mux */ -static const struct tz1090_pdc_function tz1090_pdc_functions[] = { - /* MUX fn pingroups */ - FUNCTION(IR_MOD_STABLE_OUT, ir_mod_stable_out, gpio0), - FUNCTION(IR_MOD_POWER_OUT, ir_mod_power_out, gpio1), -}; - -/** - * MUX_PG() - Initialise a pin group with mux control - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - * @f0: Function 0 (TZ1090_PDC_MUX_ is prepended) - * @mux_r: Mux register (REG_PINCTRL_ is prepended) - * @mux_b: Bit number in register of mux field - */ -#define MUX_PG(pg_name, f0, mux_r, mux_b) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .func = TZ1090_PDC_MUX_ ## f0, \ - .reg = (REG_ ## mux_r), \ - .bit = (mux_b), \ - } - -/** - * DRV_PG() - Initialise a pin group with drive control - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - */ -#define DRV_PG(pg_name) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .drv = true, \ - } - -static const struct tz1090_pdc_pingroup tz1090_pdc_groups[] = { - /* Muxing pin groups */ - /* pg_name, f0, mux register, mux bit */ - MUX_PG(gpio0, IR_MOD_STABLE_OUT, GPIO_CONTROL0, 7), - MUX_PG(gpio1, IR_MOD_POWER_OUT, GPIO_CONTROL0, 6), - - /* Drive pin groups */ - /* pg_name */ - DRV_PG(pdc), -}; - -/** - * struct tz1090_pdc_pmx - Private pinctrl data - * @dev: Platform device - * @pctl: Pin control device - * @regs: Register region - * @lock: Lock protecting coherency of mux_en and gpio_en - * @mux_en: Muxes that have been enabled - * @gpio_en: Muxable GPIOs that have been enabled - */ -struct tz1090_pdc_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *regs; - spinlock_t lock; - u32 mux_en; - u32 gpio_en; -}; - -static inline u32 pmx_read(struct tz1090_pdc_pmx *pmx, u32 reg) -{ - return ioread32(pmx->regs + reg); -} - -static inline void pmx_write(struct tz1090_pdc_pmx *pmx, u32 val, u32 reg) -{ - iowrite32(val, pmx->regs + reg); -} - -/* - * Pin control operations - */ - -static int tz1090_pdc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(tz1090_pdc_groups); -} - -static const char *tz1090_pdc_pinctrl_get_group_name(struct pinctrl_dev *pctl, - unsigned int group) -{ - return tz1090_pdc_groups[group].name; -} - -static int tz1090_pdc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group, - const unsigned int **pins, - unsigned int *num_pins) -{ - *pins = tz1090_pdc_groups[group].pins; - *num_pins = tz1090_pdc_groups[group].npins; - - return 0; -} - -#ifdef CONFIG_DEBUG_FS -static void tz1090_pdc_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned int offset) -{ - seq_printf(s, " %s", dev_name(pctldev->dev)); -} -#endif - -static int reserve_map(struct device *dev, struct pinctrl_map **map, - unsigned int *reserved_maps, unsigned int *num_maps, - unsigned int reserve) -{ - unsigned int old_num = *reserved_maps; - unsigned int new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) { - dev_err(dev, "krealloc(map) failed\n"); - return -ENOMEM; - } - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps, - unsigned int *num_maps, const char *group, - const char *function) -{ - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -/** - * get_group_selector() - returns the group selector for a group - * @pin_group: the pin group to look up - * - * This is the same as pinctrl_get_group_selector except it doesn't produce an - * error message if the group isn't found or debug messages. - */ -static int get_group_selector(const char *pin_group) -{ - unsigned int group; - - for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group) - if (!strcmp(tz1090_pdc_groups[group].name, pin_group)) - return group; - - return -EINVAL; -} - -static int add_map_configs(struct device *dev, - struct pinctrl_map **map, - unsigned int *reserved_maps, unsigned int *num_maps, - const char *group, unsigned long *configs, - unsigned int num_configs) -{ - unsigned long *dup_configs; - enum pinctrl_map_type type; - - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) - return -ENOMEM; - - /* - * We support both pins and pin groups, but we need to figure out which - * one we have. - */ - if (get_group_selector(group) >= 0) - type = PIN_MAP_TYPE_CONFIGS_GROUP; - else - type = PIN_MAP_TYPE_CONFIGS_PIN; - (*map)[*num_maps].type = type; - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -static void tz1090_pdc_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, - unsigned int num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - - kfree(map); -} - -static int tz1090_pdc_pinctrl_dt_subnode_to_map(struct device *dev, - struct device_node *np, - struct pinctrl_map **map, - unsigned int *reserved_maps, - unsigned int *num_maps) -{ - int ret; - const char *function; - unsigned long *configs = NULL; - unsigned int num_configs = 0; - unsigned int reserve; - struct property *prop; - const char *group; - - ret = of_property_read_string(np, "tz1090,function", &function); - if (ret < 0) { - /* EINVAL=missing, which is fine since it's optional */ - if (ret != -EINVAL) - dev_err(dev, - "could not parse property function\n"); - function = NULL; - } - - ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); - if (ret) - return ret; - - reserve = 0; - if (function != NULL) - reserve++; - if (num_configs) - reserve++; - ret = of_property_count_strings(np, "tz1090,pins"); - if (ret < 0) { - dev_err(dev, "could not parse property pins\n"); - goto exit; - } - reserve *= ret; - - ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "tz1090,pins", prop, group) { - if (function) { - ret = add_map_mux(map, reserved_maps, num_maps, - group, function); - if (ret < 0) - goto exit; - } - - if (num_configs) { - ret = add_map_configs(dev, map, reserved_maps, - num_maps, group, configs, - num_configs); - if (ret < 0) - goto exit; - } - } - - ret = 0; - -exit: - kfree(configs); - return ret; -} - -static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - unsigned int *num_maps) -{ - unsigned int reserved_maps; - struct device_node *np; - int ret; - - reserved_maps = 0; - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = tz1090_pdc_pinctrl_dt_subnode_to_map(pctldev->dev, np, - map, &reserved_maps, - num_maps); - if (ret < 0) { - tz1090_pdc_pinctrl_dt_free_map(pctldev, *map, - *num_maps); - return ret; - } - } - - return 0; -} - -static const struct pinctrl_ops tz1090_pdc_pinctrl_ops = { - .get_groups_count = tz1090_pdc_pinctrl_get_groups_count, - .get_group_name = tz1090_pdc_pinctrl_get_group_name, - .get_group_pins = tz1090_pdc_pinctrl_get_group_pins, -#ifdef CONFIG_DEBUG_FS - .pin_dbg_show = tz1090_pdc_pinctrl_pin_dbg_show, -#endif - .dt_node_to_map = tz1090_pdc_pinctrl_dt_node_to_map, - .dt_free_map = tz1090_pdc_pinctrl_dt_free_map, -}; - -/* - * Pin mux operations - */ - -static int tz1090_pdc_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(tz1090_pdc_functions); -} - -static const char *tz1090_pdc_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned int function) -{ - return tz1090_pdc_functions[function].name; -} - -static int tz1090_pdc_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const num_groups) -{ - *groups = tz1090_pdc_functions[function].groups; - *num_groups = tz1090_pdc_functions[function].ngroups; - - return 0; -} - -/** - * tz1090_pdc_pinctrl_mux() - update mux bit - * @pmx: Pinmux data - * @grp: Pin mux group - */ -static void tz1090_pdc_pinctrl_mux(struct tz1090_pdc_pmx *pmx, - const struct tz1090_pdc_pingroup *grp) -{ - u32 reg, select; - unsigned int pin_shift = grp->pins[0]; - unsigned long flags; - - /* select = mux && !gpio */ - select = ((pmx->mux_en & ~pmx->gpio_en) >> pin_shift) & 1; - - /* set up the mux */ - __global_lock2(flags); - reg = pmx_read(pmx, grp->reg); - reg &= ~BIT(grp->bit); - reg |= select << grp->bit; - pmx_write(pmx, reg, grp->reg); - __global_unlock2(flags); -} - -static int tz1090_pdc_pinctrl_set_mux(struct pinctrl_dev *pctldev, - unsigned int function, - unsigned int group) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *grp = &tz1090_pdc_groups[group]; - - dev_dbg(pctldev->dev, "%s(func=%u (%s), group=%u (%s))\n", - __func__, - function, tz1090_pdc_functions[function].name, - group, tz1090_pdc_groups[group].name); - - /* is it even a mux? */ - if (grp->drv) - return -EINVAL; - - /* does this group even control the function? */ - if (function != grp->func) - return -EINVAL; - - /* record the pin being muxed and update mux bit */ - spin_lock(&pmx->lock); - pmx->mux_en |= BIT(grp->pins[0]); - tz1090_pdc_pinctrl_mux(pmx, grp); - spin_unlock(&pmx->lock); - return 0; -} - -static const struct tz1090_pdc_pingroup *find_mux_group( - struct tz1090_pdc_pmx *pmx, - unsigned int pin) -{ - const struct tz1090_pdc_pingroup *grp; - unsigned int group; - - grp = tz1090_pdc_groups; - for (group = 0; group < ARRAY_SIZE(tz1090_pdc_groups); ++group, ++grp) { - /* only match muxes */ - if (grp->drv) - continue; - - /* with a matching pin */ - if (grp->pins[0] == pin) - return grp; - } - - return NULL; -} - -static int tz1090_pdc_pinctrl_gpio_request_enable( - struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); - - if (grp) { - /* record the pin in GPIO use and update mux bit */ - spin_lock(&pmx->lock); - pmx->gpio_en |= BIT(pin); - tz1090_pdc_pinctrl_mux(pmx, grp); - spin_unlock(&pmx->lock); - } - return 0; -} - -static void tz1090_pdc_pinctrl_gpio_disable_free( - struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *grp = find_mux_group(pmx, pin); - - if (grp) { - /* record the pin not in GPIO use and update mux bit */ - spin_lock(&pmx->lock); - pmx->gpio_en &= ~BIT(pin); - tz1090_pdc_pinctrl_mux(pmx, grp); - spin_unlock(&pmx->lock); - } -} - -static const struct pinmux_ops tz1090_pdc_pinmux_ops = { - .get_functions_count = tz1090_pdc_pinctrl_get_funcs_count, - .get_function_name = tz1090_pdc_pinctrl_get_func_name, - .get_function_groups = tz1090_pdc_pinctrl_get_func_groups, - .set_mux = tz1090_pdc_pinctrl_set_mux, - .gpio_request_enable = tz1090_pdc_pinctrl_gpio_request_enable, - .gpio_disable_free = tz1090_pdc_pinctrl_gpio_disable_free, -}; - -/* - * Pin config operations - */ - -static int tz1090_pdc_pinconf_reg(struct pinctrl_dev *pctldev, - unsigned int pin, - enum pin_config_param param, - bool report_err, - u32 *reg, u32 *width, u32 *mask, u32 *shift, - u32 *val) -{ - /* Find information about parameter's register */ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - *val = REG_PU_PD_TRISTATE; - break; - case PIN_CONFIG_BIAS_PULL_UP: - *val = REG_PU_PD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - *val = REG_PU_PD_DOWN; - break; - case PIN_CONFIG_BIAS_BUS_HOLD: - *val = REG_PU_PD_REPEATER; - break; - default: - return -ENOTSUPP; - } - - /* Only input bias parameters supported */ - *reg = REG_GPIO_CONTROL2; - *shift = REG_GPIO_CONTROL2_PU_PD_S + pin*2; - *width = 2; - - /* Calculate field information */ - *mask = (BIT(*width) - 1) << *shift; - - return 0; -} - -static int tz1090_pdc_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - int ret; - u32 reg, width, mask, shift, val, tmp, arg; - - /* Get register information */ - ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; - - /* Extract field from register */ - tmp = pmx_read(pmx, reg); - arg = ((tmp & mask) >> shift) == val; - - /* Config not active */ - if (!arg) - return -EINVAL; - - /* And pack config */ - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int tz1090_pdc_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned num_configs) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param; - unsigned int arg; - int ret; - u32 reg, width, mask, shift, val, tmp; - unsigned long flags; - int i; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", - __func__, tz1090_pdc_pins[pin].name, configs[i]); - - /* Get register information */ - ret = tz1090_pdc_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; - - /* Unpack argument and range check it */ - if (arg > 1) { - dev_dbg(pctldev->dev, "%s: arg %u out of range\n", - __func__, arg); - return -EINVAL; - } - - /* Write register field */ - __global_lock2(flags); - tmp = pmx_read(pmx, reg); - tmp &= ~mask; - if (arg) - tmp |= val << shift; - pmx_write(pmx, tmp, reg); - __global_unlock2(flags); - } /* for each config */ - - return 0; -} - -static const int tz1090_pdc_boolean_map[] = { - [0] = -EINVAL, - [1] = 1, -}; - -static const int tz1090_pdc_dr_map[] = { - [REG_DR_2mA] = 2, - [REG_DR_4mA] = 4, - [REG_DR_8mA] = 8, - [REG_DR_12mA] = 12, -}; - -static int tz1090_pdc_pinconf_group_reg(struct pinctrl_dev *pctldev, - const struct tz1090_pdc_pingroup *g, - enum pin_config_param param, - bool report_err, u32 *reg, u32 *width, - u32 *mask, u32 *shift, const int **map) -{ - /* Drive configuration applies in groups, but not to all groups. */ - if (!g->drv) { - if (report_err) - dev_dbg(pctldev->dev, - "%s: group %s has no drive control\n", - __func__, g->name); - return -ENOTSUPP; - } - - /* Find information about drive parameter's register */ - *reg = REG_GPIO_CONTROL2; - switch (param) { - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - *shift = REG_GPIO_CONTROL2_PDC_SCHMITT_S; - *width = 1; - *map = tz1090_pdc_boolean_map; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - *shift = REG_GPIO_CONTROL2_PDC_DR_S; - *width = 2; - *map = tz1090_pdc_dr_map; - break; - case PIN_CONFIG_LOW_POWER_MODE: - *shift = REG_GPIO_CONTROL2_PDC_POS_S; - *width = 1; - *map = tz1090_pdc_boolean_map; - break; - default: - return -ENOTSUPP; - } - - /* Calculate field information */ - *mask = (BIT(*width) - 1) << *shift; - - return 0; -} - -static int tz1090_pdc_pinconf_group_get(struct pinctrl_dev *pctldev, - unsigned int group, - unsigned long *config) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; - enum pin_config_param param = pinconf_to_config_param(*config); - int ret, arg; - u32 reg, width, mask, shift, val; - const int *map; - - /* Get register information */ - ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, - ®, &width, &mask, &shift, &map); - if (ret < 0) - return ret; - - /* Extract field from register */ - val = pmx_read(pmx, reg); - arg = map[(val & mask) >> shift]; - if (arg < 0) - return arg; - - /* And pack config */ - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int tz1090_pdc_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned int group, - unsigned long *configs, - unsigned num_configs) -{ - struct tz1090_pdc_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pdc_pingroup *g = &tz1090_pdc_groups[group]; - enum pin_config_param param; - const unsigned int *pit; - unsigned int i; - int ret, arg; - u32 reg, width, mask, shift, val; - unsigned long flags; - const int *map; - int j; - - for (j = 0; j < num_configs; j++) { - param = pinconf_to_config_param(configs[j]); - - dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", - __func__, g->name, configs[j]); - - /* Get register information */ - ret = tz1090_pdc_pinconf_group_reg(pctldev, g, param, true, - ®, &width, &mask, &shift, - &map); - if (ret < 0) { - /* - * Maybe we're trying to set a per-pin configuration - * of a group, so do the pins one by one. This is - * mainly as a convenience. - */ - for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { - ret = tz1090_pdc_pinconf_set(pctldev, *pit, - configs, num_configs); - if (ret) - return ret; - } - return 0; - } - - /* Unpack argument and map it to register value */ - arg = pinconf_to_config_argument(configs[j]); - for (i = 0; i < BIT(width); ++i) { - if (map[i] == arg || (map[i] == -EINVAL && !arg)) { - /* Write register field */ - __global_lock2(flags); - val = pmx_read(pmx, reg); - val &= ~mask; - val |= i << shift; - pmx_write(pmx, val, reg); - __global_unlock2(flags); - goto next_config; - } - } - - dev_dbg(pctldev->dev, "%s: arg %u not supported\n", - __func__, arg); - return 0; - -next_config: - ; - } /* for each config */ - - return 0; -} - -static const struct pinconf_ops tz1090_pdc_pinconf_ops = { - .is_generic = true, - .pin_config_get = tz1090_pdc_pinconf_get, - .pin_config_set = tz1090_pdc_pinconf_set, - .pin_config_group_get = tz1090_pdc_pinconf_group_get, - .pin_config_group_set = tz1090_pdc_pinconf_group_set, - .pin_config_config_dbg_show = pinconf_generic_dump_config, -}; - -/* - * Pin control driver setup - */ - -static struct pinctrl_desc tz1090_pdc_pinctrl_desc = { - .pctlops = &tz1090_pdc_pinctrl_ops, - .pmxops = &tz1090_pdc_pinmux_ops, - .confops = &tz1090_pdc_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int tz1090_pdc_pinctrl_probe(struct platform_device *pdev) -{ - struct tz1090_pdc_pmx *pmx; - struct resource *res; - - pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); - if (!pmx) - return -ENOMEM; - - pmx->dev = &pdev->dev; - spin_lock_init(&pmx->lock); - - tz1090_pdc_pinctrl_desc.name = dev_name(&pdev->dev); - tz1090_pdc_pinctrl_desc.pins = tz1090_pdc_pins; - tz1090_pdc_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pdc_pins); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pmx->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(pmx->regs)) - return PTR_ERR(pmx->regs); - - pmx->pctl = devm_pinctrl_register(&pdev->dev, &tz1090_pdc_pinctrl_desc, - pmx); - if (IS_ERR(pmx->pctl)) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return PTR_ERR(pmx->pctl); - } - - platform_set_drvdata(pdev, pmx); - - dev_info(&pdev->dev, "TZ1090 PDC pinctrl driver initialised\n"); - - return 0; -} - -static const struct of_device_id tz1090_pdc_pinctrl_of_match[] = { - { .compatible = "img,tz1090-pdc-pinctrl", }, - { }, -}; - -static struct platform_driver tz1090_pdc_pinctrl_driver = { - .driver = { - .name = "tz1090-pdc-pinctrl", - .of_match_table = tz1090_pdc_pinctrl_of_match, - }, - .probe = tz1090_pdc_pinctrl_probe, -}; - -static int __init tz1090_pdc_pinctrl_init(void) -{ - return platform_driver_register(&tz1090_pdc_pinctrl_driver); -} -arch_initcall(tz1090_pdc_pinctrl_init); - -static void __exit tz1090_pdc_pinctrl_exit(void) -{ - platform_driver_unregister(&tz1090_pdc_pinctrl_driver); -} -module_exit(tz1090_pdc_pinctrl_exit); - -MODULE_AUTHOR("Imagination Technologies Ltd."); -MODULE_DESCRIPTION("Toumaz Xenif TZ1090 PDC pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, tz1090_pdc_pinctrl_of_match); diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c deleted file mode 100644 index 2379ce2be365..000000000000 --- a/drivers/pinctrl/pinctrl-tz1090.c +++ /dev/null @@ -1,2005 +0,0 @@ -/* - * Pinctrl driver for the Toumaz Xenif TZ1090 SoC - * - * Copyright (c) 2013, Imagination Technologies Ltd. - * - * Derived from Tegra code: - * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. - * - * Derived from code: - * Copyright (C) 2010 Google, Inc. - * Copyright (C) 2010 NVIDIA Corporation - * Copyright (C) 2009-2011 ST-Ericsson AB - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include <linux/bitops.h> -#include <linux/io.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/platform_device.h> -#include <linux/pinctrl/machine.h> -#include <linux/pinctrl/pinconf-generic.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> -#include <linux/slab.h> -#include <linux/spinlock.h> - -/* - * The registers may be shared with other threads/cores, so we need to use the - * metag global lock2 for atomicity. - */ -#include <asm/global_lock.h> - -#include "core.h" -#include "pinconf.h" - -/* Register offsets from bank base address */ -#define REG_PINCTRL_SELECT 0x10 -#define REG_PINCTRL_SCHMITT 0x90 -#define REG_PINCTRL_PU_PD 0xa0 -#define REG_PINCTRL_SR 0xc0 -#define REG_PINCTRL_DR 0xd0 -#define REG_PINCTRL_IF_CTL 0xe0 - -/* REG_PINCTRL_PU_PD field values */ -#define REG_PU_PD_TRISTATE 0 -#define REG_PU_PD_UP 1 -#define REG_PU_PD_DOWN 2 -#define REG_PU_PD_REPEATER 3 - -/* REG_PINCTRL_DR field values */ -#define REG_DR_2mA 0 -#define REG_DR_4mA 1 -#define REG_DR_8mA 2 -#define REG_DR_12mA 3 - -/** - * struct tz1090_function - TZ1090 pinctrl mux function - * @name: The name of the function, exported to pinctrl core. - * @groups: An array of pin groups that may select this function. - * @ngroups: The number of entries in @groups. - */ -struct tz1090_function { - const char *name; - const char * const *groups; - unsigned int ngroups; -}; - -/** - * struct tz1090_muxdesc - TZ1090 individual mux description - * @funcs: Function for each mux value. - * @reg: Mux register offset. 0 if unsupported. - * @bit: Mux register bit. 0 if unsupported. - * @width: Mux field width. 0 if unsupported. - * - * A representation of a group of signals (possibly just one signal) in the - * TZ1090 which can be muxed to a set of functions or sub muxes. - */ -struct tz1090_muxdesc { - int funcs[5]; - u16 reg; - u8 bit; - u8 width; -}; - -/** - * struct tz1090_pingroup - TZ1090 pin group - * @name: Name of pin group. - * @pins: Array of pin numbers in this pin group. - * @npins: Number of pins in this pin group. - * @mux: Top level mux. - * @drv: Drive control supported, 0 if unsupported. - * This means Schmitt, Slew, and Drive strength. - * @slw_bit: Slew register bit. 0 if unsupported. - * The same bit is used for Schmitt, and Drive (*2). - * @func: Currently muxed function. - * @func_count: Number of pins using current mux function. - * - * A representation of a group of pins (possibly just one pin) in the TZ1090 - * pin controller. Each group allows some parameter or parameters to be - * configured. The most common is mux function selection. - */ -struct tz1090_pingroup { - const char *name; - const unsigned int *pins; - unsigned int npins; - struct tz1090_muxdesc mux; - - bool drv; - u8 slw_bit; - - int func; - unsigned int func_count; -}; - -/* - * Most pins affected by the pinmux can also be GPIOs. Define these first. - * These must match how the GPIO driver names/numbers its pins. - */ - -enum tz1090_pin { - /* GPIO pins */ - TZ1090_PIN_SDIO_CLK, - TZ1090_PIN_SDIO_CMD, - TZ1090_PIN_SDIO_D0, - TZ1090_PIN_SDIO_D1, - TZ1090_PIN_SDIO_D2, - TZ1090_PIN_SDIO_D3, - TZ1090_PIN_SDH_CD, - TZ1090_PIN_SDH_WP, - TZ1090_PIN_SPI0_MCLK, - TZ1090_PIN_SPI0_CS0, - TZ1090_PIN_SPI0_CS1, - TZ1090_PIN_SPI0_CS2, - TZ1090_PIN_SPI0_DOUT, - TZ1090_PIN_SPI0_DIN, - TZ1090_PIN_SPI1_MCLK, - TZ1090_PIN_SPI1_CS0, - TZ1090_PIN_SPI1_CS1, - TZ1090_PIN_SPI1_CS2, - TZ1090_PIN_SPI1_DOUT, - TZ1090_PIN_SPI1_DIN, - TZ1090_PIN_UART0_RXD, - TZ1090_PIN_UART0_TXD, - TZ1090_PIN_UART0_CTS, - TZ1090_PIN_UART0_RTS, - TZ1090_PIN_UART1_RXD, - TZ1090_PIN_UART1_TXD, - TZ1090_PIN_SCB0_SDAT, - TZ1090_PIN_SCB0_SCLK, - TZ1090_PIN_SCB1_SDAT, - TZ1090_PIN_SCB1_SCLK, - TZ1090_PIN_SCB2_SDAT, - TZ1090_PIN_SCB2_SCLK, - TZ1090_PIN_I2S_MCLK, - TZ1090_PIN_I2S_BCLK_OUT, - TZ1090_PIN_I2S_LRCLK_OUT, - TZ1090_PIN_I2S_DOUT0, - TZ1090_PIN_I2S_DOUT1, - TZ1090_PIN_I2S_DOUT2, - TZ1090_PIN_I2S_DIN, - TZ1090_PIN_PDM_A, - TZ1090_PIN_PDM_B, - TZ1090_PIN_PDM_C, - TZ1090_PIN_PDM_D, - TZ1090_PIN_TFT_RED0, - TZ1090_PIN_TFT_RED1, - TZ1090_PIN_TFT_RED2, - TZ1090_PIN_TFT_RED3, - TZ1090_PIN_TFT_RED4, - TZ1090_PIN_TFT_RED5, - TZ1090_PIN_TFT_RED6, - TZ1090_PIN_TFT_RED7, - TZ1090_PIN_TFT_GREEN0, - TZ1090_PIN_TFT_GREEN1, - TZ1090_PIN_TFT_GREEN2, - TZ1090_PIN_TFT_GREEN3, - TZ1090_PIN_TFT_GREEN4, - TZ1090_PIN_TFT_GREEN5, - TZ1090_PIN_TFT_GREEN6, - TZ1090_PIN_TFT_GREEN7, - TZ1090_PIN_TFT_BLUE0, - TZ1090_PIN_TFT_BLUE1, - TZ1090_PIN_TFT_BLUE2, - TZ1090_PIN_TFT_BLUE3, - TZ1090_PIN_TFT_BLUE4, - TZ1090_PIN_TFT_BLUE5, - TZ1090_PIN_TFT_BLUE6, - TZ1090_PIN_TFT_BLUE7, - TZ1090_PIN_TFT_VDDEN_GD, - TZ1090_PIN_TFT_PANELCLK, - TZ1090_PIN_TFT_BLANK_LS, - TZ1090_PIN_TFT_VSYNC_NS, - TZ1090_PIN_TFT_HSYNC_NR, - TZ1090_PIN_TFT_VD12ACB, - TZ1090_PIN_TFT_PWRSAVE, - TZ1090_PIN_TX_ON, - TZ1090_PIN_RX_ON, - TZ1090_PIN_PLL_ON, - TZ1090_PIN_PA_ON, - TZ1090_PIN_RX_HP, - TZ1090_PIN_GAIN0, - TZ1090_PIN_GAIN1, - TZ1090_PIN_GAIN2, - TZ1090_PIN_GAIN3, - TZ1090_PIN_GAIN4, - TZ1090_PIN_GAIN5, - TZ1090_PIN_GAIN6, - TZ1090_PIN_GAIN7, - TZ1090_PIN_ANT_SEL0, - TZ1090_PIN_ANT_SEL1, - TZ1090_PIN_SDH_CLK_IN, - - /* Non-GPIO pins */ - TZ1090_PIN_TCK, - TZ1090_PIN_TRST, - TZ1090_PIN_TDI, - TZ1090_PIN_TDO, - TZ1090_PIN_TMS, - TZ1090_PIN_CLK_OUT0, - TZ1090_PIN_CLK_OUT1, - - NUM_GPIOS = TZ1090_PIN_TCK, -}; - -/* Pin names */ - -static const struct pinctrl_pin_desc tz1090_pins[] = { - /* GPIO pins */ - PINCTRL_PIN(TZ1090_PIN_SDIO_CLK, "sdio_clk"), - PINCTRL_PIN(TZ1090_PIN_SDIO_CMD, "sdio_cmd"), - PINCTRL_PIN(TZ1090_PIN_SDIO_D0, "sdio_d0"), - PINCTRL_PIN(TZ1090_PIN_SDIO_D1, "sdio_d1"), - PINCTRL_PIN(TZ1090_PIN_SDIO_D2, "sdio_d2"), - PINCTRL_PIN(TZ1090_PIN_SDIO_D3, "sdio_d3"), - PINCTRL_PIN(TZ1090_PIN_SDH_CD, "sdh_cd"), - PINCTRL_PIN(TZ1090_PIN_SDH_WP, "sdh_wp"), - PINCTRL_PIN(TZ1090_PIN_SPI0_MCLK, "spi0_mclk"), - PINCTRL_PIN(TZ1090_PIN_SPI0_CS0, "spi0_cs0"), - PINCTRL_PIN(TZ1090_PIN_SPI0_CS1, "spi0_cs1"), - PINCTRL_PIN(TZ1090_PIN_SPI0_CS2, "spi0_cs2"), - PINCTRL_PIN(TZ1090_PIN_SPI0_DOUT, "spi0_dout"), - PINCTRL_PIN(TZ1090_PIN_SPI0_DIN, "spi0_din"), - PINCTRL_PIN(TZ1090_PIN_SPI1_MCLK, "spi1_mclk"), - PINCTRL_PIN(TZ1090_PIN_SPI1_CS0, "spi1_cs0"), - PINCTRL_PIN(TZ1090_PIN_SPI1_CS1, "spi1_cs1"), - PINCTRL_PIN(TZ1090_PIN_SPI1_CS2, "spi1_cs2"), - PINCTRL_PIN(TZ1090_PIN_SPI1_DOUT, "spi1_dout"), - PINCTRL_PIN(TZ1090_PIN_SPI1_DIN, "spi1_din"), - PINCTRL_PIN(TZ1090_PIN_UART0_RXD, "uart0_rxd"), - PINCTRL_PIN(TZ1090_PIN_UART0_TXD, "uart0_txd"), - PINCTRL_PIN(TZ1090_PIN_UART0_CTS, "uart0_cts"), - PINCTRL_PIN(TZ1090_PIN_UART0_RTS, "uart0_rts"), - PINCTRL_PIN(TZ1090_PIN_UART1_RXD, "uart1_rxd"), - PINCTRL_PIN(TZ1090_PIN_UART1_TXD, "uart1_txd"), - PINCTRL_PIN(TZ1090_PIN_SCB0_SDAT, "scb0_sdat"), - PINCTRL_PIN(TZ1090_PIN_SCB0_SCLK, "scb0_sclk"), - PINCTRL_PIN(TZ1090_PIN_SCB1_SDAT, "scb1_sdat"), - PINCTRL_PIN(TZ1090_PIN_SCB1_SCLK, "scb1_sclk"), - PINCTRL_PIN(TZ1090_PIN_SCB2_SDAT, "scb2_sdat"), - PINCTRL_PIN(TZ1090_PIN_SCB2_SCLK, "scb2_sclk"), - PINCTRL_PIN(TZ1090_PIN_I2S_MCLK, "i2s_mclk"), - PINCTRL_PIN(TZ1090_PIN_I2S_BCLK_OUT, "i2s_bclk_out"), - PINCTRL_PIN(TZ1090_PIN_I2S_LRCLK_OUT, "i2s_lrclk_out"), - PINCTRL_PIN(TZ1090_PIN_I2S_DOUT0, "i2s_dout0"), - PINCTRL_PIN(TZ1090_PIN_I2S_DOUT1, "i2s_dout1"), - PINCTRL_PIN(TZ1090_PIN_I2S_DOUT2, "i2s_dout2"), - PINCTRL_PIN(TZ1090_PIN_I2S_DIN, "i2s_din"), - PINCTRL_PIN(TZ1090_PIN_PDM_A, "pdm_a"), - PINCTRL_PIN(TZ1090_PIN_PDM_B, "pdm_b"), - PINCTRL_PIN(TZ1090_PIN_PDM_C, "pdm_c"), - PINCTRL_PIN(TZ1090_PIN_PDM_D, "pdm_d"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED0, "tft_red0"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED1, "tft_red1"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED2, "tft_red2"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED3, "tft_red3"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED4, "tft_red4"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED5, "tft_red5"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED6, "tft_red6"), - PINCTRL_PIN(TZ1090_PIN_TFT_RED7, "tft_red7"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN0, "tft_green0"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN1, "tft_green1"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN2, "tft_green2"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN3, "tft_green3"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN4, "tft_green4"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN5, "tft_green5"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN6, "tft_green6"), - PINCTRL_PIN(TZ1090_PIN_TFT_GREEN7, "tft_green7"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE0, "tft_blue0"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE1, "tft_blue1"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE2, "tft_blue2"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE3, "tft_blue3"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE4, "tft_blue4"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE5, "tft_blue5"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE6, "tft_blue6"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLUE7, "tft_blue7"), - PINCTRL_PIN(TZ1090_PIN_TFT_VDDEN_GD, "tft_vdden_gd"), - PINCTRL_PIN(TZ1090_PIN_TFT_PANELCLK, "tft_panelclk"), - PINCTRL_PIN(TZ1090_PIN_TFT_BLANK_LS, "tft_blank_ls"), - PINCTRL_PIN(TZ1090_PIN_TFT_VSYNC_NS, "tft_vsync_ns"), - PINCTRL_PIN(TZ1090_PIN_TFT_HSYNC_NR, "tft_hsync_nr"), - PINCTRL_PIN(TZ1090_PIN_TFT_VD12ACB, "tft_vd12acb"), - PINCTRL_PIN(TZ1090_PIN_TFT_PWRSAVE, "tft_pwrsave"), - PINCTRL_PIN(TZ1090_PIN_TX_ON, "tx_on"), - PINCTRL_PIN(TZ1090_PIN_RX_ON, "rx_on"), - PINCTRL_PIN(TZ1090_PIN_PLL_ON, "pll_on"), - PINCTRL_PIN(TZ1090_PIN_PA_ON, "pa_on"), - PINCTRL_PIN(TZ1090_PIN_RX_HP, "rx_hp"), - PINCTRL_PIN(TZ1090_PIN_GAIN0, "gain0"), - PINCTRL_PIN(TZ1090_PIN_GAIN1, "gain1"), - PINCTRL_PIN(TZ1090_PIN_GAIN2, "gain2"), - PINCTRL_PIN(TZ1090_PIN_GAIN3, "gain3"), - PINCTRL_PIN(TZ1090_PIN_GAIN4, "gain4"), - PINCTRL_PIN(TZ1090_PIN_GAIN5, "gain5"), - PINCTRL_PIN(TZ1090_PIN_GAIN6, "gain6"), - PINCTRL_PIN(TZ1090_PIN_GAIN7, "gain7"), - PINCTRL_PIN(TZ1090_PIN_ANT_SEL0, "ant_sel0"), - PINCTRL_PIN(TZ1090_PIN_ANT_SEL1, "ant_sel1"), - PINCTRL_PIN(TZ1090_PIN_SDH_CLK_IN, "sdh_clk_in"), - - /* Non-GPIO pins */ - PINCTRL_PIN(TZ1090_PIN_TCK, "tck"), - PINCTRL_PIN(TZ1090_PIN_TRST, "trst"), - PINCTRL_PIN(TZ1090_PIN_TDI, "tdi"), - PINCTRL_PIN(TZ1090_PIN_TDO, "tdo"), - PINCTRL_PIN(TZ1090_PIN_TMS, "tms"), - PINCTRL_PIN(TZ1090_PIN_CLK_OUT0, "clk_out0"), - PINCTRL_PIN(TZ1090_PIN_CLK_OUT1, "clk_out1"), -}; - -/* Pins in each pin group */ - -static const unsigned int spi1_cs2_pins[] = { - TZ1090_PIN_SPI1_CS2, -}; - -static const unsigned int pdm_d_pins[] = { - TZ1090_PIN_PDM_D, -}; - -static const unsigned int tft_pins[] = { - TZ1090_PIN_TFT_RED0, - TZ1090_PIN_TFT_RED1, - TZ1090_PIN_TFT_RED2, - TZ1090_PIN_TFT_RED3, - TZ1090_PIN_TFT_RED4, - TZ1090_PIN_TFT_RED5, - TZ1090_PIN_TFT_RED6, - TZ1090_PIN_TFT_RED7, - TZ1090_PIN_TFT_GREEN0, - TZ1090_PIN_TFT_GREEN1, - TZ1090_PIN_TFT_GREEN2, - TZ1090_PIN_TFT_GREEN3, - TZ1090_PIN_TFT_GREEN4, - TZ1090_PIN_TFT_GREEN5, - TZ1090_PIN_TFT_GREEN6, - TZ1090_PIN_TFT_GREEN7, - TZ1090_PIN_TFT_BLUE0, - TZ1090_PIN_TFT_BLUE1, - TZ1090_PIN_TFT_BLUE2, - TZ1090_PIN_TFT_BLUE3, - TZ1090_PIN_TFT_BLUE4, - TZ1090_PIN_TFT_BLUE5, - TZ1090_PIN_TFT_BLUE6, - TZ1090_PIN_TFT_BLUE7, - TZ1090_PIN_TFT_VDDEN_GD, - TZ1090_PIN_TFT_PANELCLK, - TZ1090_PIN_TFT_BLANK_LS, - TZ1090_PIN_TFT_VSYNC_NS, - TZ1090_PIN_TFT_HSYNC_NR, - TZ1090_PIN_TFT_VD12ACB, - TZ1090_PIN_TFT_PWRSAVE, -}; - -static const unsigned int afe_pins[] = { - TZ1090_PIN_TX_ON, - TZ1090_PIN_RX_ON, - TZ1090_PIN_PLL_ON, - TZ1090_PIN_PA_ON, - TZ1090_PIN_RX_HP, - TZ1090_PIN_ANT_SEL0, - TZ1090_PIN_ANT_SEL1, - TZ1090_PIN_GAIN0, - TZ1090_PIN_GAIN1, - TZ1090_PIN_GAIN2, - TZ1090_PIN_GAIN3, - TZ1090_PIN_GAIN4, - TZ1090_PIN_GAIN5, - TZ1090_PIN_GAIN6, - TZ1090_PIN_GAIN7, -}; - -static const unsigned int sdio_pins[] = { - TZ1090_PIN_SDIO_CLK, - TZ1090_PIN_SDIO_CMD, - TZ1090_PIN_SDIO_D0, - TZ1090_PIN_SDIO_D1, - TZ1090_PIN_SDIO_D2, - TZ1090_PIN_SDIO_D3, -}; - -static const unsigned int sdh_pins[] = { - TZ1090_PIN_SDH_CD, - TZ1090_PIN_SDH_WP, - TZ1090_PIN_SDH_CLK_IN, -}; - -static const unsigned int spi0_pins[] = { - TZ1090_PIN_SPI0_MCLK, - TZ1090_PIN_SPI0_CS0, - TZ1090_PIN_SPI0_CS1, - TZ1090_PIN_SPI0_CS2, - TZ1090_PIN_SPI0_DOUT, - TZ1090_PIN_SPI0_DIN, -}; - -static const unsigned int spi1_pins[] = { - TZ1090_PIN_SPI1_MCLK, - TZ1090_PIN_SPI1_CS0, - TZ1090_PIN_SPI1_CS1, - TZ1090_PIN_SPI1_CS2, - TZ1090_PIN_SPI1_DOUT, - TZ1090_PIN_SPI1_DIN, -}; - -static const unsigned int uart0_pins[] = { - TZ1090_PIN_UART0_RTS, - TZ1090_PIN_UART0_CTS, - TZ1090_PIN_UART0_TXD, - TZ1090_PIN_UART0_RXD, -}; - -static const unsigned int uart1_pins[] = { - TZ1090_PIN_UART1_TXD, - TZ1090_PIN_UART1_RXD, -}; - -static const unsigned int uart_pins[] = { - TZ1090_PIN_UART1_TXD, - TZ1090_PIN_UART1_RXD, - TZ1090_PIN_UART0_RTS, - TZ1090_PIN_UART0_CTS, - TZ1090_PIN_UART0_TXD, - TZ1090_PIN_UART0_RXD, -}; - -static const unsigned int scb0_pins[] = { - TZ1090_PIN_SCB0_SDAT, - TZ1090_PIN_SCB0_SCLK, -}; - -static const unsigned int scb1_pins[] = { - TZ1090_PIN_SCB1_SDAT, - TZ1090_PIN_SCB1_SCLK, -}; - -static const unsigned int scb2_pins[] = { - TZ1090_PIN_SCB2_SDAT, - TZ1090_PIN_SCB2_SCLK, -}; - -static const unsigned int i2s_pins[] = { - TZ1090_PIN_I2S_MCLK, - TZ1090_PIN_I2S_BCLK_OUT, - TZ1090_PIN_I2S_LRCLK_OUT, - TZ1090_PIN_I2S_DOUT0, - TZ1090_PIN_I2S_DOUT1, - TZ1090_PIN_I2S_DOUT2, - TZ1090_PIN_I2S_DIN, -}; - -static const unsigned int jtag_pins[] = { - TZ1090_PIN_TCK, - TZ1090_PIN_TRST, - TZ1090_PIN_TDI, - TZ1090_PIN_TDO, - TZ1090_PIN_TMS, -}; - -/* Pins in each drive pin group */ - -static const unsigned int drive_sdio_pins[] = { - TZ1090_PIN_SDIO_CLK, - TZ1090_PIN_SDIO_CMD, - TZ1090_PIN_SDIO_D0, - TZ1090_PIN_SDIO_D1, - TZ1090_PIN_SDIO_D2, - TZ1090_PIN_SDIO_D3, - TZ1090_PIN_SDH_WP, - TZ1090_PIN_SDH_CD, - TZ1090_PIN_SDH_CLK_IN, -}; - -static const unsigned int drive_i2s_pins[] = { - TZ1090_PIN_CLK_OUT1, - TZ1090_PIN_I2S_DIN, - TZ1090_PIN_I2S_DOUT0, - TZ1090_PIN_I2S_DOUT1, - TZ1090_PIN_I2S_DOUT2, - TZ1090_PIN_I2S_LRCLK_OUT, - TZ1090_PIN_I2S_BCLK_OUT, - TZ1090_PIN_I2S_MCLK, -}; - -static const unsigned int drive_scb0_pins[] = { - TZ1090_PIN_SCB0_SCLK, - TZ1090_PIN_SCB0_SDAT, - TZ1090_PIN_PDM_D, - TZ1090_PIN_PDM_C, -}; - -static const unsigned int drive_pdm_pins[] = { - TZ1090_PIN_CLK_OUT0, - TZ1090_PIN_PDM_B, - TZ1090_PIN_PDM_A, -}; - -/* Pin groups each function can be muxed to */ - -/* - * The magic "perip" function allows otherwise non-muxing pins to be enabled in - * peripheral mode. - */ -static const char * const perip_groups[] = { - /* non-muxing convenient gpio pingroups */ - "uart", - "uart0", - "uart1", - "spi0", - "spi1", - "scb0", - "scb1", - "scb2", - "i2s", - /* individual pins not part of a pin mux group */ - "spi0_mclk", - "spi0_cs0", - "spi0_cs1", - "spi0_cs2", - "spi0_dout", - "spi0_din", - "spi1_mclk", - "spi1_cs0", - "spi1_cs1", - "spi1_dout", - "spi1_din", - "uart0_rxd", - "uart0_txd", - "uart0_cts", - "uart0_rts", - "uart1_rxd", - "uart1_txd", - "scb0_sdat", - "scb0_sclk", - "scb1_sdat", - "scb1_sclk", - "scb2_sdat", - "scb2_sclk", - "i2s_mclk", - "i2s_bclk_out", - "i2s_lrclk_out", - "i2s_dout0", - "i2s_dout1", - "i2s_dout2", - "i2s_din", - "pdm_a", - "pdm_b", - "pdm_c", -}; - -static const char * const sdh_sdio_groups[] = { - "sdh", - "sdio", - /* sdh pins */ - "sdh_cd", - "sdh_wp", - "sdh_clk_in", - /* sdio pins */ - "sdio_clk", - "sdio_cmd", - "sdio_d0", - "sdio_d1", - "sdio_d2", - "sdio_d3", -}; - -static const char * const spi1_cs2_groups[] = { - "spi1_cs2", -}; - -static const char * const pdm_dac_groups[] = { - "pdm_d", -}; - -static const char * const usb_vbus_groups[] = { - "spi1_cs2", - "pdm_d", -}; - -static const char * const afe_groups[] = { - "afe", - /* afe pins */ - "tx_on", - "rx_on", - "pll_on", - "pa_on", - "rx_hp", - "ant_sel0", - "ant_sel1", - "gain0", - "gain1", - "gain2", - "gain3", - "gain4", - "gain5", - "gain6", - "gain7", -}; - -static const char * const tft_groups[] = { - "tft", - /* tft pins */ - "tft_red0", - "tft_red1", - "tft_red2", - "tft_red3", - "tft_red4", - "tft_red5", - "tft_red6", - "tft_red7", - "tft_green0", - "tft_green1", - "tft_green2", - "tft_green3", - "tft_green4", - "tft_green5", - "tft_green6", - "tft_green7", - "tft_blue0", - "tft_blue1", - "tft_blue2", - "tft_blue3", - "tft_blue4", - "tft_blue5", - "tft_blue6", - "tft_blue7", - "tft_vdden_gd", - "tft_panelclk", - "tft_blank_ls", - "tft_vsync_ns", - "tft_hsync_nr", - "tft_vd12acb", - "tft_pwrsave", -}; - -/* Mux functions that can be used by a mux */ - -enum tz1090_mux { - /* internal placeholder */ - TZ1090_MUX_NA = -1, - /* magic per-non-muxing-GPIO-pin peripheral mode mux */ - TZ1090_MUX_PERIP, - /* SDH/SDIO mux */ - TZ1090_MUX_SDH, - TZ1090_MUX_SDIO, - /* USB_VBUS muxes */ - TZ1090_MUX_SPI1_CS2, - TZ1090_MUX_PDM_DAC, - TZ1090_MUX_USB_VBUS, - /* AFE mux */ - TZ1090_MUX_AFE, - TZ1090_MUX_TS_OUT_0, - /* EXT_DAC mux */ - TZ1090_MUX_DAC, - TZ1090_MUX_NOT_IQADC_STB, - TZ1090_MUX_IQDAC_STB, - /* TFT mux */ - TZ1090_MUX_TFT, - TZ1090_MUX_EXT_DAC, - TZ1090_MUX_TS_OUT_1, - TZ1090_MUX_LCD_TRACE, - TZ1090_MUX_PHY_RINGOSC, -}; - -#define FUNCTION(mux, fname, group) \ - [(TZ1090_MUX_ ## mux)] = { \ - .name = #fname, \ - .groups = group##_groups, \ - .ngroups = ARRAY_SIZE(group##_groups), \ - } -/* For intermediate functions with submuxes */ -#define NULL_FUNCTION(mux, fname) \ - [(TZ1090_MUX_ ## mux)] = { \ - .name = #fname, \ - } - -/* Must correlate with enum tz1090_mux */ -static const struct tz1090_function tz1090_functions[] = { - /* FUNCTION function name pingroups */ - FUNCTION(PERIP, perip, perip), - FUNCTION(SDH, sdh, sdh_sdio), - FUNCTION(SDIO, sdio, sdh_sdio), - FUNCTION(SPI1_CS2, spi1_cs2, spi1_cs2), - FUNCTION(PDM_DAC, pdm_dac, pdm_dac), - FUNCTION(USB_VBUS, usb_vbus, usb_vbus), - FUNCTION(AFE, afe, afe), - FUNCTION(TS_OUT_0, ts_out_0, afe), - FUNCTION(DAC, ext_dac, tft), - FUNCTION(NOT_IQADC_STB, not_iqadc_stb, tft), - FUNCTION(IQDAC_STB, iqdac_stb, tft), - FUNCTION(TFT, tft, tft), - NULL_FUNCTION(EXT_DAC, _ext_dac), - FUNCTION(TS_OUT_1, ts_out_1, tft), - FUNCTION(LCD_TRACE, lcd_trace, tft), - FUNCTION(PHY_RINGOSC, phy_ringosc, tft), -}; - -/* Sub muxes */ - -/** - * MUX() - Initialise a mux description. - * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) - * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) - * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) - * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) - * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) - * @mux_r: Mux register (REG_PINCTRL_ is prepended) - * @mux_b: Bit number in register that the mux field begins - * @mux_w: Width of mux field in register - */ -#define MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \ - { \ - .funcs = { \ - TZ1090_MUX_ ## f0, \ - TZ1090_MUX_ ## f1, \ - TZ1090_MUX_ ## f2, \ - TZ1090_MUX_ ## f3, \ - TZ1090_MUX_ ## f4, \ - }, \ - .reg = (REG_PINCTRL_ ## mux_r), \ - .bit = (mux_b), \ - .width = (mux_w), \ - } - -/** - * DEFINE_SUBMUX() - Defines a submux description separate from a pin group. - * @mux: Mux name (_submux is appended) - * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) - * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) - * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) - * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) - * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) - * @mux_r: Mux register (REG_PINCTRL_ is prepended) - * @mux_b: Bit number in register that the mux field begins - * @mux_w: Width of mux field in register - * - * A sub mux is a nested mux that can be bound to a magic function number used - * by another mux description. For example value 4 of the top level mux might - * correspond to a function which has a submux pointed to in tz1090_submux[]. - * The outer mux can then take on any function in the top level mux or the - * submux, and if a submux function is chosen both muxes are updated to route - * the signal from the submux. - * - * The submux can be defined with DEFINE_SUBMUX and pointed to from - * tz1090_submux[] using SUBMUX. - */ -#define DEFINE_SUBMUX(mux, f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \ - static struct tz1090_muxdesc mux ## _submux = \ - MUX(f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) - -/** - * SUBMUX() - Link a submux to a function number. - * @f: Function name (TZ1090_MUX_ is prepended) - * @submux: Submux name (_submux is appended) - * - * For use in tz1090_submux[] initialisation to link an intermediate function - * number to a particular submux description. It indicates that when the - * function is chosen the signal is connected to the submux. - */ -#define SUBMUX(f, submux) [(TZ1090_MUX_ ## f)] = &(submux ## _submux) - -/** - * MUX_PG() - Initialise a pin group with mux control - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - * @f0: Function 0 (TZ1090_MUX_ is prepended, NA for none) - * @f1: Function 1 (TZ1090_MUX_ is prepended, NA for none) - * @f2: Function 2 (TZ1090_MUX_ is prepended, NA for none) - * @f3: Function 3 (TZ1090_MUX_ is prepended, NA for none) - * @f4: Function 4 (TZ1090_MUX_ is prepended, NA for none) - * @mux_r: Mux register (REG_PINCTRL_ is prepended) - * @mux_b: Bit number in register that the mux field begins - * @mux_w: Width of mux field in register - */ -#define MUX_PG(pg_name, f0, f1, f2, f3, f4, \ - mux_r, mux_b, mux_w) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .mux = MUX(f0, f1, f2, f3, f4, \ - mux_r, mux_b, mux_w), \ - } - -/** - * SIMPLE_PG() - Initialise a simple convenience pin group - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - * - * A simple pin group is simply used for binding pins together so they can be - * referred to by a single name instead of having to list every pin - * individually. - */ -#define SIMPLE_PG(pg_name) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - } - -/** - * DRV_PG() - Initialise a pin group with drive control - * @pg_name: Pin group name (stringified, _pins appended to get pins array) - * @slw_b: Slew register bit. - * The same bit is used for Schmitt, and Drive (*2). - */ -#define DRV_PG(pg_name, slw_b) \ - { \ - .name = #pg_name, \ - .pins = pg_name##_pins, \ - .npins = ARRAY_SIZE(pg_name##_pins), \ - .drv = true, \ - .slw_bit = (slw_b), \ - } - -/* - * Define main muxing pin groups - */ - -/* submuxes */ - -/* name f0, f1, f2, f3, f4, mux r/b/w */ -DEFINE_SUBMUX(ext_dac, DAC, NOT_IQADC_STB, IQDAC_STB, NA, NA, IF_CTL, 6, 2); - -/* bind submuxes to internal functions */ -static struct tz1090_muxdesc *tz1090_submux[] = { - SUBMUX(EXT_DAC, ext_dac), -}; - -/* - * These are the pin mux groups. Pin muxing can be enabled and disabled for each - * pin individually so these groups are internal. The mapping of pins to pin mux - * group is below (tz1090_mux_pins). - */ -static struct tz1090_pingroup tz1090_mux_groups[] = { - /* Muxing pin groups */ - /* pg_name, f0, f1, f2, f3, f4, mux r/b/w */ - MUX_PG(sdh, SDH, SDIO, NA, NA, NA, IF_CTL, 20, 2), - MUX_PG(sdio, SDIO, SDH, NA, NA, NA, IF_CTL, 16, 2), - MUX_PG(spi1_cs2, SPI1_CS2, USB_VBUS, NA, NA, NA, IF_CTL, 10, 2), - MUX_PG(pdm_d, PDM_DAC, USB_VBUS, NA, NA, NA, IF_CTL, 8, 2), - MUX_PG(afe, AFE, TS_OUT_0, NA, NA, NA, IF_CTL, 4, 2), - MUX_PG(tft, TFT, EXT_DAC, TS_OUT_1, LCD_TRACE, PHY_RINGOSC, IF_CTL, 0, 3), -}; - -/* - * This is the mapping from GPIO pins to pin mux groups in tz1090_mux_groups[]. - * Pins which aren't muxable to multiple peripherals are set to - * TZ1090_MUX_GROUP_MAX to enable the "perip" function to enable/disable - * peripheral control of the pin. - * - * This array is initialised in tz1090_init_mux_pins(). - */ -static u8 tz1090_mux_pins[NUM_GPIOS]; - -/* TZ1090_MUX_GROUP_MAX is used in tz1090_mux_pins[] for non-muxing pins */ -#define TZ1090_MUX_GROUP_MAX ARRAY_SIZE(tz1090_mux_groups) - -/** - * tz1090_init_mux_pins() - Initialise GPIO pin to mux group mapping. - * - * Initialises the tz1090_mux_pins[] array to be the inverse of the pin lists in - * each pin mux group in tz1090_mux_groups[]. - * - * It is assumed that no pin mux groups overlap (share pins). - */ -static void __init tz1090_init_mux_pins(void) -{ - unsigned int g, p; - const struct tz1090_pingroup *grp; - const unsigned int *pin; - - for (p = 0; p < NUM_GPIOS; ++p) - tz1090_mux_pins[p] = TZ1090_MUX_GROUP_MAX; - - grp = tz1090_mux_groups; - for (g = 0, grp = tz1090_mux_groups; - g < ARRAY_SIZE(tz1090_mux_groups); ++g, ++grp) - for (pin = grp->pins, p = 0; p < grp->npins; ++p, ++pin) - tz1090_mux_pins[*pin] = g; -} - -/* - * These are the externally visible pin groups. Some of them allow group control - * of drive configuration. Some are just simple convenience pingroups. All the - * internal pin mux groups in tz1090_mux_groups[] are mirrored here with the - * same pins. - * Pseudo pin groups follow in the group numbers after this array for each GPIO - * pin. Any group used for muxing must have all pins belonging to the same pin - * mux group. - */ -static struct tz1090_pingroup tz1090_groups[] = { - /* Pin groups with drive control (with no out of place pins) */ - /* pg_name, slw/schmitt/drv b */ - DRV_PG(jtag, 11 /* 11, 22 */), - DRV_PG(tft, 10 /* 10, 20 */), - DRV_PG(scb2, 9 /* 9, 18 */), - DRV_PG(spi0, 7 /* 7, 14 */), - DRV_PG(uart, 5 /* 5, 10 */), - DRV_PG(scb1, 4 /* 4, 8 */), - DRV_PG(spi1, 3 /* 3, 6 */), - DRV_PG(afe, 0 /* 0, 0 */), - - /* - * Drive specific pin groups (with odd combinations of pins which makes - * the pin group naming somewhat arbitrary) - */ - /* pg_name, slw/schmitt/drv b */ - DRV_PG(drive_sdio, 8 /* 8, 16 */), /* sdio_* + sdh_* */ - DRV_PG(drive_i2s, 6 /* 6, 12 */), /* i2s_* + clk_out1 */ - DRV_PG(drive_scb0, 2 /* 2, 4 */), /* scb0_* + pdm_{c,d} */ - DRV_PG(drive_pdm, 1 /* 1, 2 */), /* pdm_{a,b} + clk_out0 */ - - /* Convenience pin groups */ - /* pg_name */ - SIMPLE_PG(uart0), - SIMPLE_PG(uart1), - SIMPLE_PG(scb0), - SIMPLE_PG(i2s), - SIMPLE_PG(sdh), - SIMPLE_PG(sdio), - - /* pseudo-pingroups for each GPIO pin follow */ -}; - -/** - * struct tz1090_pmx - Private pinctrl data - * @dev: Platform device - * @pctl: Pin control device - * @regs: Register region - * @lock: Lock protecting coherency of pin_en, gpio_en, and SELECT regs - * @pin_en: Pins that have been enabled (32 pins packed into each element) - * @gpio_en: GPIOs that have been enabled (32 pins packed into each element) - */ -struct tz1090_pmx { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *regs; - spinlock_t lock; - u32 pin_en[3]; - u32 gpio_en[3]; -}; - -static inline u32 pmx_read(struct tz1090_pmx *pmx, u32 reg) -{ - return ioread32(pmx->regs + reg); -} - -static inline void pmx_write(struct tz1090_pmx *pmx, u32 val, u32 reg) -{ - iowrite32(val, pmx->regs + reg); -} - -/* - * Pin control operations - */ - -/* each GPIO pin has it's own pseudo pingroup containing only itself */ - -static int tz1090_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(tz1090_groups) + NUM_GPIOS; -} - -static const char *tz1090_pinctrl_get_group_name(struct pinctrl_dev *pctldev, - unsigned int group) -{ - if (group < ARRAY_SIZE(tz1090_groups)) { - /* normal pingroup */ - return tz1090_groups[group].name; - } else { - /* individual gpio pin pseudo-pingroup */ - unsigned int pin = group - ARRAY_SIZE(tz1090_groups); - return tz1090_pins[pin].name; - } -} - -static int tz1090_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, - unsigned int group, - const unsigned int **pins, - unsigned int *num_pins) -{ - if (group < ARRAY_SIZE(tz1090_groups)) { - /* normal pingroup */ - *pins = tz1090_groups[group].pins; - *num_pins = tz1090_groups[group].npins; - } else { - /* individual gpio pin pseudo-pingroup */ - unsigned int pin = group - ARRAY_SIZE(tz1090_groups); - *pins = &tz1090_pins[pin].number; - *num_pins = 1; - } - - return 0; -} - -#ifdef CONFIG_DEBUG_FS -static void tz1090_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, - struct seq_file *s, - unsigned int offset) -{ - seq_printf(s, " %s", dev_name(pctldev->dev)); -} -#endif - -static int reserve_map(struct device *dev, struct pinctrl_map **map, - unsigned int *reserved_maps, unsigned int *num_maps, - unsigned int reserve) -{ - unsigned int old_num = *reserved_maps; - unsigned int new_num = *num_maps + reserve; - struct pinctrl_map *new_map; - - if (old_num >= new_num) - return 0; - - new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); - if (!new_map) { - dev_err(dev, "krealloc(map) failed\n"); - return -ENOMEM; - } - - memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); - - *map = new_map; - *reserved_maps = new_num; - - return 0; -} - -static int add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps, - unsigned int *num_maps, const char *group, - const char *function) -{ - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; - (*map)[*num_maps].data.mux.group = group; - (*map)[*num_maps].data.mux.function = function; - (*num_maps)++; - - return 0; -} - -static int add_map_configs(struct device *dev, - struct pinctrl_map **map, - unsigned int *reserved_maps, unsigned int *num_maps, - const char *group, unsigned long *configs, - unsigned int num_configs) -{ - unsigned long *dup_configs; - - if (WARN_ON(*num_maps == *reserved_maps)) - return -ENOSPC; - - dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), - GFP_KERNEL); - if (!dup_configs) - return -ENOMEM; - - (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; - (*map)[*num_maps].data.configs.group_or_pin = group; - (*map)[*num_maps].data.configs.configs = dup_configs; - (*map)[*num_maps].data.configs.num_configs = num_configs; - (*num_maps)++; - - return 0; -} - -static void tz1090_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, - struct pinctrl_map *map, - unsigned int num_maps) -{ - int i; - - for (i = 0; i < num_maps; i++) - if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP) - kfree(map[i].data.configs.configs); - - kfree(map); -} - -static int tz1090_pinctrl_dt_subnode_to_map(struct device *dev, - struct device_node *np, - struct pinctrl_map **map, - unsigned int *reserved_maps, - unsigned int *num_maps) -{ - int ret; - const char *function; - unsigned long *configs = NULL; - unsigned int num_configs = 0; - unsigned int reserve; - struct property *prop; - const char *group; - - ret = of_property_read_string(np, "tz1090,function", &function); - if (ret < 0) { - /* EINVAL=missing, which is fine since it's optional */ - if (ret != -EINVAL) - dev_err(dev, "could not parse property function\n"); - function = NULL; - } - - ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); - if (ret) - return ret; - - reserve = 0; - if (function != NULL) - reserve++; - if (num_configs) - reserve++; - ret = of_property_count_strings(np, "tz1090,pins"); - if (ret < 0) { - dev_err(dev, "could not parse property pins\n"); - goto exit; - } - reserve *= ret; - - ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); - if (ret < 0) - goto exit; - - of_property_for_each_string(np, "tz1090,pins", prop, group) { - if (function) { - ret = add_map_mux(map, reserved_maps, num_maps, - group, function); - if (ret < 0) - goto exit; - } - - if (num_configs) { - ret = add_map_configs(dev, map, reserved_maps, - num_maps, group, configs, - num_configs); - if (ret < 0) - goto exit; - } - } - - ret = 0; - -exit: - kfree(configs); - return ret; -} - -static int tz1090_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - unsigned int *num_maps) -{ - unsigned int reserved_maps; - struct device_node *np; - int ret; - - reserved_maps = 0; - *map = NULL; - *num_maps = 0; - - for_each_child_of_node(np_config, np) { - ret = tz1090_pinctrl_dt_subnode_to_map(pctldev->dev, np, map, - &reserved_maps, - num_maps); - if (ret < 0) { - tz1090_pinctrl_dt_free_map(pctldev, *map, *num_maps); - return ret; - } - } - - return 0; -} - -static const struct pinctrl_ops tz1090_pinctrl_ops = { - .get_groups_count = tz1090_pinctrl_get_groups_count, - .get_group_name = tz1090_pinctrl_get_group_name, - .get_group_pins = tz1090_pinctrl_get_group_pins, -#ifdef CONFIG_DEBUG_FS - .pin_dbg_show = tz1090_pinctrl_pin_dbg_show, -#endif - .dt_node_to_map = tz1090_pinctrl_dt_node_to_map, - .dt_free_map = tz1090_pinctrl_dt_free_map, -}; - -/* - * Pin mux operations - */ - -static int tz1090_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(tz1090_functions); -} - -static const char *tz1090_pinctrl_get_func_name(struct pinctrl_dev *pctldev, - unsigned int function) -{ - return tz1090_functions[function].name; -} - -static int tz1090_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, - unsigned int function, - const char * const **groups, - unsigned int * const num_groups) -{ - /* pingroup functions */ - *groups = tz1090_functions[function].groups; - *num_groups = tz1090_functions[function].ngroups; - return 0; -} - -/** - * tz1090_pinctrl_select() - update bit in SELECT register - * @pmx: Pinmux data - * @pin: Pin number (must be within GPIO range) - */ -static void tz1090_pinctrl_select(struct tz1090_pmx *pmx, - unsigned int pin) -{ - u32 reg, reg_shift, select, val; - unsigned int pmx_index, pmx_shift; - unsigned long flags; - - /* uses base 32 instead of base 30 */ - pmx_index = pin >> 5; - pmx_shift = pin & 0x1f; - - /* select = !perip || gpio */ - select = ((~pmx->pin_en[pmx_index] | - pmx->gpio_en[pmx_index]) >> pmx_shift) & 1; - - /* find register and bit offset (base 30) */ - reg = REG_PINCTRL_SELECT + 4*(pin / 30); - reg_shift = pin % 30; - - /* modify gpio select bit */ - __global_lock2(flags); - val = pmx_read(pmx, reg); - val &= ~BIT(reg_shift); - val |= select << reg_shift; - pmx_write(pmx, val, reg); - __global_unlock2(flags); -} - -/** - * tz1090_pinctrl_gpio_select() - enable/disable GPIO usage for a pin - * @pmx: Pinmux data - * @pin: Pin number - * @gpio_select: true to enable pin as GPIO, - * false to leave control to whatever function is enabled - * - * Records that GPIO usage is enabled/disabled so that enabling a function - * doesn't override the SELECT register bit. - */ -static void tz1090_pinctrl_gpio_select(struct tz1090_pmx *pmx, - unsigned int pin, - bool gpio_select) -{ - unsigned int index, shift; - u32 gpio_en; - - if (pin >= NUM_GPIOS) - return; - - /* uses base 32 instead of base 30 */ - index = pin >> 5; - shift = pin & 0x1f; - - spin_lock(&pmx->lock); - - /* keep a record whether gpio is selected */ - gpio_en = pmx->gpio_en[index]; - gpio_en &= ~BIT(shift); - if (gpio_select) - gpio_en |= BIT(shift); - pmx->gpio_en[index] = gpio_en; - - /* update the select bit */ - tz1090_pinctrl_select(pmx, pin); - - spin_unlock(&pmx->lock); -} - -/** - * tz1090_pinctrl_perip_select() - enable/disable peripheral interface for a pin - * @pmx: Pinmux data - * @pin: Pin number - * @perip_select: true to enable peripheral interface when not GPIO, - * false to leave pin in GPIO mode - * - * Records that peripheral usage is enabled/disabled so that SELECT register can - * be set appropriately when GPIO is disabled. - */ -static void tz1090_pinctrl_perip_select(struct tz1090_pmx *pmx, - unsigned int pin, - bool perip_select) -{ - unsigned int index, shift; - u32 pin_en; - - if (pin >= NUM_GPIOS) - return; - - /* uses base 32 instead of base 30 */ - index = pin >> 5; - shift = pin & 0x1f; - - spin_lock(&pmx->lock); - - /* keep a record whether peripheral is selected */ - pin_en = pmx->pin_en[index]; - pin_en &= ~BIT(shift); - if (perip_select) - pin_en |= BIT(shift); - pmx->pin_en[index] = pin_en; - - /* update the select bit */ - tz1090_pinctrl_select(pmx, pin); - - spin_unlock(&pmx->lock); -} - -/** - * tz1090_pinctrl_enable_mux() - Switch a pin mux group to a function. - * @pmx: Pinmux data - * @desc: Pinmux description - * @function: Function to switch to - * - * Enable a particular function on a pin mux group. Since pin mux descriptions - * are nested this function is recursive. - */ -static int tz1090_pinctrl_enable_mux(struct tz1090_pmx *pmx, - const struct tz1090_muxdesc *desc, - unsigned int function) -{ - const int *fit; - unsigned long flags; - int mux; - unsigned int func, ret; - u32 reg, mask; - - /* find the mux value for this function, searching recursively */ - for (mux = 0, fit = desc->funcs; - mux < ARRAY_SIZE(desc->funcs); ++mux, ++fit) { - func = *fit; - if (func == function) - goto found_mux; - - /* maybe it's a sub-mux */ - if (func < ARRAY_SIZE(tz1090_submux) && tz1090_submux[func]) { - ret = tz1090_pinctrl_enable_mux(pmx, - tz1090_submux[func], - function); - if (!ret) - goto found_mux; - } - } - - return -EINVAL; -found_mux: - - /* Set up the mux */ - if (desc->width) { - mask = (BIT(desc->width) - 1) << desc->bit; - __global_lock2(flags); - reg = pmx_read(pmx, desc->reg); - reg &= ~mask; - reg |= (mux << desc->bit) & mask; - pmx_write(pmx, reg, desc->reg); - __global_unlock2(flags); - } - - return 0; -} - -/** - * tz1090_pinctrl_enable() - Enable a function on a pin group. - * @pctldev: Pin control data - * @function: Function index to enable - * @group: Group index to enable - * - * Enable a particular function on a group of pins. The per GPIO pin pseudo pin - * groups can be used (in which case the pin will be enabled in peripheral mode - * and if it belongs to a pin mux group the mux will be switched if it isn't - * already in use. Some convenience pin groups can also be used in which case - * the effect is the same as enabling the function on each individual pin in the - * group. - */ -static int tz1090_pinctrl_set_mux(struct pinctrl_dev *pctldev, - unsigned int function, unsigned int group) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - struct tz1090_pingroup *grp; - int ret; - unsigned int pin_num, mux_group, i, npins; - const unsigned int *pins; - - /* group of pins? */ - if (group < ARRAY_SIZE(tz1090_groups)) { - grp = &tz1090_groups[group]; - npins = grp->npins; - pins = grp->pins; - /* - * All pins in the group must belong to the same mux group, - * which allows us to just use the mux group of the first pin. - * By explicitly listing permitted pingroups for each function - * the pinmux core should ensure this is always the case. - */ - } else { - pin_num = group - ARRAY_SIZE(tz1090_groups); - npins = 1; - pins = &pin_num; - } - mux_group = tz1090_mux_pins[*pins]; - - /* no mux group, but can still be individually muxed to peripheral */ - if (mux_group >= TZ1090_MUX_GROUP_MAX) { - if (function == TZ1090_MUX_PERIP) - goto mux_pins; - return -EINVAL; - } - - /* mux group already set to a different function? */ - grp = &tz1090_mux_groups[mux_group]; - if (grp->func_count && grp->func != function) { - dev_err(pctldev->dev, - "%s: can't mux pin(s) to '%s', group already muxed to '%s'\n", - __func__, tz1090_functions[function].name, - tz1090_functions[grp->func].name); - return -EBUSY; - } - - dev_dbg(pctldev->dev, "%s: muxing %u pin(s) in '%s' to '%s'\n", - __func__, npins, grp->name, tz1090_functions[function].name); - - /* if first pin in mux group to be enabled, enable the group mux */ - if (!grp->func_count) { - grp->func = function; - ret = tz1090_pinctrl_enable_mux(pmx, &grp->mux, function); - if (ret) - return ret; - } - /* add pins to ref count and mux individually to peripheral */ - grp->func_count += npins; -mux_pins: - for (i = 0; i < npins; ++i) - tz1090_pinctrl_perip_select(pmx, pins[i], true); - - return 0; -} - -/** - * tz1090_pinctrl_gpio_request_enable() - Put pin in GPIO mode. - * @pctldev: Pin control data - * @range: GPIO range - * @pin: Pin number - * - * Puts a particular pin into GPIO mode, disabling peripheral control until it's - * disabled again. - */ -static int tz1090_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - tz1090_pinctrl_gpio_select(pmx, pin, true); - return 0; -} - -/** - * tz1090_pinctrl_gpio_disable_free() - Take pin out of GPIO mode. - * @pctldev: Pin control data - * @range: GPIO range - * @pin: Pin number - * - * Take a particular pin out of GPIO mode. If the pin is enabled for a - * peripheral it will return to peripheral mode. - */ -static void tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int pin) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - tz1090_pinctrl_gpio_select(pmx, pin, false); -} - -static const struct pinmux_ops tz1090_pinmux_ops = { - .get_functions_count = tz1090_pinctrl_get_funcs_count, - .get_function_name = tz1090_pinctrl_get_func_name, - .get_function_groups = tz1090_pinctrl_get_func_groups, - .set_mux = tz1090_pinctrl_set_mux, - .gpio_request_enable = tz1090_pinctrl_gpio_request_enable, - .gpio_disable_free = tz1090_pinctrl_gpio_disable_free, -}; - -/* - * Pin config operations - */ - -struct tz1090_pinconf_pullup { - unsigned char index; - unsigned char shift; -}; - -/* The mapping of pin to pull up/down register index and shift */ -static struct tz1090_pinconf_pullup tz1090_pinconf_pullup[] = { - {5, 22}, /* 0 - TZ1090_PIN_SDIO_CLK */ - {0, 14}, /* 1 - TZ1090_PIN_SDIO_CMD */ - {0, 6}, /* 2 - TZ1090_PIN_SDIO_D0 */ - {0, 8}, /* 3 - TZ1090_PIN_SDIO_D1 */ - {0, 10}, /* 4 - TZ1090_PIN_SDIO_D2 */ - {0, 12}, /* 5 - TZ1090_PIN_SDIO_D3 */ - {0, 2}, /* 6 - TZ1090_PIN_SDH_CD */ - {0, 4}, /* 7 - TZ1090_PIN_SDH_WP */ - {0, 16}, /* 8 - TZ1090_PIN_SPI0_MCLK */ - {0, 18}, /* 9 - TZ1090_PIN_SPI0_CS0 */ - {0, 20}, /* 10 - TZ1090_PIN_SPI0_CS1 */ - {0, 22}, /* 11 - TZ1090_PIN_SPI0_CS2 */ - {0, 24}, /* 12 - TZ1090_PIN_SPI0_DOUT */ - {0, 26}, /* 13 - TZ1090_PIN_SPI0_DIN */ - {0, 28}, /* 14 - TZ1090_PIN_SPI1_MCLK */ - {0, 30}, /* 15 - TZ1090_PIN_SPI1_CS0 */ - {1, 0}, /* 16 - TZ1090_PIN_SPI1_CS1 */ - {1, 2}, /* 17 - TZ1090_PIN_SPI1_CS2 */ - {1, 4}, /* 18 - TZ1090_PIN_SPI1_DOUT */ - {1, 6}, /* 19 - TZ1090_PIN_SPI1_DIN */ - {1, 8}, /* 20 - TZ1090_PIN_UART0_RXD */ - {1, 10}, /* 21 - TZ1090_PIN_UART0_TXD */ - {1, 12}, /* 22 - TZ1090_PIN_UART0_CTS */ - {1, 14}, /* 23 - TZ1090_PIN_UART0_RTS */ - {1, 16}, /* 24 - TZ1090_PIN_UART1_RXD */ - {1, 18}, /* 25 - TZ1090_PIN_UART1_TXD */ - {1, 20}, /* 26 - TZ1090_PIN_SCB0_SDAT */ - {1, 22}, /* 27 - TZ1090_PIN_SCB0_SCLK */ - {1, 24}, /* 28 - TZ1090_PIN_SCB1_SDAT */ - {1, 26}, /* 29 - TZ1090_PIN_SCB1_SCLK */ - - {1, 28}, /* 30 - TZ1090_PIN_SCB2_SDAT */ - {1, 30}, /* 31 - TZ1090_PIN_SCB2_SCLK */ - {2, 0}, /* 32 - TZ1090_PIN_I2S_MCLK */ - {2, 2}, /* 33 - TZ1090_PIN_I2S_BCLK_OUT */ - {2, 4}, /* 34 - TZ1090_PIN_I2S_LRCLK_OUT */ - {2, 6}, /* 35 - TZ1090_PIN_I2S_DOUT0 */ - {2, 8}, /* 36 - TZ1090_PIN_I2S_DOUT1 */ - {2, 10}, /* 37 - TZ1090_PIN_I2S_DOUT2 */ - {2, 12}, /* 38 - TZ1090_PIN_I2S_DIN */ - {4, 12}, /* 39 - TZ1090_PIN_PDM_A */ - {4, 14}, /* 40 - TZ1090_PIN_PDM_B */ - {4, 18}, /* 41 - TZ1090_PIN_PDM_C */ - {4, 20}, /* 42 - TZ1090_PIN_PDM_D */ - {2, 14}, /* 43 - TZ1090_PIN_TFT_RED0 */ - {2, 16}, /* 44 - TZ1090_PIN_TFT_RED1 */ - {2, 18}, /* 45 - TZ1090_PIN_TFT_RED2 */ - {2, 20}, /* 46 - TZ1090_PIN_TFT_RED3 */ - {2, 22}, /* 47 - TZ1090_PIN_TFT_RED4 */ - {2, 24}, /* 48 - TZ1090_PIN_TFT_RED5 */ - {2, 26}, /* 49 - TZ1090_PIN_TFT_RED6 */ - {2, 28}, /* 50 - TZ1090_PIN_TFT_RED7 */ - {2, 30}, /* 51 - TZ1090_PIN_TFT_GREEN0 */ - {3, 0}, /* 52 - TZ1090_PIN_TFT_GREEN1 */ - {3, 2}, /* 53 - TZ1090_PIN_TFT_GREEN2 */ - {3, 4}, /* 54 - TZ1090_PIN_TFT_GREEN3 */ - {3, 6}, /* 55 - TZ1090_PIN_TFT_GREEN4 */ - {3, 8}, /* 56 - TZ1090_PIN_TFT_GREEN5 */ - {3, 10}, /* 57 - TZ1090_PIN_TFT_GREEN6 */ - {3, 12}, /* 58 - TZ1090_PIN_TFT_GREEN7 */ - {3, 14}, /* 59 - TZ1090_PIN_TFT_BLUE0 */ - - {3, 16}, /* 60 - TZ1090_PIN_TFT_BLUE1 */ - {3, 18}, /* 61 - TZ1090_PIN_TFT_BLUE2 */ - {3, 20}, /* 62 - TZ1090_PIN_TFT_BLUE3 */ - {3, 22}, /* 63 - TZ1090_PIN_TFT_BLUE4 */ - {3, 24}, /* 64 - TZ1090_PIN_TFT_BLUE5 */ - {3, 26}, /* 65 - TZ1090_PIN_TFT_BLUE6 */ - {3, 28}, /* 66 - TZ1090_PIN_TFT_BLUE7 */ - {3, 30}, /* 67 - TZ1090_PIN_TFT_VDDEN_GD */ - {4, 0}, /* 68 - TZ1090_PIN_TFT_PANELCLK */ - {4, 2}, /* 69 - TZ1090_PIN_TFT_BLANK_LS */ - {4, 4}, /* 70 - TZ1090_PIN_TFT_VSYNC_NS */ - {4, 6}, /* 71 - TZ1090_PIN_TFT_HSYNC_NR */ - {4, 8}, /* 72 - TZ1090_PIN_TFT_VD12ACB */ - {4, 10}, /* 73 - TZ1090_PIN_TFT_PWRSAVE */ - {4, 24}, /* 74 - TZ1090_PIN_TX_ON */ - {4, 26}, /* 75 - TZ1090_PIN_RX_ON */ - {4, 28}, /* 76 - TZ1090_PIN_PLL_ON */ - {4, 30}, /* 77 - TZ1090_PIN_PA_ON */ - {5, 0}, /* 78 - TZ1090_PIN_RX_HP */ - {5, 6}, /* 79 - TZ1090_PIN_GAIN0 */ - {5, 8}, /* 80 - TZ1090_PIN_GAIN1 */ - {5, 10}, /* 81 - TZ1090_PIN_GAIN2 */ - {5, 12}, /* 82 - TZ1090_PIN_GAIN3 */ - {5, 14}, /* 83 - TZ1090_PIN_GAIN4 */ - {5, 16}, /* 84 - TZ1090_PIN_GAIN5 */ - {5, 18}, /* 85 - TZ1090_PIN_GAIN6 */ - {5, 20}, /* 86 - TZ1090_PIN_GAIN7 */ - {5, 2}, /* 87 - TZ1090_PIN_ANT_SEL0 */ - {5, 4}, /* 88 - TZ1090_PIN_ANT_SEL1 */ - {0, 0}, /* 89 - TZ1090_PIN_SDH_CLK_IN */ - - {5, 24}, /* 90 - TZ1090_PIN_TCK */ - {5, 26}, /* 91 - TZ1090_PIN_TRST */ - {5, 28}, /* 92 - TZ1090_PIN_TDI */ - {5, 30}, /* 93 - TZ1090_PIN_TDO */ - {6, 0}, /* 94 - TZ1090_PIN_TMS */ - {4, 16}, /* 95 - TZ1090_PIN_CLK_OUT0 */ - {4, 22}, /* 96 - TZ1090_PIN_CLK_OUT1 */ -}; - -static int tz1090_pinconf_reg(struct pinctrl_dev *pctldev, - unsigned int pin, - enum pin_config_param param, - bool report_err, - u32 *reg, u32 *width, u32 *mask, u32 *shift, - u32 *val) -{ - struct tz1090_pinconf_pullup *pu; - - /* All supported pins have controllable input bias */ - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: - case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: - *val = REG_PU_PD_TRISTATE; - break; - case PIN_CONFIG_BIAS_PULL_UP: - *val = REG_PU_PD_UP; - break; - case PIN_CONFIG_BIAS_PULL_DOWN: - *val = REG_PU_PD_DOWN; - break; - case PIN_CONFIG_BIAS_BUS_HOLD: - *val = REG_PU_PD_REPEATER; - break; - default: - return -ENOTSUPP; - } - - /* Only input bias parameters supported */ - pu = &tz1090_pinconf_pullup[pin]; - *reg = REG_PINCTRL_PU_PD + 4*pu->index; - *shift = pu->shift; - *width = 2; - - /* Calculate field information */ - *mask = (BIT(*width) - 1) << *shift; - - return 0; -} - -static int tz1090_pinconf_get(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *config) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param = pinconf_to_config_param(*config); - int ret; - u32 reg, width, mask, shift, val, tmp, arg; - - /* Get register information */ - ret = tz1090_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; - - /* Extract field from register */ - tmp = pmx_read(pmx, reg); - arg = ((tmp & mask) >> shift) == val; - - /* Config not active */ - if (!arg) - return -EINVAL; - - /* And pack config */ - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int tz1090_pinconf_set(struct pinctrl_dev *pctldev, - unsigned int pin, unsigned long *configs, - unsigned num_configs) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - enum pin_config_param param; - unsigned int arg; - int ret; - u32 reg, width, mask, shift, val, tmp; - unsigned long flags; - int i; - - for (i = 0; i < num_configs; i++) { - param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); - - dev_dbg(pctldev->dev, "%s(pin=%s, config=%#lx)\n", - __func__, tz1090_pins[pin].name, configs[i]); - - /* Get register information */ - ret = tz1090_pinconf_reg(pctldev, pin, param, true, - ®, &width, &mask, &shift, &val); - if (ret < 0) - return ret; - - /* Unpack argument and range check it */ - if (arg > 1) { - dev_dbg(pctldev->dev, "%s: arg %u out of range\n", - __func__, arg); - return -EINVAL; - } - - /* Write register field */ - __global_lock2(flags); - tmp = pmx_read(pmx, reg); - tmp &= ~mask; - if (arg) - tmp |= val << shift; - pmx_write(pmx, tmp, reg); - __global_unlock2(flags); - } /* for each config */ - - return 0; -} - -static const int tz1090_boolean_map[] = { - [0] = -EINVAL, - [1] = 1, -}; - -static const int tz1090_dr_map[] = { - [REG_DR_2mA] = 2, - [REG_DR_4mA] = 4, - [REG_DR_8mA] = 8, - [REG_DR_12mA] = 12, -}; - -static int tz1090_pinconf_group_reg(struct pinctrl_dev *pctldev, - const struct tz1090_pingroup *g, - enum pin_config_param param, - bool report_err, - u32 *reg, u32 *width, u32 *mask, u32 *shift, - const int **map) -{ - /* Drive configuration applies in groups, but not to all groups. */ - if (!g->drv) { - if (report_err) - dev_dbg(pctldev->dev, - "%s: group %s has no drive control\n", - __func__, g->name); - return -ENOTSUPP; - } - - /* Find information about drive parameter's register */ - switch (param) { - case PIN_CONFIG_INPUT_SCHMITT_ENABLE: - *reg = REG_PINCTRL_SCHMITT; - *width = 1; - *map = tz1090_boolean_map; - break; - case PIN_CONFIG_DRIVE_STRENGTH: - *reg = REG_PINCTRL_DR; - *width = 2; - *map = tz1090_dr_map; - break; - default: - return -ENOTSUPP; - } - - /* Calculate field information */ - *shift = g->slw_bit * *width; - *mask = (BIT(*width) - 1) << *shift; - - return 0; -} - -static int tz1090_pinconf_group_get(struct pinctrl_dev *pctldev, - unsigned int group, - unsigned long *config) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pingroup *g; - enum pin_config_param param = pinconf_to_config_param(*config); - int ret, arg; - unsigned int pin; - u32 reg, width, mask, shift, val; - const int *map; - - if (group >= ARRAY_SIZE(tz1090_groups)) { - pin = group - ARRAY_SIZE(tz1090_groups); - return tz1090_pinconf_get(pctldev, pin, config); - } - - g = &tz1090_groups[group]; - if (g->npins == 1) { - pin = g->pins[0]; - ret = tz1090_pinconf_get(pctldev, pin, config); - if (ret != -ENOTSUPP) - return ret; - } - - /* Get register information */ - ret = tz1090_pinconf_group_reg(pctldev, g, param, true, - ®, &width, &mask, &shift, &map); - if (ret < 0) - return ret; - - /* Extract field from register */ - val = pmx_read(pmx, reg); - arg = map[(val & mask) >> shift]; - if (arg < 0) - return arg; - - /* And pack config */ - *config = pinconf_to_config_packed(param, arg); - - return 0; -} - -static int tz1090_pinconf_group_set(struct pinctrl_dev *pctldev, - unsigned int group, unsigned long *configs, - unsigned num_configs) -{ - struct tz1090_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); - const struct tz1090_pingroup *g; - enum pin_config_param param; - unsigned int arg, pin, i; - const unsigned int *pit; - int ret; - u32 reg, width, mask, shift, val; - unsigned long flags; - const int *map; - int j; - - if (group >= ARRAY_SIZE(tz1090_groups)) { - pin = group - ARRAY_SIZE(tz1090_groups); - return tz1090_pinconf_set(pctldev, pin, configs, num_configs); - } - - g = &tz1090_groups[group]; - if (g->npins == 1) { - pin = g->pins[0]; - ret = tz1090_pinconf_set(pctldev, pin, configs, num_configs); - if (ret != -ENOTSUPP) - return ret; - } - - for (j = 0; j < num_configs; j++) { - param = pinconf_to_config_param(configs[j]); - - dev_dbg(pctldev->dev, "%s(group=%s, config=%#lx)\n", - __func__, g->name, configs[j]); - - /* Get register information */ - ret = tz1090_pinconf_group_reg(pctldev, g, param, true, ®, - &width, &mask, &shift, &map); - if (ret < 0) { - /* - * Maybe we're trying to set a per-pin configuration - * of a group, so do the pins one by one. This is - * mainly as a convenience. - */ - for (i = 0, pit = g->pins; i < g->npins; ++i, ++pit) { - ret = tz1090_pinconf_set(pctldev, *pit, configs, - num_configs); - if (ret) - return ret; - } - return 0; - } - - /* Unpack argument and map it to register value */ - arg = pinconf_to_config_argument(configs[j]); - for (i = 0; i < BIT(width); ++i) { - if (map[i] == arg || (map[i] == -EINVAL && !arg)) { - /* Write register field */ - __global_lock2(flags); - val = pmx_read(pmx, reg); - val &= ~mask; - val |= i << shift; - pmx_write(pmx, val, reg); - __global_unlock2(flags); - goto next_config; - } - } - - dev_dbg(pctldev->dev, "%s: arg %u not supported\n", - __func__, arg); - return -EINVAL; - -next_config: - ; - } /* for each config */ - - return 0; -} - -static const struct pinconf_ops tz1090_pinconf_ops = { - .is_generic = true, - .pin_config_get = tz1090_pinconf_get, - .pin_config_set = tz1090_pinconf_set, - .pin_config_group_get = tz1090_pinconf_group_get, - .pin_config_group_set = tz1090_pinconf_group_set, - .pin_config_config_dbg_show = pinconf_generic_dump_config, -}; - -/* - * Pin control driver setup - */ - -static struct pinctrl_desc tz1090_pinctrl_desc = { - .pctlops = &tz1090_pinctrl_ops, - .pmxops = &tz1090_pinmux_ops, - .confops = &tz1090_pinconf_ops, - .owner = THIS_MODULE, -}; - -static int tz1090_pinctrl_probe(struct platform_device *pdev) -{ - struct tz1090_pmx *pmx; - struct resource *res; - - pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); - if (!pmx) - return -ENOMEM; - - pmx->dev = &pdev->dev; - spin_lock_init(&pmx->lock); - - tz1090_pinctrl_desc.name = dev_name(&pdev->dev); - tz1090_pinctrl_desc.pins = tz1090_pins; - tz1090_pinctrl_desc.npins = ARRAY_SIZE(tz1090_pins); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pmx->regs = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(pmx->regs)) - return PTR_ERR(pmx->regs); - - pmx->pctl = devm_pinctrl_register(&pdev->dev, &tz1090_pinctrl_desc, - pmx); - if (IS_ERR(pmx->pctl)) { - dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); - return PTR_ERR(pmx->pctl); - } - - platform_set_drvdata(pdev, pmx); - - dev_info(&pdev->dev, "TZ1090 pinctrl driver initialised\n"); - - return 0; -} - -static const struct of_device_id tz1090_pinctrl_of_match[] = { - { .compatible = "img,tz1090-pinctrl", }, - { }, -}; - -static struct platform_driver tz1090_pinctrl_driver = { - .driver = { - .name = "tz1090-pinctrl", - .of_match_table = tz1090_pinctrl_of_match, - }, - .probe = tz1090_pinctrl_probe, -}; - -static int __init tz1090_pinctrl_init(void) -{ - tz1090_init_mux_pins(); - return platform_driver_register(&tz1090_pinctrl_driver); -} -arch_initcall(tz1090_pinctrl_init); - -static void __exit tz1090_pinctrl_exit(void) -{ - platform_driver_unregister(&tz1090_pinctrl_driver); -} -module_exit(tz1090_pinctrl_exit); - -MODULE_AUTHOR("Imagination Technologies Ltd."); -MODULE_DESCRIPTION("Toumaz Xenif TZ1090 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, tz1090_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index fcaaa92d76df..195492033075 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -147,4 +147,13 @@ config PINCTRL_QCOM_SSBI_PMIC which are using SSBI for communication with SoC. Example PMIC's devices are pm8058 and pm8921. +config PINCTRL_SDM845 + tristate "Qualcomm Technologies Inc SDM845 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SDM845 platform. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 8cb45bbd2e7f..0c6f3ddc296d 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -19,3 +19,4 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o +obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 495432f3341b..95e5c5ea40af 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -818,7 +818,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) return -EINVAL; chip = &pctrl->chip; - chip->base = 0; + chip->base = -1; chip->ngpio = ngpio; chip->label = dev_name(pctrl->dev); chip->parent = pctrl->dev; diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c new file mode 100644 index 000000000000..2ab7a8885757 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -0,0 +1,1323 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define NORTH 0x00500000 +#define SOUTH 0x00900000 +#define EAST 0x00100000 +#define REG_SIZE 0x1000 +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9, \ + msm_mux_##f10 \ + }, \ + .nfuncs = 11, \ + .ctl_reg = base + REG_SIZE * id, \ + .io_reg = base + 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ + .intr_status_reg = base + 0xc + REG_SIZE * id, \ + .intr_target_reg = base + 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sdm845_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "SDC2_CLK"), + PINCTRL_PIN(151, "SDC2_CMD"), + PINCTRL_PIN(152, "SDC2_DATA"), + PINCTRL_PIN(153, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); + +static const unsigned int sdc2_clk_pins[] = { 150 }; +static const unsigned int sdc2_cmd_pins[] = { 151 }; +static const unsigned int sdc2_data_pins[] = { 152 }; +static const unsigned int ufs_reset_pins[] = { 153 }; + +enum sdm845_functions { + msm_mux_gpio, + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_atest_char, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb2, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_audio_ref, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_edp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_slimbus, + msm_mux_m_voc, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mss_lte, + msm_mux_nav_pps, + msm_mux_pa_indicator, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data, + msm_mux_qua_mi2s, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sdc4_data, + msm_mux_sec_mi2s, + msm_mux_sp_cmu, + msm_mux_spkr_i2s, + msm_mux_ter_mi2s, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_tsif2_clk, + msm_mux_tsif2_data, + msm_mux_tsif2_en, + msm_mux_tsif2_error, + msm_mux_tsif2_sync, + msm_mux_uim1_clk, + msm_mux_uim1_data, + msm_mux_uim1_present, + msm_mux_uim1_reset, + msm_mux_uim2_clk, + msm_mux_uim2_data, + msm_mux_uim2_present, + msm_mux_uim2_reset, + msm_mux_uim_batt, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux__, +}; + +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio13", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", + "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const qup1_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const gcc_gp2_groups[] = { + "gpio21", "gpio58", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", "gpio59", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const qup2_groups[] = { + "gpio27", "gpio28", "gpio29", "gpio30", +}; +static const char * const phase_flag_groups[] = { + "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio74", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", + "gpio96", "gpio99", "gpio100", "gpio103", "gpio137", "gpio138", + "gpio139", "gpio140", "gpio141", "gpio142", "gpio143", +}; +static const char * const qup11_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const qup14_groups[] = { + "gpio31", "gpio32", "gpio33", "gpio34", +}; +static const char * const pci_e0_groups[] = { + "gpio35", "gpio36", +}; +static const char * const jitter_bist_groups[] = { + "gpio35", +}; +static const char * const pll_bist_groups[] = { + "gpio36", +}; +static const char * const atest_tsens_groups[] = { + "gpio36", +}; +static const char * const agera_pll_groups[] = { + "gpio37", +}; +static const char * const usb_phy_groups[] = { + "gpio38", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio39", "gpio70", "gpio71", "gpio72", +}; +static const char * const sd_write_groups[] = { + "gpio40", +}; +static const char * const tsif1_error_groups[] = { + "gpio40", +}; +static const char * const qup3_groups[] = { + "gpio41", "gpio42", "gpio43", "gpio44", +}; +static const char * const qup6_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", +}; +static const char * const qup12_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const qup10_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const qua_mi2s_groups[] = { + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const gcc_gp1_groups[] = { + "gpio57", "gpio78", +}; +static const char * const cri_trng0_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const cri_trng_groups[] = { + "gpio62", +}; +static const char * const pri_mi2s_groups[] = { + "gpio64", "gpio65", "gpio67", "gpio68", +}; +static const char * const sp_cmu_groups[] = { + "gpio64", +}; +static const char * const qup8_groups[] = { + "gpio65", "gpio66", "gpio67", "gpio68", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio66", +}; +static const char * const spkr_i2s_groups[] = { + "gpio69", "gpio70", "gpio71", "gpio72", +}; +static const char * const audio_ref_groups[] = { + "gpio69", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio71", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio71", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio73", "gpio74", +}; +static const char * const atest_usb2_groups[] = { + "gpio73", +}; +static const char * const ter_mi2s_groups[] = { + "gpio74", "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const atest_usb23_groups[] = { + "gpio74", +}; +static const char * const atest_usb22_groups[] = { + "gpio75", +}; +static const char * const atest_usb21_groups[] = { + "gpio76", +}; +static const char * const atest_usb20_groups[] = { + "gpio77", +}; +static const char * const sec_mi2s_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", +}; +static const char * const qup15_groups[] = { + "gpio81", "gpio82", "gpio83", "gpio84", +}; +static const char * const qup5_groups[] = { + "gpio85", "gpio86", "gpio87", "gpio88", +}; +static const char * const tsif1_clk_groups[] = { + "gpio89", +}; +static const char * const qup4_groups[] = { + "gpio89", "gpio90", "gpio91", "gpio92", +}; +static const char * const qspi_cs_groups[] = { + "gpio89", "gpio90", +}; +static const char * const tgu_ch3_groups[] = { + "gpio89", +}; +static const char * const tsif1_en_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio90", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio90", +}; +static const char * const tgu_ch0_groups[] = { + "gpio90", +}; +static const char * const tsif1_data_groups[] = { + "gpio91", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio91", +}; +static const char * const qspi_data_groups[] = { + "gpio91", "gpio92", "gpio93", "gpio94", +}; +static const char * const tgu_ch1_groups[] = { + "gpio91", +}; +static const char * const tsif2_error_groups[] = { + "gpio92", +}; +static const char * const sdc4_data_groups[] = { + "gpio92", + "gpio94", + "gpio95", + "gpio96", +}; +static const char * const vfr_1_groups[] = { + "gpio92", +}; +static const char * const tgu_ch2_groups[] = { + "gpio92", +}; +static const char * const tsif2_clk_groups[] = { + "gpio93", +}; +static const char * const sdc4_clk_groups[] = { + "gpio93", +}; +static const char * const qup7_groups[] = { + "gpio93", "gpio94", "gpio95", "gpio96", +}; +static const char * const tsif2_en_groups[] = { + "gpio94", +}; +static const char * const tsif2_data_groups[] = { + "gpio95", +}; +static const char * const qspi_clk_groups[] = { + "gpio95", +}; +static const char * const tsif2_sync_groups[] = { + "gpio96", +}; +static const char * const ldo_en_groups[] = { + "gpio97", +}; +static const char * const ldo_update_groups[] = { + "gpio98", +}; +static const char * const pci_e1_groups[] = { + "gpio102", "gpio103", +}; +static const char * const prng_rosc_groups[] = { + "gpio102", +}; +static const char * const uim2_data_groups[] = { + "gpio105", +}; +static const char * const qup13_groups[] = { + "gpio105", "gpio106", "gpio107", "gpio108", +}; +static const char * const uim2_clk_groups[] = { + "gpio106", +}; +static const char * const uim2_reset_groups[] = { + "gpio107", +}; +static const char * const uim2_present_groups[] = { + "gpio108", +}; +static const char * const uim1_data_groups[] = { + "gpio109", +}; +static const char * const uim1_clk_groups[] = { + "gpio110", +}; +static const char * const uim1_reset_groups[] = { + "gpio111", +}; +static const char * const uim1_present_groups[] = { + "gpio112", +}; +static const char * const uim_batt_groups[] = { + "gpio113", +}; +static const char * const edp_hot_groups[] = { + "gpio113", +}; +static const char * const nav_pps_groups[] = { + "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128", + "gpio129", "gpio129", "gpio143", "gpio143", +}; +static const char * const atest_char_groups[] = { + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", +}; +static const char * const adsp_ext_groups[] = { + "gpio118", +}; +static const char * const qlink_request_groups[] = { + "gpio130", +}; +static const char * const qlink_enable_groups[] = { + "gpio131", +}; +static const char * const pa_indicator_groups[] = { + "gpio135", +}; +static const char * const mss_lte_groups[] = { + "gpio144", "gpio145", +}; +static const char * const qup0_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", +}; +static const char * const qup9_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const qdss_cti_groups[] = { + "gpio4", "gpio5", "gpio51", "gpio52", "gpio62", "gpio63", "gpio90", + "gpio91", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const vsense_trigger_groups[] = { + "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const qup_l4_groups[] = { + "gpio8", "gpio35", "gpio105", "gpio123", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio8", +}; +static const char * const atest_usb13_groups[] = { + "gpio8", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio8", "gpio9", +}; +static const char * const qup_l5_groups[] = { + "gpio9", "gpio36", "gpio106", "gpio124", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio9", +}; +static const char * const atest_usb12_groups[] = { + "gpio9", +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio97", "gpio98", +}; +static const char * const qup_l6_groups[] = { + "gpio10", "gpio37", "gpio107", "gpio125", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio10", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio10", "gpio11", +}; +static const char * const edp_lcd_groups[] = { + "gpio11", +}; +static const char * const dbg_out_groups[] = { + "gpio11", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const tsif1_sync_groups[] = { + "gpio12", +}; + +static const struct msm_function sdm845_functions[] = { + FUNCTION(gpio), + FUNCTION(adsp_ext), + FUNCTION(agera_pll), + FUNCTION(atest_char), + FUNCTION(atest_tsens), + FUNCTION(atest_tsens2), + FUNCTION(atest_usb1), + FUNCTION(atest_usb10), + FUNCTION(atest_usb11), + FUNCTION(atest_usb12), + FUNCTION(atest_usb13), + FUNCTION(atest_usb2), + FUNCTION(atest_usb20), + FUNCTION(atest_usb21), + FUNCTION(atest_usb22), + FUNCTION(atest_usb23), + FUNCTION(audio_ref), + FUNCTION(btfm_slimbus), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(edp_hot), + FUNCTION(edp_lcd), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(jitter_bist), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(lpass_slimbus), + FUNCTION(m_voc), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mss_lte), + FUNCTION(nav_pps), + FUNCTION(pa_indicator), + FUNCTION(pci_e0), + FUNCTION(pci_e1), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_bypassnl), + FUNCTION(pll_reset), + FUNCTION(pri_mi2s), + FUNCTION(pri_mi2s_ws), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss), + FUNCTION(qlink_enable), + FUNCTION(qlink_request), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qspi_data), + FUNCTION(qua_mi2s), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup2), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(qup6), + FUNCTION(qup7), + FUNCTION(qup8), + FUNCTION(qup9), + FUNCTION(qup_l4), + FUNCTION(qup_l5), + FUNCTION(qup_l6), + FUNCTION(sd_write), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(sdc4_data), + FUNCTION(sec_mi2s), + FUNCTION(sp_cmu), + FUNCTION(spkr_i2s), + FUNCTION(ter_mi2s), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(tsif1_clk), + FUNCTION(tsif1_data), + FUNCTION(tsif1_en), + FUNCTION(tsif1_error), + FUNCTION(tsif1_sync), + FUNCTION(tsif2_clk), + FUNCTION(tsif2_data), + FUNCTION(tsif2_en), + FUNCTION(tsif2_error), + FUNCTION(tsif2_sync), + FUNCTION(uim1_clk), + FUNCTION(uim1_data), + FUNCTION(uim1_present), + FUNCTION(uim1_reset), + FUNCTION(uim2_clk), + FUNCTION(uim2_data), + FUNCTION(uim2_present), + FUNCTION(uim2_reset), + FUNCTION(uim_batt), + FUNCTION(usb_phy), + FUNCTION(vfr_1), + FUNCTION(vsense_trigger), + FUNCTION(wlan1_adc0), + FUNCTION(wlan1_adc1), + FUNCTION(wlan2_adc0), + FUNCTION(wlan2_adc1), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sdm845_groups[] = { + PINGROUP(0, EAST, qup0, _, _, _, _, _, _, _, _, _), + PINGROUP(1, EAST, qup0, _, _, _, _, _, _, _, _, _), + PINGROUP(2, EAST, qup0, _, _, _, _, _, _, _, _, _), + PINGROUP(3, EAST, qup0, _, _, _, _, _, _, _, _, _), + PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _), + PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _), + PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _, _), + PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _), + PINGROUP(8, EAST, qup_l4, _, ddr_bist, _, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), + PINGROUP(9, EAST, qup_l5, ddr_bist, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _, _), + PINGROUP(10, EAST, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _, _), + PINGROUP(11, EAST, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _, _), + PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _, _), + PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _, _), + PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _, _), + PINGROUP(15, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _), + PINGROUP(16, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _), + PINGROUP(17, SOUTH, cci_i2c, qup1, qdss, _, _, _, _, _, _, _), + PINGROUP(18, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _), + PINGROUP(19, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _), + PINGROUP(20, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _), + PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _, _), + PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _, _), + PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _, _), + PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _, _), + PINGROUP(25, SOUTH, cci_timer4, cci_async, qdss, _, _, _, _, _, _, _), + PINGROUP(26, SOUTH, cci_async, qdss, _, _, _, _, _, _, _, _), + PINGROUP(27, EAST, qup2, qdss, _, _, _, _, _, _, _, _), + PINGROUP(28, EAST, qup2, qdss, _, _, _, _, _, _, _, _), + PINGROUP(29, EAST, qup2, _, phase_flag, qdss, _, _, _, _, _, _), + PINGROUP(30, EAST, qup2, phase_flag, qdss, _, _, _, _, _, _, _), + PINGROUP(31, NORTH, qup11, qup14, _, _, _, _, _, _, _, _), + PINGROUP(32, NORTH, qup11, qup14, _, _, _, _, _, _, _, _), + PINGROUP(33, NORTH, qup11, qup14, _, _, _, _, _, _, _, _), + PINGROUP(34, NORTH, qup11, qup14, _, _, _, _, _, _, _, _), + PINGROUP(35, SOUTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _, _), + PINGROUP(36, SOUTH, pci_e0, qup_l5, pll_bist, _, atest_tsens, _, _, _, _, _), + PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _, _), + PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _, _), + PINGROUP(39, EAST, lpass_slimbus, _, _, _, _, _, _, _, _, _), + PINGROUP(40, SOUTH, sd_write, tsif1_error, _, _, _, _, _, _, _, _), + PINGROUP(41, EAST, qup3, _, qdss, _, _, _, _, _, _, _), + PINGROUP(42, EAST, qup3, _, qdss, _, _, _, _, _, _, _), + PINGROUP(43, EAST, qup3, _, qdss, _, _, _, _, _, _, _), + PINGROUP(44, EAST, qup3, _, qdss, _, _, _, _, _, _, _), + PINGROUP(45, EAST, qup6, _, _, _, _, _, _, _, _, _), + PINGROUP(46, EAST, qup6, _, _, _, _, _, _, _, _, _), + PINGROUP(47, EAST, qup6, _, _, _, _, _, _, _, _, _), + PINGROUP(48, EAST, qup6, _, _, _, _, _, _, _, _, _), + PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _, _), + PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _, _), + PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _, _), + PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _, _), + PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(54, NORTH, qup10, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(55, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _, _), + PINGROUP(58, NORTH, qua_mi2s, gcc_gp2, phase_flag, _, _, _, _, _, _, _), + PINGROUP(59, NORTH, qua_mi2s, gcc_gp3, phase_flag, _, _, _, _, _, _, _), + PINGROUP(60, NORTH, qua_mi2s, cri_trng0, phase_flag, _, _, _, _, _, _, _), + PINGROUP(61, NORTH, qua_mi2s, cri_trng1, phase_flag, _, _, _, _, _, _, _), + PINGROUP(62, NORTH, qua_mi2s, cri_trng, phase_flag, qdss_cti, _, _, _, _, _, _), + PINGROUP(63, NORTH, qua_mi2s, _, phase_flag, qdss_cti, _, _, _, _, _, _), + PINGROUP(64, NORTH, pri_mi2s, sp_cmu, phase_flag, _, _, _, _, _, _, _), + PINGROUP(65, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _), + PINGROUP(66, NORTH, pri_mi2s_ws, qup8, _, _, _, _, _, _, _, _), + PINGROUP(67, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _), + PINGROUP(68, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _), + PINGROUP(69, EAST, spkr_i2s, audio_ref, _, _, _, _, _, _, _, _), + PINGROUP(70, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _), + PINGROUP(71, EAST, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + PINGROUP(72, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _), + PINGROUP(73, EAST, btfm_slimbus, atest_usb2, _, _, _, _, _, _, _, _), + PINGROUP(74, EAST, btfm_slimbus, ter_mi2s, phase_flag, atest_usb23, _, _, _, _, _, _), + PINGROUP(75, EAST, ter_mi2s, phase_flag, qdss, atest_usb22, _, _, _, _, _, _), + PINGROUP(76, EAST, ter_mi2s, phase_flag, qdss, atest_usb21, _, _, _, _, _, _), + PINGROUP(77, EAST, ter_mi2s, phase_flag, qdss, atest_usb20, _, _, _, _, _, _), + PINGROUP(78, EAST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _, _), + PINGROUP(79, NORTH, sec_mi2s, _, _, qdss, _, _, _, _, _, _), + PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _, _), + PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _), + PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _), + PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _), + PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _, _), + PINGROUP(85, EAST, qup5, _, _, _, _, _, _, _, _, _), + PINGROUP(86, EAST, qup5, _, _, _, _, _, _, _, _, _), + PINGROUP(87, EAST, qup5, _, _, _, _, _, _, _, _, _), + PINGROUP(88, EAST, qup5, _, _, _, _, _, _, _, _, _), + PINGROUP(89, SOUTH, tsif1_clk, qup4, qspi_cs, tgu_ch3, phase_flag, _, _, _, _, _), + PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, qspi_cs, mdp_vsync1, + mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti), + PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, qspi_data, tgu_ch1, _, qdss_cti, _, _, _), + PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, qspi_data, vfr_1, tgu_ch2, _, _, _, _), + PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, qspi_data, _, qdss, _, _, _, _), + PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, qspi_data, _, _, _, _, _, _), + PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, qspi_clk, _, _, _, _, _, _), + PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _, _), + PINGROUP(97, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _, _), + PINGROUP(98, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _, _), + PINGROUP(99, NORTH, phase_flag, _, _, _, _, _, _, _, _, _), + PINGROUP(100, NORTH, phase_flag, _, _, _, _, _, _, _, _, _), + PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(102, NORTH, pci_e1, prng_rosc, _, _, _, _, _, _, _, _), + PINGROUP(103, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _, _), + PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _, _), + PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _, _), + PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _, _), + PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _, _), + PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _, _), + PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _, _), + PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _, _), + PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _, _), + PINGROUP(114, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _), + PINGROUP(115, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _), + PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _), + PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _, _), + PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _), + PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _), + PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _), + PINGROUP(122, EAST, _, qdss, _, _, _, _, _, _, _, _), + PINGROUP(123, EAST, qup_l4, _, qdss, _, _, _, _, _, _, _), + PINGROUP(124, EAST, qup_l5, _, qdss, _, _, _, _, _, _, _), + PINGROUP(125, EAST, qup_l6, _, _, _, _, _, _, _, _, _), + PINGROUP(126, EAST, _, _, _, _, _, _, _, _, _, _), + PINGROUP(127, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(128, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _), + PINGROUP(129, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _), + PINGROUP(130, NORTH, qlink_request, _, _, _, _, _, _, _, _, _), + PINGROUP(131, NORTH, qlink_enable, _, _, _, _, _, _, _, _, _), + PINGROUP(132, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(135, NORTH, _, pa_indicator, _, _, _, _, _, _, _, _), + PINGROUP(136, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(137, NORTH, _, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(138, NORTH, _, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(139, NORTH, _, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(140, NORTH, _, _, phase_flag, _, _, _, _, _, _, _), + PINGROUP(141, NORTH, _, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(142, NORTH, _, phase_flag, _, _, _, _, _, _, _, _), + PINGROUP(143, NORTH, _, nav_pps, nav_pps, _, phase_flag, _, _, _, _, _), + PINGROUP(144, NORTH, mss_lte, _, _, _, _, _, _, _, _, _), + PINGROUP(145, NORTH, mss_lte, _, _, _, _, _, _, _, _, _), + PINGROUP(146, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _), + PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _), + SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6), + SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3), + SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0), + UFS_RESET(ufs_reset, 0x99f000), +}; + +static const struct msm_pinctrl_soc_data sdm845_pinctrl = { + .pins = sdm845_pins, + .npins = ARRAY_SIZE(sdm845_pins), + .functions = sdm845_functions, + .nfunctions = ARRAY_SIZE(sdm845_functions), + .groups = sdm845_groups, + .ngroups = ARRAY_SIZE(sdm845_groups), + .ngpios = 150, +}; + +static int sdm845_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sdm845_pinctrl); +} + +static const struct of_device_id sdm845_pinctrl_of_match[] = { + { .compatible = "qcom,sdm845-pinctrl", }, + { }, +}; + +static struct platform_driver sdm845_pinctrl_driver = { + .driver = { + .name = "sdm845-pinctrl", + .of_match_table = sdm845_pinctrl_of_match, + }, + .probe = sdm845_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sdm845_pinctrl_init(void) +{ + return platform_driver_register(&sdm845_pinctrl_driver); +} +arch_initcall(sdm845_pinctrl_init); + +static void __exit sdm845_pinctrl_exit(void) +{ + platform_driver_unregister(&sdm845_pinctrl_driver); +} +module_exit(sdm845_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sdm845 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match); diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 617df163067f..6cbcff42ba47 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -268,10 +268,11 @@ static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) static struct irq_chip stm32_gpio_irq_chip = { .name = "stm32gpio", - .irq_eoi = irq_chip_eoi_parent, + .irq_ack = irq_chip_ack_parent, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, .irq_set_type = irq_chip_set_type_parent, + .irq_set_wake = irq_chip_set_wake_parent, .irq_request_resources = stm32_gpio_irq_request_resources, .irq_release_resources = stm32_gpio_irq_release_resources, }; diff --git a/include/dt-bindings/gpio/meson8b-gpio.h b/include/dt-bindings/gpio/meson8b-gpio.h index c38cb20d7182..bf0d76fa0e7b 100644 --- a/include/dt-bindings/gpio/meson8b-gpio.h +++ b/include/dt-bindings/gpio/meson8b-gpio.h @@ -15,18 +15,113 @@ #ifndef _DT_BINDINGS_MESON8B_GPIO_H #define _DT_BINDINGS_MESON8B_GPIO_H -#include <dt-bindings/gpio/meson8-gpio.h> - -/* GPIO Bank DIF */ -#define DIF_0_P 120 -#define DIF_0_N 121 -#define DIF_1_P 122 -#define DIF_1_N 123 -#define DIF_2_P 124 -#define DIF_2_N 125 -#define DIF_3_P 126 -#define DIF_3_N 127 -#define DIF_4_P 128 -#define DIF_4_N 129 +/* EE (CBUS) GPIO chip */ +#define GPIOX_0 0 +#define GPIOX_1 1 +#define GPIOX_2 2 +#define GPIOX_3 3 +#define GPIOX_4 4 +#define GPIOX_5 5 +#define GPIOX_6 6 +#define GPIOX_7 7 +#define GPIOX_8 8 +#define GPIOX_9 9 +#define GPIOX_10 10 +#define GPIOX_11 11 +#define GPIOX_16 12 +#define GPIOX_17 13 +#define GPIOX_18 14 +#define GPIOX_19 15 +#define GPIOX_20 16 +#define GPIOX_21 17 + +#define GPIOY_0 18 +#define GPIOY_1 19 +#define GPIOY_3 20 +#define GPIOY_6 21 +#define GPIOY_7 22 +#define GPIOY_8 23 +#define GPIOY_9 24 +#define GPIOY_10 25 +#define GPIOY_11 26 +#define GPIOY_12 27 +#define GPIOY_13 28 +#define GPIOY_14 29 + +#define GPIODV_9 30 +#define GPIODV_24 31 +#define GPIODV_25 32 +#define GPIODV_26 33 +#define GPIODV_27 34 +#define GPIODV_28 35 +#define GPIODV_29 36 + +#define GPIOH_0 37 +#define GPIOH_1 38 +#define GPIOH_2 39 +#define GPIOH_3 40 +#define GPIOH_4 41 +#define GPIOH_5 42 +#define GPIOH_6 43 +#define GPIOH_7 44 +#define GPIOH_8 45 +#define GPIOH_9 46 + +#define CARD_0 47 +#define CARD_1 48 +#define CARD_2 49 +#define CARD_3 50 +#define CARD_4 51 +#define CARD_5 52 +#define CARD_6 53 + +#define BOOT_0 54 +#define BOOT_1 55 +#define BOOT_2 56 +#define BOOT_3 57 +#define BOOT_4 58 +#define BOOT_5 59 +#define BOOT_6 60 +#define BOOT_7 61 +#define BOOT_8 62 +#define BOOT_9 63 +#define BOOT_10 64 +#define BOOT_11 65 +#define BOOT_12 66 +#define BOOT_13 67 +#define BOOT_14 68 +#define BOOT_15 69 +#define BOOT_16 70 +#define BOOT_17 71 +#define BOOT_18 72 + +#define DIF_0_P 73 +#define DIF_0_N 74 +#define DIF_1_P 75 +#define DIF_1_N 76 +#define DIF_2_P 77 +#define DIF_2_N 78 +#define DIF_3_P 79 +#define DIF_3_N 80 +#define DIF_4_P 81 +#define DIF_4_N 82 + +/* AO GPIO chip */ +#define GPIOAO_0 0 +#define GPIOAO_1 1 +#define GPIOAO_2 2 +#define GPIOAO_3 3 +#define GPIOAO_4 4 +#define GPIOAO_5 5 +#define GPIOAO_6 6 +#define GPIOAO_7 7 +#define GPIOAO_8 8 +#define GPIOAO_9 9 +#define GPIOAO_10 10 +#define GPIOAO_11 11 +#define GPIOAO_12 12 +#define GPIOAO_13 13 +#define GPIO_BSD_EN 14 +#define GPIO_TEST_N 15 #endif /* _DT_BINDINGS_MESON8B_GPIO_H */ diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h index 2d6a7b1d7be2..4878a67a844c 100644 --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h @@ -251,6 +251,12 @@ #define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0) #define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1) +#define MT7623_PIN_77_SDA2_FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT7623_PIN_77_SDA2_FUNC_SDA2 (MTK_PIN_NO(77) | 1) + +#define MT7623_PIN_78_SCL2_FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT7623_PIN_78_SCL2_FUNC_SCL2 (MTK_PIN_NO(78) | 1) + #define MT7623_PIN_79_URXD0_FUNC_GPIO79 (MTK_PIN_NO(79) | 0) #define MT7623_PIN_79_URXD0_FUNC_URXD0 (MTK_PIN_NO(79) | 1) #define MT7623_PIN_79_URXD0_FUNC_UTXD0 (MTK_PIN_NO(79) | 2) @@ -291,6 +297,24 @@ #define MT7623_PIN_100_MIPI_TDP0_FUNC_GPIO100 (MTK_PIN_NO(100) | 0) #define MT7623_PIN_100_MIPI_TDP0_FUNC_TDP0 (MTK_PIN_NO(100) | 1) +#define MT7623_PIN_101_SPI2_CSN_FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS (MTK_PIN_NO(101) | 1) +#define MT7623_PIN_101_SPI2_CSN_FUNC_SCL3 (MTK_PIN_NO(101) | 3) + +#define MT7623_PIN_102_SPI2_MI_FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI (MTK_PIN_NO(102) | 1) +#define MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MO (MTK_PIN_NO(102) | 2) +#define MT7623_PIN_102_SPI2_MI_FUNC_SDA3 (MTK_PIN_NO(102) | 3) + +#define MT7623_PIN_103_SPI2_MO_FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO (MTK_PIN_NO(103) | 1) +#define MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MI (MTK_PIN_NO(103) | 2) +#define MT7623_PIN_103_SPI2_MO_FUNC_SCL3 (MTK_PIN_NO(103) | 3) + +#define MT7623_PIN_104_SPI2_CK_FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK (MTK_PIN_NO(104) | 1) +#define MT7623_PIN_104_SPI2_CK_FUNC_SDA3 (MTK_PIN_NO(104) | 3) + #define MT7623_PIN_105_MSDC1_CMD_FUNC_GPIO105 (MTK_PIN_NO(105) | 0) #define MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD (MTK_PIN_NO(105) | 1) #define MT7623_PIN_105_MSDC1_CMD_FUNC_SDA1 (MTK_PIN_NO(105) | 3) |