diff options
714 files changed, 28163 insertions, 8519 deletions
diff --git a/Documentation/arm/Samsung/Overview.txt b/Documentation/arm/Samsung/Overview.txt new file mode 100644 index 000000000000..7cced1fea9c3 --- /dev/null +++ b/Documentation/arm/Samsung/Overview.txt @@ -0,0 +1,86 @@ + Samsung ARM Linux Overview + ========================== + +Introduction +------------ + + The Samsung range of ARM SoCs spans many similar devices, from the initial + ARM9 through to the newest ARM cores. This document shows an overview of + the current kernel support, how to use it and where to find the code + that supports this. + + The currently supported SoCs are: + + - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list + - S3C64XX: S3C6400 and S3C6410 + - S5PC6440 + + S5PC100 and S5PC110 support is currently being merged + + +S3C24XX Systems +--------------- + + There is still documentation in Documnetation/arm/Samsung-S3C24XX/ which + deals with the architecture and drivers specific to these devices. + + See Documentation/arm/Samsung-S3C24XX/Overview.txt for more information + on the implementation details and specific support. + + +Configuration +------------- + + A number of configurations are supplied, as there is no current way of + unifying all the SoCs into one kernel. + + s5p6440_defconfig - S5P6440 specific default configuration + s5pc100_defconfig - S5PC100 specific default configuration + + +Layout +------ + + The directory layout is currently being restructured, and consists of + several platform directories and then the machine specific directories + of the CPUs being built for. + + plat-samsung provides the base for all the implementations, and is the + last in the line of include directories that are processed for the build + specific information. It contains the base clock, GPIO and device definitions + to get the system running. + + plat-s3c is the s3c24xx/s3c64xx platform directory, although it is currently + involved in other builds this will be phased out once the relevant code is + moved elsewhere. + + plat-s3c24xx is for s3c24xx specific builds, see the S3C24XX docs. + + plat-s3c64xx is for the s3c64xx specific bits, see the S3C24XX docs. + + plat-s5p is for s5p specific builds, more to be added. + + + [ to finish ] + + +Port Contributors +----------------- + + Ben Dooks (BJD) + Vincent Sanders + Herbert Potzl + Arnaud Patard (RTP) + Roc Wu + Klaus Fetscher + Dimitry Andric + Shannon Holland + Guillaume Gourat (NexVision) + Christer Weinigel (wingel) (Acer N30) + Lucas Correia Villa Real (S3C2400 port) + + +Document Author +--------------- + +Copyright 2009-2010 Ben Dooks <[email protected]> diff --git a/Documentation/arm/Samsung/clksrc-change-registers.awk b/Documentation/arm/Samsung/clksrc-change-registers.awk new file mode 100755 index 000000000000..0c50220851fb --- /dev/null +++ b/Documentation/arm/Samsung/clksrc-change-registers.awk @@ -0,0 +1,167 @@ +#!/usr/bin/awk -f +# +# Copyright 2010 Ben Dooks <[email protected]> +# +# Released under GPLv2 + +# example usage +# ./clksrc-change-registers.awk arch/arm/plat-s5pc1xx/include/plat/regs-clock.h < src > dst + +function extract_value(s) +{ + eqat = index(s, "=") + comat = index(s, ",") + return substr(s, eqat+2, (comat-eqat)-2) +} + +function remove_brackets(b) +{ + return substr(b, 2, length(b)-2) +} + +function splitdefine(l, p) +{ + r = split(l, tp) + + p[0] = tp[2] + p[1] = remove_brackets(tp[3]) +} + +function find_length(f) +{ + if (0) + printf "find_length " f "\n" > "/dev/stderr" + + if (f ~ /0x1/) + return 1 + else if (f ~ /0x3/) + return 2 + else if (f ~ /0x7/) + return 3 + else if (f ~ /0xf/) + return 4 + + printf "unknown legnth " f "\n" > "/dev/stderr" + exit +} + +function find_shift(s) +{ + id = index(s, "<") + if (id <= 0) { + printf "cannot find shift " s "\n" > "/dev/stderr" + exit + } + + return substr(s, id+2) +} + + +BEGIN { + if (ARGC < 2) { + print "too few arguments" > "/dev/stderr" + exit + } + +# read the header file and find the mask values that we will need +# to replace and create an associative array of values + + while (getline line < ARGV[1] > 0) { + if (line ~ /\#define.*_MASK/ && + !(line ~ /S5PC100_EPLL_MASK/) && + !(line ~ /USB_SIG_MASK/)) { + splitdefine(line, fields) + name = fields[0] + if (0) + printf "MASK " line "\n" > "/dev/stderr" + dmask[name,0] = find_length(fields[1]) + dmask[name,1] = find_shift(fields[1]) + if (0) + printf "=> '" name "' LENGTH=" dmask[name,0] " SHIFT=" dmask[name,1] "\n" > "/dev/stderr" + } else { + } + } + + delete ARGV[1] +} + +/clksrc_clk.*=.*{/ { + shift="" + mask="" + divshift="" + reg_div="" + reg_src="" + indent=1 + + print $0 + + for(; indent >= 1;) { + if ((getline line) <= 0) { + printf "unexpected end of file" > "/dev/stderr" + exit 1; + } + + if (line ~ /\.shift/) { + shift = extract_value(line) + } else if (line ~ /\.mask/) { + mask = extract_value(line) + } else if (line ~ /\.reg_divider/) { + reg_div = extract_value(line) + } else if (line ~ /\.reg_source/) { + reg_src = extract_value(line) + } else if (line ~ /\.divider_shift/) { + divshift = extract_value(line) + } else if (line ~ /{/) { + indent++ + print line + } else if (line ~ /}/) { + indent-- + + if (indent == 0) { + if (0) { + printf "shift '" shift "' ='" dmask[shift,0] "'\n" > "/dev/stderr" + printf "mask '" mask "'\n" > "/dev/stderr" + printf "dshft '" divshift "'\n" > "/dev/stderr" + printf "rdiv '" reg_div "'\n" > "/dev/stderr" + printf "rsrc '" reg_src "'\n" > "/dev/stderr" + } + + generated = mask + sub(reg_src, reg_div, generated) + + if (0) { + printf "/* rsrc " reg_src " */\n" + printf "/* rdiv " reg_div " */\n" + printf "/* shift " shift " */\n" + printf "/* mask " mask " */\n" + printf "/* generated " generated " */\n" + } + + if (reg_div != "") { + printf "\t.reg_div = { " + printf ".reg = " reg_div ", " + printf ".shift = " dmask[generated,1] ", " + printf ".size = " dmask[generated,0] ", " + printf "},\n" + } + + printf "\t.reg_src = { " + printf ".reg = " reg_src ", " + printf ".shift = " dmask[mask,1] ", " + printf ".size = " dmask[mask,0] ", " + + printf "},\n" + + } + + print line + } else { + print line + } + + if (0) + printf indent ":" line "\n" > "/dev/stderr" + } +} + +// && ! /clksrc_clk.*=.*{/ { print $0 } diff --git a/Documentation/cpu-freq/governors.txt b/Documentation/cpu-freq/governors.txt index aed082f49d09..737988fca64d 100644 --- a/Documentation/cpu-freq/governors.txt +++ b/Documentation/cpu-freq/governors.txt @@ -145,8 +145,8 @@ show_sampling_rate_max: THIS INTERFACE IS DEPRECATED, DON'T USE IT. up_threshold: defines what the average CPU usage between the samplings of 'sampling_rate' needs to be for the kernel to make a decision on whether it should increase the frequency. For example when it is set -to its default value of '80' it means that between the checking -intervals the CPU needs to be on average more than 80% in use to then +to its default value of '95' it means that between the checking +intervals the CPU needs to be on average more than 95% in use to then decide that the CPU frequency needs to be increased. ignore_nice_load: this parameter takes a value of '0' or '1'. When diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 736d45602886..826b6e148316 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -199,6 +199,10 @@ and is between 256 and 4096 characters. It is defined in the file acpi_display_output=video See above. + acpi_early_pdc_eval [HW,ACPI] Evaluate processor _PDC methods + early. Needed on some platforms to properly + initialize the EC. + acpi_irq_balance [HW,ACPI] ACPI will balance active IRQs default in APIC mode diff --git a/MAINTAINERS b/MAINTAINERS index 9d7e056cb14c..776a5a46e351 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -616,10 +616,10 @@ M: Richard Purdie <[email protected]> S: Maintained ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE -M: Paulius Zaleckas <[email protected]> +M: Paulius Zaleckas <[email protected]> L: [email protected] (moderated for non-subscribers) T: git git://gitorious.org/linux-gemini/mainline.git -S: Maintained +S: Odd Fixes F: arch/arm/mach-gemini/ ARM/EBSA110 MACHINE SUPPORT @@ -641,9 +641,9 @@ T: topgit git://git.openezx.org/openezx.git F: arch/arm/mach-pxa/ezx.c ARM/FARADAY FA526 PORT -M: Paulius Zaleckas <[email protected]> +M: Paulius Zaleckas <[email protected]> L: [email protected] (moderated for non-subscribers) -S: Maintained +S: Odd Fixes F: arch/arm/mm/*-fa* ARM/FOOTBRIDGE ARCHITECTURE @@ -662,6 +662,12 @@ T: git://git.pengutronix.de/git/imx/linux-2.6.git F: arch/arm/mach-mx*/ F: arch/arm/plat-mxc/ +ARM/FREESCALE IMX51 +M: Amit Kucheria <[email protected]> +L: [email protected] (moderated for non-subscribers) +S: Maintained +F: arch/arm/mach-mx5/ + ARM/GLOMATION GESBC9312SX MACHINE SUPPORT M: Lennert Buytenhek <[email protected]> L: [email protected] (moderated for non-subscribers) @@ -3421,8 +3427,10 @@ S: Maintained F: drivers/scsi/sym53c8xx_2/ LTP (Linux Test Project) -M: Subrata Modak <[email protected]> -M: Mike Frysinger <[email protected]> +M: Rishikesh K Rajak <[email protected]> +M: Garrett Cooper <[email protected]> +M: Mike Frysinger <[email protected]> +M: Subrata Modak <[email protected]> L: [email protected] (subscribers-only) W: http://ltp.sourceforge.net/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/ltp.git @@ -3846,6 +3854,7 @@ NETWORKING DRIVERS W: http://www.linuxfoundation.org/en/Net T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6.git S: Odd Fixes F: drivers/net/ F: include/linux/if_* @@ -4429,6 +4438,13 @@ L: [email protected] (moderated for non-subscribers) T: git git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git S: Maintained +MMP2 SUPPORT (aka ARMADA610) +M: Haojian Zhuang <[email protected]> +M: Eric Miao <[email protected]> +L: [email protected] (moderated for non-subscribers) +T: git git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git +S: Maintained + PXA MMCI DRIVER S: Orphan @@ -1,7 +1,7 @@ VERSION = 2 PATCHLEVEL = 6 SUBLEVEL = 33 -EXTRAVERSION = -rc7 +EXTRAVERSION = -rc8 NAME = Man-Eating Seals of Antiquity # *DOCUMENTATION* diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 55764a1c8763..ee74c3a03883 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -310,10 +310,9 @@ config ARCH_MXC bool "Freescale MXC/iMX-based" select GENERIC_TIME select GENERIC_CLOCKEVENTS - select ARCH_MTD_XIP - select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB select HAVE_CLK + select COMMON_CLKDEV help Support for Freescale MXC/iMX-based family of processors @@ -497,7 +496,7 @@ config ARCH_ORION5X Orion-2 (5281), Orion-1-90 (6183). config ARCH_MMP - bool "Marvell PXA168/910" + bool "Marvell PXA168/910/MMP2" depends on MMU select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB @@ -508,7 +507,7 @@ config ARCH_MMP select TICK_ONESHOT select PLAT_PXA help - Support for Marvell's PXA168/910 processor line. + Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. config ARCH_KS8695 bool "Micrel/Kendin KS8695" @@ -638,6 +637,14 @@ config ARCH_S3C64XX help Samsung S3C64XX series based systems +config ARCH_S5P6440 + bool "Samsung S5P6440" + select CPU_V6 + select GENERIC_GPIO + select HAVE_CLK + help + Samsung S5P6440 CPU based systems + config ARCH_S5PC1XX bool "Samsung S5PC1XX" select GENERIC_GPIO @@ -811,6 +818,7 @@ source "arch/arm/plat-samsung/Kconfig" source "arch/arm/plat-s3c24xx/Kconfig" source "arch/arm/plat-s3c64xx/Kconfig" source "arch/arm/plat-s3c/Kconfig" +source "arch/arm/plat-s5p/Kconfig" source "arch/arm/plat-s5pc1xx/Kconfig" if ARCH_S3C2410 @@ -827,6 +835,8 @@ source "arch/arm/mach-s3c6400/Kconfig" source "arch/arm/mach-s3c6410/Kconfig" endif +source "arch/arm/mach-s5p6440/Kconfig" + source "arch/arm/mach-shmobile/Kconfig" source "arch/arm/plat-stmp3xxx/Kconfig" @@ -1082,7 +1092,7 @@ source kernel/Kconfig.preempt config HZ int default 128 if ARCH_L7200 - default 200 if ARCH_EBSA110 || ARCH_S3C2410 + default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER default AT91_TIMER_HZ if ARCH_AT91 default 100 diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 177775fe514d..10e933b2f40c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -146,6 +146,7 @@ machine-$(CONFIG_ARCH_MX1) := mx1 machine-$(CONFIG_ARCH_MX2) := mx2 machine-$(CONFIG_ARCH_MX25) := mx25 machine-$(CONFIG_ARCH_MX3) := mx3 +machine-$(CONFIG_ARCH_MX5) := mx5 machine-$(CONFIG_ARCH_MXC91231) := mxc91231 machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NOMADIK) := nomadik @@ -162,6 +163,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 +machine-$(CONFIG_ARCH_S5P6440) := s5p6440 machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SHARK) := shark @@ -186,6 +188,7 @@ plat-$(CONFIG_PLAT_PXA) := pxa plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung +plat-$(CONFIG_PLAT_S5P) := s5p samsung s3c ifeq ($(CONFIG_ARCH_EBSA110),y) # This is what happens if you forget the IOCS16 line. diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index bd36c778c819..90ae00b631c2 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -32,6 +32,12 @@ #include <asm/hardware/locomo.h> +/* LoCoMo Interrupts */ +#define IRQ_LOCOMO_KEY (0) +#define IRQ_LOCOMO_GPIO (1) +#define IRQ_LOCOMO_LT (2) +#define IRQ_LOCOMO_SPI (3) + /* M62332 output channel selection */ #define M62332_EVR_CH 1 /* M62332 volume channel number */ /* 0 : CH.1 , 1 : CH. 2 */ @@ -58,6 +64,7 @@ struct locomo { struct device *dev; unsigned long phys; unsigned int irq; + int irq_base; spinlock_t lock; void __iomem *base; #ifdef CONFIG_PM @@ -81,9 +88,7 @@ struct locomo_dev_info { static struct locomo_dev_info locomo_devices[] = { { .devid = LOCOMO_DEVID_KEYBOARD, - .irq = { - IRQ_LOCOMO_KEY, - }, + .irq = { IRQ_LOCOMO_KEY }, .name = "locomo-keyboard", .offset = LOCOMO_KEYBOARD, .length = 16, @@ -133,53 +138,20 @@ static struct locomo_dev_info locomo_devices[] = { }, }; - -/** LoCoMo interrupt handling stuff. - * NOTE: LoCoMo has a 1 to many mapping on all of its IRQs. - * that is, there is only one real hardware interrupt - * we determine which interrupt it is by reading some IO memory. - * We have two levels of expansion, first in the handler for the - * hardware interrupt we generate an interrupt - * IRQ_LOCOMO_*_BASE and those handlers generate more interrupts - * - * hardware irq reads LOCOMO_ICR & 0x0f00 - * IRQ_LOCOMO_KEY_BASE - * IRQ_LOCOMO_GPIO_BASE - * IRQ_LOCOMO_LT_BASE - * IRQ_LOCOMO_SPI_BASE - * IRQ_LOCOMO_KEY_BASE reads LOCOMO_KIC & 0x0001 - * IRQ_LOCOMO_KEY - * IRQ_LOCOMO_GPIO_BASE reads LOCOMO_GIR & LOCOMO_GPD & 0xffff - * IRQ_LOCOMO_GPIO[0-15] - * IRQ_LOCOMO_LT_BASE reads LOCOMO_LTINT & 0x0001 - * IRQ_LOCOMO_LT - * IRQ_LOCOMO_SPI_BASE reads LOCOMO_SPIIR & 0x000F - * IRQ_LOCOMO_SPI_RFR - * IRQ_LOCOMO_SPI_RFW - * IRQ_LOCOMO_SPI_OVRN - * IRQ_LOCOMO_SPI_TEND - */ - -#define LOCOMO_IRQ_START (IRQ_LOCOMO_KEY_BASE) -#define LOCOMO_IRQ_KEY_START (IRQ_LOCOMO_KEY) -#define LOCOMO_IRQ_GPIO_START (IRQ_LOCOMO_GPIO0) -#define LOCOMO_IRQ_LT_START (IRQ_LOCOMO_LT) -#define LOCOMO_IRQ_SPI_START (IRQ_LOCOMO_SPI_RFR) - static void locomo_handler(unsigned int irq, struct irq_desc *desc) { + struct locomo *lchip = get_irq_chip_data(irq); int req, i; - void __iomem *mapbase = get_irq_chip_data(irq); /* Acknowledge the parent IRQ */ desc->chip->ack(irq); /* check why this interrupt was generated */ - req = locomo_readl(mapbase + LOCOMO_ICR) & 0x0f00; + req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00; if (req) { /* generate the next interrupt(s) */ - irq = LOCOMO_IRQ_START; + irq = lchip->irq_base; for (i = 0; i <= 3; i++, irq++) { if (req & (0x0100 << i)) { generic_handle_irq(irq); @@ -195,20 +167,20 @@ static void locomo_ack_irq(unsigned int irq) static void locomo_mask_irq(unsigned int irq) { - void __iomem *mapbase = get_irq_chip_data(irq); + struct locomo *lchip = get_irq_chip_data(irq); unsigned int r; - r = locomo_readl(mapbase + LOCOMO_ICR); - r &= ~(0x0010 << (irq - LOCOMO_IRQ_START)); - locomo_writel(r, mapbase + LOCOMO_ICR); + r = locomo_readl(lchip->base + LOCOMO_ICR); + r &= ~(0x0010 << (irq - lchip->irq_base)); + locomo_writel(r, lchip->base + LOCOMO_ICR); } static void locomo_unmask_irq(unsigned int irq) { - void __iomem *mapbase = get_irq_chip_data(irq); + struct locomo *lchip = get_irq_chip_data(irq); unsigned int r; - r = locomo_readl(mapbase + LOCOMO_ICR); - r |= (0x0010 << (irq - LOCOMO_IRQ_START)); - locomo_writel(r, mapbase + LOCOMO_ICR); + r = locomo_readl(lchip->base + LOCOMO_ICR); + r |= (0x0010 << (irq - lchip->irq_base)); + locomo_writel(r, lchip->base + LOCOMO_ICR); } static struct irq_chip locomo_chip = { @@ -218,297 +190,22 @@ static struct irq_chip locomo_chip = { .unmask = locomo_unmask_irq, }; -static void locomo_key_handler(unsigned int irq, struct irq_desc *desc) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - - if (locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC) & 0x0001) { - generic_handle_irq(LOCOMO_IRQ_KEY_START); - } -} - -static void locomo_key_ack_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); - r &= ~(0x0100 << (irq - LOCOMO_IRQ_KEY_START)); - locomo_writel(r, mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); -} - -static void locomo_key_mask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); - r &= ~(0x0010 << (irq - LOCOMO_IRQ_KEY_START)); - locomo_writel(r, mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); -} - -static void locomo_key_unmask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); - r |= (0x0010 << (irq - LOCOMO_IRQ_KEY_START)); - locomo_writel(r, mapbase + LOCOMO_KEYBOARD + LOCOMO_KIC); -} - -static struct irq_chip locomo_key_chip = { - .name = "LOCOMO-key", - .ack = locomo_key_ack_irq, - .mask = locomo_key_mask_irq, - .unmask = locomo_key_unmask_irq, -}; - -static void locomo_gpio_handler(unsigned int irq, struct irq_desc *desc) -{ - int req, i; - void __iomem *mapbase = get_irq_chip_data(irq); - - req = locomo_readl(mapbase + LOCOMO_GIR) & - locomo_readl(mapbase + LOCOMO_GPD) & - 0xffff; - - if (req) { - irq = LOCOMO_IRQ_GPIO_START; - for (i = 0; i <= 15; i++, irq++) { - if (req & (0x0001 << i)) { - generic_handle_irq(irq); - } - } - } -} - -static void locomo_gpio_ack_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_GWE); - r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); - locomo_writel(r, mapbase + LOCOMO_GWE); - - r = locomo_readl(mapbase + LOCOMO_GIS); - r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); - locomo_writel(r, mapbase + LOCOMO_GIS); - - r = locomo_readl(mapbase + LOCOMO_GWE); - r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); - locomo_writel(r, mapbase + LOCOMO_GWE); -} - -static void locomo_gpio_mask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_GIE); - r &= ~(0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); - locomo_writel(r, mapbase + LOCOMO_GIE); -} - -static void locomo_gpio_unmask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_GIE); - r |= (0x0001 << (irq - LOCOMO_IRQ_GPIO_START)); - locomo_writel(r, mapbase + LOCOMO_GIE); -} - -static int GPIO_IRQ_rising_edge; -static int GPIO_IRQ_falling_edge; - -static int locomo_gpio_type(unsigned int irq, unsigned int type) -{ - unsigned int mask; - void __iomem *mapbase = get_irq_chip_data(irq); - - mask = 1 << (irq - LOCOMO_IRQ_GPIO_START); - - if (type == IRQ_TYPE_PROBE) { - if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) - return 0; - type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; - } - - if (type & IRQ_TYPE_EDGE_RISING) - GPIO_IRQ_rising_edge |= mask; - else - GPIO_IRQ_rising_edge &= ~mask; - if (type & IRQ_TYPE_EDGE_FALLING) - GPIO_IRQ_falling_edge |= mask; - else - GPIO_IRQ_falling_edge &= ~mask; - locomo_writel(GPIO_IRQ_rising_edge, mapbase + LOCOMO_GRIE); - locomo_writel(GPIO_IRQ_falling_edge, mapbase + LOCOMO_GFIE); - - return 0; -} - -static struct irq_chip locomo_gpio_chip = { - .name = "LOCOMO-gpio", - .ack = locomo_gpio_ack_irq, - .mask = locomo_gpio_mask_irq, - .unmask = locomo_gpio_unmask_irq, - .set_type = locomo_gpio_type, -}; - -static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - - if (locomo_readl(mapbase + LOCOMO_LTINT) & 0x0001) { - generic_handle_irq(LOCOMO_IRQ_LT_START); - } -} - -static void locomo_lt_ack_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_LTINT); - r &= ~(0x0100 << (irq - LOCOMO_IRQ_LT_START)); - locomo_writel(r, mapbase + LOCOMO_LTINT); -} - -static void locomo_lt_mask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_LTINT); - r &= ~(0x0010 << (irq - LOCOMO_IRQ_LT_START)); - locomo_writel(r, mapbase + LOCOMO_LTINT); -} - -static void locomo_lt_unmask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_LTINT); - r |= (0x0010 << (irq - LOCOMO_IRQ_LT_START)); - locomo_writel(r, mapbase + LOCOMO_LTINT); -} - -static struct irq_chip locomo_lt_chip = { - .name = "LOCOMO-lt", - .ack = locomo_lt_ack_irq, - .mask = locomo_lt_mask_irq, - .unmask = locomo_lt_unmask_irq, -}; - -static void locomo_spi_handler(unsigned int irq, struct irq_desc *desc) -{ - int req, i; - void __iomem *mapbase = get_irq_chip_data(irq); - - req = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIR) & 0x000F; - if (req) { - irq = LOCOMO_IRQ_SPI_START; - - for (i = 0; i <= 3; i++, irq++) { - if (req & (0x0001 << i)) { - generic_handle_irq(irq); - } - } - } -} - -static void locomo_spi_ack_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE); - r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIWE); - - r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIS); - r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIIS); - - r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIWE); - r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIWE); -} - -static void locomo_spi_mask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); - r &= ~(0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIIE); -} - -static void locomo_spi_unmask_irq(unsigned int irq) -{ - void __iomem *mapbase = get_irq_chip_data(irq); - unsigned int r; - r = locomo_readl(mapbase + LOCOMO_SPI + LOCOMO_SPIIE); - r |= (0x0001 << (irq - LOCOMO_IRQ_SPI_START)); - locomo_writel(r, mapbase + LOCOMO_SPI + LOCOMO_SPIIE); -} - -static struct irq_chip locomo_spi_chip = { - .name = "LOCOMO-spi", - .ack = locomo_spi_ack_irq, - .mask = locomo_spi_mask_irq, - .unmask = locomo_spi_unmask_irq, -}; - static void locomo_setup_irq(struct locomo *lchip) { - int irq; - void __iomem *irqbase = lchip->base; + int irq = lchip->irq_base; /* * Install handler for IRQ_LOCOMO_HW. */ set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); - set_irq_chip_data(lchip->irq, irqbase); + set_irq_chip_data(lchip->irq, lchip); set_irq_chained_handler(lchip->irq, locomo_handler); - /* Install handlers for IRQ_LOCOMO_*_BASE */ - set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip); - set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase); - set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler); - - set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip); - set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase); - set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler); - - set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip); - set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase); - set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler); - - set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip); - set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase); - set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler); - - /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */ - set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip); - set_irq_chip_data(LOCOMO_IRQ_KEY_START, irqbase); - set_irq_handler(LOCOMO_IRQ_KEY_START, handle_edge_irq); - set_irq_flags(LOCOMO_IRQ_KEY_START, IRQF_VALID | IRQF_PROBE); - - /* install handlers for IRQ_LOCOMO_GPIO_BASE generated interrupts */ - for (irq = LOCOMO_IRQ_GPIO_START; irq < LOCOMO_IRQ_GPIO_START + 16; irq++) { - set_irq_chip(irq, &locomo_gpio_chip); - set_irq_chip_data(irq, irqbase); - set_irq_handler(irq, handle_edge_irq); - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - - /* install handlers for IRQ_LOCOMO_LT_BASE generated interrupts */ - set_irq_chip(LOCOMO_IRQ_LT_START, &locomo_lt_chip); - set_irq_chip_data(LOCOMO_IRQ_LT_START, irqbase); - set_irq_handler(LOCOMO_IRQ_LT_START, handle_edge_irq); - set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE); - - /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */ - for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 4; irq++) { - set_irq_chip(irq, &locomo_spi_chip); - set_irq_chip_data(irq, irqbase); - set_irq_handler(irq, handle_edge_irq); + /* Install handlers for IRQ_LOCOMO_* */ + for ( ; irq <= lchip->irq_base + 3; irq++) { + set_irq_chip(irq, &locomo_chip); + set_irq_chip_data(irq, lchip); + set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } @@ -555,7 +252,8 @@ locomo_init_one_child(struct locomo *lchip, struct locomo_dev_info *info) dev->mapbase = 0; dev->length = info->length; - memmove(dev->irq, info->irq, sizeof(dev->irq)); + dev->irq[0] = (lchip->irq_base == NO_IRQ) ? + NO_IRQ : lchip->irq_base + info->irq[0]; ret = device_register(&dev->dev); if (ret) { @@ -672,6 +370,7 @@ static int locomo_resume(struct platform_device *dev) static int __locomo_probe(struct device *me, struct resource *mem, int irq) { + struct locomo_platform_data *pdata = me->platform_data; struct locomo *lchip; unsigned long r; int i, ret = -ENODEV; @@ -687,6 +386,7 @@ __locomo_probe(struct device *me, struct resource *mem, int irq) lchip->phys = mem->start; lchip->irq = irq; + lchip->irq_base = (pdata) ? pdata->irq_base : NO_IRQ; /* * Map the whole region. This also maps the @@ -753,7 +453,7 @@ __locomo_probe(struct device *me, struct resource *mem, int irq) * The interrupt controller must be initialised before any * other device to ensure that the interrupts are available. */ - if (lchip->irq != NO_IRQ) + if (lchip->irq != NO_IRQ && lchip->irq_base != NO_IRQ) locomo_setup_irq(lchip); for (i = 0; i < ARRAY_SIZE(locomo_devices); i++) diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 8ba7044c554d..a52a27c1d9be 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -35,6 +35,58 @@ #include <asm/hardware/sa1111.h> +/* SA1111 IRQs */ +#define IRQ_GPAIN0 (0) +#define IRQ_GPAIN1 (1) +#define IRQ_GPAIN2 (2) +#define IRQ_GPAIN3 (3) +#define IRQ_GPBIN0 (4) +#define IRQ_GPBIN1 (5) +#define IRQ_GPBIN2 (6) +#define IRQ_GPBIN3 (7) +#define IRQ_GPBIN4 (8) +#define IRQ_GPBIN5 (9) +#define IRQ_GPCIN0 (10) +#define IRQ_GPCIN1 (11) +#define IRQ_GPCIN2 (12) +#define IRQ_GPCIN3 (13) +#define IRQ_GPCIN4 (14) +#define IRQ_GPCIN5 (15) +#define IRQ_GPCIN6 (16) +#define IRQ_GPCIN7 (17) +#define IRQ_MSTXINT (18) +#define IRQ_MSRXINT (19) +#define IRQ_MSSTOPERRINT (20) +#define IRQ_TPTXINT (21) +#define IRQ_TPRXINT (22) +#define IRQ_TPSTOPERRINT (23) +#define SSPXMTINT (24) +#define SSPRCVINT (25) +#define SSPROR (26) +#define AUDXMTDMADONEA (32) +#define AUDRCVDMADONEA (33) +#define AUDXMTDMADONEB (34) +#define AUDRCVDMADONEB (35) +#define AUDTFSR (36) +#define AUDRFSR (37) +#define AUDTUR (38) +#define AUDROR (39) +#define AUDDTS (40) +#define AUDRDD (41) +#define AUDSTO (42) +#define IRQ_USBPWR (43) +#define IRQ_HCIM (44) +#define IRQ_HCIBUFFACC (45) +#define IRQ_HCIRMTWKP (46) +#define IRQ_NHCIMFCIR (47) +#define IRQ_USB_PORT_RESUME (48) +#define IRQ_S0_READY_NINT (49) +#define IRQ_S1_READY_NINT (50) +#define IRQ_S0_CD_VALID (51) +#define IRQ_S1_CD_VALID (52) +#define IRQ_S0_BVD1_STSCHG (53) +#define IRQ_S1_BVD1_STSCHG (54) + extern void __init sa1110_mb_enable(void); /* @@ -49,6 +101,7 @@ struct sa1111 { struct clk *clk; unsigned long phys; int irq; + int irq_base; /* base for cascaded on-chip IRQs */ spinlock_t lock; void __iomem *base; #ifdef CONFIG_PM @@ -152,36 +205,37 @@ static void sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned int stat0, stat1, i; - void __iomem *base = get_irq_data(irq); + struct sa1111 *sachip = get_irq_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; - stat0 = sa1111_readl(base + SA1111_INTSTATCLR0); - stat1 = sa1111_readl(base + SA1111_INTSTATCLR1); + stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); + stat1 = sa1111_readl(mapbase + SA1111_INTSTATCLR1); - sa1111_writel(stat0, base + SA1111_INTSTATCLR0); + sa1111_writel(stat0, mapbase + SA1111_INTSTATCLR0); desc->chip->ack(irq); - sa1111_writel(stat1, base + SA1111_INTSTATCLR1); + sa1111_writel(stat1, mapbase + SA1111_INTSTATCLR1); if (stat0 == 0 && stat1 == 0) { do_bad_IRQ(irq, desc); return; } - for (i = IRQ_SA1111_START; stat0; i++, stat0 >>= 1) + for (i = 0; stat0; i++, stat0 >>= 1) if (stat0 & 1) - handle_edge_irq(i, irq_desc + i); + generic_handle_irq(i + sachip->irq_base); - for (i = IRQ_SA1111_START + 32; stat1; i++, stat1 >>= 1) + for (i = 32; stat1; i++, stat1 >>= 1) if (stat1 & 1) - handle_edge_irq(i, irq_desc + i); + generic_handle_irq(i + sachip->irq_base); /* For level-based interrupts */ desc->chip->unmask(irq); } -#define SA1111_IRQMASK_LO(x) (1 << (x - IRQ_SA1111_START)) -#define SA1111_IRQMASK_HI(x) (1 << (x - IRQ_SA1111_START - 32)) +#define SA1111_IRQMASK_LO(x) (1 << (x - sachip->irq_base)) +#define SA1111_IRQMASK_HI(x) (1 << (x - sachip->irq_base - 32)) static void sa1111_ack_irq(unsigned int irq) { @@ -189,7 +243,8 @@ static void sa1111_ack_irq(unsigned int irq) static void sa1111_mask_lowirq(unsigned int irq) { - void __iomem *mapbase = get_irq_chip_data(irq); + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned long ie0; ie0 = sa1111_readl(mapbase + SA1111_INTEN0); @@ -199,7 +254,8 @@ static void sa1111_mask_lowirq(unsigned int irq) static void sa1111_unmask_lowirq(unsigned int irq) { - void __iomem *mapbase = get_irq_chip_data(irq); + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned long ie0; ie0 = sa1111_readl(mapbase + SA1111_INTEN0); @@ -216,8 +272,9 @@ static void sa1111_unmask_lowirq(unsigned int irq) */ static int sa1111_retrigger_lowirq(unsigned int irq) { + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned int mask = SA1111_IRQMASK_LO(irq); - void __iomem *mapbase = get_irq_chip_data(irq); unsigned long ip0; int i; @@ -237,8 +294,9 @@ static int sa1111_retrigger_lowirq(unsigned int irq) static int sa1111_type_lowirq(unsigned int irq, unsigned int flags) { + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned int mask = SA1111_IRQMASK_LO(irq); - void __iomem *mapbase = get_irq_chip_data(irq); unsigned long ip0; if (flags == IRQ_TYPE_PROBE) @@ -260,8 +318,9 @@ static int sa1111_type_lowirq(unsigned int irq, unsigned int flags) static int sa1111_wake_lowirq(unsigned int irq, unsigned int on) { + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned int mask = SA1111_IRQMASK_LO(irq); - void __iomem *mapbase = get_irq_chip_data(irq); unsigned long we0; we0 = sa1111_readl(mapbase + SA1111_WAKEEN0); @@ -286,7 +345,8 @@ static struct irq_chip sa1111_low_chip = { static void sa1111_mask_highirq(unsigned int irq) { - void __iomem *mapbase = get_irq_chip_data(irq); + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned long ie1; ie1 = sa1111_readl(mapbase + SA1111_INTEN1); @@ -296,7 +356,8 @@ static void sa1111_mask_highirq(unsigned int irq) static void sa1111_unmask_highirq(unsigned int irq) { - void __iomem *mapbase = get_irq_chip_data(irq); + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned long ie1; ie1 = sa1111_readl(mapbase + SA1111_INTEN1); @@ -313,8 +374,9 @@ static void sa1111_unmask_highirq(unsigned int irq) */ static int sa1111_retrigger_highirq(unsigned int irq) { + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned int mask = SA1111_IRQMASK_HI(irq); - void __iomem *mapbase = get_irq_chip_data(irq); unsigned long ip1; int i; @@ -334,8 +396,9 @@ static int sa1111_retrigger_highirq(unsigned int irq) static int sa1111_type_highirq(unsigned int irq, unsigned int flags) { + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned int mask = SA1111_IRQMASK_HI(irq); - void __iomem *mapbase = get_irq_chip_data(irq); unsigned long ip1; if (flags == IRQ_TYPE_PROBE) @@ -357,8 +420,9 @@ static int sa1111_type_highirq(unsigned int irq, unsigned int flags) static int sa1111_wake_highirq(unsigned int irq, unsigned int on) { + struct sa1111 *sachip = get_irq_chip_data(irq); + void __iomem *mapbase = sachip->base + SA1111_INTC; unsigned int mask = SA1111_IRQMASK_HI(irq); - void __iomem *mapbase = get_irq_chip_data(irq); unsigned long we1; we1 = sa1111_readl(mapbase + SA1111_WAKEEN1); @@ -412,14 +476,14 @@ static void sa1111_setup_irq(struct sa1111 *sachip) for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { set_irq_chip(irq, &sa1111_low_chip); - set_irq_chip_data(irq, irqbase); + set_irq_chip_data(irq, sachip); set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { set_irq_chip(irq, &sa1111_high_chip); - set_irq_chip_data(irq, irqbase); + set_irq_chip_data(irq, sachip); set_irq_handler(irq, handle_edge_irq); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } @@ -428,7 +492,7 @@ static void sa1111_setup_irq(struct sa1111 *sachip) * Register SA1111 interrupt */ set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); - set_irq_data(sachip->irq, irqbase); + set_irq_data(sachip->irq, sachip); set_irq_chained_handler(sachip->irq, sa1111_irq_handler); } diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 37bda5f3dde3..9012004321dd 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c @@ -140,6 +140,7 @@ EXPORT_SYMBOL(reset_scoop); EXPORT_SYMBOL(read_scoop_reg); EXPORT_SYMBOL(write_scoop_reg); +#ifdef CONFIG_PM static void check_scoop_reg(struct scoop_dev *sdev) { unsigned short mcr; @@ -149,7 +150,6 @@ static void check_scoop_reg(struct scoop_dev *sdev) iowrite16(0x0101, sdev->base + SCOOP_MCR); } -#ifdef CONFIG_PM static int scoop_suspend(struct platform_device *dev, pm_message_t state) { struct scoop_dev *sdev = platform_get_drvdata(dev); diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig new file mode 100644 index 000000000000..95d2becfc664 --- /dev/null +++ b/arch/arm/configs/imote2_defconfig @@ -0,0 +1,2077 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc8 +# Sat Feb 13 21:48:53 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +# CONFIG_RD_LZO is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_SLOW_WORK=y +# CONFIG_SLOW_WORK_DEBUG is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="deadline" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set + +# +# Intel PXA2xx/PXA3xx Implementations +# + +# +# Intel/Marvell Dev Platforms (sorted by hardware release time) +# +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_MACH_ZYLONITE300 is not set +# CONFIG_MACH_ZYLONITE320 is not set +# CONFIG_MACH_LITTLETON is not set +# CONFIG_MACH_TAVOREVB is not set +# CONFIG_MACH_SAAR is not set + +# +# Third Party Dev Platforms (sorted by vendor name) +# +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_ARCH_VIPER is not set +# CONFIG_MACH_ARCOM_ZEUS is not set +# CONFIG_MACH_BALLOON3 is not set +# CONFIG_MACH_CSB726 is not set +# CONFIG_MACH_ARMCORE is not set +# CONFIG_MACH_EM_X270 is not set +# CONFIG_MACH_EXEDA is not set +# CONFIG_MACH_CM_X300 is not set +# CONFIG_ARCH_GUMSTIX is not set +CONFIG_MACH_INTELMOTE2=y +# CONFIG_MACH_STARGATE2 is not set +# CONFIG_MACH_XCEP is not set +# CONFIG_TRIZEPS_PXA is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_PCM027 is not set +# CONFIG_MACH_COLIBRI is not set +# CONFIG_MACH_COLIBRI300 is not set +# CONFIG_MACH_COLIBRI320 is not set + +# +# End-user Products (sorted by vendor name) +# +# CONFIG_MACH_H4700 is not set +# CONFIG_MACH_H5000 is not set +# CONFIG_MACH_HIMALAYA is not set +# CONFIG_MACH_MAGICIAN is not set +# CONFIG_MACH_MIOA701 is not set +# CONFIG_PXA_EZX is not set +# CONFIG_MACH_MP900C is not set +# CONFIG_ARCH_PXA_PALM is not set +# CONFIG_PXA_SHARPSL is not set +# CONFIG_ARCH_PXA_ESERIES is not set +CONFIG_PXA27x=y +CONFIG_PXA_SSP=y +CONFIG_PXA_HAVE_BOARD_IRQS=y +CONFIG_PLAT_PXA=y + +# +# Processor Type +# +CONFIG_CPU_XSCALE=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_IWMMXT=y +CONFIG_XSCALE_PMU=y +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug" +# CONFIG_XIP_KERNEL is not set +CONFIG_KEXEC=y +CONFIG_ATAGS_PROC=y + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_DEBUG=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +CONFIG_PM_RUNTIME=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=m +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CT_ACCT=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CT_PROTO_GRE=m +CONFIG_NF_CT_PROTO_SCTP=m +CONFIG_NF_CT_PROTO_UDPLITE=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=m +CONFIG_NF_CT_NETLINK=m +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_POLICY=m +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +CONFIG_NETFILTER_XT_MATCH_REALM=m +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +CONFIG_NF_CONNTRACK_IPV4=m +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_NF_NAT_SNMP_BASIC=m +CONFIG_NF_NAT_PROTO_GRE=m +CONFIG_NF_NAT_PROTO_UDPLITE=m +CONFIG_NF_NAT_PROTO_SCTP=m +CONFIG_NF_NAT_FTP=m +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_TFTP=m +CONFIG_NF_NAT_AMANDA=m +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_CONNTRACK_IPV6=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_LOG=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_RAW=m +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_STP=m +CONFIG_BRIDGE=m +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +CONFIG_IEEE802154=y +# CONFIG_NET_SCHED is not set +CONFIG_NET_CLS_ROUTE=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIVHCI=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +# CONFIG_BT_ATH3K is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=m +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_HAVE_MTD_OTP=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +CONFIG_MTD_CFI_GEOMETRY=y +# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set +CONFIG_MTD_MAP_BANK_WIDTH_2=y +# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +# CONFIG_MTD_CFI_I2 is not set +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_OTP=y +CONFIG_MTD_CFI_INTELEXT=y +# CONFIG_MTD_CFI_AMDSTD is not set +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_XIP is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PXA2XX=y +# CONFIG_MTD_ARM_INTEGRATOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +CONFIG_IEEE802154_DRIVERS=y +# CONFIG_IEEE802154_FAKEHARD is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +# CONFIG_PPP_MPPE is not set +# CONFIG_PPPOE is not set +# CONFIG_PPPOL2TP is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +CONFIG_KEYBOARD_PXA27x=y +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +CONFIG_TOUCHSCREEN_DA9034=y +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=8 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PXA=y +# CONFIG_I2C_PXA_SLAVE is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_PXA2XX=y +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_APM_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_DA9030 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +CONFIG_PMIC_DA903X=y +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_88PM8607 is not set +# CONFIG_AB4500_CORE is not set +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_USERSPACE_CONSUMER=y +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_DA903X=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +CONFIG_IR_CORE=y +CONFIG_VIDEO_IR=y +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +CONFIG_MEDIA_TUNER_CUSTOMISE=y +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEO_V4L1=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_SG=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +CONFIG_VIDEO_IR_I2C=y + +# +# Encoders/decoders and other helper chips +# + +# +# Audio decoders +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TDA9875 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_ADV7343 is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_SAA5246A is not set +# CONFIG_VIDEO_SAA5249 is not set +CONFIG_SOC_CAMERA=y +# CONFIG_SOC_CAMERA_MT9M001 is not set +CONFIG_SOC_CAMERA_MT9M111=y +# CONFIG_SOC_CAMERA_MT9T031 is not set +# CONFIG_SOC_CAMERA_MT9T112 is not set +# CONFIG_SOC_CAMERA_MT9V022 is not set +# CONFIG_SOC_CAMERA_RJ54N1 is not set +# CONFIG_SOC_CAMERA_TW9910 is not set +# CONFIG_SOC_CAMERA_PLATFORM is not set +# CONFIG_SOC_CAMERA_OV772X is not set +# CONFIG_SOC_CAMERA_OV9640 is not set +CONFIG_VIDEO_PXA27x=y +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +# CONFIG_V4L_USB_DRIVERS is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_USB_MR800 is not set +CONFIG_RADIO_TEA5764=y +CONFIG_RADIO_TEA5764_XTAL=y +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_PXA=y +CONFIG_FB_PXA_OVERLAY=y +# CONFIG_FB_PXA_SMARTPANEL is not set +CONFIG_FB_PXA_PARAMETERS=y +# CONFIG_FB_MBX is not set +# CONFIG_FB_W100 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +# CONFIG_BACKLIGHT_DA903X is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +# CONFIG_FONT_8x16 is not set +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +CONFIG_FONT_MINI_4x6=y +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=y +CONFIG_SND_PCM_OSS=y +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +CONFIG_SND_PXA2XX_LIB=y +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_PXA2XX_SOC=y +# CONFIG_SND_PXA2XX_SOC_IMOTE2 is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +CONFIG_HID_APPLE=m +# CONFIG_HID_WACOM is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_GADGET_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AT91 is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_LH7A40X is not set +# CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_PXA25X is not set +# CONFIG_USB_GADGET_R8A66597 is not set +CONFIG_USB_GADGET_PXA27X=y +CONFIG_USB_PXA27X=y +# CONFIG_USB_GADGET_S3C_HSOTG is not set +# CONFIG_USB_GADGET_IMX is not set +# CONFIG_USB_GADGET_S3C2410 is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_FSL_QE is not set +# CONFIG_USB_GADGET_CI13XXX is not set +# CONFIG_USB_GADGET_NET2280 is not set +# CONFIG_USB_GADGET_GOKU is not set +# CONFIG_USB_GADGET_LANGWELL is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +# CONFIG_USB_GADGET_DUALSPEED is not set +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=y +# CONFIG_USB_ETH_RNDIS is not set +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_MULTI is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=m +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_PXA=y +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set +CONFIG_MMC_SPI=y +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_LP3944=y +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DA903X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SA1100 is not set +# CONFIG_RTC_DRV_PXA is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=m +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +CONFIG_CRAMFS=m +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +# CONFIG_NFS_V4 is not set +# CONFIG_ROOT_NFS is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +# CONFIG_NFSD_V4 is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_CIFS=m +CONFIG_CIFS_STATS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_UTF8=m +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_LOCK_ALLOC=y +CONFIG_PROVE_LOCKING=y +CONFIG_LOCKDEP=y +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_LOCKDEP is not set +CONFIG_TRACE_IRQFLAGS=y +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=m +CONFIG_CRYPTO_ALGAPI2=m +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=m +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=m +CONFIG_CRYPTO_HASH=m +CONFIG_CRYPTO_HASH2=m +CONFIG_CRYPTO_RNG2=m +CONFIG_CRYPTO_PCOMP=m +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=m +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=m +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_GHASH=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 5fc44c94b0ad..4611d3ce451a 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc6 -# Sat Nov 7 20:31:18 2009 +# Linux kernel version: 2.6.33-rc6 +# Thu Feb 4 23:08:54 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -32,6 +32,12 @@ CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -45,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=32 # CONFIG_RCU_FANOUT_EXACT is not set @@ -127,14 +134,41 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # @@ -163,6 +197,7 @@ CONFIG_MMU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set CONFIG_ARCH_KIRKWOOD=y # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set @@ -185,6 +220,7 @@ CONFIG_ARCH_KIRKWOOD=y # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set # CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set # # Marvell Kirkwood Implementations @@ -195,7 +231,11 @@ CONFIG_MACH_RD88F6281=y CONFIG_MACH_MV88F6281GTW_GE=y CONFIG_MACH_SHEEVAPLUG=y CONFIG_MACH_TS219=y +CONFIG_MACH_TS41X=y +CONFIG_MACH_OPENRD=y CONFIG_MACH_OPENRD_BASE=y +CONFIG_MACH_OPENRD_CLIENT=y +CONFIG_MACH_NETSPACE_V2=y CONFIG_PLAT_ORION=y # @@ -262,12 +302,10 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y @@ -398,15 +436,18 @@ CONFIG_NET_PKTGEN=m # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y CONFIG_CFG80211=y # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set # CONFIG_CFG80211_REG_DEBUG is not set CONFIG_CFG80211_DEFAULT_PS=y -CONFIG_CFG80211_DEFAULT_PS_VALUE=1 # CONFIG_CFG80211_DEBUGFS is not set CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_WIRELESS_EXT=y +CONFIG_CFG80211_WEXT=y CONFIG_WIRELESS_EXT_SYSFS=y CONFIG_LIB80211=y # CONFIG_LIB80211_DEBUG is not set @@ -556,6 +597,10 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set @@ -606,7 +651,9 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set # CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set @@ -642,6 +689,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_BFA_FC is not set # CONFIG_SCSI_DH is not set @@ -696,15 +744,16 @@ CONFIG_SATA_MV=y # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set # CONFIG_PATA_RDC is not set # CONFIG_PATA_RZ1000 is not set # CONFIG_PATA_SC1200 is not set # CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_SIL680 is not set # CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_SCH is not set @@ -720,7 +769,7 @@ CONFIG_SATA_MV=y # # -# See the help texts for more information. +# The newer stack is recommended. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set @@ -828,13 +877,6 @@ CONFIG_MV643XX_ETH=y # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y -CONFIG_LIBERTAS=y -# CONFIG_LIBERTAS_USB is not set -CONFIG_LIBERTAS_SDIO=y -# CONFIG_LIBERTAS_SPI is not set -# CONFIG_LIBERTAS_DEBUG is not set # CONFIG_LIBERTAS_THINFIRM is not set # CONFIG_ATMEL is not set # CONFIG_AT76C50X_USB is not set @@ -846,19 +888,24 @@ CONFIG_LIBERTAS_SDIO=y # CONFIG_ADM8211 is not set # CONFIG_MAC80211_HWSIM is not set # CONFIG_MWL8K is not set -# CONFIG_P54_COMMON is not set # CONFIG_ATH_COMMON is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_HOSTAP is not set # CONFIG_IPW2100 is not set # CONFIG_IPW2200 is not set # CONFIG_IWLWIFI is not set -# CONFIG_HOSTAP is not set -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -# CONFIG_ZD1211RW is not set -# CONFIG_RT2X00 is not set +# CONFIG_IWM is not set +CONFIG_LIBERTAS=y +# CONFIG_LIBERTAS_USB is not set +CONFIG_LIBERTAS_SDIO=y +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set # CONFIG_HERMES is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set # CONFIG_WL12XX is not set -# CONFIG_IWM is not set +# CONFIG_ZD1211RW is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -881,6 +928,7 @@ CONFIG_LIBERTAS_SDIO=y # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -890,6 +938,7 @@ CONFIG_LIBERTAS_SDIO=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -933,6 +982,7 @@ CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # @@ -1019,11 +1069,6 @@ CONFIG_I2C_MV64XXX=y # CONFIG_I2C_TINY_USB is not set # -# Graphics adapter I2C/DDC channel drivers -# -# CONFIG_I2C_VOODOO3 is not set - -# # Other I2C/SMBus bus drivers # # CONFIG_I2C_PCA_PLATFORM is not set @@ -1032,7 +1077,6 @@ CONFIG_I2C_MV64XXX=y # # Miscellaneous I2C Chip support # -# CONFIG_DS1682 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -1048,6 +1092,8 @@ CONFIG_SPI_MASTER=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_GPIO is not set CONFIG_SPI_ORION=y +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set # # SPI Protocol Masters @@ -1074,10 +1120,12 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: # +# CONFIG_GPIO_CS5535 is not set # CONFIG_GPIO_BT8XX is not set # CONFIG_GPIO_LANGWELL is not set @@ -1116,6 +1164,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_TMIO is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set @@ -1123,6 +1172,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_MC13783 is not set # CONFIG_AB3100_CORE is not set # CONFIG_EZX_PCAP is not set +# CONFIG_MFD_88PM8607 is not set +# CONFIG_AB4500_CORE is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set @@ -1305,6 +1356,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # OTG and related infrastructure # # CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set # CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set CONFIG_MMC=y @@ -1344,6 +1396,7 @@ CONFIG_LEDS_GPIO_PLATFORM=y # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set # # LED Triggers @@ -1388,6 +1441,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set CONFIG_RTC_DRV_S35390A=y # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set @@ -1417,7 +1471,9 @@ CONFIG_RTC_DRV_S35390A=y # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set # CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1684,7 +1740,9 @@ CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set # # Security options @@ -1692,7 +1750,11 @@ CONFIG_DEBUG_LL=y # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig index d2a90eb844a9..ff44bd1615c0 100644 --- a/arch/arm/configs/mini2440_defconfig +++ b/arch/arm/configs/mini2440_defconfig @@ -184,7 +184,7 @@ CONFIG_S3C24XX_PWM=y CONFIG_S3C24XX_GPIO_EXTRA=0 CONFIG_S3C2410_DMA=y # CONFIG_S3C2410_DMA_DEBUG is not set -CONFIG_S3C24XX_ADC=y +CONFIG_S3C_ADC=y CONFIG_PLAT_S3C=y CONFIG_CPU_LLSERIAL_S3C2440_ONLY=y CONFIG_CPU_LLSERIAL_S3C2440=y @@ -199,8 +199,8 @@ CONFIG_S3C_BOOT_UART_FORCE_FIFO=y # # Power management # -# CONFIG_S3C2410_PM_DEBUG is not set -# CONFIG_S3C2410_PM_CHECK is not set +# CONFIG_SAMSUNG_PM_DEBUG is not set +# CONFIG_SAMSUNG_PM_CHECK is not set CONFIG_S3C_LOWLEVEL_UART_PORT=0 CONFIG_S3C_GPIO_SPACE=0 diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig new file mode 100644 index 000000000000..03f76cfc941c --- /dev/null +++ b/arch/arm/configs/mmp2_defconfig @@ -0,0 +1,1194 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc2 +# Tue Jan 5 13:55:22 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +CONFIG_ARCH_MMP=y +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_MACH_TAVOREVB is not set + +# +# Marvell PXA168/910/MMP2 Implmentations +# +# CONFIG_MACH_ASPENITE is not set +# CONFIG_MACH_ZYLONITE2 is not set +# CONFIG_MACH_TTC_DKB is not set +CONFIG_MACH_FLINT=y +CONFIG_CPU_MMP2=y +CONFIG_PLAT_PXA=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_411920 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M user_debug=255" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +# CONFIG_FPE_NWFPE is not set +# CONFIG_FPE_FASTFPE is not set +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_PXA3xx is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +CONFIG_MTD_ONENAND=y +# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set +CONFIG_MTD_ONENAND_GENERIC=y +# CONFIG_MTD_ONENAND_OTP is not set +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set +# CONFIG_MTD_ONENAND_SIM is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +CONFIG_SMC91X=y +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PXA=y +# CONFIG_I2C_PXA_SLAVE is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +CONFIG_MFD_88PM8607=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_MAX8660=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +CONFIG_REGULATOR_88PM8607=y +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_EXT4_USE_FOR_EXT23=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index 6afa2c108eaa..da4710dd1da1 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -176,6 +176,7 @@ CONFIG_ARCH_MV78XX0=y # CONFIG_MACH_DB78X00_BP=y CONFIG_MACH_RD78X00_MASA=y +CONFIG_MACH_TERASTATION_WXL=y CONFIG_PLAT_ORION=y # diff --git a/arch/arm/configs/mx1ads_defconfig b/arch/arm/configs/mx1ads_defconfig deleted file mode 100644 index 3cabbb6d9276..000000000000 --- a/arch/arm/configs/mx1ads_defconfig +++ /dev/null @@ -1,742 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.12-rc1-bk2 -# Sun Mar 27 02:15:46 2005 -# -CONFIG_ARM=y -CONFIG_MMU=y -CONFIG_UID16=y -CONFIG_RWSEM_GENERIC_SPINLOCK=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_IOMAP=y - -# -# Code maturity level options -# -CONFIG_EXPERIMENTAL=y -CONFIG_CLEAN_COMPILE=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_LOCK_KERNEL=y - -# -# General setup -# -CONFIG_LOCALVERSION="" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -# CONFIG_POSIX_MQUEUE is not set -# CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_SYSCTL is not set -# CONFIG_AUDIT is not set -# CONFIG_HOTPLUG is not set -CONFIG_KOBJECT_UEVENT=y -# CONFIG_IKCONFIG is not set -CONFIG_EMBEDDED=y -# CONFIG_KALLSYMS is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_SHMEM=y -CONFIG_CC_ALIGN_FUNCTIONS=0 -CONFIG_CC_ALIGN_LABELS=0 -CONFIG_CC_ALIGN_LOOPS=0 -CONFIG_CC_ALIGN_JUMPS=0 -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 - -# -# Loadable module support -# -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_OBSOLETE_MODPARM=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y - -# -# System Type -# -# CONFIG_ARCH_CLPS7500 is not set -# CONFIG_ARCH_CLPS711X is not set -# CONFIG_ARCH_CO285 is not set -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_INTEGRATOR is not set -# CONFIG_ARCH_IOP3XX is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_IXP2000 is not set -# CONFIG_ARCH_L7200 is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C2410 is not set -# CONFIG_ARCH_SHARK is not set -# CONFIG_ARCH_LH7A40X is not set -# CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_VERSATILE is not set -CONFIG_ARCH_IMX=y -# CONFIG_ARCH_H720X is not set - -# -# IMX Implementations -# -CONFIG_ARCH_MX1ADS=y - -# -# Processor Type -# -CONFIG_CPU_ARM920T=y -CONFIG_CPU_32v4=y -CONFIG_CPU_ABRT_EV4T=y -CONFIG_CPU_CACHE_V4WT=y -CONFIG_CPU_CACHE_VIVT=y -CONFIG_CPU_COPY_V4WB=y -CONFIG_CPU_TLB_V4WBI=y - -# -# Processor Features -# -# CONFIG_ARM_THUMB is not set -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_DISABLE is not set -# CONFIG_CPU_DCACHE_WRITETHROUGH is not set - -# -# Bus support -# -CONFIG_ISA=y - -# -# PCCARD (PCMCIA/CardBus) support -# -# CONFIG_PCCARD is not set - -# -# Kernel Features -# -CONFIG_PREEMPT=y -# CONFIG_LEDS is not set -CONFIG_ALIGNMENT_TRAP=y - -# -# Boot options -# -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=ttySMX0,57600n8 ip=bootp root=/dev/nfs" -# CONFIG_XIP_KERNEL is not set - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y -CONFIG_FPE_FASTFPE=y - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_AOUT is not set -# CONFIG_BINFMT_MISC is not set -# CONFIG_ARTHUR is not set - -# -# Power management options -# -# CONFIG_PM is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -# CONFIG_FW_LOADER is not set -# CONFIG_DEBUG_DRIVER is not set - -# -# Memory Technology Devices (MTD) -# -CONFIG_MTD=y -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set -# CONFIG_MTD_AFS_PARTS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=y -CONFIG_MTD_BLOCK=y -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set - -# -# RAM/ROM/Flash chip drivers -# -# CONFIG_MTD_CFI is not set -# CONFIG_MTD_JEDECPROBE is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_RAM is not set -CONFIG_MTD_ROM=y -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLKMTD is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# -# CONFIG_MTD_NAND is not set - -# -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNP is not set - -# -# Block devices -# -# CONFIG_BLK_DEV_FD is not set -# CONFIG_BLK_DEV_XD is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_CDROM_PKTCDVD is not set - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -# CONFIG_IOSCHED_AS is not set -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_ATA_OVER_ETH is not set - -# -# SCSI device support -# -# CONFIG_SCSI is not set - -# -# Multi-device support (RAID and LVM) -# -# CONFIG_MD is not set - -# -# Fusion MPT device support -# - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Networking support -# -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=m -CONFIG_PACKET_MMAP=y -# CONFIG_NETLINK_DEV is not set -CONFIG_UNIX=y -# CONFIG_NET_KEY is not set -CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set -# CONFIG_IPV6 is not set -# CONFIG_NETFILTER is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_NET_DIVERT is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# -# CONFIG_NET_SCHED is not set -# CONFIG_NET_CLS_ROUTE is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_HAMRADIO is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set - -# -# ARCnet devices -# -# CONFIG_ARCNET is not set - -# -# Ethernet (10 or 100Mbit) -# -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_LANCE is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_SMC91X is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_NET_PCI is not set -# CONFIG_NET_POCKET is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# -# CONFIG_TR is not set - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# Wan interfaces -# -# CONFIG_WAN is not set -CONFIG_PPP=y -# CONFIG_PPP_MULTILINK is not set -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=y -# CONFIG_PPP_SYNC_TTY is not set -CONFIG_PPP_DEFLATE=y -CONFIG_PPP_BSDCOMP=y -# CONFIG_PPPOE is not set -# CONFIG_SLIP is not set -# CONFIG_SHAPER is not set -# CONFIG_NETCONSOLE is not set - -# -# ISDN subsystem -# -# CONFIG_ISDN is not set - -# -# Input device support -# -# CONFIG_INPUT is not set - -# -# Hardware I/O ports -# -# CONFIG_SERIO is not set -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y - -# -# Character devices -# -# CONFIG_VT is not set -# CONFIG_SERIAL_NONSTANDARD is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_IMX=y -CONFIG_SERIAL_IMX_CONSOLE=y -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_UNIX98_PTYS=y -# CONFIG_LEGACY_PTYS is not set - -# -# IPMI -# -# CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set -# CONFIG_NVRAM is not set -CONFIG_RTC=m -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set - -# -# Ftape, the floppy tape device driver -# -# CONFIG_DRM is not set -# CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# -# CONFIG_TCG_TPM is not set - -# -# I2C support -# -# CONFIG_I2C is not set - -# -# Misc devices -# - -# -# Multimedia devices -# -# CONFIG_VIDEO_DEV is not set - -# -# Digital Video Broadcasting Devices -# -# CONFIG_DVB is not set - -# -# Graphics support -# -# CONFIG_FB is not set - -# -# Sound -# -# CONFIG_SOUND is not set - -# -# USB support -# -CONFIG_USB_ARCH_HAS_HCD=y -# CONFIG_USB_ARCH_HAS_OHCI is not set -# CONFIG_USB is not set - -# -# USB Gadget Support -# -# CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# -# CONFIG_MMC is not set - -# -# File systems -# -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set -# CONFIG_JBD is not set -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set - -# -# XFS support -# -# CONFIG_XFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y -# CONFIG_AUTOFS_FS is not set -# CONFIG_AUTOFS4_FS is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_NTFS_FS is not set - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_SYSFS=y -CONFIG_DEVFS_FS=y -CONFIG_DEVFS_MOUNT=y -# CONFIG_DEVFS_DEBUG is not set -# CONFIG_DEVPTS_FS_XATTR is not set -CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS_FS is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=0 -# CONFIG_JFFS2_FS_NAND is not set -# CONFIG_JFFS2_FS_NOR_ECC is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -CONFIG_JFFS2_ZLIB=y -CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -CONFIG_CRAMFS=y -# CONFIG_VXFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set - -# -# Network File Systems -# -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set -CONFIG_ROOT_NFS=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -# CONFIG_SMB_FS is not set -# CONFIG_CIFS is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set - -# -# Partition Types -# -# CONFIG_PARTITION_ADVANCED is not set -CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -# CONFIG_NLS_ISO8859_1 is not set -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_UTF8 is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set - -# -# Kernel hacking -# -# CONFIG_PRINTK_TIME is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_SCHEDSTATS is not set -# CONFIG_DEBUG_SLAB is not set -CONFIG_DEBUG_PREEMPT=y -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_INFO=y -# CONFIG_DEBUG_FS is not set -CONFIG_FRAME_POINTER=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_ERRORS=y -# CONFIG_DEBUG_LL is not set - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_HMAC is not set -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_MD4 is not set -# CONFIG_CRYPTO_MD5 is not set -# CONFIG_CRYPTO_SHA1 is not set -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_DES is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_AES is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set -# CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# - -# -# Library routines -# -CONFIG_CRC_CCITT=y -CONFIG_CRC32=y -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/mx27_defconfig index edfdd6faf800..b4c1366e9e0d 100644 --- a/arch/arm/configs/mx27_defconfig +++ b/arch/arm/configs/mx27_defconfig @@ -200,7 +200,7 @@ CONFIG_MACH_MX27ADS=y CONFIG_MACH_PCM038=y CONFIG_MACH_PCM970_BASEBOARD=y CONFIG_MACH_MX27_3DS=y -CONFIG_MACH_MX27LITE=y +CONFIG_MACH_IMX27LITE=y CONFIG_MXC_IRQ_PRIOR=y CONFIG_MXC_PWM=y diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig new file mode 100644 index 000000000000..c88e9527a8ec --- /dev/null +++ b/arch/arm/configs/mx51_defconfig @@ -0,0 +1,1286 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc6 +# Tue Feb 2 15:20:48 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=18 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MXC91231 is not set +CONFIG_ARCH_MX5=y +CONFIG_ARCH_MX51=y + +# +# MX5 platforms: +# +CONFIG_MACH_MX51_BABBAGE=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_TZIC=y +# CONFIG_MXC_PWM is not set +CONFIG_ARCH_MXC_IOMUX_V3=y + +# +# Processor Type +# +CONFIG_CPU_32v6K=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_HAS_TLS_REG=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/nfs nfsroot=192.168.0.101:/shared/nfs ip=dhcp" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=m + +# +# Power management options +# +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_VERBOSE is not set +CONFIG_CAN_PM_TRACE=y +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=m +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y +CONFIG_ATA_SFF=y +# CONFIG_SATA_MV is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_LXT_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_ICPLUS_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_NATIONAL_PHY=y +CONFIG_STE10XP=y +CONFIG_LSI_ET1011C_PHY=y +CONFIG_FIXED_PHY=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_GPIO=y +CONFIG_NET_ETHERNET=y +CONFIG_MII=m +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +# CONFIG_SMSC911X is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_FEC=y +# CONFIG_FEC2 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +CONFIG_MOUSE_PS2_ELANTECH=y +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=m +# CONFIG_I2C_HELPER_AUTO is not set + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_IMX is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_MFD_88PM8607 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=m +# CONFIG_MMC_SDHCI_PLTFM is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGERS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +# CONFIG_TMPFS is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=m +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_ERRORS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index 85b05d3e279b..ee1ebd8dfa80 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.32-rc6 -# Sat Nov 7 20:52:21 2009 +# Linux kernel version: 2.6.33-rc6 +# Thu Feb 4 23:30:00 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -32,6 +32,12 @@ CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -45,6 +51,7 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=32 # CONFIG_RCU_FANOUT_EXACT is not set @@ -122,14 +129,41 @@ CONFIG_LBDAF=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # @@ -158,6 +192,7 @@ CONFIG_MMU=y # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set @@ -180,6 +215,7 @@ CONFIG_ARCH_ORION5X=y # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set # CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set # # Orion Implementations @@ -192,6 +228,7 @@ CONFIG_MACH_TS209=y CONFIG_MACH_TERASTATION_PRO2=y CONFIG_MACH_LINKSTATION_PRO=y CONFIG_MACH_LINKSTATION_MINI=y +CONFIG_MACH_LINKSTATION_LS_HGL=y CONFIG_MACH_TS409=y CONFIG_MACH_WRT350N_V2=y CONFIG_MACH_TS78XX=y @@ -268,12 +305,10 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_MLOCKED_PAGE_BIT=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_LEDS=y @@ -412,10 +447,6 @@ CONFIG_NET_PKTGEN=m # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set -CONFIG_CFG80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIRELESS_OLD_REGULATORY is not set -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_LIB80211 is not set # @@ -554,6 +585,10 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set @@ -562,6 +597,7 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_ATA_OVER_ETH is not set # CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set # CONFIG_PHANTOM is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set @@ -569,6 +605,7 @@ CONFIG_MISC_DEVICES=y # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set # CONFIG_ISL29003 is not set +# CONFIG_DS1682 is not set # CONFIG_C2PORT is not set # @@ -621,7 +658,9 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set +# CONFIG_SCSI_HPSA is not set # CONFIG_SCSI_3W_9XXX is not set +# CONFIG_SCSI_3W_SAS is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set @@ -657,6 +696,7 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_NSP32 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set +# CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_BFA_FC is not set # CONFIG_SCSI_DH is not set @@ -711,15 +751,16 @@ CONFIG_SATA_MV=y # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set # CONFIG_PATA_RDC is not set # CONFIG_PATA_RZ1000 is not set # CONFIG_PATA_SC1200 is not set # CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_SIL680 is not set # CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set @@ -736,7 +777,7 @@ CONFIG_SATA_MV=y # # -# See the help texts for more information. +# The newer stack is recommended. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set @@ -842,8 +883,10 @@ CONFIG_MV643XX_ETH=y # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set CONFIG_WLAN=y -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -866,6 +909,7 @@ CONFIG_WLAN=y # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -875,6 +919,7 @@ CONFIG_WLAN=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -993,11 +1038,6 @@ CONFIG_I2C_MV64XXX=y # CONFIG_I2C_TINY_USB is not set # -# Graphics adapter I2C/DDC channel drivers -# -# CONFIG_I2C_VOODOO3 is not set - -# # Other I2C/SMBus bus drivers # # CONFIG_I2C_PCA_PLATFORM is not set @@ -1006,7 +1046,6 @@ CONFIG_I2C_MV64XXX=y # # Miscellaneous I2C Chip support # -# CONFIG_DS1682 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set @@ -1033,10 +1072,12 @@ CONFIG_GPIO_SYSFS=y # CONFIG_GPIO_MAX732X is not set # CONFIG_GPIO_PCA953X is not set # CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_ADP5588 is not set # # PCI GPIO expanders: # +# CONFIG_GPIO_CS5535 is not set # CONFIG_GPIO_BT8XX is not set # CONFIG_GPIO_LANGWELL is not set @@ -1079,6 +1120,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set CONFIG_SENSORS_LM75=y # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set @@ -1104,6 +1146,7 @@ CONFIG_SENSORS_LM75=y # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set @@ -1118,6 +1161,7 @@ CONFIG_SENSORS_LM75=y # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -1140,11 +1184,13 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_TMIO is not set # CONFIG_MFD_TC6393XB is not set # CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_AB3100_CORE is not set +# CONFIG_MFD_88PM8607 is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set @@ -1316,6 +1362,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y # OTG and related infrastructure # # CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set # CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set # CONFIG_MMC is not set @@ -1332,6 +1379,7 @@ CONFIG_LEDS_GPIO_PLATFORM=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set # # LED Triggers @@ -1377,6 +1425,7 @@ CONFIG_RTC_DRV_PCF8563=y # CONFIG_RTC_DRV_PCF8583 is not set CONFIG_RTC_DRV_M41T80=y # CONFIG_RTC_DRV_M41T80_WDT is not set +# CONFIG_RTC_DRV_BQ32K is not set CONFIG_RTC_DRV_S35390A=y # CONFIG_RTC_DRV_FM3130 is not set # CONFIG_RTC_DRV_RX8581 is not set @@ -1398,7 +1447,9 @@ CONFIG_RTC_DRV_S35390A=y CONFIG_RTC_DRV_M48T86=y # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set # CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set # CONFIG_RTC_DRV_V3020 is not set # @@ -1686,7 +1737,9 @@ CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set # # Security options @@ -1694,7 +1747,11 @@ CONFIG_DEBUG_LL=y # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig index 791b8c39aefc..113511f91eb7 100644 --- a/arch/arm/configs/pxa168_defconfig +++ b/arch/arm/configs/pxa168_defconfig @@ -1,15 +1,13 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.29-rc3 -# Fri Mar 20 13:43:13 2009 +# Linux kernel version: 2.6.33-rc3 +# Tue Jan 12 08:57:10 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_GENERIC_GPIO=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_MMU=y -# CONFIG_NO_IOPORT is not set CONFIG_GENERIC_HARDIRQS=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y @@ -18,13 +16,12 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y CONFIG_HARDIRQS_SW_RESEND=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -35,6 +32,12 @@ CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y @@ -46,11 +49,13 @@ CONFIG_SYSVIPC_SYSCTL=y # # RCU Subsystem # -CONFIG_CLASSIC_RCU=y -# CONFIG_TREE_RCU is not set -# CONFIG_PREEMPT_RCU is not set +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set -# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_GROUP_SCHED is not set @@ -64,10 +69,10 @@ CONFIG_NAMESPACES=y # CONFIG_USER_NS is not set # CONFIG_PID_NS is not set # CONFIG_NET_NS is not set -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" +# CONFIG_BLK_DEV_INITRD is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y @@ -78,17 +83,20 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y -CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set @@ -98,6 +106,11 @@ CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -109,8 +122,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set +CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set @@ -118,31 +130,62 @@ CONFIG_BLOCK=y # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set # CONFIG_FREEZER is not set # # System Type # +CONFIG_MMU=y # CONFIG_ARCH_AAEC2000 is not set # CONFIG_ARCH_INTEGRATOR is not set # CONFIG_ARCH_REALVIEW is not set # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set # CONFIG_ARCH_EBSA110 is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set -# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_NOMADIK is not set # CONFIG_ARCH_IOP13XX is not set # CONFIG_ARCH_IOP32X is not set # CONFIG_ARCH_IOP33X is not set @@ -150,26 +193,30 @@ CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_ARCH_IXP2000 is not set # CONFIG_ARCH_IXP4XX is not set # CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set # CONFIG_ARCH_KIRKWOOD is not set -# CONFIG_ARCH_KS8695 is not set -# CONFIG_ARCH_NS9XXX is not set # CONFIG_ARCH_LOKI is not set # CONFIG_ARCH_MV78XX0 is not set -# CONFIG_ARCH_MXC is not set # CONFIG_ARCH_ORION5X is not set +CONFIG_ARCH_MMP=y +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set # CONFIG_ARCH_PNX4008 is not set # CONFIG_ARCH_PXA is not set -CONFIG_ARCH_MMP=y +# CONFIG_ARCH_MSM is not set # CONFIG_ARCH_RPC is not set # CONFIG_ARCH_SA1100 is not set # CONFIG_ARCH_S3C2410 is not set # CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set # CONFIG_ARCH_SHARK is not set # CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set -# CONFIG_ARCH_MSM is not set -# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set # CONFIG_MACH_TAVOREVB is not set # @@ -177,6 +224,7 @@ CONFIG_ARCH_MMP=y # CONFIG_MACH_ASPENITE=y CONFIG_MACH_ZYLONITE2=y +CONFIG_MACH_AVENGERS_LITE=y # CONFIG_MACH_TTC_DKB is not set CONFIG_CPU_PXA168=y CONFIG_PLAT_PXA=y @@ -187,7 +235,7 @@ CONFIG_PLAT_PXA=y CONFIG_CPU_MOHAWK=y CONFIG_CPU_32v5=y CONFIG_CPU_ABRT_EV5T=y -CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_PABRT_LEGACY=y CONFIG_CPU_CACHE_VIVT=y CONFIG_CPU_COPY_V4WB=y CONFIG_CPU_TLB_V4WBI=y @@ -201,7 +249,7 @@ CONFIG_ARM_THUMB=y # CONFIG_CPU_ICACHE_DISABLE is not set # CONFIG_CPU_DCACHE_DISABLE is not set # CONFIG_CPU_BPREDICT_DISABLE is not set -# CONFIG_OUTER_CACHE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 CONFIG_IWMMXT=y CONFIG_COMMON_CLKDEV=y @@ -223,13 +271,15 @@ CONFIG_VMSPLIT_3G=y # CONFIG_VMSPLIT_2G is not set # CONFIG_VMSPLIT_1G is not set CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y CONFIG_HZ=100 CONFIG_AEABI=y CONFIG_OABI_COMPAT=y -CONFIG_ARCH_FLATMEM_HAS_HOLES=y # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -237,12 +287,14 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4096 +CONFIG_SPLIT_PTLOCK_CPUS=999999 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set # # Boot options @@ -288,7 +340,6 @@ CONFIG_NET=y # # Networking options # -CONFIG_COMPAT_NET_DEV_OPS=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y @@ -330,6 +381,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -343,6 +395,8 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set @@ -355,13 +409,13 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_PHONET is not set CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -# CONFIG_WIRELESS_EXT is not set # CONFIG_LIB80211 is not set -# CONFIG_MAC80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set @@ -374,6 +428,7 @@ CONFIG_WIRELESS_OLD_REGULATORY=y # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set # CONFIG_STANDALONE is not set # CONFIG_PREVENT_FIRMWARE_BUILD is not set CONFIG_FW_LOADER=y @@ -412,8 +467,10 @@ CONFIG_MII=y # CONFIG_AX88796 is not set CONFIG_SMC91X=y # CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set # CONFIG_SMC911X is not set # CONFIG_SMSC911X is not set +# CONFIG_DNET is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set @@ -422,15 +479,12 @@ CONFIG_SMC91X=y # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI_LEDS is not set +CONFIG_WLAN=y +# CONFIG_HOSTAP is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers @@ -442,6 +496,7 @@ CONFIG_SMC91X=y # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set +# CONFIG_PHONE is not set # # Input device support @@ -449,6 +504,7 @@ CONFIG_SMC91X=y CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces @@ -510,6 +566,11 @@ CONFIG_UNIX98_PTYS=y # CONFIG_TCG_TPM is not set # CONFIG_I2C is not set # CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set @@ -530,11 +591,14 @@ CONFIG_GPIOLIB=y # # SPI GPIO expanders: # + +# +# AC97 GPIO expanders: +# # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y @@ -555,22 +619,8 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_T7L66XB is not set # CONFIG_MFD_TC6387XB is not set # CONFIG_MFD_TC6393XB is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_VIDEO_MEDIA is not set - -# -# Multimedia drivers -# -# CONFIG_DAB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support @@ -595,13 +645,17 @@ CONFIG_DUMMY_CONSOLE=y # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set -# CONFIG_ACCESSIBILITY is not set # CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set -# CONFIG_REGULATOR is not set +# CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set + +# +# TI VLYNQ +# # CONFIG_STAGING is not set # @@ -613,10 +667,13 @@ CONFIG_RTC_LIB=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y @@ -627,6 +684,11 @@ CONFIG_INOTIFY_USER=y CONFIG_GENERIC_ACL=y # +# Caches +# +# CONFIG_FSCACHE is not set + +# # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set @@ -673,6 +735,7 @@ CONFIG_NFS_FS=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set CONFIG_LOCKD=y @@ -681,7 +744,6 @@ CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -706,6 +768,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set @@ -714,11 +777,15 @@ CONFIG_DEBUG_KERNEL=y CONFIG_DETECT_SOFTLOCKUP=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_DEBUG_PREEMPT is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set @@ -738,28 +805,33 @@ CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set CONFIG_HAVE_FUNCTION_TRACER=y - -# -# Tracers -# +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y # CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_PREEMPT_TRACER is not set # CONFIG_SCHED_TRACER is not set -# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set # CONFIG_BOOT_TRACER is not set -# CONFIG_TRACE_BRANCH_PROFILING is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set # CONFIG_STACK_TRACER is not set -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set @@ -768,7 +840,9 @@ CONFIG_DEBUG_USER=y CONFIG_DEBUG_ERRORS=y # CONFIG_DEBUG_STACK_USAGE is not set CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set # CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set # # Security options @@ -776,13 +850,16 @@ CONFIG_DEBUG_LL=y # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y # # Crypto core or helper # -# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD2=y @@ -791,10 +868,12 @@ CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set @@ -822,11 +901,13 @@ CONFIG_CRYPTO_CBC=y # # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set @@ -863,6 +944,7 @@ CONFIG_CRYPTO_DES=y # Compression # # CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # @@ -870,6 +952,7 @@ CONFIG_CRYPTO_DES=y # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set # # Library routines @@ -884,7 +967,7 @@ CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y -CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/raumfeld_defconfig b/arch/arm/configs/raumfeld_defconfig new file mode 100644 index 000000000000..acb1a8f30e31 --- /dev/null +++ b/arch/arm/configs/raumfeld_defconfig @@ -0,0 +1,1898 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32-rc5 +# Sun Nov 1 21:57:32 2009 +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MTD_XIP=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +CONFIG_SLOW_WORK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +CONFIG_ARCH_PXA=y +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set + +# +# Intel PXA2xx/PXA3xx Implementations +# + +# +# Supported PXA3xx Processor Variants +# +CONFIG_CPU_PXA300=y +# CONFIG_CPU_PXA310 is not set +CONFIG_CPU_PXA320=y +# CONFIG_CPU_PXA930 is not set +# CONFIG_CPU_PXA935 is not set +# CONFIG_CPU_PXA950 is not set + +# +# Intel/Marvell Dev Platforms (sorted by hardware release time) +# +# CONFIG_ARCH_LUBBOCK is not set +# CONFIG_MACH_MAINSTONE is not set +# CONFIG_MACH_ZYLONITE is not set +# CONFIG_MACH_LITTLETON is not set +# CONFIG_MACH_TAVOREVB is not set +# CONFIG_MACH_SAAR is not set + +# +# Third Party Dev Platforms (sorted by vendor name) +# +# CONFIG_ARCH_PXA_IDP is not set +# CONFIG_ARCH_VIPER is not set +# CONFIG_MACH_BALLOON3 is not set +# CONFIG_MACH_CSB726 is not set +# CONFIG_MACH_ARMCORE is not set +# CONFIG_MACH_EM_X270 is not set +# CONFIG_MACH_EXEDA is not set +# CONFIG_MACH_CM_X300 is not set +# CONFIG_ARCH_GUMSTIX is not set +# CONFIG_MACH_INTELMOTE2 is not set +# CONFIG_MACH_STARGATE2 is not set +# CONFIG_MACH_XCEP is not set +# CONFIG_TRIZEPS_PXA is not set +# CONFIG_MACH_LOGICPD_PXA270 is not set +# CONFIG_MACH_PCM027 is not set +# CONFIG_MACH_COLIBRI is not set +# CONFIG_MACH_COLIBRI300 is not set +# CONFIG_MACH_COLIBRI320 is not set + +# +# End-user Products (sorted by vendor name) +# +# CONFIG_MACH_H4700 is not set +# CONFIG_MACH_H5000 is not set +# CONFIG_MACH_HIMALAYA is not set +# CONFIG_MACH_MAGICIAN is not set +# CONFIG_MACH_MIOA701 is not set +# CONFIG_PXA_EZX is not set +# CONFIG_MACH_MP900C is not set +# CONFIG_ARCH_PXA_PALM is not set +CONFIG_MACH_RAUMFELD_RC=y +CONFIG_MACH_RAUMFELD_CONNECTOR=y +CONFIG_MACH_RAUMFELD_PROTO=y +CONFIG_MACH_RAUMFELD_SPEAKER=y +# CONFIG_PXA_SHARPSL is not set +# CONFIG_ARCH_PXA_ESERIES is not set +CONFIG_PXA3xx=y +CONFIG_PXA_SSP=y +CONFIG_PLAT_PXA=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_XSC3=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5T=y +CONFIG_CPU_PABRT_LEGACY=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_IO_36=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_CACHE_XSC3L2=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_IWMMXT=y +CONFIG_COMMON_CLKDEV=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="console=ttyS0,115200 rw" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_APM_EMULATION=y +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_PRIVACY is not set +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_REG_DEBUG=y +CONFIG_CFG80211_DEFAULT_PS=y +CONFIG_CFG80211_DEFAULT_PS_VALUE=1 +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=y +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +CONFIG_NFTL=y +CONFIG_NFTL_RW=y +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +CONFIG_MTD_BLOCK2MTD=y + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_H1900 is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_SHARPSL is not set +CONFIG_MTD_NAND_PXA3xx=y +# CONFIG_MTD_NAND_PXA3xx_BUILTIN is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_ISL29003=y +CONFIG_TI_DAC7512=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +CONFIG_LIBERTAS=y +# CONFIG_LIBERTAS_USB is not set +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +# CONFIG_LIBERTAS_DEBUG is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_P54_COMMON is not set +# CONFIG_ATH_COMMON is not set +# CONFIG_HOSTAP is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_ZD1211RW is not set +# CONFIG_RT2X00 is not set +# CONFIG_WL12XX is not set +# CONFIG_IWM is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +CONFIG_USB_USBNET=y +# CONFIG_USB_NET_AX8817X is not set +CONFIG_USB_NET_CDCETHER=y +# CONFIG_USB_NET_CDC_EEM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +CONFIG_USB_NET_MCS7830=y +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PXA27x is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +CONFIG_TOUCHSCREEN_EETI=m +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +CONFIG_INPUT_GPIO_ROTARY_ENCODER=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_PXA=y +CONFIG_SERIAL_PXA_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_PXA=y +# CONFIG_I2C_PXA_SLAVE is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_DEBUG=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BITBANG=y +CONFIG_SPI_GPIO=y +# CONFIG_SPI_PXA2XX is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_DEBUG_GPIO=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +CONFIG_W1=m + +# +# 1-wire Bus Masters +# +# CONFIG_W1_MASTER_DS2490 is not set +# CONFIG_W1_MASTER_DS2482 is not set +# CONFIG_W1_MASTER_DS1WM is not set +CONFIG_W1_MASTER_GPIO=m + +# +# 1-wire Slaves +# +# CONFIG_W1_SLAVE_THERM is not set +# CONFIG_W1_SLAVE_SMEM is not set +# CONFIG_W1_SLAVE_DS2431 is not set +# CONFIG_W1_SLAVE_DS2433 is not set +CONFIG_W1_SLAVE_DS2760=m +# CONFIG_W1_SLAVE_BQ27000 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_PDA_POWER=y +# CONFIG_APM_POWER is not set +CONFIG_BATTERY_DS2760=m +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_LIS3_SPI=y +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +CONFIG_REGULATOR=y +CONFIG_REGULATOR_DEBUG=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +CONFIG_REGULATOR_MAX8660=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_PXA=y +# CONFIG_FB_PXA_OVERLAY is not set +# CONFIG_FB_PXA_SMARTPANEL is not set +# CONFIG_FB_PXA_PARAMETERS is not set +CONFIG_PXA3XX_GCU=y +# CONFIG_FB_MBX is not set +# CONFIG_FB_W100 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_RAUMFELD_CLUT224=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +CONFIG_SND_ARM=y +CONFIG_SND_PXA2XX_LIB=y +# CONFIG_SND_PXA2XX_AC97 is not set +CONFIG_SND_SPI=y +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_PXA2XX_SOC=y +CONFIG_SND_PXA_SOC_SSP=y +CONFIG_SND_SOC_RAUMFELD=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AK4104=y +CONFIG_SND_SOC_CS4270=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +# CONFIG_DRAGONRISE_FF is not set +CONFIG_HID_EZKEY=y +CONFIG_HID_KYE=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LOGITECH=y +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_NTRIG=y +CONFIG_HID_PANTHERLORD=y +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +# CONFIG_GREENASIA_FF is not set +CONFIG_HID_SMARTJOYPLUS=y +# CONFIG_SMARTJOYPLUS_FF is not set +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +# CONFIG_THRUSTMASTER_FF is not set +CONFIG_HID_ZEROPLUS=y +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +CONFIG_USB_STORAGE_FREECOM=y +CONFIG_USB_STORAGE_ISD200=y +CONFIG_USB_STORAGE_USBAT=y +CONFIG_USB_STORAGE_SDDR09=y +CONFIG_USB_STORAGE_SDDR55=y +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_PXA=m +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_LT3593=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SA1100 is not set +CONFIG_RTC_DRV_PXA=y +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +# CONFIG_UIO_PDRV is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_SERCOS3 is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT2_FS_XIP=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_XIP=y +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +CONFIG_CACHEFILES=y +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=y +CONFIG_NLS_CODEPAGE_775=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +CONFIG_NLS_CODEPAGE_855=y +CONFIG_NLS_CODEPAGE_857=y +CONFIG_NLS_CODEPAGE_860=y +CONFIG_NLS_CODEPAGE_861=y +CONFIG_NLS_CODEPAGE_862=y +CONFIG_NLS_CODEPAGE_863=y +CONFIG_NLS_CODEPAGE_864=y +CONFIG_NLS_CODEPAGE_865=y +CONFIG_NLS_CODEPAGE_866=y +CONFIG_NLS_CODEPAGE_869=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_950=y +CONFIG_NLS_CODEPAGE_932=y +CONFIG_NLS_CODEPAGE_949=y +CONFIG_NLS_CODEPAGE_874=y +CONFIG_NLS_ISO8859_8=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_ISO8859_3=y +CONFIG_NLS_ISO8859_4=y +CONFIG_NLS_ISO8859_5=y +CONFIG_NLS_ISO8859_6=y +CONFIG_NLS_ISO8859_7=y +CONFIG_NLS_ISO8859_9=y +CONFIG_NLS_ISO8859_13=y +CONFIG_NLS_ISO8859_14=y +CONFIG_NLS_ISO8859_15=y +CONFIG_NLS_KOI8_R=y +CONFIG_NLS_KOI8_U=y +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_DEBUG_ICEDCC is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 2f10dae02796..8e94c3caeb8c 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig @@ -187,7 +187,7 @@ CONFIG_S3C24XX_GPIO_EXTRA128=y CONFIG_PM_SIMTEC=y CONFIG_S3C2410_DMA=y # CONFIG_S3C2410_DMA_DEBUG is not set -CONFIG_S3C24XX_ADC=y +CONFIG_S3C_ADC=y CONFIG_MACH_SMDK=y CONFIG_PLAT_S3C=y CONFIG_CPU_LLSERIAL_S3C2410=y @@ -203,8 +203,8 @@ CONFIG_S3C_BOOT_UART_FORCE_FIFO=y # # Power management # -# CONFIG_S3C2410_PM_DEBUG is not set -# CONFIG_S3C2410_PM_CHECK is not set +# CONFIG_SAMSUNG_PM_DEBUG is not set +# CONFIG_SAMSUNG_PM_CHECK is not set CONFIG_S3C_LOWLEVEL_UART_PORT=0 CONFIG_S3C_GPIO_SPACE=0 CONFIG_S3C_DEV_HSMMC=y diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p6440_defconfig new file mode 100644 index 000000000000..279a15e53114 --- /dev/null +++ b/arch/arm/configs/s5p6440_defconfig @@ -0,0 +1,969 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.33-rc2 +# Sat Jan 9 16:33:55 2010 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_NO_IOPORT=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +# CONFIG_SYSVIPC is not set +# CONFIG_BSD_PROCESS_ACCT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +# CONFIG_EMBEDDED is not set +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_CLK=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +CONFIG_ARCH_S5P6440=y +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_U8500 is not set +CONFIG_PLAT_SAMSUNG=y +CONFIG_SAMSUNG_CLKSRC=y +CONFIG_SAMSUNG_IRQ_VIC_TIMER=y +CONFIG_SAMSUNG_IRQ_UART=y +CONFIG_SAMSUNG_GPIO_EXTRA=0 +CONFIG_PLAT_S3C=y + +# +# Boot options +# +CONFIG_S3C_BOOT_ERROR_RESET=y +CONFIG_S3C_BOOT_UART_FORCE_FIFO=y + +# +# Power management +# +CONFIG_S3C_LOWLEVEL_UART_PORT=1 +CONFIG_S3C_GPIO_SPACE=0 +CONFIG_S3C_GPIO_TRACK=y +CONFIG_PLAT_S5P=y +CONFIG_CPU_S5P6440_INIT=y +CONFIG_CPU_S5P6440_CLOCK=y +CONFIG_CPU_S5P6440=y +CONFIG_MACH_SMDK6440=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +# CONFIG_ARM_ERRATA_411920 is not set +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ=200 +CONFIG_AEABI=y +CONFIG_OABI_COMPAT=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=999999 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_FPE_NWFPE=y +# CONFIG_FPE_NWFPE_XP is not set +# CONFIG_FPE_FASTFPE is not set +# CONFIG_VFP is not set + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +# CONFIG_PM is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_NET is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_CONSOLE is not set +CONFIG_SERIAL_8250_NR_UARTS=3 +CONFIG_SERIAL_8250_RUNTIME_UARTS=3 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_UARTS=4 +# CONFIG_SERIAL_SAMSUNG_DEBUG is not set +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_S5P6440=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +CONFIG_ROMFS_FS=y +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_MTD is not set +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +CONFIG_ROMFS_ON_BLOCK=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_PI_LIST=y +# CONFIG_RT_MUTEX_TESTER is not set +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_SPINLOCK_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +# CONFIG_PAGE_POISONING is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_LL=y +# CONFIG_EARLY_PRINTK is not set +# CONFIG_DEBUG_ICEDCC is not set +# CONFIG_OC_ETM is not set +CONFIG_DEBUG_S3C_UART=1 + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_DMA=y diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index c77d2fa1f6e5..8113bb5fb66e 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -42,7 +42,8 @@ #endif #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ - defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) + defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \ + defined(CONFIG_CPU_ARM1026) # define MULTI_CACHE 1 #endif diff --git a/arch/arm/include/asm/entry-macro-vic2.S b/arch/arm/include/asm/entry-macro-vic2.S new file mode 100644 index 000000000000..3ceb85e43850 --- /dev/null +++ b/arch/arm/include/asm/entry-macro-vic2.S @@ -0,0 +1,57 @@ +/* arch/arm/include/asm/entry-macro-vic2.S + * + * Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks <[email protected]> + * + * Low-level IRQ helper macros for a device with two VICs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +/* This should be included from <mach/entry-macro.S> with the necessary + * defines for virtual addresses and IRQ bases for the two vics. + * + * The code needs the following defined: + * IRQ_VIC0_BASE IRQ number of VIC0's first IRQ + * IRQ_VIC1_BASE IRQ number of VIC1's first IRQ + * VA_VIC0 Virtual address of VIC0 + * VA_VIC1 Virtual address of VIC1 + * + * Note, code assumes VIC0's virtual address is an ARM immediate constant + * away from VIC1. +*/ + +#include <asm/hardware/vic.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =VA_VIC0 + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + @ check the vic0 + mov \irqnr, #IRQ_VIC0_BASE + 31 + ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] + teq \irqstat, #0 + + @ otherwise try vic1 + addeq \tmp, \base, #(VA_VIC1 - VA_VIC0) + addeq \irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE) + ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] + teqeq \irqstat, #0 + + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm diff --git a/arch/arm/include/asm/hardware/it8152.h b/arch/arm/include/asm/hardware/it8152.h index 74b5fff7f575..6700c7fc7ebd 100644 --- a/arch/arm/include/asm/hardware/it8152.h +++ b/arch/arm/include/asm/hardware/it8152.h @@ -75,6 +75,18 @@ extern unsigned long it8152_base_address; IT8152_PD_IRQ(1) USB (USBR) IT8152_PD_IRQ(0) Audio controller (ACR) */ +#define IT8152_IRQ(x) (IRQ_BOARD_END + (x)) + +/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ +#define IT8152_LD_IRQ_COUNT 9 +#define IT8152_LP_IRQ_COUNT 16 +#define IT8152_PD_IRQ_COUNT 15 + +/* Priorities: */ +#define IT8152_PD_IRQ(i) IT8152_IRQ(i) +#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) +#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) + /* frequently used interrupts */ #define IT8152_PCISERR IT8152_PD_IRQ(14) #define IT8152_H2PTADR IT8152_PD_IRQ(13) diff --git a/arch/arm/include/asm/hardware/locomo.h b/arch/arm/include/asm/hardware/locomo.h index 954b1be991b4..74e51d6bd93f 100644 --- a/arch/arm/include/asm/hardware/locomo.h +++ b/arch/arm/include/asm/hardware/locomo.h @@ -214,4 +214,8 @@ void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int /* Frontlight control */ void locomo_frontlight_set(struct locomo_dev *dev, int duty, int vr, int bpwf); +struct locomo_platform_data { + int irq_base; /* IRQ base for cascaded on-chip IRQs */ +}; + #endif diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h index 5da2595759e5..92ed254c175b 100644 --- a/arch/arm/include/asm/hardware/sa1111.h +++ b/arch/arm/include/asm/hardware/sa1111.h @@ -578,4 +578,8 @@ void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v); void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v); +struct sa1111_platform_data { + int irq_base; /* base for cascaded on-chip IRQs */ +}; + #endif /* _ASM_ARCH_SA1111 */ diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index c6c57b640b6b..621acad8ea43 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -102,6 +102,7 @@ struct cpu_cache_fns cpu_cache; #endif #ifdef CONFIG_OUTER_CACHE struct outer_cache_fns outer_cache; +EXPORT_SYMBOL(outer_cache); #endif struct stack { diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c index 309f3511aa20..2500f41d8d2d 100644 --- a/arch/arm/mach-at91/at91rm9200_time.c +++ b/arch/arm/mach-at91/at91rm9200_time.c @@ -58,6 +58,12 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) { u32 sr = at91_sys_read(AT91_ST_SR) & irqmask; + /* + * irqs should be disabled here, but as the irq is shared they are only + * guaranteed to be off if the timer irq is registered first. + */ + WARN_ON_ONCE(!irqs_disabled()); + /* simulate "oneshot" timer with alarm */ if (sr & AT91_ST_ALMS) { clkevt.event_handler(&clkevt); @@ -132,24 +138,11 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) static int clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) { - unsigned long flags; u32 alm; int status = 0; BUG_ON(delta < 2); - /* Use "raw" primitives so we behave correctly on RT kernels. */ - raw_local_irq_save(flags); - - /* - * According to Thomas Gleixner irqs are already disabled here. Simply - * removing raw_local_irq_save above (and the matching - * raw_local_irq_restore) was not accepted. See - * http://thread.gmane.org/gmane.linux.ports.arm.kernel/41174 - * So for now (2008-11-20) just warn once if irqs were not disabled ... - */ - WARN_ON_ONCE(!raw_irqs_disabled_flags(flags)); - /* The alarm IRQ uses absolute time (now+delta), not the relative * time (delta) in our calling convention. Like all clockevents * using such "match" hardware, we have a race to defend against. @@ -169,7 +162,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) alm += delta; at91_sys_write(AT91_ST_RTAR, alm); - raw_local_irq_restore(flags); return status; } diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index 4bd56aee4370..608a63240b64 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -62,16 +62,12 @@ static struct clocksource pit_clk = { static void pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) { - unsigned long flags; - switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - /* update clocksource counter, then enable the IRQ */ - raw_local_irq_save(flags); + /* update clocksource counter */ pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR)); at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN); - raw_local_irq_restore(flags); break; case CLOCK_EVT_MODE_ONESHOT: BUG(); @@ -100,6 +96,11 @@ static struct clock_event_device pit_clkevt = { */ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) { + /* + * irqs should be disabled here, but as the irq is shared they are only + * guaranteed to be off if the timer irq is registered first. + */ + WARN_ON_ONCE(!irqs_disabled()); /* The PIT interrupt may be disabled, and is shared */ if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC) diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index 806972a68c87..5da2cf402c81 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -605,7 +605,7 @@ static struct platform_device dove_xor00_channel = { .dev = { .dma_mask = &dove_xor0_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&dove_xor00_data, + .platform_data = &dove_xor00_data, }, }; @@ -631,7 +631,7 @@ static struct platform_device dove_xor01_channel = { .dev = { .dma_mask = &dove_xor0_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&dove_xor01_data, + .platform_data = &dove_xor01_data, }, }; @@ -704,7 +704,7 @@ static struct platform_device dove_xor10_channel = { .dev = { .dma_mask = &dove_xor1_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&dove_xor10_data, + .platform_data = &dove_xor10_data, }, }; @@ -730,7 +730,7 @@ static struct platform_device dove_xor11_channel = { .dev = { .dma_mask = &dove_xor1_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&dove_xor11_data, + .platform_data = &dove_xor11_data, }, }; diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c index e7263854bc7b..fe3bd5ac8b10 100644 --- a/arch/arm/mach-gemini/gpio.c +++ b/arch/arm/mach-gemini/gpio.c @@ -86,7 +86,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type) unsigned int reg_both, reg_level, reg_type; reg_type = __raw_readl(base + GPIO_INT_TYPE); - reg_level = __raw_readl(base + GPIO_INT_BOTH_EDGE); + reg_level = __raw_readl(base + GPIO_INT_LEVEL); reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE); switch (type) { @@ -117,7 +117,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type) } __raw_writel(reg_type, base + GPIO_INT_TYPE); - __raw_writel(reg_level, base + GPIO_INT_BOTH_EDGE); + __raw_writel(reg_level, base + GPIO_INT_LEVEL); __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); gpio_ack_irq(irq); diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index f6c6196a51fa..17879a876be6 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -32,6 +32,12 @@ config MACH_SHEEVAPLUG Say 'Y' here if you want your kernel to support the Marvell SheevaPlug Reference Board. +config MACH_ESATA_SHEEVAPLUG + bool "Marvell eSATA SheevaPlug Reference Board" + help + Say 'Y' here if you want your kernel to support the + Marvell eSATA SheevaPlug Reference Board. + config MACH_TS219 bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS" help @@ -46,18 +52,35 @@ config MACH_TS41X QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS devices. +config MACH_OPENRD + bool + config MACH_OPENRD_BASE bool "Marvell OpenRD Base Board" + select MACH_OPENRD help Say 'Y' here if you want your kernel to support the Marvell OpenRD Base Board. +config MACH_OPENRD_CLIENT + bool "Marvell OpenRD Client Board" + select MACH_OPENRD + help + Say 'Y' here if you want your kernel to support the + Marvell OpenRD Client Board. + config MACH_NETSPACE_V2 bool "LaCie Network Space v2 NAS Board" help Say 'Y' here if you want your kernel to support the LaCie Network Space v2 NAS. +config MACH_INETSPACE_V2 + bool "LaCie Internet Space v2 NAS Board" + help + Say 'Y' here if you want your kernel to support the + LaCie Internet Space v2 NAS. + endmenu endif diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index d4d7f53b0fb9..a5530e36ba3e 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile @@ -5,9 +5,11 @@ obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o +obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o -obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o +obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o +obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index 242dd0775343..f759ca243925 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c @@ -656,7 +656,7 @@ static struct platform_device kirkwood_xor00_channel = { .dev = { .dma_mask = &kirkwood_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&kirkwood_xor00_data, + .platform_data = &kirkwood_xor00_data, }, }; @@ -682,7 +682,7 @@ static struct platform_device kirkwood_xor01_channel = { .dev = { .dma_mask = &kirkwood_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&kirkwood_xor01_data, + .platform_data = &kirkwood_xor01_data, }, }; @@ -755,7 +755,7 @@ static struct platform_device kirkwood_xor10_channel = { .dev = { .dma_mask = &kirkwood_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&kirkwood_xor10_data, + .platform_data = &kirkwood_xor10_data, }, }; @@ -781,7 +781,7 @@ static struct platform_device kirkwood_xor11_channel = { .dev = { .dma_mask = &kirkwood_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&kirkwood_xor11_data, + .platform_data = &kirkwood_xor11_data, }, }; diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c index 9a064065bebe..3ae158d72681 100644 --- a/arch/arm/mach-kirkwood/netspace_v2-setup.c +++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c @@ -182,8 +182,14 @@ static struct platform_device netspace_v2_gpio_buttons = { static struct gpio_led netspace_v2_gpio_led_pins[] = { { - .name = "ns_v2:red:fail", - .gpio = NETSPACE_V2_GPIO_RED_LED, + .name = "ns_v2:blue:sata", + .default_trigger = "default-on", + .gpio = NETSPACE_V2_GPIO_BLUE_LED_CMD, + .active_low = 1, + }, + { + .name = "ns_v2:red:fail", + .gpio = NETSPACE_V2_GPIO_RED_LED, }, }; @@ -202,30 +208,19 @@ static struct platform_device netspace_v2_gpio_leds = { static void __init netspace_v2_gpio_leds_init(void) { - platform_device_register(&netspace_v2_gpio_leds); + int err; - /* - * Configure the front blue LED to blink in relation with the SATA - * activity. - */ - if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, - "SATA blue LED slow") != 0) - return; - if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0) != 0) - goto err_free_1; - if (gpio_request(NETSPACE_V2_GPIO_BLUE_LED_CMD, - "SATA blue LED command") != 0) - goto err_free_1; - if (gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_CMD, 0) != 0) - goto err_free_2; - - return; - -err_free_2: - gpio_free(NETSPACE_V2_GPIO_BLUE_LED_CMD); -err_free_1: - gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW); - pr_err("netspace_v2: failed to configure SATA blue LED\n"); + /* Configure register slow_led to allow SATA activity LED blinking */ + err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow"); + if (err == 0) { + err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0); + if (err) + gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW); + } + if (err) + pr_err("netspace_v2: failed to configure blue LED slow GPIO\n"); + + platform_device_register(&netspace_v2_gpio_leds); } /***************************************************************************** @@ -314,6 +309,7 @@ static void __init netspace_v2_init(void) pr_err("netspace_v2: failed to configure power-off GPIO\n"); } +#ifdef CONFIG_MACH_NETSPACE_V2 MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") .phys_io = KIRKWOOD_REGS_PHYS_BASE, .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, @@ -323,3 +319,16 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") .init_irq = kirkwood_init_irq, .timer = &netspace_v2_timer, MACHINE_END +#endif + +#ifdef CONFIG_MACH_INETSPACE_V2 +MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = netspace_v2_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &netspace_v2_timer, +MACHINE_END +#endif diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c new file mode 100644 index 000000000000..ad3f1ec33796 --- /dev/null +++ b/arch/arm/mach-kirkwood/openrd-setup.c @@ -0,0 +1,118 @@ +/* + * arch/arm/mach-kirkwood/openrd-setup.c + * + * Marvell OpenRD (Base|Client) Board Setup + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/kirkwood.h> +#include <plat/mvsdio.h> +#include "common.h" +#include "mpp.h" + +static struct mtd_partition openrd_nand_parts[] = { + { + .name = "u-boot", + .offset = 0, + .size = SZ_1M, + .mask_flags = MTD_WRITEABLE + }, { + .name = "uImage", + .offset = MTDPART_OFS_NXTBLK, + .size = SZ_4M + }, { + .name = "root", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL + }, +}; + +static struct mv643xx_eth_platform_data openrd_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + +static struct mv643xx_eth_platform_data openrd_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(24), +}; + +static struct mv_sata_platform_data openrd_sata_data = { + .n_ports = 2, +}; + +static struct mvsdio_platform_data openrd_mvsdio_data = { + .gpio_card_detect = 29, /* MPP29 used as SD card detect */ +}; + +static unsigned int openrd_mpp_config[] __initdata = { + MPP29_GPIO, + 0 +}; + +static void __init openrd_init(void) +{ + /* + * Basic setup. Needs to be called early. + */ + kirkwood_init(); + kirkwood_mpp_conf(openrd_mpp_config); + + kirkwood_uart0_init(); + kirkwood_nand_init(ARRAY_AND_SIZE(openrd_nand_parts), 25); + + kirkwood_ehci_init(); + + kirkwood_ge00_init(&openrd_ge00_data); + if (machine_is_openrd_client()) + kirkwood_ge01_init(&openrd_ge01_data); + kirkwood_sata_init(&openrd_sata_data); + kirkwood_sdio_init(&openrd_mvsdio_data); + + kirkwood_i2c_init(); +} + +static int __init openrd_pci_init(void) +{ + if (machine_is_openrd_base() || machine_is_openrd_client()) + kirkwood_pcie_init(); + + return 0; +} +subsys_initcall(openrd_pci_init); + +#ifdef CONFIG_MACH_OPENRD_BASE +MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board") + /* Maintainer: Dhaval Vasa <[email protected]> */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = openrd_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_OPENRD_CLIENT +MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board") + /* Maintainer: Dhaval Vasa <[email protected]> */ + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = openrd_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END +#endif diff --git a/arch/arm/mach-kirkwood/openrd_base-setup.c b/arch/arm/mach-kirkwood/openrd_base-setup.c deleted file mode 100644 index 77617c722299..000000000000 --- a/arch/arm/mach-kirkwood/openrd_base-setup.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * arch/arm/mach-kirkwood/openrd_base-setup.c - * - * Marvell OpenRD Base Board Setup - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/mtd/partitions.h> -#include <linux/ata_platform.h> -#include <linux/mv643xx_eth.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/kirkwood.h> -#include <plat/mvsdio.h> -#include "common.h" -#include "mpp.h" - -static struct mtd_partition openrd_base_nand_parts[] = { - { - .name = "u-boot", - .offset = 0, - .size = SZ_1M - }, { - .name = "uImage", - .offset = MTDPART_OFS_NXTBLK, - .size = SZ_4M - }, { - .name = "root", - .offset = MTDPART_OFS_NXTBLK, - .size = MTDPART_SIZ_FULL - }, -}; - -static struct mv643xx_eth_platform_data openrd_base_ge00_data = { - .phy_addr = MV643XX_ETH_PHY_ADDR(8), -}; - -static struct mv_sata_platform_data openrd_base_sata_data = { - .n_ports = 2, -}; - -static struct mvsdio_platform_data openrd_base_mvsdio_data = { - .gpio_card_detect = 29, /* MPP29 used as SD card detect */ -}; - -static unsigned int openrd_base_mpp_config[] __initdata = { - MPP29_GPIO, - 0 -}; - -static void __init openrd_base_init(void) -{ - /* - * Basic setup. Needs to be called early. - */ - kirkwood_init(); - kirkwood_mpp_conf(openrd_base_mpp_config); - - kirkwood_uart0_init(); - kirkwood_nand_init(ARRAY_AND_SIZE(openrd_base_nand_parts), 25); - - kirkwood_ehci_init(); - - kirkwood_ge00_init(&openrd_base_ge00_data); - kirkwood_sata_init(&openrd_base_sata_data); - kirkwood_sdio_init(&openrd_base_mvsdio_data); - - kirkwood_i2c_init(); -} - -static int __init openrd_base_pci_init(void) -{ - if (machine_is_openrd_base()) - kirkwood_pcie_init(); - - return 0; - } -subsys_initcall(openrd_base_pci_init); - - -MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board") - /* Maintainer: Dhaval Vasa <[email protected]> */ - .phys_io = KIRKWOOD_REGS_PHYS_BASE, - .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, - .boot_params = 0x00000100, - .init_machine = openrd_base_init, - .map_io = kirkwood_map_io, - .init_irq = kirkwood_init_irq, - .timer = &kirkwood_timer, -MACHINE_END diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c index c7319eeac8bb..a00879d34d54 100644 --- a/arch/arm/mach-kirkwood/sheevaplug-setup.c +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c @@ -11,6 +11,7 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> +#include <linux/ata_platform.h> #include <linux/mtd/partitions.h> #include <linux/mv643xx_eth.h> #include <linux/gpio.h> @@ -42,10 +43,19 @@ static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { .phy_addr = MV643XX_ETH_PHY_ADDR(0), }; +static struct mv_sata_platform_data sheeva_esata_sata_data = { + .n_ports = 2, +}; + static struct mvsdio_platform_data sheevaplug_mvsdio_data = { /* unfortunately the CD signal has not been connected */ }; +static struct mvsdio_platform_data sheeva_esata_mvsdio_data = { + .gpio_write_protect = 44, /* MPP44 used as SD write protect */ + .gpio_card_detect = 47, /* MPP47 used as SD card detect */ +}; + static struct gpio_led sheevaplug_led_pins[] = { { .name = "plug:green:health", @@ -74,13 +84,26 @@ static unsigned int sheevaplug_mpp_config[] __initdata = { 0 }; +static unsigned int sheeva_esata_mpp_config[] __initdata = { + MPP29_GPIO, /* USB Power Enable */ + MPP44_GPIO, /* SD Write Protect */ + MPP47_GPIO, /* SD Card Detect */ + MPP49_GPIO, /* LED Green */ + 0 +}; + static void __init sheevaplug_init(void) { /* * Basic setup. Needs to be called early. */ kirkwood_init(); - kirkwood_mpp_conf(sheevaplug_mpp_config); + + /* setup gpio pin select */ + if (machine_is_sheeva_esata()) + kirkwood_mpp_conf(sheeva_esata_mpp_config); + else + kirkwood_mpp_conf(sheevaplug_mpp_config); kirkwood_uart0_init(); kirkwood_nand_init(ARRAY_AND_SIZE(sheevaplug_nand_parts), 25); @@ -91,11 +114,21 @@ static void __init sheevaplug_init(void) kirkwood_ehci_init(); kirkwood_ge00_init(&sheevaplug_ge00_data); - kirkwood_sdio_init(&sheevaplug_mvsdio_data); + + /* honor lower power consumption for plugs with out eSATA */ + if (machine_is_sheeva_esata()) + kirkwood_sata_init(&sheeva_esata_sata_data); + + /* enable sd wp and sd cd on plugs with esata */ + if (machine_is_sheeva_esata()) + kirkwood_sdio_init(&sheeva_esata_mvsdio_data); + else + kirkwood_sdio_init(&sheevaplug_mvsdio_data); platform_device_register(&sheevaplug_leds); } +#ifdef CONFIG_MACH_SHEEVAPLUG MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") /* Maintainer: shadi Ammouri <[email protected]> */ .phys_io = KIRKWOOD_REGS_PHYS_BASE, @@ -106,3 +139,16 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") .init_irq = kirkwood_init_irq, .timer = &kirkwood_timer, MACHINE_END +#endif + +#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG +MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board") + .phys_io = KIRKWOOD_REGS_PHYS_BASE, + .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = sheevaplug_init, + .map_io = kirkwood_map_io, + .init_irq = kirkwood_init_irq, + .timer = &kirkwood_timer, +MACHINE_END +#endif diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index c6a564fc4a7c..6ab843eaa35b 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -1,6 +1,6 @@ if ARCH_MMP -menu "Marvell PXA168/910 Implmentations" +menu "Marvell PXA168/910/MMP2 Implmentations" config MACH_ASPENITE bool "Marvell's PXA168 Aspenite Development Board" @@ -16,6 +16,13 @@ config MACH_ZYLONITE2 Say 'Y' here if you want to support the Marvell PXA168-based Zylonite2 Development Board. +config MACH_AVENGERS_LITE + bool "Marvell's PXA168 Avengers Lite Development Board" + select CPU_PXA168 + help + Say 'Y' here if you want to support the Marvell PXA168-based + Avengers Lite Development Board. + config MACH_TAVOREVB bool "Marvell's PXA910 TavorEVB Development Board" select CPU_PXA910 @@ -30,6 +37,26 @@ config MACH_TTC_DKB Say 'Y' here if you want to support the Marvell PXA910-based TTC_DKB Development Board. +config MACH_FLINT + bool "Marvell's Flint Development Platform" + select CPU_MMP2 + help + Say 'Y' here if you want to support the Marvell MMP2-based + Flint Development Platform. + MMP2-based board can't be co-existed with PXA168-based & + PXA910-based development board. Since MMP2 is compatible to + ARMv6 architecture. + +config MACH_MARVELL_JASPER + bool "Marvell's Jasper Development Platform" + select CPU_MMP2 + help + Say 'Y' here if you want to support the Marvell MMP2-base + Jasper Development Platform. + MMP2-based board can't be co-existed with PXA168-based & + PXA910-based development board. Since MMP2 is compatible to + ARMv6 architecture. + endmenu config CPU_PXA168 @@ -44,4 +71,10 @@ config CPU_PXA910 help Select code specific to PXA910 +config CPU_MMP2 + bool + select CPU_V6 + select CPU_32v6K + help + Select code specific to MMP2. MMP2 is ARMv6 compatible. endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 6883e6584883..8b66d06739c4 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -2,14 +2,18 @@ # Makefile for Marvell's PXA168 processors line # -obj-y += common.o clock.o devices.o irq.o time.o +obj-y += common.o clock.o devices.o time.o # SoC support -obj-$(CONFIG_CPU_PXA168) += pxa168.o -obj-$(CONFIG_CPU_PXA910) += pxa910.o +obj-$(CONFIG_CPU_PXA168) += pxa168.o irq-pxa168.o +obj-$(CONFIG_CPU_PXA910) += pxa910.o irq-pxa168.o +obj-$(CONFIG_CPU_MMP2) += mmp2.o irq-mmp2.o # board support obj-$(CONFIG_MACH_ASPENITE) += aspenite.o obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o +obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o +obj-$(CONFIG_MACH_FLINT) += flint.o +obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c new file mode 100644 index 000000000000..8c3fa5d14f4b --- /dev/null +++ b/arch/arm/mach-mmp/avengers_lite.c @@ -0,0 +1,51 @@ +/* + * linux/arch/arm/mach-mmp/avengers_lite.c + * + * Support for the Marvell PXA168-based Avengers lite Development Platform. + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/addr-map.h> +#include <mach/mfp-pxa168.h> +#include <mach/pxa168.h> +#include <mach/irqs.h> + + +#include "common.h" +#include <linux/delay.h> + +/* Avengers lite MFP configurations */ +static unsigned long avengers_lite_pin_config_V16F[] __initdata = { + /* DEBUG_UART */ + GPIO88_UART2_TXD, + GPIO89_UART2_RXD, +}; + +static void __init avengers_lite_init(void) +{ + mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F)); + + /* on-chip devices */ + pxa168_add_uart(2); +} + +MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform") + .phys_io = APB_PHYS_BASE, + .boot_params = 0x00000100, + .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa168_init_irq, + .timer = &pxa168_timer, + .init_machine = avengers_lite_init, +MACHINE_END diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index c33fbbc49417..b4a0ba05a0f4 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -3,11 +3,15 @@ struct sys_timer; extern void timer_init(int irq); +extern void mmp2_clear_pmic_int(void); extern struct sys_timer pxa168_timer; extern struct sys_timer pxa910_timer; +extern struct sys_timer mmp2_timer; extern void __init pxa168_init_irq(void); extern void __init pxa910_init_irq(void); +extern void __init mmp2_init_icu(void); +extern void __init mmp2_init_irq(void); extern void __init icu_init_irq(void); extern void __init pxa_map_io(void); diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c new file mode 100644 index 000000000000..4ec7709a3462 --- /dev/null +++ b/arch/arm/mach-mmp/flint.c @@ -0,0 +1,123 @@ +/* + * linux/arch/arm/mach-mmp/flint.c + * + * Support for the Marvell Flint Development Platform. + * + * Copyright (C) 2009 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/smc91x.h> +#include <linux/io.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/addr-map.h> +#include <mach/mfp-mmp2.h> +#include <mach/mmp2.h> + +#include "common.h" + +static unsigned long flint_pin_config[] __initdata = { + /* UART1 */ + GPIO45_UART1_RXD, + GPIO46_UART1_TXD, + + /* UART2 */ + GPIO47_UART2_RXD, + GPIO48_UART2_TXD, + + /* SMC */ + GPIO151_SMC_SCLK, + GPIO145_SMC_nCS0, + GPIO146_SMC_nCS1, + GPIO152_SMC_BE0, + GPIO153_SMC_BE1, + GPIO154_SMC_IRQ, + GPIO113_SMC_RDY, + + /*Ethernet*/ + GPIO155_GPIO155, + + /* DFI */ + GPIO168_DFI_D0, + GPIO167_DFI_D1, + GPIO166_DFI_D2, + GPIO165_DFI_D3, + GPIO107_DFI_D4, + GPIO106_DFI_D5, + GPIO105_DFI_D6, + GPIO104_DFI_D7, + GPIO111_DFI_D8, + GPIO164_DFI_D9, + GPIO163_DFI_D10, + GPIO162_DFI_D11, + GPIO161_DFI_D12, + GPIO110_DFI_D13, + GPIO109_DFI_D14, + GPIO108_DFI_D15, + GPIO143_ND_nCS0, + GPIO144_ND_nCS1, + GPIO147_ND_nWE, + GPIO148_ND_nRE, + GPIO150_ND_ALE, + GPIO149_ND_CLE, + GPIO112_ND_RDY0, + GPIO160_ND_RDY1, +}; + +static struct smc91x_platdata flint_smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, +}; + +static struct resource smc91x_resources[] = { + [0] = { + .start = SMC_CS1_PHYS_BASE + 0x300, + .end = SMC_CS1_PHYS_BASE + 0xfffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = gpio_to_irq(155), + .end = gpio_to_irq(155), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, + } +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .dev = { + .platform_data = &flint_smc91x_info, + }, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static void __init flint_init(void) +{ + mfp_config(ARRAY_AND_SIZE(flint_pin_config)); + + /* on-chip devices */ + mmp2_add_uart(1); + mmp2_add_uart(2); + + /* off-chip devices */ + platform_device_register(&smc91x_device); +} + +MACHINE_START(FLINT, "Flint Development Platform") + .phys_io = APB_PHYS_BASE, + .boot_params = 0x00000100, + .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = mmp2_init_irq, + .timer = &mmp2_timer, + .init_machine = flint_init, +MACHINE_END diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h index 25e797b09083..83b18721d933 100644 --- a/arch/arm/mach-mmp/include/mach/cputype.h +++ b/arch/arm/mach-mmp/include/mach/cputype.h @@ -8,6 +8,7 @@ * * PXA168 A0 0x41159263 0x56158400 0x00A0A333 * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 + * MMP2 Z0 0x560f5811 */ #ifdef CONFIG_CPU_PXA168 @@ -24,7 +25,15 @@ # define __cpu_is_pxa910(id) (0) #endif +#ifdef CONFIG_CPU_MMP2 +# define __cpu_is_mmp2(id) \ + ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; }) +#else +# define __cpu_is_mmp2(id) (0) +#endif + #define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) #define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); }) +#define cpu_is_mmp2() ({ __cpu_is_mmp2(read_cpuid_id()); }) #endif /* __ASM_MACH_CPUTYPE_H */ diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h index 24585397217e..1fa0a492454a 100644 --- a/arch/arm/mach-mmp/include/mach/devices.h +++ b/arch/arm/mach-mmp/include/mach/devices.h @@ -34,4 +34,16 @@ struct pxa_device_desc pxa910_device_##_name __initdata = { \ .size = _size, \ .dma = { _dma }, \ }; + +#define MMP2_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ +struct pxa_device_desc mmp2_device_##_name __initdata = { \ + .dev_name = "mmp2-" #_name, \ + .drv_name = _drv, \ + .id = _id, \ + .irq = IRQ_MMP2_##_irq, \ + .start = _start, \ + .size = _size, \ + .dma = { _dma }, \ +} + extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S index 6d3cd35478b5..c42d9d4e892d 100644 --- a/arch/arm/mach-mmp/include/mach/entry-macro.S +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S @@ -15,7 +15,12 @@ .endm .macro get_irqnr_preamble, base, tmp - ldr \base, =ICU_AP_IRQ_SEL_INT_NUM + mrc p15, 0, \tmp, c0, c0, 0 @ CPUID + and \tmp, \tmp, #0xff00 + cmp \tmp, #0x5800 + ldr \base, =ICU_VIRT_BASE + addne \base, \base, #0x10c @ PJ1 AP INT SEL register + addeq \base, \base, #0x104 @ PJ4 IRQ SEL register .endm .macro get_irqnr_and_base, irqnr, irqstat, base, tmp diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index d68871b0f28c..02701196ea03 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h @@ -113,10 +113,119 @@ #define IRQ_PXA910_AP_PMU 60 #define IRQ_PXA910_SM_INT 63 /* from PinMux */ -#define IRQ_GPIO_START 64 -#define IRQ_GPIO_NUM 128 +/* + * Interrupt numbers for MMP2 + */ +#define IRQ_MMP2_NONE (-1) +#define IRQ_MMP2_SSP1 0 +#define IRQ_MMP2_SSP2 1 +#define IRQ_MMP2_SSPA1 2 +#define IRQ_MMP2_SSPA2 3 +#define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */ +#define IRQ_MMP2_RTC_MUX 5 +#define IRQ_MMP2_TWSI1 7 +#define IRQ_MMP2_GPU 8 +#define IRQ_MMP2_KEYPAD 9 +#define IRQ_MMP2_ROTARY 10 +#define IRQ_MMP2_TRACKBALL 11 +#define IRQ_MMP2_ONEWIRE 12 +#define IRQ_MMP2_TIMER1 13 +#define IRQ_MMP2_TIMER2 14 +#define IRQ_MMP2_TIMER3 15 +#define IRQ_MMP2_RIPC 16 +#define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */ +#define IRQ_MMP2_HDMI 19 +#define IRQ_MMP2_SSP3 20 +#define IRQ_MMP2_SSP4 21 +#define IRQ_MMP2_USB_HS1 22 +#define IRQ_MMP2_USB_HS2 23 +#define IRQ_MMP2_UART3 24 +#define IRQ_MMP2_UART1 27 +#define IRQ_MMP2_UART2 28 +#define IRQ_MMP2_MIPI_DSI 29 +#define IRQ_MMP2_CI2 30 +#define IRQ_MMP2_PMU_TIMER1 31 +#define IRQ_MMP2_PMU_TIMER2 32 +#define IRQ_MMP2_PMU_TIMER3 33 +#define IRQ_MMP2_USB_FS 34 +#define IRQ_MMP2_MISC_MUX 35 +#define IRQ_MMP2_WDT1 36 +#define IRQ_MMP2_NAND_DMA 37 +#define IRQ_MMP2_USIM 38 +#define IRQ_MMP2_MMC 39 +#define IRQ_MMP2_WTM 40 +#define IRQ_MMP2_LCD 41 +#define IRQ_MMP2_CI 42 +#define IRQ_MMP2_IRE 43 +#define IRQ_MMP2_USB_OTG 44 +#define IRQ_MMP2_NAND 45 +#define IRQ_MMP2_UART4 46 +#define IRQ_MMP2_DMA_FIQ 47 +#define IRQ_MMP2_DMA_RIQ 48 +#define IRQ_MMP2_GPIO 49 +#define IRQ_MMP2_SSP_MUX 51 +#define IRQ_MMP2_MMC2 52 +#define IRQ_MMP2_MMC3 53 +#define IRQ_MMP2_MMC4 54 +#define IRQ_MMP2_MIPI_HSI 55 +#define IRQ_MMP2_MSP 58 +#define IRQ_MMP2_MIPI_SLIM_DMA 59 +#define IRQ_MMP2_PJ4_FREQ_CHG 60 +#define IRQ_MMP2_MIPI_SLIM 62 +#define IRQ_MMP2_SM 63 + +#define IRQ_MMP2_MUX_BASE 64 + +/* secondary interrupt of INT #4 */ +#define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE) +#define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0) +#define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1) + +/* secondary interrupt of INT #5 */ +#define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2) +#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0) +#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1) + +/* secondary interrupt of INT #17 */ +#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_RTC_BASE + 2) +#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0) +#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1) +#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2) +#define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3) +#define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4) + +/* secondary interrupt of INT #35 */ +#define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5) +#define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0) +#define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1) +#define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2) +#define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3) +#define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4) +#define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5) +#define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6) +#define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7) +#define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9) +#define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10) +#define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11) +#define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12) +#define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13) +#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14) + +/* secondary interrupt of INT #51 */ +#define IRQ_MMP2_SSP_BASE (IRQ_MMP2_MISC_BASE + 15) +#define IRQ_MMP2_SSP1_SRDY (IRQ_MMP2_SSP_BASE + 0) +#define IRQ_MMP2_SSP3_SRDY (IRQ_MMP2_SSP_BASE + 1) + +#define IRQ_MMP2_MUX_END (IRQ_MMP2_SSP_BASE + 2) + +#define IRQ_GPIO_START 128 +#define IRQ_GPIO_NUM 192 #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) -#define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM) +/* Board IRQ - 64 by default, increase if not enough */ +#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM) +#define IRQ_BOARD_END (IRQ_BOARD_START + 64) + +#define NR_IRQS (IRQ_BOARD_END) #endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h new file mode 100644 index 000000000000..9f9f8143e272 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h @@ -0,0 +1,240 @@ +#ifndef __ASM_MACH_MFP_MMP2_H +#define __ASM_MACH_MFP_MMP2_H + +#include <mach/mfp.h> + +#define MFP_DRIVE_VERY_SLOW (0x0 << 13) +#define MFP_DRIVE_SLOW (0x2 << 13) +#define MFP_DRIVE_MEDIUM (0x4 << 13) +#define MFP_DRIVE_FAST (0x8 << 13) + +/* GPIO */ + +/* DFI */ +#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0) +#define GPIO109_DFI_D14 MFP_CFG(GPIO109, AF0) +#define GPIO110_DFI_D13 MFP_CFG(GPIO110, AF0) +#define GPIO161_DFI_D12 MFP_CFG(GPIO161, AF0) +#define GPIO162_DFI_D11 MFP_CFG(GPIO162, AF0) +#define GPIO163_DFI_D10 MFP_CFG(GPIO163, AF0) +#define GPIO164_DFI_D9 MFP_CFG(GPIO164, AF0) +#define GPIO111_DFI_D8 MFP_CFG(GPIO111, AF0) +#define GPIO104_DFI_D7 MFP_CFG(GPIO104, AF0) +#define GPIO105_DFI_D6 MFP_CFG(GPIO105, AF0) +#define GPIO106_DFI_D5 MFP_CFG(GPIO106, AF0) +#define GPIO107_DFI_D4 MFP_CFG(GPIO107, AF0) +#define GPIO165_DFI_D3 MFP_CFG(GPIO165, AF0) +#define GPIO166_DFI_D2 MFP_CFG(GPIO166, AF0) +#define GPIO167_DFI_D1 MFP_CFG(GPIO167, AF0) +#define GPIO168_DFI_D0 MFP_CFG(GPIO168, AF0) +#define GPIO143_ND_nCS0 MFP_CFG(GPIO143, AF0) +#define GPIO144_ND_nCS1 MFP_CFG(GPIO144, AF0) +#define GPIO147_ND_nWE MFP_CFG(GPIO147, AF0) +#define GPIO148_ND_nRE MFP_CFG(GPIO148, AF0) +#define GPIO150_ND_ALE MFP_CFG(GPIO150, AF0) +#define GPIO149_ND_CLE MFP_CFG(GPIO149, AF0) +#define GPIO112_ND_RDY0 MFP_CFG(GPIO112, AF0) +#define GPIO160_ND_RDY1 MFP_CFG(GPIO160, AF0) + +/* Static Memory Controller */ +#define GPIO145_SMC_nCS0 MFP_CFG(GPIO145, AF0) +#define GPIO146_SMC_nCS1 MFP_CFG(GPIO146, AF0) +#define GPIO152_SMC_BE0 MFP_CFG(GPIO152, AF0) +#define GPIO153_SMC_BE1 MFP_CFG(GPIO153, AF0) +#define GPIO154_SMC_IRQ MFP_CFG(GPIO154, AF0) +#define GPIO113_SMC_RDY MFP_CFG(GPIO113, AF0) +#define GPIO151_SMC_SCLK MFP_CFG(GPIO151, AF0) + +/* Ethernet */ +#define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2) +#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1) + +/* UART1 */ +#define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1) +#define GPIO46_UART1_TXD MFP_CFG(GPIO46, AF1) +#define GPIO29_UART1_RXD MFP_CFG(GPIO29, AF1) +#define GPIO30_UART1_TXD MFP_CFG(GPIO30, AF1) +#define GPIO31_UART1_CTS MFP_CFG(GPIO31, AF1) +#define GPIO32_UART1_RTS MFP_CFG(GPIO32, AF1) + +/* UART2 */ +#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF1) +#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF1) +#define GPIO49_UART2_CTS MFP_CFG(GPIO49, AF1) +#define GPIO50_UART2_RTS MFP_CFG(GPIO50, AF1) + +/* UART3 */ +#define GPIO51_UART3_RXD MFP_CFG(GPIO51, AF1) +#define GPIO52_UART3_TXD MFP_CFG(GPIO52, AF1) +#define GPIO53_UART3_CTS MFP_CFG(GPIO53, AF1) +#define GPIO54_UART3_RTS MFP_CFG(GPIO54, AF1) + +/* MMC1 */ +#define GPIO124_MMC1_DAT7 MFP_CFG_DRV(GPIO124, AF1, FAST) +#define GPIO125_MMC1_DAT6 MFP_CFG_DRV(GPIO125, AF1, FAST) +#define GPIO129_MMC1_DAT5 MFP_CFG_DRV(GPIO129, AF1, FAST) +#define GPIO130_MMC1_DAT4 MFP_CFG_DRV(GPIO130, AF1, FAST) +#define GPIO131_MMC1_DAT3 MFP_CFG_DRV(GPIO131, AF1, FAST) +#define GPIO132_MMC1_DAT2 MFP_CFG_DRV(GPIO132, AF1, FAST) +#define GPIO133_MMC1_DAT1 MFP_CFG_DRV(GPIO133, AF1, FAST) +#define GPIO134_MMC1_DAT0 MFP_CFG_DRV(GPIO134, AF1, FAST) +#define GPIO136_MMC1_CMD MFP_CFG_DRV(GPIO136, AF1, FAST) +#define GPIO139_MMC1_CLK MFP_CFG_DRV(GPIO139, AF1, FAST) +#define GPIO140_MMC1_CD MFP_CFG_DRV(GPIO140, AF1, FAST) +#define GPIO141_MMC1_WP MFP_CFG_DRV(GPIO141, AF1, FAST) + +/*MMC2*/ +#define GPIO37_MMC2_DAT3 MFP_CFG_DRV(GPIO37, AF1, FAST) +#define GPIO38_MMC2_DAT2 MFP_CFG_DRV(GPIO38, AF1, FAST) +#define GPIO39_MMC2_DAT1 MFP_CFG_DRV(GPIO39, AF1, FAST) +#define GPIO40_MMC2_DAT0 MFP_CFG_DRV(GPIO40, AF1, FAST) +#define GPIO41_MMC2_CMD MFP_CFG_DRV(GPIO41, AF1, FAST) +#define GPIO42_MMC2_CLK MFP_CFG_DRV(GPIO42, AF1, FAST) + +/*MMC3*/ +#define GPIO165_MMC3_DAT7 MFP_CFG_DRV(GPIO165, AF2, FAST) +#define GPIO162_MMC3_DAT6 MFP_CFG_DRV(GPIO162, AF2, FAST) +#define GPIO166_MMC3_DAT5 MFP_CFG_DRV(GPIO166, AF2, FAST) +#define GPIO163_MMC3_DAT4 MFP_CFG_DRV(GPIO163, AF2, FAST) +#define GPIO167_MMC3_DAT3 MFP_CFG_DRV(GPIO167, AF2, FAST) +#define GPIO164_MMC3_DAT2 MFP_CFG_DRV(GPIO164, AF2, FAST) +#define GPIO168_MMC3_DAT1 MFP_CFG_DRV(GPIO168, AF2, FAST) +#define GPIO111_MMC3_DAT0 MFP_CFG_DRV(GPIO111, AF2, FAST) +#define GPIO112_MMC3_CMD MFP_CFG_DRV(GPIO112, AF2, FAST) +#define GPIO151_MMC3_CLK MFP_CFG_DRV(GPIO151, AF2, FAST) + +/* LCD */ +#define GPIO74_LCD_FCLK MFP_CFG_DRV(GPIO74, AF1, FAST) +#define GPIO75_LCD_LCLK MFP_CFG_DRV(GPIO75, AF1, FAST) +#define GPIO76_LCD_PCLK MFP_CFG_DRV(GPIO76, AF1, FAST) +#define GPIO77_LCD_DENA MFP_CFG_DRV(GPIO77, AF1, FAST) +#define GPIO78_LCD_DD0 MFP_CFG_DRV(GPIO78, AF1, FAST) +#define GPIO79_LCD_DD1 MFP_CFG_DRV(GPIO79, AF1, FAST) +#define GPIO80_LCD_DD2 MFP_CFG_DRV(GPIO80, AF1, FAST) +#define GPIO81_LCD_DD3 MFP_CFG_DRV(GPIO81, AF1, FAST) +#define GPIO82_LCD_DD4 MFP_CFG_DRV(GPIO82, AF1, FAST) +#define GPIO83_LCD_DD5 MFP_CFG_DRV(GPIO83, AF1, FAST) +#define GPIO84_LCD_DD6 MFP_CFG_DRV(GPIO84, AF1, FAST) +#define GPIO85_LCD_DD7 MFP_CFG_DRV(GPIO85, AF1, FAST) +#define GPIO86_LCD_DD8 MFP_CFG_DRV(GPIO86, AF1, FAST) +#define GPIO87_LCD_DD9 MFP_CFG_DRV(GPIO87, AF1, FAST) +#define GPIO88_LCD_DD10 MFP_CFG_DRV(GPIO88, AF1, FAST) +#define GPIO89_LCD_DD11 MFP_CFG_DRV(GPIO89, AF1, FAST) +#define GPIO90_LCD_DD12 MFP_CFG_DRV(GPIO90, AF1, FAST) +#define GPIO91_LCD_DD13 MFP_CFG_DRV(GPIO91, AF1, FAST) +#define GPIO92_LCD_DD14 MFP_CFG_DRV(GPIO92, AF1, FAST) +#define GPIO93_LCD_DD15 MFP_CFG_DRV(GPIO93, AF1, FAST) +#define GPIO94_LCD_DD16 MFP_CFG_DRV(GPIO94, AF1, FAST) +#define GPIO95_LCD_DD17 MFP_CFG_DRV(GPIO95, AF1, FAST) +#define GPIO96_LCD_DD18 MFP_CFG_DRV(GPIO96, AF1, FAST) +#define GPIO97_LCD_DD19 MFP_CFG_DRV(GPIO97, AF1, FAST) +#define GPIO98_LCD_DD20 MFP_CFG_DRV(GPIO98, AF1, FAST) +#define GPIO99_LCD_DD21 MFP_CFG_DRV(GPIO99, AF1, FAST) +#define GPIO100_LCD_DD22 MFP_CFG_DRV(GPIO100, AF1, FAST) +#define GPIO101_LCD_DD23 MFP_CFG_DRV(GPIO101, AF1, FAST) +#define GPIO94_SPI_DCLK MFP_CFG_DRV(GPIO94, AF3, FAST) +#define GPIO95_SPI_CS0 MFP_CFG_DRV(GPIO95, AF3, FAST) +#define GPIO96_SPI_DIN MFP_CFG_DRV(GPIO96, AF3, FAST) +#define GPIO97_SPI_DOUT MFP_CFG_DRV(GPIO97, AF3, FAST) +#define GPIO98_LCD_RST MFP_CFG_DRV(GPIO98, AF0, FAST) + +#define GPIO114_MN_CLK_OUT MFP_CFG_DRV(GPIO114, AF1, FAST) + +/*LCD TV path*/ +#define GPIO124_LCD_DD24 MFP_CFG_DRV(GPIO124, AF2, FAST) +#define GPIO125_LCD_DD25 MFP_CFG_DRV(GPIO125, AF2, FAST) +#define GPIO126_LCD_DD33 MFP_CFG_DRV(GPIO126, AF2, FAST) +#define GPIO127_LCD_DD26 MFP_CFG_DRV(GPIO127, AF2, FAST) +#define GPIO128_LCD_DD27 MFP_CFG_DRV(GPIO128, AF2, FAST) +#define GPIO129_LCD_DD28 MFP_CFG_DRV(GPIO129, AF2, FAST) +#define GPIO130_LCD_DD29 MFP_CFG_DRV(GPIO130, AF2, FAST) +#define GPIO135_LCD_DD30 MFP_CFG_DRV(GPIO135, AF2, FAST) +#define GPIO137_LCD_DD31 MFP_CFG_DRV(GPIO137, AF2, FAST) +#define GPIO138_LCD_DD32 MFP_CFG_DRV(GPIO138, AF2, FAST) +#define GPIO140_LCD_DD34 MFP_CFG_DRV(GPIO140, AF2, FAST) +#define GPIO141_LCD_DD35 MFP_CFG_DRV(GPIO141, AF2, FAST) + +/* I2C */ +#define GPIO43_TWSI2_SCL MFP_CFG_DRV(GPIO43, AF1, SLOW) +#define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW) +#define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW) +#define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW) +#define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW) +#define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW) +#define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW) +#define GPIO98_TWSI6_SDA MFP_CFG_DRV(GPIO98, AF2, SLOW) + +/* SSPA1 */ +#define GPIO24_I2S_SYSCLK MFP_CFG(GPIO24, AF1) +#define GPIO25_I2S_BITCLK MFP_CFG(GPIO25, AF1) +#define GPIO26_I2S_SYNC MFP_CFG(GPIO26, AF1) +#define GPIO27_I2S_DATA_OUT MFP_CFG(GPIO27, AF1) +#define GPIO28_I2S_SDATA_IN MFP_CFG(GPIO28, AF1) +#define GPIO114_I2S_MCLK MFP_CFG(GPIO114, AF1) + +/* SSPA2 */ +#define GPIO33_SSPA2_CLK MFP_CFG(GPIO33, AF1) +#define GPIO34_SSPA2_FRM MFP_CFG(GPIO34, AF1) +#define GPIO35_SSPA2_TXD MFP_CFG(GPIO35, AF1) +#define GPIO36_SSPA2_RXD MFP_CFG(GPIO36, AF1) + +/* Keypad */ +#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1) +#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1) +#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1) +#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1) +#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1) +#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1) +#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1) +#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1) +#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1) +#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1) +#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1) +#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1) +#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1) +#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1) +#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1) +#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1) +#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1) +#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1) +#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1) +#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1) +#define GPIO20_KP_DKIN4 MFP_CFG(GPIO20, AF1) +#define GPIO21_KP_DKIN5 MFP_CFG(GPIO21, AF1) +#define GPIO22_KP_DKIN6 MFP_CFG(GPIO22, AF1) +#define GPIO23_KP_DKIN7 MFP_CFG(GPIO23, AF1) + +/* CAMERA */ +#define GPIO59_CCIC_IN7 MFP_CFG_DRV(GPIO59, AF1, FAST) +#define GPIO60_CCIC_IN6 MFP_CFG_DRV(GPIO60, AF1, FAST) +#define GPIO61_CCIC_IN5 MFP_CFG_DRV(GPIO61, AF1, FAST) +#define GPIO62_CCIC_IN4 MFP_CFG_DRV(GPIO62, AF1, FAST) +#define GPIO63_CCIC_IN3 MFP_CFG_DRV(GPIO63, AF1, FAST) +#define GPIO64_CCIC_IN2 MFP_CFG_DRV(GPIO64, AF1, FAST) +#define GPIO65_CCIC_IN1 MFP_CFG_DRV(GPIO65, AF1, FAST) +#define GPIO66_CCIC_IN0 MFP_CFG_DRV(GPIO66, AF1, FAST) +#define GPIO67_CAM_HSYNC MFP_CFG_DRV(GPIO67, AF1, FAST) +#define GPIO68_CAM_VSYNC MFP_CFG_DRV(GPIO68, AF1, FAST) +#define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST) +#define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST) + +/* Wifi */ +#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0) +#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0) +#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0) +#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0) +#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0) +#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0) +#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0) + +/* Codec*/ +#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0) + +#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0) + +/* PMIC */ +#define PMIC_PMIC_INT MFP_CFG(PMIC_INT, AF0) + +#endif /* __ASM_MACH_MFP_MMP2_H */ + diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h index 3b216bf41e7f..ded43c455ec3 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h @@ -193,7 +193,9 @@ #define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3) #define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3) -/* UART1 */ +/* UART */ +#define GPIO88_UART2_TXD MFP_CFG(GPIO88, AF2) +#define GPIO89_UART2_RXD MFP_CFG(GPIO89, AF2) #define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST) #define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST) #define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST) diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h new file mode 100644 index 000000000000..459f3be9cfb2 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mmp2.h @@ -0,0 +1,60 @@ +#ifndef __ASM_MACH_MMP2_H +#define __ASM_MACH_MMP2_H + +#include <linux/i2c.h> +#include <mach/devices.h> +#include <plat/i2c.h> + +extern struct pxa_device_desc mmp2_device_uart1; +extern struct pxa_device_desc mmp2_device_uart2; +extern struct pxa_device_desc mmp2_device_uart3; +extern struct pxa_device_desc mmp2_device_uart4; +extern struct pxa_device_desc mmp2_device_twsi1; +extern struct pxa_device_desc mmp2_device_twsi2; +extern struct pxa_device_desc mmp2_device_twsi3; +extern struct pxa_device_desc mmp2_device_twsi4; +extern struct pxa_device_desc mmp2_device_twsi5; +extern struct pxa_device_desc mmp2_device_twsi6; + +static inline int mmp2_add_uart(int id) +{ + struct pxa_device_desc *d = NULL; + + switch (id) { + case 1: d = &mmp2_device_uart1; break; + case 2: d = &mmp2_device_uart2; break; + case 3: d = &mmp2_device_uart3; break; + case 4: d = &mmp2_device_uart4; break; + default: + return -EINVAL; + } + + return pxa_register_device(d, NULL, 0); +} + +static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data, + struct i2c_board_info *info, unsigned size) +{ + struct pxa_device_desc *d = NULL; + int ret; + + switch (id) { + case 0: d = &mmp2_device_twsi1; break; + case 1: d = &mmp2_device_twsi2; break; + case 2: d = &mmp2_device_twsi3; break; + case 3: d = &mmp2_device_twsi4; break; + case 4: d = &mmp2_device_twsi5; break; + case 5: d = &mmp2_device_twsi6; break; + default: + return -EINVAL; + } + + ret = i2c_register_board_info(id, info, size); + if (ret) + return ret; + + return pxa_register_device(d, data, sizeof(*data)); +} + +#endif /* __ASM_MACH_MMP2_H */ + diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index 98ccbee4bd0c..712af03fd1af 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -69,6 +69,47 @@ #define APBC_PXA910_ASFAR APBC_REG(0x050) #define APBC_PXA910_ASSAR APBC_REG(0x054) +/* + * APB Clock register offsets for MMP2 + */ +#define APBC_MMP2_RTC APBC_REG(0x000) +#define APBC_MMP2_TWSI1 APBC_REG(0x004) +#define APBC_MMP2_TWSI2 APBC_REG(0x008) +#define APBC_MMP2_TWSI3 APBC_REG(0x00c) +#define APBC_MMP2_TWSI4 APBC_REG(0x010) +#define APBC_MMP2_ONEWIRE APBC_REG(0x014) +#define APBC_MMP2_KPC APBC_REG(0x018) +#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c) +#define APBC_MMP2_SW_JTAG APBC_REG(0x020) +#define APBC_MMP2_TIMERS APBC_REG(0x024) +#define APBC_MMP2_UART1 APBC_REG(0x02c) +#define APBC_MMP2_UART2 APBC_REG(0x030) +#define APBC_MMP2_UART3 APBC_REG(0x034) +#define APBC_MMP2_GPIO APBC_REG(0x038) +#define APBC_MMP2_PWM0 APBC_REG(0x03c) +#define APBC_MMP2_PWM1 APBC_REG(0x040) +#define APBC_MMP2_PWM2 APBC_REG(0x044) +#define APBC_MMP2_PWM3 APBC_REG(0x048) +#define APBC_MMP2_SSP0 APBC_REG(0x04c) +#define APBC_MMP2_SSP1 APBC_REG(0x050) +#define APBC_MMP2_SSP2 APBC_REG(0x054) +#define APBC_MMP2_SSP3 APBC_REG(0x058) +#define APBC_MMP2_SSP4 APBC_REG(0x05c) +#define APBC_MMP2_SSP5 APBC_REG(0x060) +#define APBC_MMP2_AIB APBC_REG(0x064) +#define APBC_MMP2_ASFAR APBC_REG(0x068) +#define APBC_MMP2_ASSAR APBC_REG(0x06c) +#define APBC_MMP2_USIM APBC_REG(0x070) +#define APBC_MMP2_MPMU APBC_REG(0x074) +#define APBC_MMP2_IPC APBC_REG(0x078) +#define APBC_MMP2_TWSI5 APBC_REG(0x07c) +#define APBC_MMP2_TWSI6 APBC_REG(0x080) +#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084) +#define APBC_MMP2_UART4 APBC_REG(0x088) +#define APBC_MMP2_RIPC APBC_REG(0x08c) +#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */ +#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4) + /* Common APB clock register bit definitions */ #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h index e5f08723e0cc..f882d91894be 100644 --- a/arch/arm/mach-mmp/include/mach/regs-icu.h +++ b/arch/arm/mach-mmp/include/mach/regs-icu.h @@ -17,10 +17,12 @@ #define ICU_REG(x) (ICU_VIRT_BASE + (x)) #define ICU_INT_CONF(n) ICU_REG((n) << 2) +#define ICU_INT_CONF_MASK (0xf) + +/************ PXA168/PXA910 (MMP) *********************/ #define ICU_INT_CONF_AP_INT (1 << 6) #define ICU_INT_CONF_CP_INT (1 << 5) #define ICU_INT_CONF_IRQ (1 << 4) -#define ICU_INT_CONF_MASK (0xf) #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ @@ -28,4 +30,42 @@ #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ +/************************** MMP2 ***********************/ + +/* + * IRQ0/FIQ0 is routed to SP IRQ/FIQ. + * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ. + */ +#define ICU_INT_ROUTE_SP_IRQ (1 << 4) +#define ICU_INT_ROUTE_PJ4_IRQ (1 << 5) +#define ICU_INT_ROUTE_PJ4_FIQ (1 << 6) + +#define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138) +#define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c) +#define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140) +#define MMP2_ICU_PJ4_FIQ_STATUS1 ICU_REG(0x144) + +#define MMP2_ICU_INT4_STATUS ICU_REG(0x150) +#define MMP2_ICU_INT5_STATUS ICU_REG(0x154) +#define MMP2_ICU_INT17_STATUS ICU_REG(0x158) +#define MMP2_ICU_INT35_STATUS ICU_REG(0x15c) +#define MMP2_ICU_INT51_STATUS ICU_REG(0x160) + +#define MMP2_ICU_INT4_MASK ICU_REG(0x168) +#define MMP2_ICU_INT5_MASK ICU_REG(0x16C) +#define MMP2_ICU_INT17_MASK ICU_REG(0x170) +#define MMP2_ICU_INT35_MASK ICU_REG(0x174) +#define MMP2_ICU_INT51_MASK ICU_REG(0x178) + +#define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100) +#define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104) +#define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108) + +#define MMP2_ICU_INVERT ICU_REG(0x164) + +#define MMP2_ICU_INV_PMIC (1 << 0) +#define MMP2_ICU_INV_PERF (1 << 1) +#define MMP2_ICU_INV_COMMTX (1 << 2) +#define MMP2_ICU_INV_COMMRX (1 << 3) + #endif /* __ASM_MACH_ICU_H */ diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h index c93d5fa5865c..a7dcc5307216 100644 --- a/arch/arm/mach-mmp/include/mach/uncompress.h +++ b/arch/arm/mach-mmp/include/mach/uncompress.h @@ -8,15 +8,16 @@ #include <linux/serial_reg.h> #include <mach/addr-map.h> +#include <asm/mach-types.h> #define UART1_BASE (APB_PHYS_BASE + 0x36000) #define UART2_BASE (APB_PHYS_BASE + 0x17000) #define UART3_BASE (APB_PHYS_BASE + 0x18000) +static volatile unsigned long *UART = (unsigned long *)UART2_BASE; + static inline void putc(char c) { - volatile unsigned long *UART = (unsigned long *)UART2_BASE; - /* UART enabled? */ if (!(UART[UART_IER] & UART_IER_UUE)) return; @@ -34,8 +35,14 @@ static inline void flush(void) { } +static inline void arch_decomp_setup(void) +{ + if (machine_is_avengers_lite()) + UART = (unsigned long *)UART3_BASE; +} + /* * nothing to do */ -#define arch_decomp_setup() + #define arch_decomp_wdog() diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c new file mode 100644 index 000000000000..cb18221c0af3 --- /dev/null +++ b/arch/arm/mach-mmp/irq-mmp2.c @@ -0,0 +1,154 @@ +/* + * linux/arch/arm/mach-mmp/irq-mmp2.c + * + * Generic IRQ handling, GPIO IRQ demultiplexing, etc. + * + * Author: Haojian Zhuang <[email protected]> + * Copyright: Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/regs-icu.h> + +#include "common.h" + +static void icu_mask_irq(unsigned int irq) +{ + uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + + r &= ~ICU_INT_ROUTE_PJ4_IRQ; + __raw_writel(r, ICU_INT_CONF(irq)); +} + +static void icu_unmask_irq(unsigned int irq) +{ + uint32_t r = __raw_readl(ICU_INT_CONF(irq)); + + r |= ICU_INT_ROUTE_PJ4_IRQ; + __raw_writel(r, ICU_INT_CONF(irq)); +} + +static struct irq_chip icu_irq_chip = { + .name = "icu_irq", + .mask = icu_mask_irq, + .mask_ack = icu_mask_irq, + .unmask = icu_unmask_irq, +}; + +static void pmic_irq_ack(unsigned int irq) +{ + if (irq == IRQ_MMP2_PMIC) + mmp2_clear_pmic_int(); +} + +#define SECOND_IRQ_MASK(_name_, irq_base, prefix) \ +static void _name_##_mask_irq(unsigned int irq) \ +{ \ + uint32_t r; \ + r = __raw_readl(prefix##_MASK) | (1 << (irq - irq_base)); \ + __raw_writel(r, prefix##_MASK); \ +} + +#define SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ +static void _name_##_unmask_irq(unsigned int irq) \ +{ \ + uint32_t r; \ + r = __raw_readl(prefix##_MASK) & ~(1 << (irq - irq_base)); \ + __raw_writel(r, prefix##_MASK); \ +} + +#define SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ +static void _name_##_irq_demux(unsigned int irq, struct irq_desc *desc) \ +{ \ + unsigned long status, mask, n; \ + mask = __raw_readl(prefix##_MASK); \ + while (1) { \ + status = __raw_readl(prefix##_STATUS) & ~mask; \ + if (status == 0) \ + break; \ + n = find_first_bit(&status, BITS_PER_LONG); \ + while (n < BITS_PER_LONG) { \ + generic_handle_irq(irq_base + n); \ + n = find_next_bit(&status, BITS_PER_LONG, n+1); \ + } \ + } \ +} + +#define SECOND_IRQ_CHIP(_name_, irq_base, prefix) \ +SECOND_IRQ_MASK(_name_, irq_base, prefix) \ +SECOND_IRQ_UNMASK(_name_, irq_base, prefix) \ +SECOND_IRQ_DEMUX(_name_, irq_base, prefix) \ +static struct irq_chip _name_##_irq_chip = { \ + .name = #_name_, \ + .mask = _name_##_mask_irq, \ + .unmask = _name_##_unmask_irq, \ +} + +SECOND_IRQ_CHIP(pmic, IRQ_MMP2_PMIC_BASE, MMP2_ICU_INT4); +SECOND_IRQ_CHIP(rtc, IRQ_MMP2_RTC_BASE, MMP2_ICU_INT5); +SECOND_IRQ_CHIP(twsi, IRQ_MMP2_TWSI_BASE, MMP2_ICU_INT17); +SECOND_IRQ_CHIP(misc, IRQ_MMP2_MISC_BASE, MMP2_ICU_INT35); +SECOND_IRQ_CHIP(ssp, IRQ_MMP2_SSP_BASE, MMP2_ICU_INT51); + +static void init_mux_irq(struct irq_chip *chip, int start, int num) +{ + int irq; + + for (irq = start; num > 0; irq++, num--) { + /* mask and clear the IRQ */ + chip->mask(irq); + if (chip->ack) + chip->ack(irq); + + set_irq_chip(irq, chip); + set_irq_flags(irq, IRQF_VALID); + set_irq_handler(irq, handle_level_irq); + } +} + +void __init mmp2_init_icu(void) +{ + int irq; + + for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { + icu_mask_irq(irq); + set_irq_chip(irq, &icu_irq_chip); + set_irq_flags(irq, IRQF_VALID); + + switch (irq) { + case IRQ_MMP2_PMIC_MUX: + case IRQ_MMP2_RTC_MUX: + case IRQ_MMP2_TWSI_MUX: + case IRQ_MMP2_MISC_MUX: + case IRQ_MMP2_SSP_MUX: + break; + default: + set_irq_handler(irq, handle_level_irq); + break; + } + } + + /* NOTE: IRQ_MMP2_PMIC requires the PMIC MFPR register + * to be written to clear the interrupt + */ + pmic_irq_chip.ack = pmic_irq_ack; + + init_mux_irq(&pmic_irq_chip, IRQ_MMP2_PMIC_BASE, 2); + init_mux_irq(&rtc_irq_chip, IRQ_MMP2_RTC_BASE, 2); + init_mux_irq(&twsi_irq_chip, IRQ_MMP2_TWSI_BASE, 5); + init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); + init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); + + set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); + set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); + set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); + set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); + set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); +} diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq-pxa168.c index 52ff2f065eba..52ff2f065eba 100644 --- a/arch/arm/mach-mmp/irq.c +++ b/arch/arm/mach-mmp/irq-pxa168.c diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c new file mode 100644 index 000000000000..cfd4d66ef800 --- /dev/null +++ b/arch/arm/mach-mmp/jasper.c @@ -0,0 +1,80 @@ +/* + * linux/arch/arm/mach-mmp/jasper.c + * + * Support for the Marvell Jasper Development Platform. + * + * Copyright (C) 2009-2010 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <mach/addr-map.h> +#include <mach/mfp-mmp2.h> +#include <mach/mmp2.h> + +#include "common.h" + +static unsigned long jasper_pin_config[] __initdata = { + /* UART1 */ + GPIO29_UART1_RXD, + GPIO30_UART1_TXD, + + /* UART3 */ + GPIO51_UART3_RXD, + GPIO52_UART3_TXD, + + /* DFI */ + GPIO168_DFI_D0, + GPIO167_DFI_D1, + GPIO166_DFI_D2, + GPIO165_DFI_D3, + GPIO107_DFI_D4, + GPIO106_DFI_D5, + GPIO105_DFI_D6, + GPIO104_DFI_D7, + GPIO111_DFI_D8, + GPIO164_DFI_D9, + GPIO163_DFI_D10, + GPIO162_DFI_D11, + GPIO161_DFI_D12, + GPIO110_DFI_D13, + GPIO109_DFI_D14, + GPIO108_DFI_D15, + GPIO143_ND_nCS0, + GPIO144_ND_nCS1, + GPIO147_ND_nWE, + GPIO148_ND_nRE, + GPIO150_ND_ALE, + GPIO149_ND_CLE, + GPIO112_ND_RDY0, + GPIO160_ND_RDY1, +}; + +static void __init jasper_init(void) +{ + mfp_config(ARRAY_AND_SIZE(jasper_pin_config)); + + /* on-chip devices */ + mmp2_add_uart(1); + mmp2_add_uart(3); +} + +MACHINE_START(MARVELL_JASPER, "Jasper Development Platform") + .phys_io = APB_PHYS_BASE, + .boot_params = 0x00000100, + .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = mmp2_init_irq, + .timer = &mmp2_timer, + .init_machine = jasper_init, +MACHINE_END diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c new file mode 100644 index 000000000000..72eb9daeea99 --- /dev/null +++ b/arch/arm/mach-mmp/mmp2.c @@ -0,0 +1,123 @@ +/* + * linux/arch/arm/mach-mmp/mmp2.c + * + * code name MMP2 + * + * Copyright (C) 2009 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/io.h> + +#include <mach/addr-map.h> +#include <mach/regs-apbc.h> +#include <mach/regs-apmu.h> +#include <mach/cputype.h> +#include <mach/irqs.h> +#include <mach/mfp.h> +#include <mach/gpio.h> +#include <mach/devices.h> + +#include "common.h" +#include "clock.h" + +#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) + +#define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c) + +static struct mfp_addr_map mmp2_addr_map[] __initdata = { + MFP_ADDR(PMIC_INT, 0x2c4), + + MFP_ADDR_END, +}; + +void mmp2_clear_pmic_int(void) +{ + unsigned long mfpr_pmic, data; + + mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; + data = __raw_readl(mfpr_pmic); + __raw_writel(data | (1 << 6), mfpr_pmic); + __raw_writel(data, mfpr_pmic); +} + +static void __init mmp2_init_gpio(void) +{ + int i; + + /* enable GPIO clock */ + __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO); + + /* unmask GPIO edge detection for all 6 banks -- APMASKx */ + for (i = 0; i < 6; i++) + __raw_writel(0xffffffff, APMASK(i)); + + pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL); +} + +void __init mmp2_init_irq(void) +{ + mmp2_init_icu(); + mmp2_init_gpio(); +} + +/* APB peripheral clocks */ +static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); +static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); +static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); +static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); +static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); +static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); +static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); +static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); +static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); +static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); +static APBC_CLK(rtc, MMP2_RTC, 0, 32768); + +static APMU_CLK(nand, NAND, 0xbf, 100000000); + +static struct clk_lookup mmp2_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), + INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), + INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), + INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), +}; + +static int __init mmp2_init(void) +{ + if (cpu_is_mmp2()) { + mfp_init_base(MFPR_VIRT_BASE); + mfp_init_addr(mmp2_addr_map); + clks_register(ARRAY_AND_SIZE(mmp2_clkregs)); + } + + return 0; +} +postcore_initcall(mmp2_init); + +/* on-chip devices */ +MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); +MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); +MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); +MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); +MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); +MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); +MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); +MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); +MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); +MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); +MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); + diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index a8400bb891e7..cf75694e9687 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -30,7 +30,10 @@ #include <mach/addr-map.h> #include <mach/regs-timers.h> +#include <mach/regs-apbc.h> #include <mach/irqs.h> +#include <mach/cputype.h> +#include <asm/mach/time.h> #include "clock.h" @@ -158,7 +161,7 @@ static void __init timer_config(void) __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */ - ccr &= TMR_CCR_CS_0(0x3); + ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3); __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); /* free-running mode */ @@ -197,3 +200,24 @@ void __init timer_init(int irq) clocksource_register(&cksrc); clockevents_register_device(&ckevt); } + +static void __init mmp2_timer_init(void) +{ + unsigned long clk_rst; + + __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); + + /* + * enable bus/functional clock, enable 6.5MHz (divider 4), + * release reset + */ + clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); + __raw_writel(clk_rst, APBC_MMP2_TIMERS); + + timer_init(IRQ_MMP2_TIMER1); +} + +struct sys_timer mmp2_timer = { + .init = mmp2_timer_init, +}; + diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index 6fbe68fe4412..f2d309d0619e 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig @@ -14,6 +14,12 @@ config MACH_RD78X00_MASA Say 'Y' here if you want your kernel to support the Marvell RD-78x00-mASA Reference Design. +config MACH_TERASTATION_WXL + bool "Buffalo WLX (Terastation Duo) NAS" + help + Say 'Y' here if you want your kernel to support the + Buffalo WXL Nas. + endmenu endif diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index da628b7f3bb6..67a13f9bfe64 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile @@ -1,3 +1,4 @@ -obj-y += common.o addr-map.o irq.o pcie.o +obj-y += common.o addr-map.o mpp.o irq.o pcie.o obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o +obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c new file mode 100644 index 000000000000..61e5e583603b --- /dev/null +++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c @@ -0,0 +1,155 @@ +/* + * arch/arm/mach-mv78xx0/buffalo-wxl-setup.c + * + * Buffalo WXL (Terastation Duo) Setup routines + * + * sebastien requiem <[email protected]> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/mv643xx_eth.h> +#include <linux/ethtool.h> +#include <linux/i2c.h> +#include <mach/mv78xx0.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include "common.h" +#include "mpp.h" + + +/* This arch has 2 Giga Ethernet */ + +static struct mv643xx_eth_platform_data db78x00_ge00_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(0), +}; + +static struct mv643xx_eth_platform_data db78x00_ge01_data = { + .phy_addr = MV643XX_ETH_PHY_ADDR(8), +}; + + +/* 2 SATA controller supporting HotPlug */ + +static struct mv_sata_platform_data db78x00_sata_data = { + .n_ports = 2, +}; + +static struct i2c_board_info __initdata db78x00_i2c_rtc = { + I2C_BOARD_INFO("ds1338", 0x68), +}; + + +static unsigned int wxl_mpp_config[] __initdata = { + MPP0_GE1_TXCLK, + MPP1_GE1_TXCTL, + MPP2_GE1_RXCTL, + MPP3_GE1_RXCLK, + MPP4_GE1_TXD0, + MPP5_GE1_TXD1, + MPP6_GE1_TXD2, + MPP7_GE1_TXD3, + MPP8_GE1_RXD0, + MPP9_GE1_RXD1, + MPP10_GE1_RXD2, + MPP11_GE1_RXD3, + MPP12_GPIO, + MPP13_SYSRST_OUTn, + MPP14_SATA1_ACTn, + MPP15_SATA0_ACTn, + MPP16_GPIO, + MPP17_GPIO, + MPP18_GPIO, + MPP19_GPIO, + MPP20_GPIO, + MPP21_GPIO, + MPP22_GPIO, + MPP23_GPIO, + MPP24_UA2_TXD, + MPP25_UA2_RXD, + MPP26_UA2_CTSn, + MPP27_UA2_RTSn, + MPP28_GPIO, + MPP29_SYSRST_OUTn, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_UNUSED, + MPP41_UNUSED, + MPP42_UNUSED, + MPP43_UNUSED, + MPP44_UNUSED, + MPP45_UNUSED, + MPP46_UNUSED, + MPP47_UNUSED, + MPP48_SATA1_ACTn, + MPP49_SATA0_ACTn, + 0 +}; + + +static void __init wxl_init(void) +{ + /* + * Basic MV78xx0 setup. Needs to be called early. + */ + mv78xx0_init(); + mv78xx0_mpp_conf(wxl_mpp_config); + + /* + * Partition on-chip peripherals between the two CPU cores. + */ + mv78xx0_ehci0_init(); + mv78xx0_ehci1_init(); + mv78xx0_ehci2_init(); + mv78xx0_ge00_init(&db78x00_ge00_data); + mv78xx0_ge01_init(&db78x00_ge01_data); + mv78xx0_sata_init(&db78x00_sata_data); + mv78xx0_uart0_init(); + mv78xx0_uart1_init(); + mv78xx0_uart2_init(); + mv78xx0_uart3_init(); + mv78xx0_i2c_init(); + i2c_register_board_info(0, &db78x00_i2c_rtc, 1); +} + +static int __init wxl_pci_init(void) +{ + if (machine_is_terastation_wxl()) { + /* + * Assign the x16 PCIe slot on the board to CPU core + * #0, and let CPU core #1 have the four x1 slots. + */ + if (mv78xx0_core_index() == 0) + mv78xx0_pcie_init(0, 1); + else + mv78xx0_pcie_init(1, 0); + } + + return 0; +} +subsys_initcall(wxl_pci_init); + +MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL") + /* Maintainer: Sebastien Requiem <[email protected]> */ + .phys_io = MV78XX0_REGS_PHYS_BASE, + .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc, + .boot_params = 0x00000100, + .init_machine = wxl_init, + .map_io = mv78xx0_map_io, + .init_irq = mv78xx0_init_irq, + .timer = &mv78xx0_timer, +MACHINE_END diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c new file mode 100644 index 000000000000..354ac514eb89 --- /dev/null +++ b/arch/arm/mach-mv78xx0/mpp.c @@ -0,0 +1,96 @@ +/* + * arch/arm/mach-mv78x00/mpp.c + * + * MPP functions for Marvell MV78x00 SoCs + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <asm/gpio.h> +#include <mach/hardware.h> +#include "common.h" +#include "mpp.h" + +static unsigned int __init mv78xx0_variant(void) +{ + u32 dev, rev; + + mv78xx0_pcie_id(&dev, &rev); + + if (dev == MV78100_DEV_ID && rev >= MV78100_REV_A0) + return MPP_78100_A0_MASK; + + printk(KERN_ERR "MPP setup: unknown mv78x00 variant " + "(dev %#x rev %#x)\n", dev, rev); + return 0; +} + +#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4) +#define MPP_NR_REGS (1 + MPP_MAX/8) + +void __init mv78xx0_mpp_conf(unsigned int *mpp_list) +{ + u32 mpp_ctrl[MPP_NR_REGS]; + unsigned int variant_mask; + int i; + + variant_mask = mv78xx0_variant(); + if (!variant_mask) + return; + + /* Initialize gpiolib. */ + orion_gpio_init(); + + printk(KERN_DEBUG "initial MPP regs:"); + for (i = 0; i < MPP_NR_REGS; i++) { + mpp_ctrl[i] = readl(MPP_CTRL(i)); + printk(" %08x", mpp_ctrl[i]); + } + printk("\n"); + + while (*mpp_list) { + unsigned int num = MPP_NUM(*mpp_list); + unsigned int sel = MPP_SEL(*mpp_list); + int shift, gpio_mode; + + if (num > MPP_MAX) { + printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP " + "number (%u)\n", num); + continue; + } + if (!(*mpp_list & variant_mask)) { + printk(KERN_WARNING + "mv78xx0_mpp_conf: requested MPP%u config " + "unavailable on this hardware\n", num); + continue; + } + + shift = (num & 7) << 2; + mpp_ctrl[num / 8] &= ~(0xf << shift); + mpp_ctrl[num / 8] |= sel << shift; + + gpio_mode = 0; + if (*mpp_list & MPP_INPUT_MASK) + gpio_mode |= GPIO_INPUT_OK; + if (*mpp_list & MPP_OUTPUT_MASK) + gpio_mode |= GPIO_OUTPUT_OK; + if (sel != 0) + gpio_mode = 0; + orion_gpio_set_valid(num, gpio_mode); + + mpp_list++; + } + + printk(KERN_DEBUG " final MPP regs:"); + for (i = 0; i < MPP_NR_REGS; i++) { + writel(mpp_ctrl[i], MPP_CTRL(i)); + printk(" %08x", mpp_ctrl[i]); + } + printk("\n"); +} diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h new file mode 100644 index 000000000000..80840b781eaa --- /dev/null +++ b/arch/arm/mach-mv78xx0/mpp.h @@ -0,0 +1,347 @@ +/* + * linux/arch/arm/mach-mv78xx0/mpp.h -- Multi Purpose Pins + * + * + * sebastien requiem <[email protected]> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MV78X00_MPP_H +#define __MV78X00_MPP_H + +#define MPP(_num, _sel, _in, _out, _78100_A0) (\ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13) | \ + /* available on A0 */ ((!!(_78100_A0)) << 14)) + +#define MPP_NUM(x) ((x) & 0xff) +#define MPP_SEL(x) (((x) >> 8) & 0xf) + + /* num sel i o 78100_A0 */ + +#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0) +#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0) + +#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) + +#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) +#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) +#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) +#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) + +#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) +#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) +#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) +#define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) + +#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) +#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) +#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) +#define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) + +#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) +#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) +#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) +#define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) + +#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) +#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) +#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) +#define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) + +#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) +#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) +#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) +#define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) + +#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) +#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) +#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) +#define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) + +#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) +#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) +#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) +#define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) + +#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) +#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) +#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) +#define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) + +#define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) +#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) +#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) +#define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) + +#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) +#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) +#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) +#define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) + +#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) +#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) +#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) +#define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) + +#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) +#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) +#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) +#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) +#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) +#define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) + +#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) +#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) +#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) +#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) +#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) +#define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) + +#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) +#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) +#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) +#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) +#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) +#define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) + +#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) +#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) +#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) +#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) +#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) +#define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) + +#define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) +#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) +#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) +#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) +#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) +#define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) + + +#define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) +#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) +#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) +#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) +#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) +#define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) + + +#define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) +#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) +#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) +#define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) + + + +#define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) +#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) +#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) +#define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) + + +#define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) +#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) +#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) +#define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) + + + +#define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) +#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) +#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) +#define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) + + + +#define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) +#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) +#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) +#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) +#define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) + + + +#define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) +#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) +#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) +#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) +#define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) + + +#define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) +#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) +#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) +#define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) + + +#define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) +#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) +#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) +#define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) + + +#define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) +#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) +#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) +#define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) + + +#define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) +#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) +#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) +#define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) + + +#define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) +#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) +#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) +#define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) + +#define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) +#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) +#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) +#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) +#define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) + +#define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) +#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) +#define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) + +#define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) +#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) +#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) +#define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) + + +#define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) +#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) +#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) +#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) +#define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) + + +#define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) +#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) +#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) +#define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) + + + +#define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) +#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) +#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) +#define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) + + + +#define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) +#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) +#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) +#define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) + +#define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) +#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) +#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) +#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) +#define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) + + +#define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) +#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) +#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) +#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) +#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) +#define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) + + + + +#define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) +#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) +#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) +#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) +#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) +#define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) + + + + +#define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) +#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) +#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) +#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) +#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) +#define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) + + + +#define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) +#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) +#define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) + + + +#define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) +#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) +#define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) + + + +#define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) +#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) +#define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) + + + +#define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) +#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) +#define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) + + + +#define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) +#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) +#define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) + + + +#define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) +#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) +#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) +#define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) + + +#define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) +#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) +#define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) + + +#define MPP47_GPIO MPP(47, 0x1, 1, 1, 1) +#define MPP47_UNUSED MPP(47, 0x0, 0, 0, 1) + + + +#define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) +#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) +#define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) + + + +#define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) +#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) +#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) +#define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) + + +#define MPP_MAX 49 + +void mv78xx0_mpp_conf(unsigned int *mpp_list); + +#endif diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile index 7f86fe073ec6..fc2ddf82441b 100644 --- a/arch/arm/mach-mx1/Makefile +++ b/arch/arm/mach-mx1/Makefile @@ -4,11 +4,12 @@ # Object file lists. +EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS obj-y += generic.o clock.o devices.o # Support for CMOS sensor interface obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o # Specific board support -obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o -obj-$(CONFIG_MACH_SCB9328) += scb9328.o
\ No newline at end of file +obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o +obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c index 30f04e56fafe..51f3cfd83db2 100644 --- a/arch/arm/mach-mx1/mx1ads.c +++ b/arch/arm/mach-mx1/mach-mx1ads.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-imx/mx1ads.c + * arch/arm/mach-imx/mach-mx1ads.c * * Initially based on: * linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c @@ -27,7 +27,7 @@ #include <mach/hardware.h> #include <mach/i2c.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx1.h> #include <mach/irqs.h> #include "devices.h" @@ -147,7 +147,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS") /* Maintainer: Sascha Hauer, Pengutronix */ .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, .timer = &mx1ads_timer, @@ -157,7 +157,7 @@ MACHINE_END MACHINE_START(MXLADS, "Freescale MXLADS") .phys_io = IMX_IO_PHYS, .io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX1_PHYS_OFFSET + 0x100, .map_io = mx1_map_io, .init_irq = mx1_init_irq, .timer = &mx1ads_timer, diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c index 325d98df6053..7587a7a12460 100644 --- a/arch/arm/mach-mx1/scb9328.c +++ b/arch/arm/mach-mx1/mach-scb9328.c @@ -1,5 +1,5 @@ /* - * linux/arch/arm/mach-mx1/scb9328.c + * linux/arch/arm/mach-mx1/mach-scb9328.c * * Copyright (c) 2004 Sascha Hauer <[email protected]> * Copyright (c) 2006-2008 Juergen Beisert <[email protected]> @@ -23,7 +23,7 @@ #include <mach/hardware.h> #include <mach/irqs.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx1.h> #include "devices.h" diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index b96c6a389363..742fd4e6dcb9 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig @@ -37,6 +37,7 @@ config MACH_MX27ADS config MACH_PCM038 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" depends on MACH_MX27 + select MXC_ULPI if USB_ULPI help Include support for phyCORE-i.MX27 (aka pcm038) platform. This includes specific configurations for the module and its peripherals. @@ -55,7 +56,7 @@ config MACH_PCM970_BASEBOARD endchoice -config MACH_EUKREA_CPUIMX27 +config MACH_CPUIMX27 bool "Eukrea CPUIMX27 module" depends on MACH_MX27 help @@ -64,14 +65,14 @@ config MACH_EUKREA_CPUIMX27 config MACH_EUKREA_CPUIMX27_USESDHC2 bool "CPUIMX27 integrates SDHC2 module" - depends on MACH_EUKREA_CPUIMX27 + depends on MACH_CPUIMX27 help This adds support for the internal SDHC2 used on CPUIMX27 used for wifi or eMMC. choice prompt "Baseboard" - depends on MACH_EUKREA_CPUIMX27 + depends on MACH_CPUIMX27 default MACH_EUKREA_MBIMX27_BASEBOARD config MACH_EUKREA_MBIMX27_BASEBOARD @@ -90,7 +91,7 @@ config MACH_MX27_3DS Include support for MX27PDK platform. This includes specific configurations for the board and its peripherals. -config MACH_MX27LITE +config MACH_IMX27LITE bool "LogicPD MX27 LITEKIT platform" depends on MACH_MX27 help @@ -100,6 +101,7 @@ config MACH_MX27LITE config MACH_PCA100 bool "Phytec phyCARD-s (pca100)" depends on MACH_MX27 + select MXC_ULPI if USB_ULPI help Include support for phyCARD-s (aka pca100) platform. This includes specific configurations for the module and its peripherals. diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index 52aca0aaf9b5..e3254faac828 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile @@ -4,21 +4,20 @@ # Object file lists. -obj-y := generic.o devices.o serial.o +obj-y := devices.o serial.o -obj-$(CONFIG_MACH_MX21) += clock_imx21.o +obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o obj-$(CONFIG_MACH_MX27) += cpu_imx27.o -obj-$(CONFIG_MACH_MX27) += clock_imx27.o +obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o -obj-$(CONFIG_MACH_MX21ADS) += mx21ads.o -obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o -obj-$(CONFIG_MACH_PCM038) += pcm038.o +obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o +obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o +obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o -obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o -obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o -obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o +obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o +obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o +obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o -obj-$(CONFIG_MACH_PCA100) += pca100.o -obj-$(CONFIG_MACH_MXT_TD60) += mxt_td60.o - +obj-$(CONFIG_MACH_PCA100) += mach-pca100.o +obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c index 91901b5d56c2..8974faf9cef0 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-mx2/clock_imx21.c @@ -23,11 +23,242 @@ #include <linux/module.h> #include <mach/clock.h> +#include <mach/hardware.h> #include <mach/common.h> #include <asm/clkdev.h> #include <asm/div64.h> -#include "crm_regs.h" +#define IO_ADDR_CCM(off) (MX21_IO_ADDRESS(MX21_CCM_BASE_ADDR + (off))) + +/* Register offsets */ +#define CCM_CSCR IO_ADDR_CCM(0x0) +#define CCM_MPCTL0 IO_ADDR_CCM(0x4) +#define CCM_MPCTL1 IO_ADDR_CCM(0x8) +#define CCM_SPCTL0 IO_ADDR_CCM(0xc) +#define CCM_SPCTL1 IO_ADDR_CCM(0x10) +#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) +#define CCM_PCDR0 IO_ADDR_CCM(0x18) +#define CCM_PCDR1 IO_ADDR_CCM(0x1c) +#define CCM_PCCR0 IO_ADDR_CCM(0x20) +#define CCM_PCCR1 IO_ADDR_CCM(0x24) +#define CCM_CCSR IO_ADDR_CCM(0x28) +#define CCM_PMCTL IO_ADDR_CCM(0x2c) +#define CCM_PMCOUNT IO_ADDR_CCM(0x30) +#define CCM_WKGDCTL IO_ADDR_CCM(0x34) + +#define CCM_CSCR_PRESC_OFFSET 29 +#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) + +#define CCM_CSCR_USB_OFFSET 26 +#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET) +#define CCM_CSCR_SD_OFFSET 24 +#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET) +#define CCM_CSCR_SPLLRES (1 << 22) +#define CCM_CSCR_MPLLRES (1 << 21) +#define CCM_CSCR_SSI2_OFFSET 20 +#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET) +#define CCM_CSCR_SSI1_OFFSET 19 +#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET) +#define CCM_CSCR_FIR_OFFSET 18 +#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET) +#define CCM_CSCR_SP (1 << 17) +#define CCM_CSCR_MCU (1 << 16) +#define CCM_CSCR_BCLK_OFFSET 10 +#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET) +#define CCM_CSCR_IPDIV_OFFSET 9 +#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET) + +#define CCM_CSCR_OSC26MDIV (1 << 4) +#define CCM_CSCR_OSC26M (1 << 3) +#define CCM_CSCR_FPM (1 << 2) +#define CCM_CSCR_SPEN (1 << 1) +#define CCM_CSCR_MPEN 1 + +#define CCM_MPCTL0_CPLM (1 << 31) +#define CCM_MPCTL0_PD_OFFSET 26 +#define CCM_MPCTL0_PD_MASK (0xf << 26) +#define CCM_MPCTL0_MFD_OFFSET 16 +#define CCM_MPCTL0_MFD_MASK (0x3ff << 16) +#define CCM_MPCTL0_MFI_OFFSET 10 +#define CCM_MPCTL0_MFI_MASK (0xf << 10) +#define CCM_MPCTL0_MFN_OFFSET 0 +#define CCM_MPCTL0_MFN_MASK 0x3ff + +#define CCM_MPCTL1_LF (1 << 15) +#define CCM_MPCTL1_BRMO (1 << 6) + +#define CCM_SPCTL0_CPLM (1 << 31) +#define CCM_SPCTL0_PD_OFFSET 26 +#define CCM_SPCTL0_PD_MASK (0xf << 26) +#define CCM_SPCTL0_MFD_OFFSET 16 +#define CCM_SPCTL0_MFD_MASK (0x3ff << 16) +#define CCM_SPCTL0_MFI_OFFSET 10 +#define CCM_SPCTL0_MFI_MASK (0xf << 10) +#define CCM_SPCTL0_MFN_OFFSET 0 +#define CCM_SPCTL0_MFN_MASK 0x3ff + +#define CCM_SPCTL1_LF (1 << 15) +#define CCM_SPCTL1_BRMO (1 << 6) + +#define CCM_OSC26MCTL_PEAK_OFFSET 16 +#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) +#define CCM_OSC26MCTL_AGC_OFFSET 8 +#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8) +#define CCM_OSC26MCTL_ANATEST_OFFSET 0 +#define CCM_OSC26MCTL_ANATEST_MASK 0x3f + +#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 +#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) +#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 +#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) +#define CCM_PCDR0_NFCDIV_OFFSET 12 +#define CCM_PCDR0_NFCDIV_MASK (0xf << 12) +#define CCM_PCDR0_48MDIV_OFFSET 5 +#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET) +#define CCM_PCDR0_FIRIDIV_OFFSET 0 +#define CCM_PCDR0_FIRIDIV_MASK 0x1f +#define CCM_PCDR1_PERDIV4_OFFSET 24 +#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) +#define CCM_PCDR1_PERDIV3_OFFSET 16 +#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16) +#define CCM_PCDR1_PERDIV2_OFFSET 8 +#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8) +#define CCM_PCDR1_PERDIV1_OFFSET 0 +#define CCM_PCDR1_PERDIV1_MASK 0x3f + +#define CCM_PCCR_HCLK_CSI_OFFSET 31 +#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_DMA_OFFSET 30 +#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_BROM_OFFSET 28 +#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_EMMA_OFFSET 27 +#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_LCDC_OFFSET 26 +#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_SLCDC_OFFSET 25 +#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_USBOTG_OFFSET 24 +#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0 +#define CCM_PCCR_HCLK_BMI_OFFSET 23 +#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK) +#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0 +#define CCM_PCCR_PERCLK4_OFFSET 22 +#define CCM_PCCR_PERCLK4_REG CCM_PCCR0 +#define CCM_PCCR_SLCDC_OFFSET 21 +#define CCM_PCCR_SLCDC_REG CCM_PCCR0 +#define CCM_PCCR_FIRI_BAUD_OFFSET 20 +#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK) +#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0 +#define CCM_PCCR_NFC_OFFSET 19 +#define CCM_PCCR_NFC_REG CCM_PCCR0 +#define CCM_PCCR_LCDC_OFFSET 18 +#define CCM_PCCR_LCDC_REG CCM_PCCR0 +#define CCM_PCCR_SSI1_BAUD_OFFSET 17 +#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0 +#define CCM_PCCR_SSI2_BAUD_OFFSET 16 +#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0 +#define CCM_PCCR_EMMA_OFFSET 15 +#define CCM_PCCR_EMMA_REG CCM_PCCR0 +#define CCM_PCCR_USBOTG_OFFSET 14 +#define CCM_PCCR_USBOTG_REG CCM_PCCR0 +#define CCM_PCCR_DMA_OFFSET 13 +#define CCM_PCCR_DMA_REG CCM_PCCR0 +#define CCM_PCCR_I2C1_OFFSET 12 +#define CCM_PCCR_I2C1_REG CCM_PCCR0 +#define CCM_PCCR_GPIO_OFFSET 11 +#define CCM_PCCR_GPIO_REG CCM_PCCR0 +#define CCM_PCCR_SDHC2_OFFSET 10 +#define CCM_PCCR_SDHC2_REG CCM_PCCR0 +#define CCM_PCCR_SDHC1_OFFSET 9 +#define CCM_PCCR_SDHC1_REG CCM_PCCR0 +#define CCM_PCCR_FIRI_OFFSET 8 +#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK) +#define CCM_PCCR_FIRI_REG CCM_PCCR0 +#define CCM_PCCR_SSI2_IPG_OFFSET 7 +#define CCM_PCCR_SSI2_REG CCM_PCCR0 +#define CCM_PCCR_SSI1_IPG_OFFSET 6 +#define CCM_PCCR_SSI1_REG CCM_PCCR0 +#define CCM_PCCR_CSPI2_OFFSET 5 +#define CCM_PCCR_CSPI2_REG CCM_PCCR0 +#define CCM_PCCR_CSPI1_OFFSET 4 +#define CCM_PCCR_CSPI1_REG CCM_PCCR0 +#define CCM_PCCR_UART4_OFFSET 3 +#define CCM_PCCR_UART4_REG CCM_PCCR0 +#define CCM_PCCR_UART3_OFFSET 2 +#define CCM_PCCR_UART3_REG CCM_PCCR0 +#define CCM_PCCR_UART2_OFFSET 1 +#define CCM_PCCR_UART2_REG CCM_PCCR0 +#define CCM_PCCR_UART1_OFFSET 0 +#define CCM_PCCR_UART1_REG CCM_PCCR0 + +#define CCM_PCCR_OWIRE_OFFSET 31 +#define CCM_PCCR_OWIRE_REG CCM_PCCR1 +#define CCM_PCCR_KPP_OFFSET 30 +#define CCM_PCCR_KPP_REG CCM_PCCR1 +#define CCM_PCCR_RTC_OFFSET 29 +#define CCM_PCCR_RTC_REG CCM_PCCR1 +#define CCM_PCCR_PWM_OFFSET 28 +#define CCM_PCCR_PWM_REG CCM_PCCR1 +#define CCM_PCCR_GPT3_OFFSET 27 +#define CCM_PCCR_GPT3_REG CCM_PCCR1 +#define CCM_PCCR_GPT2_OFFSET 26 +#define CCM_PCCR_GPT2_REG CCM_PCCR1 +#define CCM_PCCR_GPT1_OFFSET 25 +#define CCM_PCCR_GPT1_REG CCM_PCCR1 +#define CCM_PCCR_WDT_OFFSET 24 +#define CCM_PCCR_WDT_REG CCM_PCCR1 +#define CCM_PCCR_CSPI3_OFFSET 23 +#define CCM_PCCR_CSPI3_REG CCM_PCCR1 + +#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET) +#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET) +#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET) +#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET) +#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET) +#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET) +#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET) +#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET) +#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET) +#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET) +#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET) +#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET) +#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET) +#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET) +#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET) +#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET) +#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET) +#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET) +#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET) +#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET) +#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET) +#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET) +#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET) +#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET) +#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET) +#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET) +#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET) +#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET) +#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET) +#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET) +#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET) +#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET) +#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET) +#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET) +#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET) +#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET) +#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET) + +#define CCM_CCSR_32KSR (1 << 15) + +#define CCM_CCSR_CLKMODE1 (1 << 9) +#define CCM_CCSR_CLKMODE0 (1 << 8) + +#define CCM_CCSR_CLKOSEL_OFFSET 0 +#define CCM_CCSR_CLKOSEL_MASK 0x1f + +#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */ +#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ static int _clk_enable(struct clk *clk) { @@ -1004,6 +1235,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) clk_enable(&uart_clk[0]); #endif - mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); + mxc_timer_init(&gpt_clk[0], MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), + MX21_INT_GPT1); return 0; } diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index b010bf9ceaab..68bf93e6e907 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c @@ -29,21 +29,23 @@ #include <mach/common.h> #include <mach/hardware.h> +#define IO_ADDR_CCM(off) (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off))) + /* Register offsets */ -#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) -#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) -#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) -#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) -#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) -#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) -#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) -#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) -#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) -#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) -#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) -#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) -#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) -#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) +#define CCM_CSCR IO_ADDR_CCM(0x0) +#define CCM_MPCTL0 IO_ADDR_CCM(0x4) +#define CCM_MPCTL1 IO_ADDR_CCM(0x8) +#define CCM_SPCTL0 IO_ADDR_CCM(0xc) +#define CCM_SPCTL1 IO_ADDR_CCM(0x10) +#define CCM_OSC26MCTL IO_ADDR_CCM(0x14) +#define CCM_PCDR0 IO_ADDR_CCM(0x18) +#define CCM_PCDR1 IO_ADDR_CCM(0x1c) +#define CCM_PCCR0 IO_ADDR_CCM(0x20) +#define CCM_PCCR1 IO_ADDR_CCM(0x24) +#define CCM_CCSR IO_ADDR_CCM(0x28) +#define CCM_PMCTL IO_ADDR_CCM(0x2c) +#define CCM_PMCOUNT IO_ADDR_CCM(0x30) +#define CCM_WKGDCTL IO_ADDR_CCM(0x34) #define CCM_CSCR_UPDATE_DIS (1 << 31) #define CCM_CSCR_SSI2 (1 << 23) @@ -755,7 +757,8 @@ int __init mx27_clocks_init(unsigned long fref) clk_enable(&uart1_clk); #endif - mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1); + mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), + MX27_INT_GPT1); return 0; } diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c index d9e3bf9644c9..d8d3b2d84dc5 100644 --- a/arch/arm/mach-mx2/cpu_imx27.c +++ b/arch/arm/mach-mx2/cpu_imx27.c @@ -39,7 +39,8 @@ static void query_silicon_parameter(void) * the silicon revision very early we read it here to * avoid any further hooks */ - val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID); + val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR + + SYS_CHIP_ID)); cpu_silicon_rev = (int)(val >> 28); cpu_partnumber = (int)((val >> 12) & 0xFFFF); diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h deleted file mode 100644 index 749de76b3f95..000000000000 --- a/arch/arm/mach-mx2/crm_regs.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2008 Juergen Beisert, [email protected] - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301, USA. - */ - -#ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX2_CRM_REGS_H__ - -#include <mach/hardware.h> - -/* Register offsets */ -#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) -#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) -#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) -#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) -#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) -#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) -#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) -#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) -#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) -#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) -#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) -#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) -#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) -#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) - -#define CCM_CSCR_PRESC_OFFSET 29 -#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) - -#define CCM_CSCR_USB_OFFSET 26 -#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET) -#define CCM_CSCR_SD_OFFSET 24 -#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET) -#define CCM_CSCR_SPLLRES (1 << 22) -#define CCM_CSCR_MPLLRES (1 << 21) -#define CCM_CSCR_SSI2_OFFSET 20 -#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET) -#define CCM_CSCR_SSI1_OFFSET 19 -#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET) -#define CCM_CSCR_FIR_OFFSET 18 -#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET) -#define CCM_CSCR_SP (1 << 17) -#define CCM_CSCR_MCU (1 << 16) -#define CCM_CSCR_BCLK_OFFSET 10 -#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET) -#define CCM_CSCR_IPDIV_OFFSET 9 -#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET) - -#define CCM_CSCR_OSC26MDIV (1 << 4) -#define CCM_CSCR_OSC26M (1 << 3) -#define CCM_CSCR_FPM (1 << 2) -#define CCM_CSCR_SPEN (1 << 1) -#define CCM_CSCR_MPEN 1 - - - -#define CCM_MPCTL0_CPLM (1 << 31) -#define CCM_MPCTL0_PD_OFFSET 26 -#define CCM_MPCTL0_PD_MASK (0xf << 26) -#define CCM_MPCTL0_MFD_OFFSET 16 -#define CCM_MPCTL0_MFD_MASK (0x3ff << 16) -#define CCM_MPCTL0_MFI_OFFSET 10 -#define CCM_MPCTL0_MFI_MASK (0xf << 10) -#define CCM_MPCTL0_MFN_OFFSET 0 -#define CCM_MPCTL0_MFN_MASK 0x3ff - -#define CCM_MPCTL1_LF (1 << 15) -#define CCM_MPCTL1_BRMO (1 << 6) - -#define CCM_SPCTL0_CPLM (1 << 31) -#define CCM_SPCTL0_PD_OFFSET 26 -#define CCM_SPCTL0_PD_MASK (0xf << 26) -#define CCM_SPCTL0_MFD_OFFSET 16 -#define CCM_SPCTL0_MFD_MASK (0x3ff << 16) -#define CCM_SPCTL0_MFI_OFFSET 10 -#define CCM_SPCTL0_MFI_MASK (0xf << 10) -#define CCM_SPCTL0_MFN_OFFSET 0 -#define CCM_SPCTL0_MFN_MASK 0x3ff - -#define CCM_SPCTL1_LF (1 << 15) -#define CCM_SPCTL1_BRMO (1 << 6) - -#define CCM_OSC26MCTL_PEAK_OFFSET 16 -#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16) -#define CCM_OSC26MCTL_AGC_OFFSET 8 -#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8) -#define CCM_OSC26MCTL_ANATEST_OFFSET 0 -#define CCM_OSC26MCTL_ANATEST_MASK 0x3f - -#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 -#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) -#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 -#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) -#define CCM_PCDR0_NFCDIV_OFFSET 12 -#define CCM_PCDR0_NFCDIV_MASK (0xf << 12) -#define CCM_PCDR0_48MDIV_OFFSET 5 -#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET) -#define CCM_PCDR0_FIRIDIV_OFFSET 0 -#define CCM_PCDR0_FIRIDIV_MASK 0x1f -#define CCM_PCDR1_PERDIV4_OFFSET 24 -#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) -#define CCM_PCDR1_PERDIV3_OFFSET 16 -#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16) -#define CCM_PCDR1_PERDIV2_OFFSET 8 -#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8) -#define CCM_PCDR1_PERDIV1_OFFSET 0 -#define CCM_PCDR1_PERDIV1_MASK 0x3f - -#define CCM_PCCR_HCLK_CSI_OFFSET 31 -#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_DMA_OFFSET 30 -#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_BROM_OFFSET 28 -#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_EMMA_OFFSET 27 -#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_LCDC_OFFSET 26 -#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_SLCDC_OFFSET 25 -#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_USBOTG_OFFSET 24 -#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0 -#define CCM_PCCR_HCLK_BMI_OFFSET 23 -#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK) -#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0 -#define CCM_PCCR_PERCLK4_OFFSET 22 -#define CCM_PCCR_PERCLK4_REG CCM_PCCR0 -#define CCM_PCCR_SLCDC_OFFSET 21 -#define CCM_PCCR_SLCDC_REG CCM_PCCR0 -#define CCM_PCCR_FIRI_BAUD_OFFSET 20 -#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK) -#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0 -#define CCM_PCCR_NFC_OFFSET 19 -#define CCM_PCCR_NFC_REG CCM_PCCR0 -#define CCM_PCCR_LCDC_OFFSET 18 -#define CCM_PCCR_LCDC_REG CCM_PCCR0 -#define CCM_PCCR_SSI1_BAUD_OFFSET 17 -#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0 -#define CCM_PCCR_SSI2_BAUD_OFFSET 16 -#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0 -#define CCM_PCCR_EMMA_OFFSET 15 -#define CCM_PCCR_EMMA_REG CCM_PCCR0 -#define CCM_PCCR_USBOTG_OFFSET 14 -#define CCM_PCCR_USBOTG_REG CCM_PCCR0 -#define CCM_PCCR_DMA_OFFSET 13 -#define CCM_PCCR_DMA_REG CCM_PCCR0 -#define CCM_PCCR_I2C1_OFFSET 12 -#define CCM_PCCR_I2C1_REG CCM_PCCR0 -#define CCM_PCCR_GPIO_OFFSET 11 -#define CCM_PCCR_GPIO_REG CCM_PCCR0 -#define CCM_PCCR_SDHC2_OFFSET 10 -#define CCM_PCCR_SDHC2_REG CCM_PCCR0 -#define CCM_PCCR_SDHC1_OFFSET 9 -#define CCM_PCCR_SDHC1_REG CCM_PCCR0 -#define CCM_PCCR_FIRI_OFFSET 8 -#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK) -#define CCM_PCCR_FIRI_REG CCM_PCCR0 -#define CCM_PCCR_SSI2_IPG_OFFSET 7 -#define CCM_PCCR_SSI2_REG CCM_PCCR0 -#define CCM_PCCR_SSI1_IPG_OFFSET 6 -#define CCM_PCCR_SSI1_REG CCM_PCCR0 -#define CCM_PCCR_CSPI2_OFFSET 5 -#define CCM_PCCR_CSPI2_REG CCM_PCCR0 -#define CCM_PCCR_CSPI1_OFFSET 4 -#define CCM_PCCR_CSPI1_REG CCM_PCCR0 -#define CCM_PCCR_UART4_OFFSET 3 -#define CCM_PCCR_UART4_REG CCM_PCCR0 -#define CCM_PCCR_UART3_OFFSET 2 -#define CCM_PCCR_UART3_REG CCM_PCCR0 -#define CCM_PCCR_UART2_OFFSET 1 -#define CCM_PCCR_UART2_REG CCM_PCCR0 -#define CCM_PCCR_UART1_OFFSET 0 -#define CCM_PCCR_UART1_REG CCM_PCCR0 - -#define CCM_PCCR_OWIRE_OFFSET 31 -#define CCM_PCCR_OWIRE_REG CCM_PCCR1 -#define CCM_PCCR_KPP_OFFSET 30 -#define CCM_PCCR_KPP_REG CCM_PCCR1 -#define CCM_PCCR_RTC_OFFSET 29 -#define CCM_PCCR_RTC_REG CCM_PCCR1 -#define CCM_PCCR_PWM_OFFSET 28 -#define CCM_PCCR_PWM_REG CCM_PCCR1 -#define CCM_PCCR_GPT3_OFFSET 27 -#define CCM_PCCR_GPT3_REG CCM_PCCR1 -#define CCM_PCCR_GPT2_OFFSET 26 -#define CCM_PCCR_GPT2_REG CCM_PCCR1 -#define CCM_PCCR_GPT1_OFFSET 25 -#define CCM_PCCR_GPT1_REG CCM_PCCR1 -#define CCM_PCCR_WDT_OFFSET 24 -#define CCM_PCCR_WDT_REG CCM_PCCR1 -#define CCM_PCCR_CSPI3_OFFSET 23 -#define CCM_PCCR_CSPI3_REG CCM_PCCR1 - -#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET) -#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET) -#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET) -#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET) -#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET) -#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET) -#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET) -#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET) -#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET) -#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET) -#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET) -#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET) -#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET) -#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET) -#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET) -#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET) -#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET) -#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET) -#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET) -#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET) -#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET) -#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET) -#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET) -#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET) -#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET) -#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET) -#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET) -#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET) -#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET) -#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET) -#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET) -#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET) -#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET) -#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET) -#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET) -#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET) -#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET) - - -#define CCM_CCSR_32KSR (1 << 15) - -#define CCM_CCSR_CLKMODE1 (1 << 9) -#define CCM_CCSR_CLKMODE0 (1 << 8) - -#define CCM_CCSR_CLKOSEL_OFFSET 0 -#define CCM_CCSR_CLKOSEL_MASK 0x1f - -#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */ -#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ - -#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */ diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 3d398ce09b31..a4b809b82fa3 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c @@ -46,65 +46,31 @@ * - i.MX21: 2 channel * - i.MX27: 3 channel */ -static struct resource mxc_spi_resources0[] = { - { - .start = CSPI1_BASE_ADDR, - .end = CSPI1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI1, - .end = MXC_INT_CSPI1, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource mxc_spi_resources1[] = { - { - .start = CSPI2_BASE_ADDR, - .end = CSPI2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI2, - .end = MXC_INT_CSPI2, - .flags = IORESOURCE_IRQ, - }, -}; - -#ifdef CONFIG_MACH_MX27 -static struct resource mxc_spi_resources2[] = { - { - .start = CSPI3_BASE_ADDR, - .end = CSPI3_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_CSPI3, - .end = MXC_INT_CSPI3, - .flags = IORESOURCE_IRQ, - }, -}; -#endif - -struct platform_device mxc_spi_device0 = { - .name = "spi_imx", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_spi_resources0), - .resource = mxc_spi_resources0, -}; +#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_spi_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device mxc_spi_device ## n = { \ + .name = "spi_imx", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \ + .resource = mxc_spi_resources ## n, \ + } -struct platform_device mxc_spi_device1 = { - .name = "spi_imx", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_spi_resources1), - .resource = mxc_spi_resources1, -}; +DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1); +DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2); #ifdef CONFIG_MACH_MX27 -struct platform_device mxc_spi_device2 = { - .name = "spi_imx", - .id = 2, - .num_resources = ARRAY_SIZE(mxc_spi_resources2), - .resource = mxc_spi_resources2, -}; +DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3); #endif /* @@ -112,104 +78,34 @@ struct platform_device mxc_spi_device2 = { * - i.MX21: 3 timers * - i.MX27: 6 timers */ - -/* We use gpt0 as system timer, so do not add a device for this one */ - -static struct resource timer1_resources[] = { - { - .start = GPT2_BASE_ADDR, - .end = GPT2_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT2, - .end = MXC_INT_GPT2, - .flags = IORESOURCE_IRQ, +#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \ + static struct resource timer ## n ##_resources[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + } \ + }; \ + \ + struct platform_device mxc_gpt ## n = { \ + .name = "imx_gpt", \ + .id = n, \ + .num_resources = ARRAY_SIZE(timer ## n ## _resources), \ + .resource = timer ## n ## _resources, \ } -}; - -struct platform_device mxc_gpt1 = { - .name = "imx_gpt", - .id = 1, - .num_resources = ARRAY_SIZE(timer1_resources), - .resource = timer1_resources, -}; -static struct resource timer2_resources[] = { - { - .start = GPT3_BASE_ADDR, - .end = GPT3_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT3, - .end = MXC_INT_GPT3, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt2 = { - .name = "imx_gpt", - .id = 2, - .num_resources = ARRAY_SIZE(timer2_resources), - .resource = timer2_resources, -}; +/* We use gpt1 as system timer, so do not add a device for this one */ +DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2); +DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3); #ifdef CONFIG_MACH_MX27 -static struct resource timer3_resources[] = { - { - .start = GPT4_BASE_ADDR, - .end = GPT4_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT4, - .end = MXC_INT_GPT4, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt3 = { - .name = "imx_gpt", - .id = 3, - .num_resources = ARRAY_SIZE(timer3_resources), - .resource = timer3_resources, -}; - -static struct resource timer4_resources[] = { - { - .start = GPT5_BASE_ADDR, - .end = GPT5_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT5, - .end = MXC_INT_GPT5, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt4 = { - .name = "imx_gpt", - .id = 4, - .num_resources = ARRAY_SIZE(timer4_resources), - .resource = timer4_resources, -}; - -static struct resource timer5_resources[] = { - { - .start = GPT6_BASE_ADDR, - .end = GPT6_BASE_ADDR + 0x17, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_GPT6, - .end = MXC_INT_GPT6, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_gpt5 = { - .name = "imx_gpt", - .id = 5, - .num_resources = ARRAY_SIZE(timer5_resources), - .resource = timer5_resources, -}; +DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4); +DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); +DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); #endif /* @@ -220,9 +116,9 @@ struct platform_device mxc_gpt5 = { */ static struct resource mxc_wdt_resources[] = { { - .start = WDOG_BASE_ADDR, - .end = WDOG_BASE_ADDR + 0x30, - .flags = IORESOURCE_MEM, + .start = MX2x_WDOG_BASE_ADDR, + .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, }; @@ -235,8 +131,8 @@ struct platform_device mxc_wdt = { static struct resource mxc_w1_master_resources[] = { { - .start = OWIRE_BASE_ADDR, - .end = OWIRE_BASE_ADDR + SZ_4K - 1, + .start = MX2x_OWIRE_BASE_ADDR, + .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, }, }; @@ -248,24 +144,33 @@ struct platform_device mxc_w1_master_device = { .resource = mxc_w1_master_resources, }; -static struct resource mxc_nand_resources[] = { - { - .start = NFC_BASE_ADDR, - .end = NFC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_NANDFC, - .end = MXC_INT_NANDFC, - .flags = IORESOURCE_IRQ, - }, -}; +#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq) \ + static struct resource pfx ## _nand_resources[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, \ + }; \ + \ + struct platform_device pfx ## _nand_device = { \ + .name = "mxc_nand", \ + .id = 0, \ + .num_resources = ARRAY_SIZE(pfx ## _nand_resources), \ + .resource = pfx ## _nand_resources, \ + } -struct platform_device mxc_nand_device = { - .name = "mxc_nand", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_nand_resources), - .resource = mxc_nand_resources, -}; +#ifdef CONFIG_MACH_MX21 +DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC); +#endif + +#ifdef CONFIG_MACH_MX27 +DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC); +#endif /* * lcdc: @@ -275,12 +180,12 @@ struct platform_device mxc_nand_device = { */ static struct resource mxc_fb[] = { { - .start = LCDC_BASE_ADDR, - .end = LCDC_BASE_ADDR + 0xFFF, + .start = MX2x_LCDC_BASE_ADDR, + .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_LCDC, - .end = MXC_INT_LCDC, + .start = MX2x_INT_LCDC, + .end = MX2x_INT_LCDC, .flags = IORESOURCE_IRQ, } }; @@ -299,13 +204,13 @@ struct platform_device mxc_fb_device = { #ifdef CONFIG_MACH_MX27 static struct resource mxc_fec_resources[] = { { - .start = FEC_BASE_ADDR, - .end = FEC_BASE_ADDR + 0xfff, - .flags = IORESOURCE_MEM, + .start = MX27_FEC_BASE_ADDR, + .end = MX27_FEC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_FEC, - .end = MXC_INT_FEC, - .flags = IORESOURCE_IRQ, + .start = MX27_INT_FEC, + .end = MX27_INT_FEC, + .flags = IORESOURCE_IRQ, }, }; @@ -317,55 +222,41 @@ struct platform_device mxc_fec_device = { }; #endif -static struct resource mxc_i2c_1_resources[] = { - { - .start = I2C_BASE_ADDR, - .end = I2C_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C, - .end = MXC_INT_I2C, - .flags = IORESOURCE_IRQ, +#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \ + static struct resource mxc_i2c_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + } \ + }; \ + \ + struct platform_device mxc_i2c_device ## n = { \ + .name = "imx-i2c", \ + .id = n, \ + .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \ + .resource = mxc_i2c_resources ## n, \ } -}; -struct platform_device mxc_i2c_device0 = { - .name = "imx-i2c", - .id = 0, - .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), - .resource = mxc_i2c_1_resources, -}; +DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C); #ifdef CONFIG_MACH_MX27 -static struct resource mxc_i2c_2_resources[] = { - { - .start = I2C2_BASE_ADDR, - .end = I2C2_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_I2C2, - .end = MXC_INT_I2C2, - .flags = IORESOURCE_IRQ, - } -}; - -struct platform_device mxc_i2c_device1 = { - .name = "imx-i2c", - .id = 1, - .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), - .resource = mxc_i2c_2_resources, -}; +DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2); #endif static struct resource mxc_pwm_resources[] = { { - .start = PWM_BASE_ADDR, - .end = PWM_BASE_ADDR + 0x0fff, - .flags = IORESOURCE_MEM, + .start = MX2x_PWM_BASE_ADDR, + .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_PWM, - .end = MXC_INT_PWM, - .flags = IORESOURCE_IRQ, + .start = MX2x_INT_PWM, + .end = MX2x_INT_PWM, + .flags = IORESOURCE_IRQ, } }; @@ -379,74 +270,49 @@ struct platform_device mxc_pwm_device = { /* * Resource definition for the MXC SDHC */ -static struct resource mxc_sdhc1_resources[] = { - { - .start = SDHC1_BASE_ADDR, - .end = SDHC1_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SDHC1, - .end = MXC_INT_SDHC1, - .flags = IORESOURCE_IRQ, - }, { - .start = DMA_REQ_SDHC1, - .end = DMA_REQ_SDHC1, - .flags = IORESOURCE_DMA, - }, -}; - -static u64 mxc_sdhc1_dmamask = 0xffffffffUL; - -struct platform_device mxc_sdhc_device0 = { - .name = "mxc-mmc", - .id = 0, - .dev = { - .dma_mask = &mxc_sdhc1_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), - .resource = mxc_sdhc1_resources, -}; - -static struct resource mxc_sdhc2_resources[] = { - { - .start = SDHC2_BASE_ADDR, - .end = SDHC2_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SDHC2, - .end = MXC_INT_SDHC2, - .flags = IORESOURCE_IRQ, - }, { - .start = DMA_REQ_SDHC2, - .end = DMA_REQ_SDHC2, - .flags = IORESOURCE_DMA, - }, -}; +#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \ + static struct resource mxc_sdhc_resources ## n[] = { \ + { \ + .start = baseaddr, \ + .end = baseaddr + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = irq, \ + .end = irq, \ + .flags = IORESOURCE_IRQ, \ + }, { \ + .start = dmareq, \ + .end = dmareq, \ + .flags = IORESOURCE_DMA, \ + }, \ + }; \ + \ + static u64 mxc_sdhc ## n ## _dmamask = 0xffffffffUL; \ + \ + struct platform_device mxc_sdhc_device ## n = { \ + .name = "mxc-mmc", \ + .id = n, \ + .dev = { \ + .dma_mask = &mxc_sdhc ## n ## _dmamask, \ + .coherent_dma_mask = 0xffffffff, \ + }, \ + .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \ + .resource = mxc_sdhc_resources ## n, \ + } -static u64 mxc_sdhc2_dmamask = 0xffffffffUL; - -struct platform_device mxc_sdhc_device1 = { - .name = "mxc-mmc", - .id = 1, - .dev = { - .dma_mask = &mxc_sdhc2_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(mxc_sdhc2_resources), - .resource = mxc_sdhc2_resources, -}; +DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1); +DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2); #ifdef CONFIG_MACH_MX27 static struct resource otg_resources[] = { { - .start = OTG_BASE_ADDR, - .end = OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, + .start = MX27_USBOTG_BASE_ADDR, + .end = MX27_USBOTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB3, - .end = MXC_INT_USB3, - .flags = IORESOURCE_IRQ, + .start = MX27_INT_USB3, + .end = MX27_INT_USB3, + .flags = IORESOURCE_IRQ, }, }; @@ -454,14 +320,14 @@ static u64 otg_dmamask = 0xffffffffUL; /* OTG gadget device */ struct platform_device mxc_otg_udc_device = { - .name = "fsl-usb2-udc", - .id = -1, - .dev = { - .dma_mask = &otg_dmamask, - .coherent_dma_mask = 0xffffffffUL, + .name = "fsl-usb2-udc", + .id = -1, + .dev = { + .dma_mask = &otg_dmamask, + .coherent_dma_mask = 0xffffffffUL, }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), + .resource = otg_resources, + .num_resources = ARRAY_SIZE(otg_resources), }; /* OTG host */ @@ -482,12 +348,12 @@ static u64 usbh1_dmamask = 0xffffffffUL; static struct resource mxc_usbh1_resources[] = { { - .start = OTG_BASE_ADDR + 0x200, - .end = OTG_BASE_ADDR + 0x3ff, + .start = MX27_USBOTG_BASE_ADDR + 0x200, + .end = MX27_USBOTG_BASE_ADDR + 0x3ff, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB1, - .end = MXC_INT_USB1, + .start = MX27_INT_USB1, + .end = MX27_INT_USB1, .flags = IORESOURCE_IRQ, }, }; @@ -508,12 +374,12 @@ static u64 usbh2_dmamask = 0xffffffffUL; static struct resource mxc_usbh2_resources[] = { { - .start = OTG_BASE_ADDR + 0x400, - .end = OTG_BASE_ADDR + 0x5ff, + .start = MX27_USBOTG_BASE_ADDR + 0x400, + .end = MX27_USBOTG_BASE_ADDR + 0x5ff, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_USB2, - .end = MXC_INT_USB2, + .start = MX27_INT_USB2, + .end = MX27_INT_USB2, .flags = IORESOURCE_IRQ, }, }; @@ -530,115 +396,88 @@ struct platform_device mxc_usbh2 = { }; #endif -static struct resource imx_ssi_resources0[] = { - { - .start = SSI1_BASE_ADDR, - .end = SSI1_BASE_ADDR + 0x6F, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SSI1, - .end = MXC_INT_SSI1, - .flags = IORESOURCE_IRQ, - }, { - .name = "tx0", - .start = DMA_REQ_SSI1_TX0, - .end = DMA_REQ_SSI1_TX0, - .flags = IORESOURCE_DMA, - }, { - .name = "rx0", - .start = DMA_REQ_SSI1_RX0, - .end = DMA_REQ_SSI1_RX0, - .flags = IORESOURCE_DMA, - }, { - .name = "tx1", - .start = DMA_REQ_SSI1_TX1, - .end = DMA_REQ_SSI1_TX1, - .flags = IORESOURCE_DMA, - }, { - .name = "rx1", - .start = DMA_REQ_SSI1_RX1, - .end = DMA_REQ_SSI1_RX1, - .flags = IORESOURCE_DMA, - }, -}; - -static struct resource imx_ssi_resources1[] = { - { - .start = SSI2_BASE_ADDR, - .end = SSI2_BASE_ADDR + 0x6F, - .flags = IORESOURCE_MEM, - }, { - .start = MXC_INT_SSI2, - .end = MXC_INT_SSI2, - .flags = IORESOURCE_IRQ, - }, { - .name = "tx0", - .start = DMA_REQ_SSI2_TX0, - .end = DMA_REQ_SSI2_TX0, - .flags = IORESOURCE_DMA, - }, { - .name = "rx0", - .start = DMA_REQ_SSI2_RX0, - .end = DMA_REQ_SSI2_RX0, - .flags = IORESOURCE_DMA, - }, { - .name = "tx1", - .start = DMA_REQ_SSI2_TX1, - .end = DMA_REQ_SSI2_TX1, - .flags = IORESOURCE_DMA, - }, { - .name = "rx1", - .start = DMA_REQ_SSI2_RX1, - .end = DMA_REQ_SSI2_RX1, - .flags = IORESOURCE_DMA, - }, -}; +#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \ + { \ + .name = _name, \ + .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \ + .flags = IORESOURCE_DMA, \ + } -struct platform_device imx_ssi_device0 = { - .name = "imx-ssi", - .id = 0, - .num_resources = ARRAY_SIZE(imx_ssi_resources0), - .resource = imx_ssi_resources0, -}; +#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \ + static struct resource imx_ssi_resources ## n[] = { \ + { \ + .start = MX2x_SSI ## ssin ## _BASE_ADDR, \ + .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \ + .flags = IORESOURCE_MEM, \ + }, { \ + .start = MX2x_INT_SSI1, \ + .end = MX2x_INT_SSI1, \ + .flags = IORESOURCE_IRQ, \ + }, \ + DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \ + DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \ + DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \ + DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \ + }; \ + \ + struct platform_device imx_ssi_device ## n = { \ + .name = "imx-ssi", \ + .id = n, \ + .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \ + .resource = imx_ssi_resources ## n, \ + } -struct platform_device imx_ssi_device1 = { - .name = "imx-ssi", - .id = 1, - .num_resources = ARRAY_SIZE(imx_ssi_resources1), - .resource = imx_ssi_resources1, -}; +DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); +DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1); /* GPIO port description */ -static struct mxc_gpio_port imx_gpio_ports[] = { - { - .chip.label = "gpio-0", - .irq = MXC_INT_GPIO, - .base = IO_ADDRESS(GPIO_BASE_ADDR), - .virtual_irq_start = MXC_GPIO_IRQ_START, - }, { - .chip.label = "gpio-1", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), - .virtual_irq_start = MXC_GPIO_IRQ_START + 32, - }, { - .chip.label = "gpio-2", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), - .virtual_irq_start = MXC_GPIO_IRQ_START + 64, - }, { - .chip.label = "gpio-3", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), - .virtual_irq_start = MXC_GPIO_IRQ_START + 96, - }, { - .chip.label = "gpio-4", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), - .virtual_irq_start = MXC_GPIO_IRQ_START + 128, - }, { - .chip.label = "gpio-5", - .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), - .virtual_irq_start = MXC_GPIO_IRQ_START + 160, +#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ + { \ + .chip.label = "gpio-" #n, \ + .irq = _irq, \ + .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ + n * 0x100), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ } -}; + +#define DEFINE_MXC_GPIO_PORT(SOC, n) \ + { \ + .chip.label = "gpio-" #n, \ + .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \ + n * 0x100), \ + .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \ + } + +#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \ + static struct mxc_gpio_port pfx ## _gpio_ports[] = { \ + DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \ + DEFINE_MXC_GPIO_PORT(SOC, 1), \ + DEFINE_MXC_GPIO_PORT(SOC, 2), \ + DEFINE_MXC_GPIO_PORT(SOC, 3), \ + DEFINE_MXC_GPIO_PORT(SOC, 4), \ + DEFINE_MXC_GPIO_PORT(SOC, 5), \ + } + +#ifdef CONFIG_MACH_MX21 +DEFINE_MXC_GPIO_PORTS(MX21, imx21); +#endif + +#ifdef CONFIG_MACH_MX27 +DEFINE_MXC_GPIO_PORTS(MX27, imx27); +#endif int __init mxc_register_gpios(void) { - return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) + return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports)); + else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); + else +#endif + return 0; } diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index 97306aa18f1c..f15df2aaae4d 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h @@ -1,8 +1,10 @@ extern struct platform_device mxc_gpt1; extern struct platform_device mxc_gpt2; +#ifdef CONFIG_MACH_MX27 extern struct platform_device mxc_gpt3; extern struct platform_device mxc_gpt4; extern struct platform_device mxc_gpt5; +#endif extern struct platform_device mxc_wdt; extern struct platform_device mxc_uart_device0; extern struct platform_device mxc_uart_device1; @@ -11,12 +13,19 @@ extern struct platform_device mxc_uart_device3; extern struct platform_device mxc_uart_device4; extern struct platform_device mxc_uart_device5; extern struct platform_device mxc_w1_master_device; -extern struct platform_device mxc_nand_device; +#ifdef CONFIG_MACH_MX21 +extern struct platform_device imx21_nand_device; +#endif +#ifdef CONFIG_MACH_MX27 +extern struct platform_device imx27_nand_device; +#endif extern struct platform_device mxc_fb_device; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_pwm_device; extern struct platform_device mxc_i2c_device0; +#ifdef CONFIG_MACH_MX27 extern struct platform_device mxc_i2c_device1; +#endif extern struct platform_device mxc_sdhc_device0; extern struct platform_device mxc_sdhc_device1; extern struct platform_device mxc_otg_udc_device; @@ -25,6 +34,8 @@ extern struct platform_device mxc_usbh1; extern struct platform_device mxc_usbh2; extern struct platform_device mxc_spi_device0; extern struct platform_device mxc_spi_device1; +#ifdef CONFIG_MACH_MX27 extern struct platform_device mxc_spi_device2; +#endif extern struct platform_device imx_ssi_device0; extern struct platform_device imx_ssi_device1; diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c index 7382b6d27ee1..f3b169d5245f 100644 --- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c +++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c @@ -28,7 +28,7 @@ #include <asm/mach/arch.h> #include <mach/common.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/imxfb.h> #include <mach/hardware.h> #include <mach/mmc.h> diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c index 7b187606682c..1f616dcaabc9 100644 --- a/arch/arm/mach-mx2/eukrea_cpuimx27.c +++ b/arch/arm/mach-mx2/mach-cpuimx27.c @@ -36,7 +36,7 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/i2c.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/imx-uart.h> #include <mach/mxc_nand.h> @@ -142,28 +142,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = { #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) static struct plat_serial8250_port serial_platform_data[] = { { - .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000), + .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000), .irq = IRQ_GPIOB(23), .uartclk = 14745600, .regshift = 1, .iotype = UPIO_MEM, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { - .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000), + .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000), .irq = IRQ_GPIOB(22), .uartclk = 14745600, .regshift = 1, .iotype = UPIO_MEM, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { - .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000), + .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000), .irq = IRQ_GPIOB(27), .uartclk = 14745600, .regshift = 1, .iotype = UPIO_MEM, .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP, }, { - .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000), + .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000), .irq = IRQ_GPIOB(30), .uartclk = 14745600, .regshift = 1, @@ -189,7 +189,8 @@ static void __init eukrea_cpuimx27_init(void) mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); - mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info); + mxc_register_device(&imx27_nand_device, + &eukrea_cpuimx27_nand_board_info); i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); @@ -224,9 +225,9 @@ static struct sys_timer eukrea_cpuimx27_timer = { }; MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = eukrea_cpuimx27_init, diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c index 82ea227ea0cf..b5710bf18b96 100644 --- a/arch/arm/mach-mx2/mx27lite.c +++ b/arch/arm/mach-mx2/mach-imx27lite.c @@ -27,7 +27,7 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/board-mx27lite.h> #include "devices.h" @@ -85,9 +85,9 @@ static struct sys_timer mx27lite_timer = { }; MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = mx27lite_init, diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c index cf5f77cbc2f1..113e58d7cb40 100644 --- a/arch/arm/mach-mx2/mx21ads.c +++ b/arch/arm/mach-mx2/mach-mx21ads.c @@ -30,7 +30,7 @@ #include <asm/mach/map.h> #include <mach/imx-uart.h> #include <mach/imxfb.h> -#include <mach/iomux.h> +#include <mach/iomux-mx21.h> #include <mach/mxc_nand.h> #include <mach/mmc.h> #include <mach/board-mx21ads.h> @@ -118,8 +118,8 @@ static struct physmap_flash_data mx21ads_flash_data = { }; static struct resource mx21ads_flash_resource = { - .start = CS0_BASE_ADDR, - .end = CS0_BASE_ADDR + 0x02000000 - 1, + .start = MX21_CS0_BASE_ADDR, + .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1, .flags = IORESOURCE_MEM, }; @@ -242,7 +242,7 @@ static struct map_desc mx21ads_io_desc[] __initdata = { */ { .virtual = MX21ADS_MMIO_BASE_ADDR, - .pfn = __phys_to_pfn(CS1_BASE_ADDR), + .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR), .length = MX21ADS_MMIO_SIZE, .type = MT_DEVICE, }, @@ -268,7 +268,7 @@ static void __init mx21ads_board_init(void) mxc_register_device(&mxc_uart_device3, &uart_pdata); mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); - mxc_register_device(&mxc_nand_device, &mx21ads_nand_board_info); + mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info); platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } @@ -284,9 +284,9 @@ static struct sys_timer mx21ads_timer = { MACHINE_START(MX21ADS, "Freescale i.MX21ADS") /* maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX21_AIPI_BASE_ADDR, + .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX21_PHYS_OFFSET + 0x100, .map_io = mx21ads_map_io, .init_irq = mx21_init_irq, .init_machine = mx21ads_board_init, diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mach-mx27_3ds.c index 6761d1b79e43..b2f4e0db3fb3 100644 --- a/arch/arm/mach-mx2/mx27pdk.c +++ b/arch/arm/mach-mx2/mach-mx27_3ds.c @@ -26,7 +26,7 @@ #include <mach/hardware.h> #include <mach/common.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/board-mx27pdk.h> #include "devices.h" @@ -85,9 +85,9 @@ static struct sys_timer mx27pdk_timer = { MACHINE_START(MX27_3DS, "Freescale MX27PDK") /* maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = mx27pdk_init, diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c index 83e412b713e6..6ce323669e58 100644 --- a/arch/arm/mach-mx2/mx27ads.c +++ b/arch/arm/mach-mx2/mach-mx27ads.c @@ -33,7 +33,7 @@ #include <asm/mach/map.h> #include <mach/gpio.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/board-mx27ads.h> #include <mach/mxc_nand.h> #include <mach/i2c.h> @@ -290,7 +290,7 @@ static void __init mx27ads_board_init(void) mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); - mxc_register_device(&mxc_nand_device, &mx27ads_nand_board_info); + mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, mx27ads_i2c_devices, @@ -320,7 +320,7 @@ static struct sys_timer mx27ads_timer = { static struct map_desc mx27ads_io_desc[] __initdata = { { .virtual = PBC_BASE_ADDRESS, - .pfn = __phys_to_pfn(CS4_BASE_ADDR), + .pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR), .length = SZ_1M, .type = MT_DEVICE, }, @@ -334,9 +334,9 @@ static void __init mx27ads_map_io(void) MACHINE_START(MX27ADS, "Freescale i.MX27ADS") /* maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27ads_map_io, .init_irq = mx27_init_irq, .init_machine = mx27ads_board_init, diff --git a/arch/arm/mach-mx2/mxt_td60.c b/arch/arm/mach-mx2/mach-mxt_td60.c index 8bcc1a5b8829..bc3855992677 100644 --- a/arch/arm/mach-mx2/mxt_td60.c +++ b/arch/arm/mach-mx2/mach-mxt_td60.c @@ -33,7 +33,7 @@ #include <asm/mach/map.h> #include <linux/gpio.h> #include <mach/imx-uart.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/mxc_nand.h> #include <mach/i2c.h> #include <linux/i2c/pca953x.h> @@ -257,7 +257,7 @@ static void __init mxt_td60_board_init(void) mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); - mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info); + mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info); i2c_register_board_info(0, mxt_td60_i2c_devices, ARRAY_SIZE(mxt_td60_i2c_devices)); @@ -284,9 +284,9 @@ static struct sys_timer mxt_td60_timer = { MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") /* maintainer: Maxtrack Industrial */ - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = mxt_td60_board_init, diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/mach-pca100.c index aea3d340d2e1..778fff230918 100644 --- a/arch/arm/mach-mx2/pca100.c +++ b/arch/arm/mach-mx2/mach-pca100.c @@ -25,25 +25,36 @@ #include <linux/spi/spi.h> #include <linux/spi/eeprom.h> #include <linux/irq.h> +#include <linux/delay.h> #include <linux/gpio.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/fsl_devices.h> #include <asm/mach/arch.h> #include <asm/mach-types.h> #include <mach/common.h> #include <mach/hardware.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/i2c.h> #include <asm/mach/time.h> #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) #include <mach/spi.h> #endif #include <mach/imx-uart.h> +#include <mach/audmux.h> +#include <mach/ssi.h> #include <mach/mxc_nand.h> #include <mach/irqs.h> #include <mach/mmc.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> #include "devices.h" +#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) +#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) + static int pca100_pins[] = { /* UART1 */ PE12_PF_UART1_TXD, @@ -92,6 +103,34 @@ static int pca100_pins[] = { PD29_PF_CSPI1_SCLK, PD30_PF_CSPI1_MISO, PD31_PF_CSPI1_MOSI, + /* OTG */ + OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, + PC7_PF_USBOTG_DATA5, + PC8_PF_USBOTG_DATA6, + PC9_PF_USBOTG_DATA0, + PC10_PF_USBOTG_DATA2, + PC11_PF_USBOTG_DATA1, + PC12_PF_USBOTG_DATA4, + PC13_PF_USBOTG_DATA3, + PE0_PF_USBOTG_NXT, + PE1_PF_USBOTG_STP, + PE2_PF_USBOTG_DIR, + PE24_PF_USBOTG_CLK, + PE25_PF_USBOTG_DATA7, + /* USBH2 */ + USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT, + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, }; static struct imxuart_platform_data uart_pdata = { @@ -157,6 +196,37 @@ static struct spi_imx_master pca100_spi_0_data = { }; #endif +static void pca100_ac97_warm_reset(struct snd_ac97 *ac97) +{ + mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); + gpio_set_value(GPIO_PORTC + 20, 1); + udelay(2); + gpio_set_value(GPIO_PORTC + 20, 0); + mxc_gpio_mode(PC20_PF_SSI1_FS); + msleep(2); +} + +static void pca100_ac97_cold_reset(struct snd_ac97 *ac97) +{ + mxc_gpio_mode(GPIO_PORTC | 20 | GPIO_GPIO | GPIO_OUT); /* FS */ + gpio_set_value(GPIO_PORTC + 20, 0); + mxc_gpio_mode(GPIO_PORTC | 22 | GPIO_GPIO | GPIO_OUT); /* TX */ + gpio_set_value(GPIO_PORTC + 22, 0); + mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_OUT); /* reset */ + gpio_set_value(GPIO_PORTC + 28, 0); + udelay(10); + gpio_set_value(GPIO_PORTC + 28, 1); + mxc_gpio_mode(PC20_PF_SSI1_FS); + mxc_gpio_mode(PC22_PF_SSI1_TXD); + msleep(2); +} + +static struct imx_ssi_platform_data pca100_ssi_pdata = { + .ac97_reset = pca100_ac97_cold_reset, + .ac97_warm_reset = pca100_ac97_warm_reset, + .flags = IMX_SSI_USE_AC97, +}; + static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data) { @@ -182,21 +252,79 @@ static struct imxmmc_platform_data sdhc_pdata = { .exit = pca100_sdhc2_exit, }; +static int otg_phy_init(struct platform_device *pdev) +{ + gpio_set_value(OTG_PHY_CS_GPIO, 0); + return 0; +} + +static struct mxc_usbh_platform_data otg_pdata = { + .init = otg_phy_init, + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static int usbh2_phy_init(struct platform_device *pdev) +{ + gpio_set_value(USBH2_PHY_CS_GPIO, 0); + return 0; +} + +static struct mxc_usbh_platform_data usbh2_pdata = { + .init = usbh2_phy_init, + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + +static int otg_mode_host; + +static int __init pca100_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", pca100_otg_mode); + static void __init pca100_init(void) { int ret; + /* SSI unit */ + mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0, + MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */ + MXC_AUDMUX_V1_PCR_TFCSEL(3) | + MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */ + MXC_AUDMUX_V1_PCR_RXDSEL(3)); + mxc_audmux_v1_configure_port(3, + MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */ + MXC_AUDMUX_V1_PCR_TFCSEL(0) | + MXC_AUDMUX_V1_PCR_TFSDIR | + MXC_AUDMUX_V1_PCR_RXDSEL(0)); + ret = mxc_gpio_setup_multiple_pins(pca100_pins, ARRAY_SIZE(pca100_pins), "PCA100"); if (ret) printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); + mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata); + mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN); mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); - mxc_register_device(&mxc_nand_device, &pca100_nand_board_info); + mxc_register_device(&imx27_nand_device, &pca100_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pca100_i2c_devices, @@ -220,6 +348,29 @@ static void __init pca100_init(void) mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data); #endif + gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs"); + gpio_direction_output(OTG_PHY_CS_GPIO, 1); + gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs"); + gpio_direction_output(USBH2_PHY_CS_GPIO, 1); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_usbh2, &usbh2_pdata); +#endif + if (!otg_mode_host) { + gpio_set_value(OTG_PHY_CS_GPIO, 0); + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + } + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); } @@ -233,9 +384,9 @@ static struct sys_timer pca100_timer = { }; MACHINE_START(PCA100, "phyCARD-i.MX27") - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = pca100_init, diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c index 906d59b0a7aa..035fbe046ec0 100644 --- a/arch/arm/mach-mx2/pcm038.c +++ b/arch/arm/mach-mx2/mach-pcm038.c @@ -36,10 +36,12 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/i2c.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/imx-uart.h> #include <mach/mxc_nand.h> #include <mach/spi.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> #include "devices.h" @@ -96,6 +98,19 @@ static int pcm038_pins[] = { PC17_PF_SSI4_RXD, PC18_PF_SSI4_TXD, PC19_PF_SSI4_CLK, + /* USB host */ + PA0_PF_USBH2_CLK, + PA1_PF_USBH2_DIR, + PA2_PF_USBH2_DATA7, + PA3_PF_USBH2_NXT, + PA4_PF_USBH2_STP, + PD19_AF_USBH2_DATA4, + PD20_AF_USBH2_DATA3, + PD21_AF_USBH2_DATA6, + PD22_AF_USBH2_DATA0, + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, }; /* @@ -108,8 +123,8 @@ static struct platdata_mtd_ram pcm038_sram_data = { }; static struct resource pcm038_sram_resource = { - .start = CS1_BASE_ADDR, - .end = CS1_BASE_ADDR + 512 * 1024 - 1, + .start = MX27_CS1_BASE_ADDR, + .end = MX27_CS1_BASE_ADDR + 512 * 1024 - 1, .flags = IORESOURCE_MEM, }; @@ -173,9 +188,7 @@ static struct platform_device *platform_devices[] __initdata = { * setup other stuffs to access the sram. */ static void __init pcm038_init_sram(void) { - __raw_writel(0x0000d843, CSCR_U(1)); - __raw_writel(0x22252521, CSCR_L(1)); - __raw_writel(0x22220a00, CSCR_A(1)); + mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00); } static struct imxi2c_platform_data pcm038_i2c_1_data = { @@ -279,6 +292,11 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = { } }; +static struct mxc_usbh_platform_data usbh2_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, +}; + static void __init pcm038_init(void) { mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins), @@ -291,7 +309,7 @@ static void __init pcm038_init(void) mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); mxc_gpio_mode(PE16_AF_OWIRE); - mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); + mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info); /* only the i2c master 1 is used on this CPU card */ i2c_register_board_info(1, pcm038_i2c_devices, @@ -311,6 +329,8 @@ static void __init pcm038_init(void) spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); + mxc_register_device(&mxc_usbh2, &usbh2_pdata); + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); #ifdef CONFIG_MACH_PCM970_BASEBOARD @@ -328,9 +348,9 @@ static struct sys_timer pcm038_timer = { }; MACHINE_START(PCM038, "phyCORE-i.MX27") - .phys_io = AIPI_BASE_ADDR, - .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX27_AIPI_BASE_ADDR, + .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX27_PHYS_OFFSET + 0x100, .map_io = mx27_map_io, .init_irq = mx27_init_irq, .init_machine = pcm038_init, diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-mx2/mm-imx21.c new file mode 100644 index 000000000000..64134314d012 --- /dev/null +++ b/arch/arm/mach-mx2/mm-imx21.c @@ -0,0 +1,83 @@ +/* + * arch/arm/mach-mx2/mm-imx21.c + * + * Copyright (C) 2008 Juergen Beisert ([email protected]) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <linux/mm.h> +#include <linux/init.h> +#include <mach/hardware.h> +#include <mach/common.h> +#include <asm/pgtable.h> +#include <asm/mach/map.h> + +/* MX21 memory map definition */ +static struct map_desc imx21_io_desc[] __initdata = { + /* + * this fixed mapping covers: + * - AIPI1 + * - AIPI2 + * - AITC + * - ROM Patch + * - and some reserved space + */ + { + .virtual = MX21_AIPI_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR), + .length = MX21_AIPI_SIZE, + .type = MT_DEVICE + }, + /* + * this fixed mapping covers: + * - CSI + * - ATA + */ + { + .virtual = MX21_SAHB1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR), + .length = MX21_SAHB1_SIZE, + .type = MT_DEVICE + }, + /* + * this fixed mapping covers: + * - EMI + */ + { + .virtual = MX21_X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR), + .length = MX21_X_MEMC_SIZE, + .type = MT_DEVICE + }, +}; + +/* + * Initialize the memory map. It is called during the + * system startup to create static physical to virtual + * memory map for the IO modules. + */ +void __init mx21_map_io(void) +{ + mxc_set_cpu_type(MXC_CPU_MX21); + mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR)); + + iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc)); +} + +void __init mx21_init_irq(void) +{ + mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR)); +} diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/mm-imx27.c index ae8f759134d1..3366ed44cfd5 100644 --- a/arch/arm/mach-mx2/generic.c +++ b/arch/arm/mach-mx2/mm-imx27.c @@ -1,5 +1,5 @@ /* - * generic.c + * arch/arm/mach-mx2/mm-imx27.c * * Copyright (C) 2008 Juergen Beisert ([email protected]) * @@ -26,7 +26,7 @@ #include <asm/mach/map.h> /* MX27 memory map definition */ -static struct map_desc mxc_io_desc[] __initdata = { +static struct map_desc imx27_io_desc[] __initdata = { /* * this fixed mapping covers: * - AIPI1 @@ -36,9 +36,9 @@ static struct map_desc mxc_io_desc[] __initdata = { * - and some reserved space */ { - .virtual = AIPI_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(AIPI_BASE_ADDR), - .length = AIPI_SIZE, + .virtual = MX27_AIPI_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR), + .length = MX27_AIPI_SIZE, .type = MT_DEVICE }, /* @@ -47,9 +47,9 @@ static struct map_desc mxc_io_desc[] __initdata = { * - ATA */ { - .virtual = SAHB1_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(SAHB1_BASE_ADDR), - .length = SAHB1_SIZE, + .virtual = MX27_SAHB1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR), + .length = MX27_SAHB1_SIZE, .type = MT_DEVICE }, /* @@ -57,11 +57,11 @@ static struct map_desc mxc_io_desc[] __initdata = { * - EMI */ { - .virtual = X_MEMC_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR), - .length = X_MEMC_SIZE, + .virtual = MX27_X_MEMC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR), + .length = MX27_X_MEMC_SIZE, .type = MT_DEVICE - } + }, }; /* @@ -69,29 +69,15 @@ static struct map_desc mxc_io_desc[] __initdata = { * system startup to create static physical to virtual * memory map for the IO modules. */ -void __init mx21_map_io(void) -{ - mxc_set_cpu_type(MXC_CPU_MX21); - mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); - - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); -} - void __init mx27_map_io(void) { mxc_set_cpu_type(MXC_CPU_MX27); - mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); + mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); - iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); + iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc)); } void __init mx27_init_irq(void) { - mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); + mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); } - -void __init mx21_init_irq(void) -{ - mx27_init_irq(); -} - diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c index 3cb7f457e5d0..4aafd5b8b85b 100644 --- a/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/arch/arm/mach-mx2/pcm970-baseboard.c @@ -24,7 +24,7 @@ #include <asm/mach/arch.h> #include <mach/common.h> -#include <mach/iomux.h> +#include <mach/iomux-mx27.h> #include <mach/imxfb.h> #include <mach/hardware.h> #include <mach/mmc.h> @@ -190,8 +190,8 @@ static struct imx_fb_platform_data pcm038_fb_data = { static struct resource pcm970_sja1000_resources[] = { { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 0x100 - 1, + .start = MX27_CS4_BASE_ADDR, + .end = MX27_CS4_BASE_ADDR + 0x100 - 1, .flags = IORESOURCE_MEM, }, { .start = IRQ_GPIOE(19), diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c index 40a485cdc10e..1c0c835b2252 100644 --- a/arch/arm/mach-mx2/serial.c +++ b/arch/arm/mach-mx2/serial.c @@ -26,12 +26,12 @@ static struct resource uart0[] = { { - .start = UART1_BASE_ADDR, - .end = UART1_BASE_ADDR + 0x0B5, + .start = MX2x_UART1_BASE_ADDR, + .end = MX2x_UART1_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART1, - .end = MXC_INT_UART1, + .start = MX2x_INT_UART1, + .end = MX2x_INT_UART1, .flags = IORESOURCE_IRQ, }, }; @@ -45,12 +45,12 @@ struct platform_device mxc_uart_device0 = { static struct resource uart1[] = { { - .start = UART2_BASE_ADDR, - .end = UART2_BASE_ADDR + 0x0B5, + .start = MX2x_UART2_BASE_ADDR, + .end = MX2x_UART2_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART2, - .end = MXC_INT_UART2, + .start = MX2x_INT_UART2, + .end = MX2x_INT_UART2, .flags = IORESOURCE_IRQ, }, }; @@ -64,12 +64,12 @@ struct platform_device mxc_uart_device1 = { static struct resource uart2[] = { { - .start = UART3_BASE_ADDR, - .end = UART3_BASE_ADDR + 0x0B5, + .start = MX2x_UART3_BASE_ADDR, + .end = MX2x_UART3_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART3, - .end = MXC_INT_UART3, + .start = MX2x_INT_UART3, + .end = MX2x_INT_UART3, .flags = IORESOURCE_IRQ, }, }; @@ -83,12 +83,12 @@ struct platform_device mxc_uart_device2 = { static struct resource uart3[] = { { - .start = UART4_BASE_ADDR, - .end = UART4_BASE_ADDR + 0x0B5, + .start = MX2x_UART4_BASE_ADDR, + .end = MX2x_UART4_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART4, - .end = MXC_INT_UART4, + .start = MX2x_INT_UART4, + .end = MX2x_INT_UART4, .flags = IORESOURCE_IRQ, }, }; @@ -103,12 +103,12 @@ struct platform_device mxc_uart_device3 = { #ifdef CONFIG_MACH_MX27 static struct resource uart4[] = { { - .start = UART5_BASE_ADDR, - .end = UART5_BASE_ADDR + 0x0B5, + .start = MX27_UART5_BASE_ADDR, + .end = MX27_UART5_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART5, - .end = MXC_INT_UART5, + .start = MX27_INT_UART5, + .end = MX27_INT_UART5, .flags = IORESOURCE_IRQ, }, }; @@ -122,12 +122,12 @@ struct platform_device mxc_uart_device4 = { static struct resource uart5[] = { { - .start = UART6_BASE_ADDR, - .end = UART6_BASE_ADDR + 0x0B5, + .start = MX27_UART6_BASE_ADDR, + .end = MX27_UART6_BASE_ADDR + 0x0B5, .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_UART6, - .end = MXC_INT_UART6, + .start = MX27_INT_UART6, + .end = MX27_INT_UART6, .flags = IORESOURCE_IRQ, }, }; diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig index cc28f56eae80..54d217314ee9 100644 --- a/arch/arm/mach-mx25/Kconfig +++ b/arch/arm/mach-mx25/Kconfig @@ -3,7 +3,6 @@ if ARCH_MX25 comment "MX25 platforms:" config MACH_MX25_3DS - select ARCH_MXC_IOMUX_V3 bool "Support MX25PDK (3DS) Platform" endif diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile index fe23836a9f3d..10cebc5ced8c 100644 --- a/arch/arm/mach-mx25/Makefile +++ b/arch/arm/mach-mx25/Makefile @@ -1,3 +1,3 @@ obj-y := mm.o devices.o obj-$(CONFIG_ARCH_MX25) += clock.o -obj-$(CONFIG_MACH_MX25_3DS) += mx25pdk.o +obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25pdk.o diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c index 6acc88bcdc40..56bf958d8c34 100644 --- a/arch/arm/mach-mx25/clock.c +++ b/arch/arm/mach-mx25/clock.c @@ -124,6 +124,11 @@ static unsigned long get_rate_gpt(struct clk *clk) return get_rate_per(5); } +static unsigned long get_rate_lcdc(struct clk *clk) +{ + return get_rate_per(7); +} + static unsigned long get_rate_otg(struct clk *clk) { return 48000000; /* FIXME */ @@ -167,6 +172,8 @@ DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); +DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); +DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk); DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk); @@ -182,6 +189,8 @@ DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL); DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL); DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk); +DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1, 8, get_rate_ipg, NULL, NULL); +DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk); #define _REGISTER_CLOCK(d, n, c) \ { \ @@ -214,6 +223,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk) _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk) _REGISTER_CLOCK("fec.0", NULL, fec_clk) + _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) + _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) }; int __init mx25_clocks_init(void) @@ -231,6 +242,9 @@ int __init mx25_clocks_init(void) __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1); __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2); + /* Clock source for lcdc is upll */ + __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64); + mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); return 0; diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index 9fdeea1c083b..3f4b8a0b5fac 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -438,3 +438,65 @@ struct platform_device mx25_fec_device = { .num_resources = ARRAY_SIZE(mx25_fec_resources), .resource = mx25_fec_resources, }; + +static struct resource mxc_nand_resources[] = { + { + .start = MX25_NFC_BASE_ADDR, + .end = MX25_NFC_BASE_ADDR + 0x1fff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_NANDFC, + .end = MX25_INT_NANDFC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_nand_device = { + .name = "mxc_nand", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_nand_resources), + .resource = mxc_nand_resources, +}; + +static struct resource mx25_rtc_resources[] = { + { + .start = MX25_DRYICE_BASE_ADDR, + .end = MX25_DRYICE_BASE_ADDR + 0x40, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_DRYICE, + .flags = IORESOURCE_IRQ + }, +}; + +struct platform_device mx25_rtc_device = { + .name = "imxdi_rtc", + .id = 0, + .num_resources = ARRAY_SIZE(mx25_rtc_resources), + .resource = mx25_rtc_resources, +}; + +static struct resource mx25_fb_resources[] = { + { + .start = MX25_LCDC_BASE_ADDR, + .end = MX25_LCDC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, + { + .start = MX25_INT_LCDC, + .end = MX25_INT_LCDC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mx25_fb_device = { + .name = "imx-fb", + .id = 0, + .resource = mx25_fb_resources, + .num_resources = ARRAY_SIZE(mx25_fb_resources), + .dev = { + .coherent_dma_mask = 0xFFFFFFFF, + }, +}; diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h index fe5420fcd11f..39560e13bc0d 100644 --- a/arch/arm/mach-mx25/devices.h +++ b/arch/arm/mach-mx25/devices.h @@ -18,3 +18,6 @@ extern struct platform_device mxc_i2c_device0; extern struct platform_device mxc_i2c_device1; extern struct platform_device mxc_i2c_device2; extern struct platform_device mx25_fec_device; +extern struct platform_device mxc_nand_device; +extern struct platform_device mx25_rtc_device; +extern struct platform_device mx25_fb_device; diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mach-mx25pdk.c index 6f06089246eb..83d74109e7d8 100644 --- a/arch/arm/mach-mx25/mx25pdk.c +++ b/arch/arm/mach-mx25/mach-mx25pdk.c @@ -35,8 +35,9 @@ #include <mach/imx-uart.h> #include <mach/mx25.h> #include <mach/mxc_nand.h> +#include <mach/imxfb.h> #include "devices.h" -#include <mach/iomux.h> +#include <mach/iomux-mx25.h> static struct imxuart_platform_data uart_pdata = { .flags = IMXUART_HAVE_RTSCTS, @@ -54,6 +55,31 @@ static struct pad_desc mx25pdk_pads[] = { MX25_PAD_FEC_TX_CLK__FEC_TX_CLK, MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */ MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */ + + /* LCD */ + MX25_PAD_LD0__LD0, + MX25_PAD_LD1__LD1, + MX25_PAD_LD2__LD2, + MX25_PAD_LD3__LD3, + MX25_PAD_LD4__LD4, + MX25_PAD_LD5__LD5, + MX25_PAD_LD6__LD6, + MX25_PAD_LD7__LD7, + MX25_PAD_LD8__LD8, + MX25_PAD_LD9__LD9, + MX25_PAD_LD10__LD10, + MX25_PAD_LD11__LD11, + MX25_PAD_LD12__LD12, + MX25_PAD_LD13__LD13, + MX25_PAD_LD14__LD14, + MX25_PAD_LD15__LD15, + MX25_PAD_GPIO_E__LD16, + MX25_PAD_GPIO_F__LD17, + MX25_PAD_HSYNC__HSYNC, + MX25_PAD_VSYNC__VSYNC, + MX25_PAD_LSCLK__LSCLK, + MX25_PAD_OE_ACD__OE_ACD, + MX25_PAD_CONTRAST__CONTRAST, }; static struct fec_platform_data mx25_fec_pdata = { @@ -77,6 +103,40 @@ static void __init mx25pdk_fec_reset(void) gpio_set_value(FEC_RESET_B_GPIO, 1); } +static struct mxc_nand_platform_data mx25pdk_nand_board_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, +}; + +static struct imx_fb_videomode mx25pdk_modes[] = { + { + .mode = { + .name = "CRT-VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39683, + .left_margin = 45, + .right_margin = 114, + .upper_margin = 33, + .lower_margin = 11, + .hsync_len = 1, + .vsync_len = 1, + }, + .bpp = 16, + .pcr = 0xFA208B80, + }, +}; + +static struct imx_fb_platform_data mx25pdk_fb_pdata = { + .mode = mx25pdk_modes, + .num_modes = ARRAY_SIZE(mx25pdk_modes), + .pwmr = 0x00A903FF, + .lscr1 = 0x00120300, + .dmacr = 0x00020010, +}; + static void __init mx25pdk_init(void) { mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, @@ -84,6 +144,9 @@ static void __init mx25pdk_init(void) mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_usbh2, NULL); + mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info); + mxc_register_device(&mx25_rtc_device, NULL); + mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); mx25pdk_fec_reset(); mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); @@ -102,7 +165,7 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = MX25_AIPS1_BASE_ADDR, .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MX25_PHYS_OFFSET + 0x100, .map_io = mx25_map_io, .init_irq = mx25_init_irq, .init_machine = mx25pdk_init, diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 28294416b0af..3872af1cf2c3 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig @@ -34,6 +34,7 @@ config MACH_MX31ADS_WM1133_EV1 config MACH_PCM037 bool "Support Phytec pcm037 (i.MX31) platforms" select ARCH_MX31 + select MXC_ULPI if USB_ULPI help Include support for Phytec pcm037 platform. This includes specific configurations for the board and its peripherals. @@ -86,6 +87,7 @@ config MACH_QONG config MACH_PCM043 bool "Support Phytec pcm043 (i.MX35) platforms" select ARCH_MX35 + select MXC_ULPI if USB_ULPI help Include support for Phytec pcm043 platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 93c7b296be6a..5d650fda5d5d 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile @@ -5,18 +5,22 @@ # Object file lists. obj-y := mm.o devices.o cpu.o -obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o +CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o obj-$(CONFIG_ARCH_MX35) += clock-imx35.o -obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o -obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o -obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o mx31lite-db.o -obj-$(CONFIG_MACH_PCM037) += pcm037.o -obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o -obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o -obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \ - mx31moboard-marxbot.o -obj-$(CONFIG_MACH_QONG) += qong.o -obj-$(CONFIG_MACH_PCM043) += pcm043.o -obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o -obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o -obj-$(CONFIG_MACH_KZM_ARM11_01) += kzmarm11.o +obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o +obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o +obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o +obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o +obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o +obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o +CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS +obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ + mx31moboard-marxbot.o mx31moboard-smartbot.o +obj-$(CONFIG_MACH_QONG) += mach-qong.o +obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o +obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o +obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35pdk.o +obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock-imx31.c index 27a318af0d20..d22a66f502a8 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock-imx31.c @@ -618,14 +618,15 @@ int __init mx31_clocks_init(unsigned long fref) mx31_read_cpu_rev(); - if (mx31_revision() >= CHIP_REV_2_0) { + if (mx31_revision() >= MX31_CHIP_REV_2_0) { reg = __raw_readl(MXC_CCM_PMCR1); /* No PLL restart on DVFS switch; enable auto EMI handshake */ reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; __raw_writel(reg, MXC_CCM_PMCR1); } - mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); + mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), + MX31_INT_GPT); return 0; } diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 7584b4c6c556..07d630ebc286 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c @@ -28,7 +28,7 @@ #include <mach/hardware.h> #include <mach/common.h> -#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) +#define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR) #define CCM_CCMR 0x00 #define CCM_PDR0 0x04 @@ -504,7 +504,8 @@ int __init mx35_clocks_init() __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); __raw_writel(0, CCM_BASE + CCM_CGR3); - mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT); + mxc_timer_init(&gpt_clk, + MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); return 0; } diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c index db828809c675..861afe0fe3ad 100644 --- a/arch/arm/mach-mx3/cpu.c +++ b/arch/arm/mach-mx3/cpu.c @@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void) u32 i, srev; /* read SREV register from IIM module */ - srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV); + srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMSREV)); for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) if (srev == mx31_cpu_type[i].srev) { diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h index adfa3627ad84..37a8a07beda3 100644 --- a/arch/arm/mach-mx3/crm_regs.h +++ b/arch/arm/mach-mx3/crm_regs.h @@ -24,7 +24,7 @@ #define CKIH_CLK_FREQ_27MHZ 27000000 #define CKIL_CLK_FREQ 32768 -#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) +#define MXC_CCM_BASE MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR) /* Register addresses */ #define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00) diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux-imx31.c index c66ccbcdc11b..a1d7fa5123dc 100644 --- a/arch/arm/mach-mx3/iomux.c +++ b/arch/arm/mach-mx3/iomux-imx31.c @@ -29,7 +29,7 @@ /* * IOMUX register (base) addresses */ -#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) +#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR) #define IOMUXINT_OBS1 (IOMUX_BASE + 0x000) #define IOMUXINT_OBS2 (IOMUX_BASE + 0x004) #define IOMUXGPR (IOMUX_BASE + 0x008) diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c index 54aab401dbdf..3d72b0b89705 100644 --- a/arch/arm/mach-mx3/armadillo5x0.c +++ b/arch/arm/mach-mx3/mach-armadillo5x0.c @@ -182,8 +182,8 @@ static struct physmap_flash_data armadillo5x0_nor_flash_pdata = { static struct resource armadillo5x0_nor_flash_resource = { .flags = IORESOURCE_MEM, - .start = CS0_BASE_ADDR, - .end = CS0_BASE_ADDR + SZ_64M - 1, + .start = MX31_CS0_BASE_ADDR, + .end = MX31_CS0_BASE_ADDR + SZ_64M - 1, }; static struct platform_device armadillo5x0_nor_flash = { @@ -311,8 +311,8 @@ static struct imxmmc_platform_data sdhc_pdata = { */ static struct resource armadillo5x0_smc911x_resources[] = { { - .start = CS3_BASE_ADDR, - .end = CS3_BASE_ADDR + SZ_32M - 1, + .start = MX31_CS3_BASE_ADDR, + .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, .flags = IORESOURCE_MEM, }, { .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0), @@ -406,9 +406,9 @@ static struct sys_timer armadillo5x0_timer = { MACHINE_START(ARMADILLO5X0, "Armadillo-500") /* Maintainer: Alberto Panizzo */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x00000100, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .timer = &armadillo5x0_timer, diff --git a/arch/arm/mach-mx3/kzmarm11.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c index 6fa99ce3008a..f085d5d1a6de 100644 --- a/arch/arm/mach-mx3/kzmarm11.c +++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c @@ -46,13 +46,18 @@ #include "devices.h" +#define KZM_ARM11_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX31_CS4) ?: \ + IMX_IO_ADDRESS(x, MX31_CS5) ?: \ + MX31_IO_ADDRESS(x)) + #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) /* * KZM-ARM11-01 has an external UART on FPGA */ static struct plat_serial8250_port serial_platform_data[] = { { - .membase = IO_ADDRESS(KZM_ARM11_16550), + .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550), .mapbase = KZM_ARM11_16550, .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), .irqflags = IRQ_TYPE_EDGE_RISING, @@ -102,9 +107,9 @@ static int __init kzm_init_ext_uart(void) /* * Unmask UART interrupt */ - tmp = __raw_readb(IO_ADDRESS(KZM_ARM11_CTL1)); + tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); tmp |= 0x2; - __raw_writeb(tmp, IO_ADDRESS(KZM_ARM11_CTL1)); + __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1)); return platform_device_register(&serial_device); } @@ -128,8 +133,8 @@ static struct smsc911x_platform_config kzm_smsc9118_config = { static struct resource kzm_smsc9118_resources[] = { { - .start = CS5_BASE_ADDR, - .end = CS5_BASE_ADDR + SZ_128K - 1, + .start = MX31_CS5_BASE_ADDR, + .end = MX31_CS5_BASE_ADDR + SZ_128K - 1, .flags = IORESOURCE_MEM, }, { @@ -222,15 +227,15 @@ static void __init kzm_board_init(void) */ static struct map_desc kzm_io_desc[] __initdata = { { - .virtual = CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS4_BASE_ADDR), - .length = CS4_SIZE, + .virtual = MX31_CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), + .length = MX31_CS4_SIZE, .type = MT_DEVICE }, { - .virtual = CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS5_BASE_ADDR), - .length = CS5_SIZE, + .virtual = MX31_CS5_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), + .length = MX31_CS5_SIZE, .type = MT_DEVICE }, }; @@ -258,9 +263,9 @@ static struct sys_timer kzm_timer = { * initialize __mach_desc_KZM_ARM11_01 data structure. */ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = kzm_map_io, .init_irq = mx31_init_irq, .init_machine = kzm_board_init, diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 18715f1aa7eb..b88c18ad7698 100644 --- a/arch/arm/mach-mx3/mx31pdk.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c @@ -211,9 +211,9 @@ static int __init mx31pdk_init_expio(void) */ static struct map_desc mx31pdk_io_desc[] __initdata = { { - .virtual = CS5_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS5_BASE_ADDR), - .length = CS5_SIZE, + .virtual = MX31_CS5_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), + .length = MX31_CS5_SIZE, .type = MT_DEVICE, }, }; @@ -256,9 +256,9 @@ static struct sys_timer mx31pdk_timer = { */ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") /* Maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31pdk_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c index 938c549767dc..b3d1a1895c20 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mach-mx31ads.c @@ -60,7 +60,7 @@ static struct plat_serial8250_port serial_platform_data[] = { { .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA), - .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTA), + .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA), .irq = EXPIO_INT_XUART_INTA, .uartclk = 14745600, .regshift = 0, @@ -68,7 +68,7 @@ static struct plat_serial8250_port serial_platform_data[] = { .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ, }, { .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB), - .mapbase = (unsigned long)(CS4_BASE_ADDR + PBC_SC16C652_UARTB), + .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB), .irq = EXPIO_INT_XUART_INTB, .uartclk = 14745600, .regshift = 0, @@ -309,12 +309,8 @@ static struct regulator_init_data ldo1_data = { }; static struct regulator_consumer_supply ldo2_consumers[] = { - { - .supply = "AVDD", - }, - { - .supply = "HPVDD", - }, + { .supply = "AVDD", .dev_name = "1-001a" }, + { .supply = "HPVDD", .dev_name = "1-001a" }, }; /* CODEC and SIM */ @@ -385,8 +381,6 @@ static struct wm8350_audio_platform_data imx32ads_wm8350_setup = { static int mx31_wm8350_init(struct wm8350 *wm8350) { - int i; - wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, @@ -422,10 +416,6 @@ static int mx31_wm8350_init(struct wm8350 *wm8350) WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, WM8350_GPIO_DEBOUNCE_OFF); - /* Fix up for our own supplies. */ - for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++) - ldo2_consumers[i].dev = wm8350->dev; - wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); @@ -493,14 +483,27 @@ static void mxc_init_i2c(void) } #endif +static unsigned int ssi_pins[] = { + MX31_PIN_SFS5__SFS5, + MX31_PIN_SCK5__SCK5, + MX31_PIN_SRXD5__SRXD5, + MX31_PIN_STXD5__STXD5, +}; + +static void mxc_init_audio(void) +{ + mxc_register_device(&imx_ssi_device0, NULL); + mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); +} + /*! * This structure defines static mappings for the i.MX31ADS board. */ static struct map_desc mx31ads_io_desc[] __initdata = { { - .virtual = CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS4_BASE_ADDR), - .length = CS4_SIZE / 2, + .virtual = MX31_CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), + .length = MX31_CS4_SIZE / 2, .type = MT_DEVICE }, }; @@ -528,6 +531,7 @@ static void __init mxc_board_init(void) mxc_init_extuart(); mxc_init_imx_uart(); mxc_init_i2c(); + mxc_init_audio(); } static void __init mx31ads_timer_init(void) @@ -545,9 +549,9 @@ static struct sys_timer mx31ads_timer = { */ MACHINE_START(MX31ADS, "Freescale MX31ADS") /* Maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31ads_map_io, .init_irq = mx31ads_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 9ce029f554b9..80847b04c063 100644 --- a/arch/arm/mach-mx3/mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c @@ -57,8 +57,8 @@ static struct resource smsc91x_resources[] = { { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 0xffff, + .start = MX31_CS4_BASE_ADDR, + .end = MX31_CS4_BASE_ADDR + 0xffff, .flags = IORESOURCE_MEM, }, { @@ -195,9 +195,9 @@ static struct sys_timer mx31lilly_timer = { }; MACHINE_START(LILLY1131, "INCO startec LILLY-1131") - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mx31lilly_board_init, diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c index 789b20d1730f..2b6d11400877 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mach-mx31lite.c @@ -82,8 +82,8 @@ static struct smsc911x_platform_config smsc911x_config = { static struct resource smsc911x_resources[] = { { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 0x100, + .start = MX31_CS4_BASE_ADDR, + .end = MX31_CS4_BASE_ADDR + 0x100, .flags = IORESOURCE_MEM, }, { .start = IOMUX_TO_IRQ(MX31_PIN_SFS6), @@ -214,9 +214,9 @@ static struct platform_device physmap_flash_device = { */ static struct map_desc mx31lite_io_desc[] __initdata = { { - .virtual = CS4_BASE_ADDR_VIRT, - .pfn = __phys_to_pfn(CS4_BASE_ADDR), - .length = CS4_SIZE, + .virtual = MX31_CS4_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), + .length = MX31_CS4_SIZE, .type = MT_DEVICE } }; @@ -287,9 +287,9 @@ struct sys_timer mx31lite_timer = { MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") /* Maintainer: Freescale Semiconductor, Inc. */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31lite_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index cfd605d078ec..a7dc5191bf5e 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c @@ -96,9 +96,6 @@ static unsigned int moboard_pins[] = { /* LEDs */ MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, - /* SEL */ - MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, - MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, /* SPI1 */ MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO, MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, @@ -352,9 +349,7 @@ static struct fsl_usb2_platform_data usb_pdata = { static int moboard_usbh2_hw_init(struct platform_device *pdev) { - int ret = gpio_request(USBH2_EN_B, "usbh2-en"); - if (ret) - return ret; + int ret; mxc_iomux_set_gpr(MUX_PGP_UH2, true); @@ -371,6 +366,9 @@ static int moboard_usbh2_hw_init(struct platform_device *pdev) mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); + ret = gpio_request(USBH2_EN_B, "usbh2-en"); + if (ret) + return ret; gpio_direction_output(USBH2_EN_B, 0); return 0; @@ -431,34 +429,6 @@ static struct platform_device mx31moboard_leds_device = { }, }; -#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) -#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) -#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) -#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) - -static void mx31moboard_init_sel_gpios(void) -{ - if (!gpio_request(SEL0, "sel0")) { - gpio_direction_input(SEL0); - gpio_export(SEL0, true); - } - - if (!gpio_request(SEL1, "sel1")) { - gpio_direction_input(SEL1); - gpio_export(SEL1, true); - } - - if (!gpio_request(SEL2, "sel2")) { - gpio_direction_input(SEL2); - gpio_export(SEL2, true); - } - - if (!gpio_request(SEL3, "sel3")) { - gpio_direction_input(SEL3); - gpio_export(SEL3, true); - } -} - static struct ipu_platform_data mx3_ipu_data = { .irq_base = MXC_IPU_IRQ_START, }; @@ -518,8 +488,6 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_uart_device4, &uart4_pdata); - mx31moboard_init_sel_gpios(); - mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); @@ -552,6 +520,9 @@ static void __init mxc_board_init(void) case MX31MARXBOT: mx31moboard_marxbot_init(); break; + case MX31SMARTBOT: + mx31moboard_smartbot_init(); + break; default: printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", mx31moboard_baseboard); @@ -569,9 +540,9 @@ struct sys_timer mx31moboard_timer = { MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") /* Maintainer: Valentin Longchamp, EPFL Mobots group */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mach-mx35pdk.c index 0bbc65ea23c8..bcac84d4dca4 100644 --- a/arch/arm/mach-mx3/mx35pdk.c +++ b/arch/arm/mach-mx3/mach-mx35pdk.c @@ -106,9 +106,9 @@ struct sys_timer mx35pdk_timer = { MACHINE_START(MX35_3DS, "Freescale MX35PDK") /* Maintainer: Freescale Semiconductor, Inc */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX35_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx35_map_io, .init_irq = mx35_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 5be396917c99..11f531559169 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c @@ -33,6 +33,9 @@ #include <linux/irq.h> #include <linux/fsl_devices.h> #include <linux/can/platform/sja1000.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/fsl_devices.h> #include <media/soc_camera.h> @@ -51,6 +54,8 @@ #include <mach/mx3_camera.h> #include <mach/mx3fb.h> #include <mach/mxc_nand.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> #include "devices.h" #include "pcm037.h" @@ -172,19 +177,7 @@ static unsigned int pcm037_pins[] = { MX31_PIN_CSI_VSYNC__CSI_VSYNC, /* GPIO */ IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO), -}; - -static struct physmap_flash_data pcm037_flash_data = { - .width = 2, -}; - -static struct resource pcm037_flash_resource = { - .start = 0xa0000000, - .end = 0xa1ffffff, - .flags = IORESOURCE_MEM, -}; - -static int usbotg_pins[] = { + /* OTG */ MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, @@ -197,39 +190,29 @@ static int usbotg_pins[] = { MX31_PIN_USBOTG_DIR__USBOTG_DIR, MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, + /* USB host 2 */ + IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC), + IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC), }; -/* USB OTG HS port */ -static int __init gpio_usbotg_hs_activate(void) -{ - int ret = mxc_iomux_setup_multiple_pins(usbotg_pins, - ARRAY_SIZE(usbotg_pins), "usbotg"); - - if (ret < 0) { - printk(KERN_ERR "Cannot set up OTG pins\n"); - return ret; - } - - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); - - return 0; -} +static struct physmap_flash_data pcm037_flash_data = { + .width = 2, +}; -/* OTG config */ -static struct fsl_usb2_platform_data usb_pdata = { - .operating_mode = FSL_USB2_DR_DEVICE, - .phy_mode = FSL_USB2_PHY_ULPI, +static struct resource pcm037_flash_resource = { + .start = 0xa0000000, + .end = 0xa1ffffff, + .flags = IORESOURCE_MEM, }; static struct platform_device pcm037_flash = { @@ -248,8 +231,8 @@ static struct imxuart_platform_data uart_pdata = { static struct resource smsc911x_resources[] = { { - .start = CS1_BASE_ADDR + 0x300, - .end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1, + .start = MX31_CS1_BASE_ADDR + 0x300, + .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1, .flags = IORESOURCE_MEM, }, { .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), @@ -281,8 +264,8 @@ static struct platdata_mtd_ram pcm038_sram_data = { }; static struct resource pcm038_sram_resource = { - .start = CS4_BASE_ADDR, - .end = CS4_BASE_ADDR + 512 * 1024 - 1, + .start = MX31_CS4_BASE_ADDR, + .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1, .flags = IORESOURCE_MEM, }; @@ -536,8 +519,8 @@ static struct mx3fb_platform_data mx3fb_pdata = { static struct resource pcm970_sja1000_resources[] = { { - .start = CS5_BASE_ADDR, - .end = CS5_BASE_ADDR + 0x100 - 1, + .start = MX31_CS5_BASE_ADDR, + .end = MX31_CS5_BASE_ADDR + 0x100 - 1, .flags = IORESOURCE_MEM, }, { .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)), @@ -561,16 +544,65 @@ static struct platform_device pcm970_sja1000 = { .num_resources = ARRAY_SIZE(pcm970_sja1000_resources), }; +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh2_pdata = { + .portsc = MXC_EHCI_MODE_ULPI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_ULPI, +}; + +static int otg_mode_host; + +static int __init pcm037_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", pcm037_otg_mode); + /* * Board specific initialization. */ static void __init mxc_board_init(void) { int ret; + u32 tmp; + + mxc_iomux_set_gpr(MUX_PGP_UH2, 1); mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins), "pcm037"); +#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \ + | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + + mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ + mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ + mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ + mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ + mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ + mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ + mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ + mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ + if (pcm037_variant() == PCM037_EET) mxc_iomux_setup_multiple_pins(pcm037_uart1_pins, ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1"); @@ -608,8 +640,6 @@ static void __init mxc_board_init(void) mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); - if (!gpio_usbotg_hs_activate()) - mxc_register_device(&mxc_otg_udc_device, &usb_pdata); /* CSI */ /* Camera power: default - off */ @@ -623,6 +653,23 @@ static void __init mxc_board_init(void) mxc_register_device(&mx3_camera, &camera_pdata); platform_device_register(&pcm970_sja1000); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + + usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_usbh2, &usbh2_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + } static void __init pcm037_timer_init(void) @@ -636,9 +683,9 @@ struct sys_timer pcm037_timer = { MACHINE_START(PCM037, "Phytec Phycore pcm037") /* Maintainer: Pengutronix */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c index 8d386000fc40..8d386000fc40 100644 --- a/arch/arm/mach-mx3/pcm037_eet.c +++ b/arch/arm/mach-mx3/mach-pcm037_eet.c diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index e3aa829be586..1bf1ec2eef5e 100644 --- a/arch/arm/mach-mx3/pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c @@ -26,8 +26,12 @@ #include <linux/gpio.h> #include <linux/smc911x.h> #include <linux/interrupt.h> +#include <linux/delay.h> #include <linux/i2c.h> #include <linux/i2c/at24.h> +#include <linux/usb/otg.h> +#include <linux/usb/ulpi.h> +#include <linux/fsl_devices.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -44,6 +48,10 @@ #include <mach/ipu.h> #include <mach/mx3fb.h> #include <mach/mxc_nand.h> +#include <mach/mxc_ehci.h> +#include <mach/ulpi.h> +#include <mach/audmux.h> +#include <mach/ssi.h> #include "devices.h" @@ -205,6 +213,94 @@ static struct pad_desc pcm043_pads[] = { MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, /* gpio */ MX35_PAD_ATA_CS0__GPIO2_6, + /* USB host */ + MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, + MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, + /* SSI */ + MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, + MX35_PAD_STXD4__AUDMUX_AUD4_TXD, + MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, + MX35_PAD_SCK4__AUDMUX_AUD4_TXC, +}; + +#define AC97_GPIO_TXFS (1 * 32 + 31) +#define AC97_GPIO_TXD (1 * 32 + 28) +#define AC97_GPIO_RESET (1 * 32 + 0) + +static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) +{ + struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; + struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; + int ret; + + ret = gpio_request(AC97_GPIO_TXFS, "SSI"); + if (ret) { + printk("failed to get GPIO_TXFS: %d\n", ret); + return; + } + + mxc_iomux_v3_setup_pad(&txfs_gpio); + + /* warm reset */ + gpio_direction_output(AC97_GPIO_TXFS, 1); + udelay(2); + gpio_set_value(AC97_GPIO_TXFS, 0); + + gpio_free(AC97_GPIO_TXFS); + mxc_iomux_v3_setup_pad(&txfs); +} + +static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) +{ + struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; + struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; + struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28; + struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; + struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; + int ret; + + ret = gpio_request(AC97_GPIO_TXFS, "SSI"); + if (ret) + goto err1; + + ret = gpio_request(AC97_GPIO_TXD, "SSI"); + if (ret) + goto err2; + + ret = gpio_request(AC97_GPIO_RESET, "SSI"); + if (ret) + goto err3; + + mxc_iomux_v3_setup_pad(&txfs_gpio); + mxc_iomux_v3_setup_pad(&txd_gpio); + mxc_iomux_v3_setup_pad(&reset_gpio); + + gpio_direction_output(AC97_GPIO_TXFS, 0); + gpio_direction_output(AC97_GPIO_TXD, 0); + + /* cold reset */ + gpio_direction_output(AC97_GPIO_RESET, 0); + udelay(10); + gpio_direction_output(AC97_GPIO_RESET, 1); + + mxc_iomux_v3_setup_pad(&txd); + mxc_iomux_v3_setup_pad(&txfs); + + gpio_free(AC97_GPIO_RESET); +err3: + gpio_free(AC97_GPIO_TXD); +err2: + gpio_free(AC97_GPIO_TXFS); +err1: + if (ret) + printk("%s failed with %d\n", __func__, ret); + mdelay(1); +} + +static struct imx_ssi_platform_data pcm043_ssi_pdata = { + .ac97_reset = pcm043_ac97_cold_reset, + .ac97_warm_reset = pcm043_ac97_warm_reset, + .flags = IMX_SSI_USE_AC97, }; static struct mxc_nand_platform_data pcm037_nand_board_info = { @@ -212,6 +308,37 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = { .hw_ecc = 1, }; +static struct mxc_usbh_platform_data otg_pdata = { + .portsc = MXC_EHCI_MODE_UTMI, + .flags = MXC_EHCI_INTERFACE_DIFF_UNI, +}; + +static struct mxc_usbh_platform_data usbh1_pdata = { + .portsc = MXC_EHCI_MODE_SERIAL, + .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | + MXC_EHCI_IPPUE_DOWN, +}; + +static struct fsl_usb2_platform_data otg_device_pdata = { + .operating_mode = FSL_USB2_DR_DEVICE, + .phy_mode = FSL_USB2_PHY_UTMI, +}; + +static int otg_mode_host; + +static int __init pcm043_otg_mode(char *options) +{ + if (!strcmp(options, "host")) + otg_mode_host = 1; + else if (!strcmp(options, "device")) + otg_mode_host = 0; + else + pr_info("otg_mode neither \"host\" nor \"device\". " + "Defaulting to device\n"); + return 0; +} +__setup("otg_mode=", pcm043_otg_mode); + /* * Board specific initialization. */ @@ -219,10 +346,23 @@ static void __init mxc_board_init(void) { mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); + mxc_audmux_v2_configure_port(3, + MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ + MXC_AUDMUX_V2_PTCR_TFSEL(0) | + MXC_AUDMUX_V2_PTCR_TFSDIR, + MXC_AUDMUX_V2_PDCR_RXDSEL(0)); + + mxc_audmux_v2_configure_port(0, + MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ + MXC_AUDMUX_V2_PTCR_TCSEL(3) | + MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */ + MXC_AUDMUX_V2_PDCR_RXDSEL(3)); + platform_add_devices(devices, ARRAY_SIZE(devices)); mxc_register_device(&mxc_uart_device0, &uart_pdata); mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); + mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata); mxc_register_device(&mxc_uart_device1, &uart_pdata); @@ -235,6 +375,20 @@ static void __init mxc_board_init(void) mxc_register_device(&mx3_ipu, &mx3_ipu_data); mxc_register_device(&mx3_fb, &mx3fb_pdata); + +#if defined(CONFIG_USB_ULPI) + if (otg_mode_host) { + otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, + USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); + + mxc_register_device(&mxc_otg_host, &otg_pdata); + } + + mxc_register_device(&mxc_usbh1, &usbh1_pdata); +#endif + if (!otg_mode_host) + mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); + } static void __init pcm043_timer_init(void) @@ -248,9 +402,9 @@ struct sys_timer pcm043_timer = { MACHINE_START(PCM043, "Phytec Phycore pcm043") /* Maintainer: Pengutronix */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX35_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx35_map_io, .init_irq = mx35_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/mach-qong.c index 044511f1b9a9..e5b5b8323a17 100644 --- a/arch/arm/mach-mx3/qong.c +++ b/arch/arm/mach-mx3/mach-qong.c @@ -43,7 +43,7 @@ #define QONG_FPGA_VERSION(major, minor, rev) \ (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) -#define QONG_FPGA_BASEADDR CS1_BASE_ADDR +#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR #define QONG_FPGA_PERIPH_SIZE (1 << 24) #define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR @@ -115,8 +115,8 @@ static struct physmap_flash_data qong_flash_data = { }; static struct resource qong_flash_resource = { - .start = CS0_BASE_ADDR, - .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1, + .start = MX31_CS0_BASE_ADDR, + .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1, .flags = IORESOURCE_MEM, }; @@ -180,8 +180,8 @@ static struct platform_nand_data qong_nand_data = { }; static struct resource qong_nand_resource = { - .start = CS3_BASE_ADDR, - .end = CS3_BASE_ADDR + SZ_32M - 1, + .start = MX31_CS3_BASE_ADDR, + .end = MX31_CS3_BASE_ADDR + SZ_32M - 1, .flags = IORESOURCE_MEM, }; @@ -198,9 +198,7 @@ static struct platform_device qong_nand_device = { static void __init qong_init_nand_mtd(void) { /* init CS */ - __raw_writel(0x00004f00, CSCR_U(3)); - __raw_writel(0x20013b31, CSCR_L(3)); - __raw_writel(0x00020800, CSCR_A(3)); + mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800); mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); /* enable pin */ @@ -275,9 +273,9 @@ static struct sys_timer qong_timer = { MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") /* Maintainer: DENX Software Engineering GmbH */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .phys_io = MX31_AIPS1_BASE_ADDR, + .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc, + .boot_params = MX3x_PHYS_OFFSET + 0x100, .map_io = mx31_map_io, .init_irq = mx31_init_irq, .init_machine = mxc_board_init, diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 694611d6b057..ccd874225c3b 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c @@ -67,6 +67,13 @@ static unsigned int litekit_db_board_pins[] __initdata = { MX31_PIN_CSPI1_SS0__SS0, MX31_PIN_CSPI1_SS1__SS1, MX31_PIN_CSPI1_SS2__SS2, + /* SDHC1 */ + MX31_PIN_SD1_DATA0__SD1_DATA0, + MX31_PIN_SD1_DATA1__SD1_DATA1, + MX31_PIN_SD1_DATA2__SD1_DATA2, + MX31_PIN_SD1_DATA3__SD1_DATA3, + MX31_PIN_SD1_CLK__SD1_CLK, + MX31_PIN_SD1_CMD__SD1_CMD, }; /* UART */ @@ -79,11 +86,11 @@ static struct imxuart_platform_data uart_pdata __initdata = { static int gpio_det, gpio_wp; #define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ - PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) + PAD_CTL_ODE_CMOS) static int mxc_mmc1_get_ro(struct device *dev) { - return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); + return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6)); } static int mxc_mmc1_init(struct device *dev, @@ -94,12 +101,17 @@ static int mxc_mmc1_init(struct device *dev, gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX31_PIN_SD1_CMD, + MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU); mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); - mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG); ret = gpio_request(gpio_det, "MMC detect"); if (ret) @@ -113,7 +125,7 @@ static int mxc_mmc1_init(struct device *dev, gpio_direction_input(gpio_wp); ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq, - IRQF_DISABLED | IRQF_TRIGGER_FALLING, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC detect", data); if (ret) goto exit_free_wp; @@ -133,7 +145,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data) { gpio_free(gpio_det); gpio_free(gpio_wp); - free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); + free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data); } static struct imxmmc_platform_data mmc_pdata = { diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index 438428eaf769..9fbad2eb3a49 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c @@ -49,6 +49,9 @@ static unsigned int devboard_pins[] = { MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, + /* SEL */ + MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, + MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, }; static struct imxuart_platform_data uart_pdata = { @@ -108,6 +111,33 @@ static struct imxmmc_platform_data sdhc2_pdata = { .exit = devboard_sdhc2_exit, }; +#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) +#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) +#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) +#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) + +static void devboard_init_sel_gpios(void) +{ + if (!gpio_request(SEL0, "sel0")) { + gpio_direction_input(SEL0); + gpio_export(SEL0, true); + } + + if (!gpio_request(SEL1, "sel1")) { + gpio_direction_input(SEL1); + gpio_export(SEL1, true); + } + + if (!gpio_request(SEL2, "sel2")) { + gpio_direction_input(SEL2); + gpio_export(SEL2, true); + } + + if (!gpio_request(SEL3, "sel3")) { + gpio_direction_input(SEL3); + gpio_export(SEL3, true); + } +} #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -196,5 +226,7 @@ void __init mx31moboard_devboard_init(void) mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); + devboard_init_sel_gpios(); + devboard_usbh1_init(); } diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 1f44b9ccbb0f..3958515d75bf 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c @@ -66,6 +66,9 @@ static unsigned int marxbot_pins[] = { MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, + /* SEL */ + MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, + MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, }; #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) @@ -127,12 +130,12 @@ static struct imxmmc_platform_data sdhc2_pdata = { static void dspics_resets_init(void) { if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { - gpio_direction_output(TRSLAT_RST_B, 1); + gpio_direction_output(TRSLAT_RST_B, 0); gpio_export(TRSLAT_RST_B, false); } if (!gpio_request(DSPICS_RST_B, "dspics-rst")) { - gpio_direction_output(DSPICS_RST_B, 1); + gpio_direction_output(DSPICS_RST_B, 0); gpio_export(DSPICS_RST_B, false); } } @@ -200,7 +203,7 @@ static int __init marxbot_cam_init(void) int ret = gpio_request(CAM_CHOICE, "cam-choice"); if (ret) return ret; - gpio_direction_output(CAM_CHOICE, 1); + gpio_direction_output(CAM_CHOICE, 0); ret = gpio_request(BASECAM_RST_B, "basecam-reset"); if (ret) @@ -223,6 +226,34 @@ static int __init marxbot_cam_init(void) return 0; } +#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) +#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) +#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) +#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) + +static void marxbot_init_sel_gpios(void) +{ + if (!gpio_request(SEL0, "sel0")) { + gpio_direction_input(SEL0); + gpio_export(SEL0, true); + } + + if (!gpio_request(SEL1, "sel1")) { + gpio_direction_input(SEL1); + gpio_export(SEL1, true); + } + + if (!gpio_request(SEL2, "sel2")) { + gpio_direction_input(SEL2); + gpio_export(SEL2, true); + } + + if (!gpio_request(SEL3, "sel3")) { + gpio_direction_input(SEL3); + gpio_export(SEL3, true); + } +} + #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) @@ -307,6 +338,8 @@ void __init mx31moboard_marxbot_init(void) mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins), "marxbot"); + marxbot_init_sel_gpios(); + dspics_resets_init(); mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c new file mode 100644 index 000000000000..52a69fc8b14f --- /dev/null +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <linux/platform_device.h> +#include <linux/types.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx3.h> + +#include <media/soc_camera.h> + +#include "devices.h" + +static unsigned int smartbot_pins[] = { + /* UART1 */ + MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, + MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, + /* CSI */ + MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5, + MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, + MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, + MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, + MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13, + MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, + MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, + MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, + MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, + /* ENABLES */ + MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, + MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, +}; + +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) +#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) + +static int smartbot_cam_power(struct device *dev, int on) +{ + gpio_set_value(CAM_POWER, !on); + return 0; +} + +static int smartbot_cam_reset(struct device *dev) +{ + gpio_set_value(CAM_RST_B, 0); + udelay(100); + gpio_set_value(CAM_RST_B, 1); + return 0; +} + +static struct i2c_board_info smartbot_i2c_devices[] = { + { + I2C_BOARD_INFO("mt9t031", 0x5d), + }, +}; + +static struct soc_camera_link base_iclink = { + .bus_id = 0, /* Must match with the camera ID */ + .power = smartbot_cam_power, + .reset = smartbot_cam_reset, + .board_info = &smartbot_i2c_devices[0], + .i2c_adapter_id = 0, + .module_name = "mt9t031", +}; + +static struct platform_device smartbot_camera[] = { + { + .name = "soc-camera-pdrv", + .id = 0, + .dev = { + .platform_data = &base_iclink, + }, + }, +}; + +static struct platform_device *smartbot_cameras[] __initdata = { + &smartbot_camera[0], +}; + +static int __init smartbot_cam_init(void) +{ + int ret = gpio_request(CAM_RST_B, "cam-reset"); + if (ret) + return ret; + gpio_direction_output(CAM_RST_B, 1); + ret = gpio_request(CAM_POWER, "cam-standby"); + if (ret) + return ret; + gpio_direction_output(CAM_POWER, 0); + + return 0; +} + +#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) +#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) +#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) +#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) + +static void smartbot_resets_init(void) +{ + if (!gpio_request(POWER_EN, "power-enable")) { + gpio_direction_output(POWER_EN, 0); + gpio_export(POWER_EN, false); + } + + if (!gpio_request(DSPIC_RST_B, "dspic-rst")) { + gpio_direction_output(DSPIC_RST_B, 0); + gpio_export(DSPIC_RST_B, false); + } + + if (!gpio_request(TRSLAT_RST_B, "translator-rst")) { + gpio_direction_output(TRSLAT_RST_B, 0); + gpio_export(TRSLAT_RST_B, false); + } + + if (!gpio_request(SEL3, "sel3")) { + gpio_direction_input(SEL3); + gpio_export(SEL3, true); + } +} +/* + * system init for baseboard usage. Will be called by mx31moboard init. + */ +void __init mx31moboard_smartbot_init(void) +{ + printk(KERN_INFO "Initializing mx31smartbot peripherals\n"); + + mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins), + "smartbot"); + + mxc_register_device(&mxc_uart_device1, &uart_pdata); + + smartbot_resets_init(); + + smartbot_cam_init(); + platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras)); +} diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig new file mode 100644 index 000000000000..1576d51e676c --- /dev/null +++ b/arch/arm/mach-mx5/Kconfig @@ -0,0 +1,18 @@ +if ARCH_MX5 + +config ARCH_MX51 + bool + default y + select MXC_TZIC + select ARCH_MXC_IOMUX_V3 + +comment "MX5 platforms:" + +config MACH_MX51_BABBAGE + bool "Support MX51 BABBAGE platforms" + help + Include support for MX51 Babbage platform, also known as MX51EVK in + u-boot. This includes specific configurations for the board and its + peripherals. + +endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile new file mode 100644 index 000000000000..bf23f869ef51 --- /dev/null +++ b/arch/arm/mach-mx5/Makefile @@ -0,0 +1,9 @@ +# +# Makefile for the linux kernel. +# + +# Object file lists. +obj-y := cpu.o mm.o clock-mx51.o devices.o + +obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o + diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot new file mode 100644 index 000000000000..9939a19d99a1 --- /dev/null +++ b/arch/arm/mach-mx5/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x90008000 +params_phys-y := 0x90000100 +initrd_phys-y := 0x90800000 diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c new file mode 100644 index 000000000000..ee67a71db80d --- /dev/null +++ b/arch/arm/mach-mx5/board-mx51_babbage.c @@ -0,0 +1,98 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009-2010 Amit Kucheria <[email protected]> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/init.h> +#include <linux/platform_device.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/imx-uart.h> +#include <mach/iomux-mx51.h> + +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "devices.h" + +static struct platform_device *devices[] __initdata = { + &mxc_fec_device, +}; + +static struct pad_desc mx51babbage_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + + /* UART2 */ + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + + /* UART3 */ + MX51_PAD_EIM_D25__UART3_RXD, + MX51_PAD_EIM_D26__UART3_TXD, + MX51_PAD_EIM_D27__UART3_RTS, + MX51_PAD_EIM_D24__UART3_CTS, +}; + +/* Serial ports */ +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) +static struct imxuart_platform_data uart_pdata = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static inline void mxc_init_imx_uart(void) +{ + mxc_register_device(&mxc_uart_device0, &uart_pdata); + mxc_register_device(&mxc_uart_device1, &uart_pdata); + mxc_register_device(&mxc_uart_device2, &uart_pdata); +} +#else /* !SERIAL_IMX */ +static inline void mxc_init_imx_uart(void) +{ +} +#endif /* SERIAL_IMX */ + +/* + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, + ARRAY_SIZE(mx51babbage_pads)); + mxc_init_imx_uart(); + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init mx51_babbage_timer_init(void) +{ + mx51_clocks_init(32768, 24000000, 22579200, 0); +} + +static struct sys_timer mxc_timer = { + .init = mx51_babbage_timer_init, +}; + +MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") + /* Maintainer: Amit Kucheria <[email protected]> */ + .phys_io = MX51_AIPS1_BASE_ADDR, + .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .map_io = mx51_map_io, + .init_irq = mx51_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c new file mode 100644 index 000000000000..be90c03101cd --- /dev/null +++ b/arch/arm/mach-mx5/clock-mx51.c @@ -0,0 +1,825 @@ +/* + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009-2010 Amit Kucheria <[email protected]> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/mm.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/io.h> + +#include <asm/clkdev.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/clock.h> + +#include "crm_regs.h" + +/* External clock values passed-in by the board code */ +static unsigned long external_high_reference, external_low_reference; +static unsigned long oscillator_reference, ckih2_reference; + +static struct clk osc_clk; +static struct clk pll1_main_clk; +static struct clk pll1_sw_clk; +static struct clk pll2_sw_clk; +static struct clk pll3_sw_clk; +static struct clk lp_apm_clk; +static struct clk periph_apm_clk; +static struct clk ahb_clk; +static struct clk ipg_clk; + +#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ + +static int _clk_ccgr_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_ccgr_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + +} + +static void _clk_ccgr_disable_inwait(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else + BUG(); + + return -EINVAL; +} + +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_main_clk) + return MX51_DPLL1_BASE; + else if (pll == &pll2_sw_clk) + return MX51_DPLL2_BASE; + else if (pll == &pll3_sw_clk) + return MX51_DPLL3_BASE; + else + BUG(); + + return NULL; +} + +static unsigned long clk_pll_get_rate(struct clk *clk) +{ + long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; + unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; + void __iomem *pllbase; + s64 temp; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + pllbase = _get_pll_base(clk); + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; + + if (pll_hfsm == 0) { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); + } else { + dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); + dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); + dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); + } + pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; + mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; + mfi = (mfi <= 5) ? 5 : mfi; + mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; + mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; + /* Sign extend to 32-bits */ + if (mfn >= 0x04000000) { + mfn |= 0xFC000000; + mfn_abs = -mfn; + } + + ref_clk = 2 * parent_rate; + if (dbl != 0) + ref_clk *= 2; + + ref_clk /= (pdf + 1); + temp = (u64) ref_clk * mfn_abs; + do_div(temp, mfd + 1); + if (mfn < 0) + temp = -temp; + temp = (ref_clk * mfi) + temp; + + return temp; +} + +static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + void __iomem *pllbase; + + long mfi, pdf, mfn, mfd = 999999; + s64 temp64; + unsigned long quad_parent_rate; + unsigned long pll_hfsm, dp_ctl; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + pllbase = _get_pll_base(clk); + + quad_parent_rate = 4 * parent_rate; + pdf = mfi = -1; + while (++pdf < 16 && mfi < 5) + mfi = rate * (pdf+1) / quad_parent_rate; + if (mfi > 15) + return -EINVAL; + pdf--; + + temp64 = rate * (pdf+1) - quad_parent_rate * mfi; + do_div(temp64, quad_parent_rate/1000000); + mfn = (long)temp64; + + dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); + /* use dpdck0_2 */ + __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); + pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; + if (pll_hfsm == 0) { + reg = mfi << 4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); + } else { + reg = mfi << 4 | pdf; + __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); + __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); + __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); + } + + return 0; +} + +static int _clk_pll_enable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + int i = 0; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); + + /* Wait for lock */ + do { + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + if (reg & MXC_PLL_DP_CTL_LRF) + break; + + udelay(1); + } while (++i < MAX_DPLL_WAIT_TRIES); + + if (i == MAX_DPLL_WAIT_TRIES) { + pr_err("MX5: pll locking failed\n"); + return -EINVAL; + } + + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + u32 reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); +} + +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, step; + + reg = __raw_readl(MXC_CCM_CCSR); + + /* When switching from pll_main_clk to a bypass clock, first select a + * multiplexed clock in 'step_sel', then shift the glitchless mux + * 'pll1_sw_clk_sel'. + * + * When switching back, do it in reverse order + */ + if (parent == &pll1_main_clk) { + /* Switch to pll1_main_clk */ + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + /* step_clk mux switched to lp_apm, to save power. */ + reg = __raw_readl(MXC_CCM_CCSR); + reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; + reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM << + MXC_CCM_CCSR_STEP_SEL_OFFSET); + } else { + if (parent == &lp_apm_clk) { + step = MXC_CCM_CCSR_STEP_SEL_LP_APM; + } else if (parent == &pll2_sw_clk) { + step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED; + } else if (parent == &pll3_sw_clk) { + step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED; + } else + return -EINVAL; + + reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; + reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CCSR); + /* Switch to step_clk */ + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +static unsigned long clk_pll1_sw_get_rate(struct clk *clk) +{ + u32 reg, div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CCSR); + + if (clk->parent == &pll2_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> + MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; + } else if (clk->parent == &pll3_sw_clk) { + div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> + MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; + } else + div = 1; + return parent_rate / div; +} + +static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll2_sw_clk) + reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + else + reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; + + __raw_writel(reg, MXC_CCM_CCSR); + return 0; +} + +static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + if (parent == &osc_clk) + reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; + else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static unsigned long clk_arm_get_rate(struct clk *clk) +{ + u32 cacrr, div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + cacrr = __raw_readl(MXC_CCM_CACRR); + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; + + return parent_rate / div; +} + +static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + int i = 0; + + mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); + + reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CBCMR); + + /* Wait for lock */ + do { + reg = __raw_readl(MXC_CCM_CDHIPR); + if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)) + break; + + udelay(1); + } while (++i < MAX_DPLL_WAIT_TRIES); + + if (i == MAX_DPLL_WAIT_TRIES) { + pr_err("MX5: Set parent for periph_apm clock failed\n"); + return -EINVAL; + } + + return 0; +} + +static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CBCDR); + + if (parent == &pll2_sw_clk) + reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; + else if (parent == &periph_apm_clk) + reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; + else + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CBCDR); + + return 0; +} + +static struct clk main_bus_clk = { + .parent = &pll2_sw_clk, + .set_parent = _clk_main_bus_set_parent, +}; + +static unsigned long clk_ahb_get_rate(struct clk *clk) +{ + u32 reg, div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; + return parent_rate / div; +} + + +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + unsigned long parent_rate; + int i = 0; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div > 8 || div < 1 || ((parent_rate / div) != rate)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + /* Wait for lock */ + do { + reg = __raw_readl(MXC_CCM_CDHIPR); + if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY)) + break; + + udelay(1); + } while (++i < MAX_DPLL_WAIT_TRIES); + + if (i == MAX_DPLL_WAIT_TRIES) { + pr_err("MX5: clk_ahb_set_rate failed\n"); + return -EINVAL; + } + + return 0; +} + +static unsigned long _clk_ahb_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return parent_rate / div; +} + + +static int _clk_max_enable(struct clk *clk) +{ + u32 reg; + + _clk_ccgr_enable(clk); + + /* Handshake with MAX when LPM is entered. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); + + return 0; +} + +static void _clk_max_disable(struct clk *clk) +{ + u32 reg; + + _clk_ccgr_disable_inwait(clk); + + /* No Handshake with MAX when LPM is entered as its disabled. */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +} + +static unsigned long clk_ipg_get_rate(struct clk *clk) +{ + u32 reg, div; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; + + return parent_rate / div; +} + +static unsigned long clk_ipg_per_get_rate(struct clk *clk) +{ + u32 reg, prediv1, prediv2, podf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { + /* the main_bus_clk is the one before the DVFS engine */ + reg = __raw_readl(MXC_CCM_CBCDR); + prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; + prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; + podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; + return parent_rate / (prediv1 * prediv2 * podf); + } else if (clk->parent == &ipg_clk) + return parent_rate; + else + BUG(); +} + +static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CBCMR); + + reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + + if (parent == &ipg_clk) + reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; + else if (parent == &lp_apm_clk) + reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; + else if (parent != &main_bus_clk) + return -EINVAL; + + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static unsigned long clk_uart_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + unsigned long parent_rate; + + parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; + + return parent_rate / (prediv * podf); +} + +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long get_high_reference_clock_rate(struct clk *clk) +{ + return external_high_reference; +} + +static unsigned long get_low_reference_clock_rate(struct clk *clk) +{ + return external_low_reference; +} + +static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) +{ + return oscillator_reference; +} + +static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) +{ + return ckih2_reference; +} + +/* External high frequency clock */ +static struct clk ckih_clk = { + .get_rate = get_high_reference_clock_rate, +}; + +static struct clk ckih2_clk = { + .get_rate = get_ckih2_reference_clock_rate, +}; + +static struct clk osc_clk = { + .get_rate = get_oscillator_reference_clock_rate, +}; + +/* External low frequency (32kHz) clock */ +static struct clk ckil_clk = { + .get_rate = get_low_reference_clock_rate, +}; + +static struct clk pll1_main_clk = { + .parent = &osc_clk, + .get_rate = clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +/* Clock tree block diagram (WIP): + * CCM: Clock Controller Module + * + * PLL output -> | + * | CCM Switcher -> CCM_CLK_ROOT_GEN -> + * PLL bypass -> | + * + */ + +/* PLL1 SW supplies to ARM core */ +static struct clk pll1_sw_clk = { + .parent = &pll1_main_clk, + .set_parent = _clk_pll1_sw_set_parent, + .get_rate = clk_pll1_sw_get_rate, +}; + +/* PLL2 SW supplies to AXI/AHB/IP buses */ +static struct clk pll2_sw_clk = { + .parent = &osc_clk, + .get_rate = clk_pll_get_rate, + .set_rate = _clk_pll_set_rate, + .set_parent = _clk_pll2_sw_set_parent, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +/* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ +static struct clk pll3_sw_clk = { + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .get_rate = clk_pll_get_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +/* Low-power Audio Playback Mode clock */ +static struct clk lp_apm_clk = { + .parent = &osc_clk, + .set_parent = _clk_lp_apm_set_parent, +}; + +static struct clk periph_apm_clk = { + .parent = &pll1_sw_clk, + .set_parent = _clk_periph_apm_set_parent, +}; + +static struct clk cpu_clk = { + .parent = &pll1_sw_clk, + .get_rate = clk_arm_get_rate, +}; + +static struct clk ahb_clk = { + .parent = &main_bus_clk, + .get_rate = clk_ahb_get_rate, + .set_rate = _clk_ahb_set_rate, + .round_rate = _clk_ahb_round_rate, +}; + +/* Main IP interface clock for access to registers */ +static struct clk ipg_clk = { + .parent = &ahb_clk, + .get_rate = clk_ipg_get_rate, +}; + +static struct clk ipg_perclk = { + .parent = &lp_apm_clk, + .get_rate = clk_ipg_per_get_rate, + .set_parent = _clk_ipg_per_set_parent, +}; + +static struct clk uart_root_clk = { + .parent = &pll2_sw_clk, + .get_rate = clk_uart_get_rate, + .set_parent = _clk_uart_set_parent, +}; + +static struct clk ahb_max_clk = { + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_max_enable, + .disable = _clk_max_disable, +}; + +static struct clk aips_tz1_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable_inwait, +}; + +static struct clk aips_tz2_clk = { + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_ccgr_enable, + .disable = _clk_ccgr_disable_inwait, +}; + +static struct clk gpt_32k_clk = { + .id = 0, + .parent = &ckil_clk, +}; + +#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ + static struct clk name = { \ + .id = i, \ + .enable_reg = er, \ + .enable_shift = es, \ + .get_rate = gr, \ + .set_rate = sr, \ + .enable = _clk_ccgr_enable, \ + .disable = _clk_ccgr_disable, \ + .parent = p, \ + .secondary = s, \ + } + +/* DEFINE_CLOCK(name, id, enable_reg, enable_shift, + get_rate, set_rate, parent, secondary); */ + +/* Shared peripheral bus arbiter */ +DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, + NULL, NULL, &ipg_clk, NULL); + +/* UART */ +DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, + NULL, NULL, &uart_root_clk, NULL); +DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, + NULL, NULL, &uart_root_clk, NULL); +DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, + NULL, NULL, &uart_root_clk, NULL); +DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, + NULL, NULL, &ipg_clk, &aips_tz1_clk); +DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, + NULL, NULL, &ipg_clk, &aips_tz1_clk); +DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, + NULL, NULL, &ipg_clk, &spba_clk); + +/* GPT */ +DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, + NULL, NULL, &ipg_perclk, NULL); +DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, + NULL, NULL, &ipg_clk, NULL); + +/* FEC */ +DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, + NULL, NULL, &ipg_clk, NULL); + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + }, + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) + _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) + _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) + _REGISTER_CLOCK(NULL, "gpt", gpt_clk) + _REGISTER_CLOCK("fec.0", NULL, fec_clk) +}; + +static void clk_tree_init(void) +{ + u32 reg; + + ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); + + /* + * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at + * 8MHz, its derived from lp_apm. + * + * FIXME: Verify if true for all boards + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; + reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; + reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); +} + +int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2) +{ + int i; + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + + clk_tree_init(); + + clk_enable(&cpu_clk); + clk_enable(&main_bus_clk); + + /* System timer */ + mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), + MX51_MXC_INT_GPT); + return 0; +} diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c new file mode 100644 index 000000000000..41c769f08c4d --- /dev/null +++ b/arch/arm/mach-mx5/cpu.c @@ -0,0 +1,47 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * This file contains the CPU initialization code. + */ + +#include <linux/types.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <mach/hardware.h> +#include <asm/io.h> + +static int __init post_cpu_init(void) +{ + unsigned int reg; + void __iomem *base; + + if (!cpu_is_mx51()) + return 0; + + base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); + __raw_writel(0x0, base + 0x40); + __raw_writel(0x0, base + 0x44); + __raw_writel(0x0, base + 0x48); + __raw_writel(0x0, base + 0x4C); + reg = __raw_readl(base + 0x50) & 0x00FFFFFF; + __raw_writel(reg, base + 0x50); + + return 0; +} + +postcore_initcall(post_cpu_init); diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h new file mode 100644 index 000000000000..c776b9af0624 --- /dev/null +++ b/arch/arm/mach-mx5/crm_regs.h @@ -0,0 +1,583 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ + +#define MX51_CCM_BASE MX51_IO_ADDRESS(MX51_CCM_BASE_ADDR) +#define MX51_DPLL1_BASE MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR) +#define MX51_DPLL2_BASE MX51_IO_ADDRESS(MX51_PLL2_BASE_ADDR) +#define MX51_DPLL3_BASE MX51_IO_ADDRESS(MX51_PLL3_BASE_ADDR) +#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) +#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) + +/* PLL Register Offsets */ +#define MXC_PLL_DP_CTL 0x00 +#define MXC_PLL_DP_CONFIG 0x04 +#define MXC_PLL_DP_OP 0x08 +#define MXC_PLL_DP_MFD 0x0C +#define MXC_PLL_DP_MFN 0x10 +#define MXC_PLL_DP_MFNMINUS 0x14 +#define MXC_PLL_DP_MFNPLUS 0x18 +#define MXC_PLL_DP_HFS_OP 0x1C +#define MXC_PLL_DP_HFS_MFD 0x20 +#define MXC_PLL_DP_HFS_MFN 0x24 +#define MXC_PLL_DP_MFN_TOGC 0x28 +#define MXC_PLL_DP_DESTAT 0x2c + +/* PLL Register Bit definitions */ +#define MXC_PLL_DP_CTL_MUL_CTRL 0x2000 +#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000 +#define MXC_PLL_DP_CTL_DPDCK0_2_OFFSET 12 +#define MXC_PLL_DP_CTL_ADE 0x800 +#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400 +#define MXC_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) +#define MXC_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 +#define MXC_PLL_DP_CTL_HFSM 0x80 +#define MXC_PLL_DP_CTL_PRE 0x40 +#define MXC_PLL_DP_CTL_UPEN 0x20 +#define MXC_PLL_DP_CTL_RST 0x10 +#define MXC_PLL_DP_CTL_RCP 0x8 +#define MXC_PLL_DP_CTL_PLM 0x4 +#define MXC_PLL_DP_CTL_BRM0 0x2 +#define MXC_PLL_DP_CTL_LRF 0x1 + +#define MXC_PLL_DP_CONFIG_BIST 0x8 +#define MXC_PLL_DP_CONFIG_SJC_CE 0x4 +#define MXC_PLL_DP_CONFIG_AREN 0x2 +#define MXC_PLL_DP_CONFIG_LDREQ 0x1 + +#define MXC_PLL_DP_OP_MFI_OFFSET 4 +#define MXC_PLL_DP_OP_MFI_MASK (0xF << 4) +#define MXC_PLL_DP_OP_PDF_OFFSET 0 +#define MXC_PLL_DP_OP_PDF_MASK 0xF + +#define MXC_PLL_DP_MFD_OFFSET 0 +#define MXC_PLL_DP_MFD_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_OFFSET 0x0 +#define MXC_PLL_DP_MFN_MASK 0x07FFFFFF + +#define MXC_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) +#define MXC_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) +#define MXC_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 +#define MXC_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF + +#define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) +#define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF + +/* Register addresses of CCM*/ +#define MXC_CCM_CCR (MX51_CCM_BASE + 0x00) +#define MXC_CCM_CCDR (MX51_CCM_BASE + 0x04) +#define MXC_CCM_CSR (MX51_CCM_BASE + 0x08) +#define MXC_CCM_CCSR (MX51_CCM_BASE + 0x0C) +#define MXC_CCM_CACRR (MX51_CCM_BASE + 0x10) +#define MXC_CCM_CBCDR (MX51_CCM_BASE + 0x14) +#define MXC_CCM_CBCMR (MX51_CCM_BASE + 0x18) +#define MXC_CCM_CSCMR1 (MX51_CCM_BASE + 0x1C) +#define MXC_CCM_CSCMR2 (MX51_CCM_BASE + 0x20) +#define MXC_CCM_CSCDR1 (MX51_CCM_BASE + 0x24) +#define MXC_CCM_CS1CDR (MX51_CCM_BASE + 0x28) +#define MXC_CCM_CS2CDR (MX51_CCM_BASE + 0x2C) +#define MXC_CCM_CDCDR (MX51_CCM_BASE + 0x30) +#define MXC_CCM_CHSCDR (MX51_CCM_BASE + 0x34) +#define MXC_CCM_CSCDR2 (MX51_CCM_BASE + 0x38) +#define MXC_CCM_CSCDR3 (MX51_CCM_BASE + 0x3C) +#define MXC_CCM_CSCDR4 (MX51_CCM_BASE + 0x40) +#define MXC_CCM_CWDR (MX51_CCM_BASE + 0x44) +#define MXC_CCM_CDHIPR (MX51_CCM_BASE + 0x48) +#define MXC_CCM_CDCR (MX51_CCM_BASE + 0x4C) +#define MXC_CCM_CTOR (MX51_CCM_BASE + 0x50) +#define MXC_CCM_CLPCR (MX51_CCM_BASE + 0x54) +#define MXC_CCM_CISR (MX51_CCM_BASE + 0x58) +#define MXC_CCM_CIMR (MX51_CCM_BASE + 0x5C) +#define MXC_CCM_CCOSR (MX51_CCM_BASE + 0x60) +#define MXC_CCM_CGPR (MX51_CCM_BASE + 0x64) +#define MXC_CCM_CCGR0 (MX51_CCM_BASE + 0x68) +#define MXC_CCM_CCGR1 (MX51_CCM_BASE + 0x6C) +#define MXC_CCM_CCGR2 (MX51_CCM_BASE + 0x70) +#define MXC_CCM_CCGR3 (MX51_CCM_BASE + 0x74) +#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78) +#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C) +#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80) +#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84) + +/* Define the bits in register CCR */ +#define MXC_CCM_CCR_COSC_EN (1 << 12) +#define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) +#define MXC_CCM_CCR_CAMP2_EN (1 << 10) +#define MXC_CCM_CCR_CAMP1_EN (1 << 9) +#define MXC_CCM_CCR_FPM_EN (1 << 8) +#define MXC_CCM_CCR_OSCNT_OFFSET (0) +#define MXC_CCM_CCR_OSCNT_MASK (0xFF) + +/* Define the bits in register CCDR */ +#define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) + +/* Define the bits in register CSR */ +#define MXC_CCM_CSR_COSR_READY (1 << 5) +#define MXC_CCM_CSR_LVS_VALUE (1 << 4) +#define MXC_CCM_CSR_CAMP2_READY (1 << 3) +#define MXC_CCM_CSR_CAMP1_READY (1 << 2) +#define MXC_CCM_CSR_FPM_READY (1 << 1) +#define MXC_CCM_CSR_REF_EN_B (1 << 0) + +/* Define the bits in register CCSR */ +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) +#define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) +#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) +#define MXC_CCM_CCSR_STEP_SEL_LP_APM 0 +#define MXC_CCM_CCSR_STEP_SEL_PLL1_BYPASS 1 /* Only when JTAG connected? */ +#define MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED 2 +#define MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED 3 +#define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) +#define MXC_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) +#define MXC_CCM_CCSR_PLL3_PODF_OFFSET (3) +#define MXC_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) +#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) /* 0: pll1_main_clk, + 1: step_clk */ +#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) +#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET (0) +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) +#define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET (16) +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET (13) +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET (10) +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET (8) +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET (0) +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) + +/* Define the bits in register CSCMR2 */ +#define MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) +#define MXC_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) +#define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) +#define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) +#define MXC_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) +#define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) +#define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) +#define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) +#define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) +#define MXC_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) + +/* Define the bits in register CS1CDR and CS2CDR */ +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) + +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) +#define MXC_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDCDR */ +#define MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) +#define MXC_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) +#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) +#define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) +#define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) +#define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) + +/* Define the bits in register CHSCCDR */ +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) +#define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) +#define MXC_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) +#define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR3 */ +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CSCDR4 */ +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) + +/* Define the bits in register CDHIPR */ +#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) +#define MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) +#define MXC_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) +#define MXC_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) +#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#define MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) +#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) +#define MXC_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) +#define MXC_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) +#define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) + +/* Define the bits in register CDCR */ +#define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) +#define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) + +/* Define the bits in register CLPCR */ +#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) +#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) +#define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) +#define MXC_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) +#define MXC_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) +#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET (9) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_VSTBY (0x1 << 8) +#define MXC_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) +#define MXC_CCM_CLPCR_SBYOS (0x1 << 6) +#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#define MXC_CCM_CLPCR_LPM_OFFSET (0) +#define MXC_CCM_CLPCR_LPM_MASK (0x3) + +/* Define the bits in register CISR */ +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CISR_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CISR_COSC_READY (0x1 << 6) +#define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) +#define MXC_CCM_CISR_CKIH_READY (0x1 << 4) +#define MXC_CCM_CISR_FPM_READY (0x1 << 3) +#define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CISR_LRF_PLL1 (0x1) + +/* Define the bits in register CIMR */ +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) +#define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) +#define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) +#define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) +#define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) +#define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) +#define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) +#define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) + +/* Define the bits in register CCOSR */ +#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (21) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET (16) +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) +#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET (4) +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET (0) +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) + +/* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) +#define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) +#define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) + +/* Define the bits in registers CCGRx */ +#define MXC_CCM_CCGRx_CG_MASK 0x3 +#define MXC_CCM_CCGRx_MOD_OFF 0x0 +#define MXC_CCM_CCGRx_MOD_ON 0x3 +#define MXC_CCM_CCGRx_MOD_IDLE 0x1 + +#define MXC_CCM_CCGRx_CG15_MASK (0x3 << 30) +#define MXC_CCM_CCGRx_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGRx_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGRx_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGRx_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGRx_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGRx_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGRx_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGRx_CG5_MASK (0x3 << 10) +#define MXC_CCM_CCGRx_CG4_MASK (0x3 << 8) +#define MXC_CCM_CCGRx_CG3_MASK (0x3 << 6) +#define MXC_CCM_CCGRx_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGRx_CG1_MASK (0x3 << 2) +#define MXC_CCM_CCGRx_CG0_MASK (0x3 << 0) + +#define MXC_CCM_CCGRx_CG15_OFFSET 30 +#define MXC_CCM_CCGRx_CG14_OFFSET 28 +#define MXC_CCM_CCGRx_CG13_OFFSET 26 +#define MXC_CCM_CCGRx_CG12_OFFSET 24 +#define MXC_CCM_CCGRx_CG11_OFFSET 22 +#define MXC_CCM_CCGRx_CG10_OFFSET 20 +#define MXC_CCM_CCGRx_CG9_OFFSET 18 +#define MXC_CCM_CCGRx_CG8_OFFSET 16 +#define MXC_CCM_CCGRx_CG7_OFFSET 14 +#define MXC_CCM_CCGRx_CG6_OFFSET 12 +#define MXC_CCM_CCGRx_CG5_OFFSET 10 +#define MXC_CCM_CCGRx_CG4_OFFSET 8 +#define MXC_CCM_CCGRx_CG3_OFFSET 6 +#define MXC_CCM_CCGRx_CG2_OFFSET 4 +#define MXC_CCM_CCGRx_CG1_OFFSET 2 +#define MXC_CCM_CCGRx_CG0_OFFSET 0 + +#define MXC_DPTC_LP_BASE (MX51_GPC_BASE + 0x80) +#define MXC_DPTC_GP_BASE (MX51_GPC_BASE + 0x100) +#define MXC_DVFS_CORE_BASE (MX51_GPC_BASE + 0x180) +#define MXC_DPTC_PER_BASE (MX51_GPC_BASE + 0x1C0) +#define MXC_PGC_IPU_BASE (MX51_GPC_BASE + 0x220) +#define MXC_PGC_VPU_BASE (MX51_GPC_BASE + 0x240) +#define MXC_PGC_GPU_BASE (MX51_GPC_BASE + 0x260) +#define MXC_SRPG_NEON_BASE (MX51_GPC_BASE + 0x280) +#define MXC_SRPG_ARM_BASE (MX51_GPC_BASE + 0x2A0) +#define MXC_SRPG_EMPGC0_BASE (MX51_GPC_BASE + 0x2C0) +#define MXC_SRPG_EMPGC1_BASE (MX51_GPC_BASE + 0x2D0) +#define MXC_SRPG_MEGAMIX_BASE (MX51_GPC_BASE + 0x2E0) +#define MXC_SRPG_EMI_BASE (MX51_GPC_BASE + 0x300) + +/* CORTEXA8 platform */ +#define MXC_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) +#define MXC_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) +#define MXC_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) +#define MXC_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) +#define MXC_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) +#define MXC_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) +#define MXC_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) +#define MXC_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) + +/* DVFS CORE */ +#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) +#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) +#define MXC_DVFSSIG1 (MXC_DVFS_CORE_BASE + 0x08) +#define MXC_DVFSSIG0 (MXC_DVFS_CORE_BASE + 0x0C) +#define MXC_DVFSGPC0 (MXC_DVFS_CORE_BASE + 0x10) +#define MXC_DVFSGPC1 (MXC_DVFS_CORE_BASE + 0x14) +#define MXC_DVFSGPBT (MXC_DVFS_CORE_BASE + 0x18) +#define MXC_DVFSEMAC (MXC_DVFS_CORE_BASE + 0x1C) +#define MXC_DVFSCNTR (MXC_DVFS_CORE_BASE + 0x20) +#define MXC_DVFSLTR0_0 (MXC_DVFS_CORE_BASE + 0x24) +#define MXC_DVFSLTR0_1 (MXC_DVFS_CORE_BASE + 0x28) +#define MXC_DVFSLTR1_0 (MXC_DVFS_CORE_BASE + 0x2C) +#define MXC_DVFSLTR1_1 (MXC_DVFS_CORE_BASE + 0x30) +#define MXC_DVFSPT0 (MXC_DVFS_CORE_BASE + 0x34) +#define MXC_DVFSPT1 (MXC_DVFS_CORE_BASE + 0x38) +#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) +#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) + +/* GPC */ +#define MXC_GPC_CNTR (MX51_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MX51_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MX51_GPC_BASE + 0x8) +#define MXC_GPC_ALL_PU (MX51_GPC_BASE + 0xC) +#define MXC_GPC_NEON (MX51_GPC_BASE + 0x10) +#define MXC_GPC_PGR_ARMPG_OFFSET 8 +#define MXC_GPC_PGR_ARMPG_MASK (3 << 8) + +/* PGC */ +#define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) +#define MXC_PGC_IPU_PGSR (MXC_PGC_IPU_BASE + 0xC) +#define MXC_PGC_VPU_PGCR (MXC_PGC_VPU_BASE + 0x0) +#define MXC_PGC_VPU_PGSR (MXC_PGC_VPU_BASE + 0xC) +#define MXC_PGC_GPU_PGCR (MXC_PGC_GPU_BASE + 0x0) +#define MXC_PGC_GPU_PGSR (MXC_PGC_GPU_BASE + 0xC) + +#define MXC_PGCR_PCR 1 +#define MXC_SRPGCR_PCR 1 +#define MXC_EMPGCR_PCR 1 +#define MXC_PGSR_PSR 1 + + +#define MXC_CORTEXA8_PLAT_LPC_DSM (1 << 0) +#define MXC_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) + +/* SRPG */ +#define MXC_SRPG_NEON_SRPGCR (MXC_SRPG_NEON_BASE + 0x0) +#define MXC_SRPG_NEON_PUPSCR (MXC_SRPG_NEON_BASE + 0x4) +#define MXC_SRPG_NEON_PDNSCR (MXC_SRPG_NEON_BASE + 0x8) + +#define MXC_SRPG_ARM_SRPGCR (MXC_SRPG_ARM_BASE + 0x0) +#define MXC_SRPG_ARM_PUPSCR (MXC_SRPG_ARM_BASE + 0x4) +#define MXC_SRPG_ARM_PDNSCR (MXC_SRPG_ARM_BASE + 0x8) + +#define MXC_SRPG_EMPGC0_SRPGCR (MXC_SRPG_EMPGC0_BASE + 0x0) +#define MXC_SRPG_EMPGC0_PUPSCR (MXC_SRPG_EMPGC0_BASE + 0x4) +#define MXC_SRPG_EMPGC0_PDNSCR (MXC_SRPG_EMPGC0_BASE + 0x8) + +#define MXC_SRPG_EMPGC1_SRPGCR (MXC_SRPG_EMPGC1_BASE + 0x0) +#define MXC_SRPG_EMPGC1_PUPSCR (MXC_SRPG_EMPGC1_BASE + 0x4) +#define MXC_SRPG_EMPGC1_PDNSCR (MXC_SRPG_EMPGC1_BASE + 0x8) + +#define MXC_SRPG_MEGAMIX_SRPGCR (MXC_SRPG_MEGAMIX_BASE + 0x0) +#define MXC_SRPG_MEGAMIX_PUPSCR (MXC_SRPG_MEGAMIX_BASE + 0x4) +#define MXC_SRPG_MEGAMIX_PDNSCR (MXC_SRPG_MEGAMIX_BASE + 0x8) + +#define MXC_SRPGC_EMI_SRPGCR (MXC_SRPGC_EMI_BASE + 0x0) +#define MXC_SRPGC_EMI_PUPSCR (MXC_SRPGC_EMI_BASE + 0x4) +#define MXC_SRPGC_EMI_PDNSCR (MXC_SRPGC_EMI_BASE + 0x8) + +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c new file mode 100644 index 000000000000..d6fd3961ade9 --- /dev/null +++ b/arch/arm/mach-mx5/devices.c @@ -0,0 +1,96 @@ +/* + * Copyright 2009 Amit Kucheria <[email protected]> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/platform_device.h> +#include <mach/hardware.h> +#include <mach/imx-uart.h> + +static struct resource uart0[] = { + { + .start = MX51_UART1_BASE_ADDR, + .end = MX51_UART1_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_UART1, + .end = MX51_MXC_INT_UART1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device0 = { + .name = "imx-uart", + .id = 0, + .resource = uart0, + .num_resources = ARRAY_SIZE(uart0), +}; + +static struct resource uart1[] = { + { + .start = MX51_UART2_BASE_ADDR, + .end = MX51_UART2_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_UART2, + .end = MX51_MXC_INT_UART2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device1 = { + .name = "imx-uart", + .id = 1, + .resource = uart1, + .num_resources = ARRAY_SIZE(uart1), +}; + +static struct resource uart2[] = { + { + .start = MX51_UART3_BASE_ADDR, + .end = MX51_UART3_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_UART3, + .end = MX51_MXC_INT_UART3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_uart_device2 = { + .name = "imx-uart", + .id = 2, + .resource = uart2, + .num_resources = ARRAY_SIZE(uart2), +}; + +static struct resource mxc_fec_resources[] = { + { + .start = MX51_MXC_FEC_BASE_ADDR, + .end = MX51_MXC_FEC_BASE_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_MXC_INT_FEC, + .end = MX51_MXC_INT_FEC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_fec_device = { + .name = "fec", + .id = 0, + .num_resources = ARRAY_SIZE(mxc_fec_resources), + .resource = mxc_fec_resources, +}; + +/* Dummy definition to allow compiling in AVIC and TZIC simultaneously */ +int __init mxc_register_gpios(void) +{ + return 0; +} diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h new file mode 100644 index 000000000000..f339ab8c19be --- /dev/null +++ b/arch/arm/mach-mx5/devices.h @@ -0,0 +1,4 @@ +extern struct platform_device mxc_uart_device0; +extern struct platform_device mxc_uart_device1; +extern struct platform_device mxc_uart_device2; +extern struct platform_device mxc_fec_device; diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c new file mode 100644 index 000000000000..c21e18be7af8 --- /dev/null +++ b/arch/arm/mach-mx5/mm.c @@ -0,0 +1,89 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + * + * Create static mapping between physical to virtual memory. + */ + +#include <linux/mm.h> +#include <linux/init.h> + +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/iomux-v3.h> + +/* + * Define the MX51 memory map. + */ +static struct map_desc mxc_io_desc[] __initdata = { + { + .virtual = MX51_IRAM_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR), + .length = MX51_IRAM_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_DEBUG_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR), + .length = MX51_DEBUG_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_TZIC_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_TZIC_BASE_ADDR), + .length = MX51_TZIC_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_AIPS1_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), + .length = MX51_AIPS1_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_SPBA0_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR), + .length = MX51_SPBA0_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_AIPS2_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), + .length = MX51_AIPS2_SIZE, + .type = MT_DEVICE + }, { + .virtual = MX51_NFC_AXI_BASE_ADDR_VIRT, + .pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR), + .length = MX51_NFC_AXI_SIZE, + .type = MT_DEVICE + }, +}; + +/* + * This function initializes the memory map. It is called during the + * system startup to create static physical to virtual memory mappings + * for the IO modules. + */ +void __init mx51_map_io(void) +{ + u32 tzic_addr; + + if (mx51_revision() < MX51_CHIP_REV_2_0) + tzic_addr = 0x8FFFC000; + else + tzic_addr = 0xE0003000; + mxc_io_desc[2].pfn = __phys_to_pfn(tzic_addr); + + mxc_set_cpu_type(MXC_CPU_MX51); + mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); + mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR)); + iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); +} + +void __init mx51_init_irq(void) +{ + tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR)); +} diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c index 7dbe4ca12efd..69816ba82930 100644 --- a/arch/arm/mach-mxc91231/magx-zn5.c +++ b/arch/arm/mach-mxc91231/magx-zn5.c @@ -55,7 +55,7 @@ struct sys_timer zn5_timer = { MACHINE_START(MAGX_ZN5, "Motorola Zn5") .phys_io = MXC91231_AIPS1_BASE_ADDR, .io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, + .boot_params = MXC91231_PHYS_OFFSET + 0x100, .map_io = mxc91231_map_io, .init_irq = mxc91231_init_irq, .timer = &zn5_timer, diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c index 0c3c72d934bf..8afe9dd3f150 100644 --- a/arch/arm/mach-omap2/mmc-twl4030.c +++ b/arch/arm/mach-omap2/mmc-twl4030.c @@ -408,6 +408,7 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) { struct twl4030_hsmmc_info *c; int nr_hsmmc = ARRAY_SIZE(hsmmc_data); + int i; if (cpu_is_omap2430()) { control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; @@ -434,7 +435,7 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); if (!mmc) { pr_err("Cannot allocate memory for mmc device!\n"); - return; + goto done; } if (c->name) @@ -532,6 +533,10 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) continue; c->dev = mmc->dev; } + +done: + for (i = 0; i < nr_hsmmc; i++) + kfree(hsmmc_data[i]); } #endif diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index c3d513cad5ac..905719a677ae 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -57,6 +57,13 @@ config MACH_LINKSTATION_MINI Say 'Y' here if you want your kernel to support the Buffalo Linkstation Mini platform. +config MACH_LINKSTATION_LS_HGL + bool "Buffalo Linkstation LS-HGL" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Buffalo Linkstation LS-HGL platform. + config MACH_TS409 bool "QNAP TS-409" help diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 89772fcd65c7..eb6eabcb41e4 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_TERASTATION_PRO2) += terastation_pro2-setup.o obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o obj-$(CONFIG_MACH_LINKSTATION_MINI) += lsmini-setup.o +obj-$(CONFIG_MACH_LINKSTATION_LS_HGL) += ls_hgl-setup.o obj-$(CONFIG_MACH_DNS323) += dns323-setup.o obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index f87fa1253803..8dc2c76d2260 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -488,7 +488,7 @@ static struct platform_device orion5x_xor0_channel = { .dev = { .dma_mask = &orion5x_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&orion5x_xor0_data, + .platform_data = &orion5x_xor0_data, }, }; @@ -514,7 +514,7 @@ static struct platform_device orion5x_xor1_channel = { .dev = { .dma_mask = &orion5x_xor_dmamask, .coherent_dma_mask = DMA_BIT_MASK(64), - .platform_data = (void *)&orion5x_xor1_data, + .platform_data = &orion5x_xor1_data, }, }; diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c index 9d4bf763f25b..7130904ad999 100644 --- a/arch/arm/mach-orion5x/d2net-setup.c +++ b/arch/arm/mach-orion5x/d2net-setup.c @@ -149,10 +149,7 @@ static void __init d2net_sata_power_init(void) /* * The blue front LED is wired to the CPLD and can blink in relation with the - * SATA activity. This feature is disabled to make this LED compatible with - * the leds-gpio driver: MPP14 and MPP15 are configured to act like output - * GPIO's and have to stay in an active state. This is needed to set the blue - * LED in a "fix on" state regardless of the SATA activity. + * SATA activity. * * The following array detail the different LED registers and the combination * of their possible values: @@ -171,12 +168,11 @@ static void __init d2net_sata_power_init(void) #define D2NET_GPIO_RED_LED 6 #define D2NET_GPIO_BLUE_LED_BLINK_CTRL 16 #define D2NET_GPIO_BLUE_LED_OFF 23 -#define D2NET_GPIO_SATA0_ACT 14 -#define D2NET_GPIO_SATA1_ACT 15 static struct gpio_led d2net_leds[] = { { - .name = "d2net:blue:power", + .name = "d2net:blue:sata", + .default_trigger = "default-on", .gpio = D2NET_GPIO_BLUE_LED_OFF, .active_low = 1, }, @@ -201,25 +197,22 @@ static struct platform_device d2net_gpio_leds = { static void __init d2net_gpio_leds_init(void) { + int err; + /* Configure GPIO over MPP max number. */ orion_gpio_set_valid(D2NET_GPIO_BLUE_LED_OFF, 1); - if (gpio_request(D2NET_GPIO_SATA0_ACT, "LED SATA0 activity") != 0) - return; - if (gpio_direction_output(D2NET_GPIO_SATA0_ACT, 1) != 0) - goto err_free_1; - if (gpio_request(D2NET_GPIO_SATA1_ACT, "LED SATA1 activity") != 0) - goto err_free_1; - if (gpio_direction_output(D2NET_GPIO_SATA1_ACT, 1) != 0) - goto err_free_2; - platform_device_register(&d2net_gpio_leds); - return; + /* Configure register blink_ctrl to allow SATA activity LED blinking. */ + err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink"); + if (err == 0) { + err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1); + if (err) + gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL); + } + if (err) + pr_err("d2net: failed to configure blue LED blink GPIO\n"); -err_free_2: - gpio_free(D2NET_GPIO_SATA1_ACT); -err_free_1: - gpio_free(D2NET_GPIO_SATA0_ACT); - return; + platform_device_register(&d2net_gpio_leds); } /**************************************************************************** @@ -289,8 +282,8 @@ static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = { { 11, MPP_UNUSED }, { 12, MPP_GPIO }, /* SATA 1 power */ { 13, MPP_UNUSED }, - { 14, MPP_GPIO }, /* SATA 0 active */ - { 15, MPP_GPIO }, /* SATA 1 active */ + { 14, MPP_SATA_LED }, /* SATA 0 active */ + { 15, MPP_SATA_LED }, /* SATA 1 active */ { 16, MPP_GPIO }, /* Blue front LED blink control */ { 17, MPP_UNUSED }, { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ @@ -301,6 +294,8 @@ static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = { /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */ }; +#define D2NET_GPIO_INHIBIT_POWER_OFF 24 + static void __init d2net_init(void) { /* @@ -333,6 +328,8 @@ static void __init d2net_init(void) i2c_register_board_info(0, d2net_i2c_devices, ARRAY_SIZE(d2net_i2c_devices)); + + orion_gpio_set_valid(D2NET_GPIO_INHIBIT_POWER_OFF, 1); } /* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 8f159db4d08a..421b82f7c63d 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c @@ -34,7 +34,8 @@ #define DNS323_GPIO_LED_RIGHT_AMBER 1 #define DNS323_GPIO_LED_LEFT_AMBER 2 #define DNS323_GPIO_SYSTEM_UP 3 -#define DNS323_GPIO_LED_POWER 5 +#define DNS323_GPIO_LED_POWER1 4 +#define DNS323_GPIO_LED_POWER2 5 #define DNS323_GPIO_OVERTEMP 6 #define DNS323_GPIO_RTC 7 #define DNS323_GPIO_POWER_OFF 8 @@ -237,11 +238,31 @@ error_fail: * GPIO LEDs (simple - doesn't use hardware blinking support) */ +#define ORION_BLINK_HALF_PERIOD 100 /* ms */ + +static int dns323_gpio_blink_set(unsigned gpio, + unsigned long *delay_on, unsigned long *delay_off) +{ + static int value = 0; + + if (!*delay_on && !*delay_off) + *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; + + if (ORION_BLINK_HALF_PERIOD == *delay_on + && ORION_BLINK_HALF_PERIOD == *delay_off) { + value = !value; + orion_gpio_set_blink(gpio, value); + return 0; + } + + return -EINVAL; +} + static struct gpio_led dns323_leds[] = { { .name = "power:blue", - .gpio = DNS323_GPIO_LED_POWER, - .default_state = LEDS_GPIO_DEFSTATE_ON, + .gpio = DNS323_GPIO_LED_POWER2, + .default_trigger = "timer", }, { .name = "right:amber", .gpio = DNS323_GPIO_LED_RIGHT_AMBER, @@ -256,6 +277,7 @@ static struct gpio_led dns323_leds[] = { static struct gpio_led_platform_data dns323_led_data = { .num_leds = ARRAY_SIZE(dns323_leds), .leds = dns323_leds, + .gpio_blink_set = dns323_gpio_blink_set, }; static struct platform_device dns323_gpio_leds = { @@ -412,6 +434,14 @@ static void __init dns323_init(void) orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); platform_device_register(&dns323_nor_flash); + /* The 5181 power LED is active low and requires + * DNS323_GPIO_LED_POWER1 to also be low. + */ + if (dns323_dev_id() == MV88F5181_DEV_ID) { + dns323_leds[0].active_low = 1; + gpio_direction_output(DNS323_GPIO_LED_POWER1, 0); + } + platform_device_register(&dns323_gpio_leds); platform_device_register(&dns323_button_device); diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c new file mode 100644 index 000000000000..8e569be6e2c7 --- /dev/null +++ b/arch/arm/mach-orion5x/ls_hgl-setup.c @@ -0,0 +1,276 @@ +/* + * arch/arm/mach-orion5x/ls_hgl-setup.c + * + * Maintainer: Zhu Qingsen <[email protected]> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/mtd/physmap.h> +#include <linux/mv643xx_eth.h> +#include <linux/leds.h> +#include <linux/gpio_keys.h> +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/ata_platform.h> +#include <linux/gpio.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/system.h> +#include <mach/orion5x.h> +#include "common.h" +#include "mpp.h" + +/***************************************************************************** + * Linkstation LS-HGL Info + ****************************************************************************/ + +/* + * 256K NOR flash Device bus boot chip select + */ + +#define LS_HGL_NOR_BOOT_BASE 0xf4000000 +#define LS_HGL_NOR_BOOT_SIZE SZ_256K + +/***************************************************************************** + * 256KB NOR Flash on BOOT Device + ****************************************************************************/ + +static struct physmap_flash_data ls_hgl_nor_flash_data = { + .width = 1, +}; + +static struct resource ls_hgl_nor_flash_resource = { + .flags = IORESOURCE_MEM, + .start = LS_HGL_NOR_BOOT_BASE, + .end = LS_HGL_NOR_BOOT_BASE + LS_HGL_NOR_BOOT_SIZE - 1, +}; + +static struct platform_device ls_hgl_nor_flash = { + .name = "physmap-flash", + .id = 0, + .dev = { + .platform_data = &ls_hgl_nor_flash_data, + }, + .num_resources = 1, + .resource = &ls_hgl_nor_flash_resource, +}; + +/***************************************************************************** + * Ethernet + ****************************************************************************/ + +static struct mv643xx_eth_platform_data ls_hgl_eth_data = { + .phy_addr = 8, +}; + +/***************************************************************************** + * RTC 5C372a on I2C bus + ****************************************************************************/ + +static struct i2c_board_info __initdata ls_hgl_i2c_rtc = { + I2C_BOARD_INFO("rs5c372a", 0x32), +}; + +/***************************************************************************** + * LEDs attached to GPIO + ****************************************************************************/ + +#define LS_HGL_GPIO_LED_ALARM 2 +#define LS_HGL_GPIO_LED_INFO 3 +#define LS_HGL_GPIO_LED_FUNC 17 +#define LS_HGL_GPIO_LED_PWR 0 + + +static struct gpio_led ls_hgl_led_pins[] = { + { + .name = "alarm:red", + .gpio = LS_HGL_GPIO_LED_ALARM, + .active_low = 1, + }, { + .name = "info:amber", + .gpio = LS_HGL_GPIO_LED_INFO, + .active_low = 1, + }, { + .name = "func:blue:top", + .gpio = LS_HGL_GPIO_LED_FUNC, + .active_low = 1, + }, { + .name = "power:blue:bottom", + .gpio = LS_HGL_GPIO_LED_PWR, + }, +}; + +static struct gpio_led_platform_data ls_hgl_led_data = { + .leds = ls_hgl_led_pins, + .num_leds = ARRAY_SIZE(ls_hgl_led_pins), +}; + +static struct platform_device ls_hgl_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &ls_hgl_led_data, + }, +}; + +/**************************************************************************** + * GPIO Attached Keys + ****************************************************************************/ +#define LS_HGL_GPIO_KEY_FUNC 15 +#define LS_HGL_GPIO_KEY_POWER 8 +#define LS_HGL_GPIO_KEY_AUTOPOWER 10 + +#define LS_HGL_SW_POWER 0x00 +#define LS_HGL_SW_AUTOPOWER 0x01 + +static struct gpio_keys_button ls_hgl_buttons[] = { + { + .code = KEY_OPTION, + .gpio = LS_HGL_GPIO_KEY_FUNC, + .desc = "Function Button", + .active_low = 1, + }, { + .type = EV_SW, + .code = LS_HGL_SW_POWER, + .gpio = LS_HGL_GPIO_KEY_POWER, + .desc = "Power-on Switch", + .active_low = 1, + }, { + .type = EV_SW, + .code = LS_HGL_SW_AUTOPOWER, + .gpio = LS_HGL_GPIO_KEY_AUTOPOWER, + .desc = "Power-auto Switch", + .active_low = 1, + }, +}; + +static struct gpio_keys_platform_data ls_hgl_button_data = { + .buttons = ls_hgl_buttons, + .nbuttons = ARRAY_SIZE(ls_hgl_buttons), +}; + +static struct platform_device ls_hgl_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &ls_hgl_button_data, + }, +}; + + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct mv_sata_platform_data ls_hgl_sata_data = { + .n_ports = 2, +}; + + +/***************************************************************************** + * Linkstation LS-HGL specific power off method: reboot + ****************************************************************************/ +/* + * On the Linkstation LS-HGL, the shutdown process is following: + * - Userland monitors key events until the power switch goes to off position + * - The board reboots + * - U-boot starts and goes into an idle mode waiting for the user + * to move the switch to ON position + */ + +static void ls_hgl_power_off(void) +{ + arm_machine_restart('h', NULL); +} + + +/***************************************************************************** + * General Setup + ****************************************************************************/ + +#define LS_HGL_GPIO_USB_POWER 9 +#define LS_HGL_GPIO_AUTO_POWER 10 +#define LS_HGL_GPIO_POWER 8 + +#define LS_HGL_GPIO_HDD_POWER 1 + +static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = { + { 0, MPP_GPIO }, /* LED_PWR */ + { 1, MPP_GPIO }, /* HDD_PWR */ + { 2, MPP_GPIO }, /* LED_ALARM */ + { 3, MPP_GPIO }, /* LED_INFO */ + { 4, MPP_UNUSED }, + { 5, MPP_UNUSED }, + { 6, MPP_GPIO }, /* FAN_LCK */ + { 7, MPP_GPIO }, /* INIT */ + { 8, MPP_GPIO }, /* POWER */ + { 9, MPP_GPIO }, /* USB_PWR */ + { 10, MPP_GPIO }, /* AUTO_POWER */ + { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ + { 12, MPP_UNUSED }, + { 13, MPP_UNUSED }, + { 14, MPP_UNUSED }, + { 15, MPP_GPIO }, /* FUNC */ + { 16, MPP_UNUSED }, + { 17, MPP_GPIO }, /* LED_FUNC */ + { 18, MPP_UNUSED }, + { 19, MPP_UNUSED }, + { -1 }, +}; + +static void __init ls_hgl_init(void) +{ + /* + * Setup basic Orion functions. Need to be called early. + */ + orion5x_init(); + + orion5x_mpp_conf(ls_hgl_mpp_modes); + + /* + * Configure peripherals. + */ + orion5x_ehci0_init(); + orion5x_ehci1_init(); + orion5x_eth_init(&ls_hgl_eth_data); + orion5x_i2c_init(); + orion5x_sata_init(&ls_hgl_sata_data); + orion5x_uart0_init(); + orion5x_xor_init(); + + orion5x_setup_dev_boot_win(LS_HGL_NOR_BOOT_BASE, + LS_HGL_NOR_BOOT_SIZE); + platform_device_register(&ls_hgl_nor_flash); + + platform_device_register(&ls_hgl_button_device); + + platform_device_register(&ls_hgl_leds); + + i2c_register_board_info(0, &ls_hgl_i2c_rtc, 1); + + /* enable USB power */ + gpio_set_value(LS_HGL_GPIO_USB_POWER, 1); + + /* register power-off method */ + pm_power_off = ls_hgl_power_off; + + pr_info("%s: finished\n", __func__); +} + +MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL") + /* Maintainer: Zhu Qingsen <[email protected]> */ + .phys_io = ORION5X_REGS_PHYS_BASE, + .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, + .boot_params = 0x00000100, + .init_machine = ls_hgl_init, + .map_io = orion5x_map_io, + .init_irq = orion5x_init_irq, + .timer = &orion5x_timer, + .fixup = tag_fixup_mem32, +MACHINE_END diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index c9bf6b81a80d..c704f056de1e 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c @@ -11,7 +11,6 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/platform_device.h> -#include <linux/pci.h> #include <linux/mtd/physmap.h> #include <linux/mv643xx_eth.h> #include <linux/leds.h> @@ -19,12 +18,13 @@ #include <linux/input.h> #include <linux/i2c.h> #include <linux/ata_platform.h> -#include <asm/mach-types.h> #include <linux/gpio.h> +#include <asm/mach-types.h> #include <asm/mach/arch.h> +#include <asm/system.h> +#include <mach/orion5x.h> #include "common.h" #include "mpp.h" -#include "include/mach/system.h" /***************************************************************************** * Linkstation Mini Info @@ -186,7 +186,7 @@ static struct mv_sata_platform_data lsmini_sata_data = { static void lsmini_power_off(void) { - arch_reset(0, NULL); + arm_machine_restart('h', NULL); } diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index dee92182749b..38fbd0a0e402 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -115,6 +115,11 @@ config MACH_CM_X300 select CPU_PXA310 select HAVE_PWM +config MACH_CAPC7117 + bool "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM" + select CPU_PXA320 + select PXA3xx + config ARCH_GUMSTIX bool "Gumstix XScale 255 boards" select PXA25x @@ -417,6 +422,24 @@ config MACH_TREO680 Say Y here if you intend to run this kernel on Palm Treo 680 smartphone. +config MACH_RAUMFELD_RC + bool "Raumfeld Controller" + select PXA3xx + select CPU_PXA300 + select HAVE_PWM + +config MACH_RAUMFELD_CONNECTOR + bool "Raumfeld Connector" + select PXA3xx + select CPU_PXA300 + select PXA_SSP + +config MACH_RAUMFELD_SPEAKER + bool "Raumfeld Speaker" + select PXA3xx + select CPU_PXA300 + select PXA_SSP + config PXA_SHARPSL bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" select SHARP_SCOOP @@ -435,6 +458,7 @@ config SHARPSL_PM config CORGI_SSP_DEPRECATED bool select PXA_SSP + select PXA_SSP_LEGACY help This option will include corgi_ssp.c and corgi_lcd.c that corgi_ts.c and other legacy drivers (corgi_bl.c @@ -446,6 +470,7 @@ config MACH_POODLE select PXA25x select SHARP_LOCOMO select PXA_SSP + select PXA_HAVE_BOARD_IRQS config MACH_CORGI bool "Enable Sharp SL-C700 (Corgi) Support" @@ -492,6 +517,11 @@ config MACH_TOSA select PXA25x select PXA_HAVE_BOARD_IRQS +config MACH_ICONTROL + bool "TMT iControl/SafeTCam based on the MXM-8x10 CoM" + select CPU_PXA320 + select PXA3xx + config ARCH_PXA_ESERIES bool "PXA based Toshiba e-series PDAs" select PXA25x @@ -629,6 +659,11 @@ config PXA_SSP help Enable support for PXA2xx SSP ports +config PXA_SSP_LEGACY + bool + help + Support of legacy SSP API + config TOSA_BT tristate "Control the state of built-in bluetooth chip on Sharp SL-6000" depends on MACH_TOSA diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index f64afda7e6f6..86bc87b7f2dd 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o endif obj-$(CONFIG_MACH_EM_X270) += em-x270.o obj-$(CONFIG_MACH_CM_X300) += cm-x300.o +obj-$(CONFIG_MACH_CAPC7117) += capc7117.o mxm8x10.o obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o @@ -82,6 +83,7 @@ obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o obj-$(CONFIG_MACH_POODLE) += poodle.o obj-$(CONFIG_MACH_TOSA) += tosa.o +obj-$(CONFIG_MACH_ICONTROL) += icontrol.o mxm8x10.o obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o obj-$(CONFIG_MACH_E330) += e330.o obj-$(CONFIG_MACH_E350) += e350.o @@ -89,6 +91,9 @@ obj-$(CONFIG_MACH_E740) += e740.o obj-$(CONFIG_MACH_E750) += e750.o obj-$(CONFIG_MACH_E400) += e400.o obj-$(CONFIG_MACH_E800) += e800.o +obj-$(CONFIG_MACH_RAUMFELD_RC) += raumfeld.o +obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o +obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o # Support for blinky lights led-y := leds.o diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index b8cd07ca9380..f3b5ace815e5 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c @@ -132,6 +132,14 @@ static void __init balloon3_init_irq(void) "enabled\n", __func__, BALLOON3_AUX_NIRQ); } +static unsigned long balloon3_ac97_pin_config[] = { + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + GPIO113_AC97_nRESET, +}; + static void balloon3_backlight_power(int on) { pr_debug("%s: power is %s\n", __func__, on ? "on" : "off"); @@ -140,26 +148,7 @@ static void balloon3_backlight_power(int on) static unsigned long balloon3_lcd_pin_config[] = { /* LCD - 16bpp Active TFT */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, GPIO99_GPIO, /* Backlight */ }; @@ -311,8 +300,10 @@ static void __init balloon3_init(void) pxa_set_stuart_info(NULL); pxa_set_i2c_info(NULL); - if (balloon3_has(BALLOON3_FEATURE_AUDIO)) + if (balloon3_has(BALLOON3_FEATURE_AUDIO)) { + pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ac97_pin_config)); pxa_set_ac97_info(NULL); + } if (balloon3_has(BALLOON3_FEATURE_TOPPOLY)) { pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_lcd_pin_config)); diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c new file mode 100644 index 000000000000..aae544631a8b --- /dev/null +++ b/arch/arm/mach-pxa/capc7117.c @@ -0,0 +1,158 @@ +/* + * linux/arch/arm/mach-pxa/capc7117.c + * + * Support for the Embedian CAPC-7117 Evaluation Kit + * based on the Embedian MXM-8x10 Computer on Module + * + * Copyright (C) 2009 Embedian Inc. + * Copyright (C) 2009 TMT Services & Supplies (Pty) Ltd. + * + * 2007-09-04: eric miao <[email protected]> + * rewrite to align with latest kernel + * + * 2010-01-09: Edwin Peer <[email protected]> + * Hennie van der Merwe <[email protected]> + * rework for upstream merge + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/ata_platform.h> +#include <linux/serial_8250.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/pxa320.h> +#include <mach/mxm8x10.h> + +#include "generic.h" + +/* IDE (PATA) Support */ +static struct pata_platform_info pata_platform_data = { + .ioport_shift = 1 +}; + +static struct resource capc7117_ide_resources[] = { + [0] = { + .start = 0x11000020, + .end = 0x1100003f, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = 0x1100001c, + .end = 0x1100001c, + .flags = IORESOURCE_MEM + }, + [2] = { + .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), + .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING + } +}; + +static struct platform_device capc7117_ide_device = { + .name = "pata_platform", + .num_resources = ARRAY_SIZE(capc7117_ide_resources), + .resource = capc7117_ide_resources, + .dev = { + .platform_data = &pata_platform_data, + .coherent_dma_mask = ~0 /* grumble */ + } +}; + +static void __init capc7117_ide_init(void) +{ + platform_device_register(&capc7117_ide_device); +} + +/* TI16C752 UART support */ +#define TI16C752_FLAGS (UPF_BOOT_AUTOCONF | \ + UPF_IOREMAP | \ + UPF_BUGGY_UART | \ + UPF_SKIP_TEST) +#define TI16C752_UARTCLK (22118400) +static struct plat_serial8250_port ti16c752_platform_data[] = { + [0] = { + .mapbase = 0x14000000, + .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO78)), + .irqflags = IRQF_TRIGGER_RISING, + .flags = TI16C752_FLAGS, + .iotype = UPIO_MEM, + .regshift = 1, + .uartclk = TI16C752_UARTCLK + }, + [1] = { + .mapbase = 0x14000040, + .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO79)), + .irqflags = IRQF_TRIGGER_RISING, + .flags = TI16C752_FLAGS, + .iotype = UPIO_MEM, + .regshift = 1, + .uartclk = TI16C752_UARTCLK + }, + [2] = { + .mapbase = 0x14000080, + .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO80)), + .irqflags = IRQF_TRIGGER_RISING, + .flags = TI16C752_FLAGS, + .iotype = UPIO_MEM, + .regshift = 1, + .uartclk = TI16C752_UARTCLK + }, + [3] = { + .mapbase = 0x140000c0, + .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO81)), + .irqflags = IRQF_TRIGGER_RISING, + .flags = TI16C752_FLAGS, + .iotype = UPIO_MEM, + .regshift = 1, + .uartclk = TI16C752_UARTCLK + }, + [4] = { + /* end of array */ + } +}; + +static struct platform_device ti16c752_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = ti16c752_platform_data + } +}; + +static void __init capc7117_uarts_init(void) +{ + platform_device_register(&ti16c752_device); +} + +static void __init capc7117_init(void) +{ + /* Init CoM */ + mxm_8x10_barebones_init(); + + /* Init evaluation board peripherals */ + mxm_8x10_ac97_init(); + mxm_8x10_usb_host_init(); + mxm_8x10_mmc_init(); + + capc7117_uarts_init(); + capc7117_ide_init(); +} + +MACHINE_START(CAPC7117, + "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM") + .phys_io = 0x40000000, + .boot_params = 0xa0000100, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, + .init_machine = capc7117_init +MACHINE_END diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c index 253fd76142d6..f1a7703d771b 100644 --- a/arch/arm/mach-pxa/cm-x255.c +++ b/arch/arm/mach-pxa/cm-x255.c @@ -50,26 +50,7 @@ static unsigned long cmx255_pin_config[] = { GPIO47_STUART_TXD, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* SSP1 */ GPIO23_SSP1_SCLK, diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index eea78b6c2bc5..a9926bb75922 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c @@ -71,26 +71,7 @@ static unsigned long cmx270_pin_config[] = { GPIO111_MMC_DAT_3, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* I2C */ GPIO117_I2C_SCL, @@ -195,33 +176,57 @@ static struct resource cmx270_2700G_resource[] = { }, }; -static unsigned long save_lcd_regs[10]; +static unsigned long cmx270_marathon_on[] = { + GPIO58_GPIO, + GPIO59_GPIO, + GPIO60_GPIO, + GPIO61_GPIO, + GPIO62_GPIO, + GPIO63_GPIO, + GPIO64_GPIO, + GPIO65_GPIO, + GPIO66_GPIO, + GPIO67_GPIO, + GPIO68_GPIO, + GPIO69_GPIO, + GPIO70_GPIO, + GPIO71_GPIO, + GPIO72_GPIO, + GPIO73_GPIO, + GPIO74_GPIO, + GPIO75_GPIO, + GPIO76_GPIO, + GPIO77_GPIO, +}; + +static unsigned long cmx270_marathon_off[] = { + GPIOxx_LCD_TFT_16BPP, +}; static int cmx270_marathon_probe(struct fb_info *fb) { - /* save PXA-270 pin settings before enabling 2700G */ - save_lcd_regs[0] = GPDR1; - save_lcd_regs[1] = GPDR2; - save_lcd_regs[2] = GAFR1_U; - save_lcd_regs[3] = GAFR2_L; - save_lcd_regs[4] = GAFR2_U; - - /* Disable PXA-270 on-chip controller driving pins */ - GPDR1 &= ~(0xfc000000); - GPDR2 &= ~(0x00c03fff); - GAFR1_U &= ~(0xfff00000); - GAFR2_L &= ~(0x0fffffff); - GAFR2_U &= ~(0x0000f000); + int gpio, err; + + for (gpio = 58; gpio <= 77; gpio++) { + err = gpio_request(gpio, "LCD"); + if (err) + return err; + gpio_direction_input(gpio); + } + + pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_marathon_on)); return 0; } static int cmx270_marathon_remove(struct fb_info *fb) { - GPDR1 = save_lcd_regs[0]; - GPDR2 = save_lcd_regs[1]; - GAFR1_U = save_lcd_regs[2]; - GAFR2_L = save_lcd_regs[3]; - GAFR2_U = save_lcd_regs[4]; + int gpio; + + pxa2xx_mfp_config(ARRAY_AND_SIZE(cmx270_marathon_off)); + + for (gpio = 58; gpio <= 77; gpio++) + gpio_free(gpio); + return 0; } diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index 7873fa3d8fa4..161fc2d61207 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c @@ -59,7 +59,7 @@ void __init cmx2xx_pci_adjust_zones(int node, unsigned long *zone_size, static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc) { /* clear our parent irq */ - GEDR(cmx2xx_it8152_irq_gpio) = GPIO_bit(cmx2xx_it8152_irq_gpio); + desc->chip->ack(irq); it8152_irq_demux(irq, desc); } diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c index 94b23a9e3877..d578021d1a10 100644 --- a/arch/arm/mach-pxa/e740.c +++ b/arch/arm/mach-pxa/e740.c @@ -134,6 +134,12 @@ static unsigned long e740_pin_config[] __initdata = { /* IrDA */ GPIO38_GPIO | MFP_LPM_DRIVE_HIGH, + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + /* Audio power control */ GPIO16_GPIO, /* AC97 codec AVDD2 supply (analogue power) */ GPIO40_GPIO, /* Mic amp power */ diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c index 5eccbce73a33..af83caa52dd4 100644 --- a/arch/arm/mach-pxa/e750.c +++ b/arch/arm/mach-pxa/e750.c @@ -132,6 +132,12 @@ static unsigned long e750_pin_config[] __initdata = { /* IrDA */ GPIO38_GPIO | MFP_LPM_DRIVE_HIGH, + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + /* Audio power control */ GPIO4_GPIO, /* Headphone amp power */ GPIO7_GPIO, /* Speaker amp power */ diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c index aad129bed199..8ea97bf53fe1 100644 --- a/arch/arm/mach-pxa/e800.c +++ b/arch/arm/mach-pxa/e800.c @@ -35,6 +35,14 @@ /* ------------------------ e800 LCD definitions ------------------------- */ +static unsigned long e800_pin_config[] __initdata = { + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, +}; + static struct w100_gen_regs e800_lcd_regs = { .lcd_format = 0x00008003, .lcdd_cntl1 = 0x02a00000, @@ -195,6 +203,7 @@ static struct platform_device *devices[] __initdata = { static void __init e800_init(void) { + pxa2xx_mfp_config(ARRAY_AND_SIZE(e800_pin_config)); pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index c8a01bc85fde..aab04f33e49b 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -109,26 +109,7 @@ static unsigned long common_pin_config[] = { GPIO111_MMC_DAT_3, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* QCI */ GPIO84_CIF_FV, diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c new file mode 100644 index 000000000000..771137fc1a82 --- /dev/null +++ b/arch/arm/mach-pxa/icontrol.c @@ -0,0 +1,202 @@ +/* + * linux/arch/arm/mach-pxa/icontrol.c + * + * Support for the iControl and SafeTcam platforms from TMT Services + * using the Embedian MXM-8x10 Computer on Module + * + * Copyright (C) 2009 TMT Services & Supplies (Pty) Ltd. + * + * 2010-01-21 Hennie van der Merve <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/irq.h> +#include <linux/platform_device.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/pxa320.h> +#include <mach/mxm8x10.h> + +#include <linux/spi/spi.h> +#include <mach/pxa2xx_spi.h> +#include <linux/can/platform/mcp251x.h> + +#include "generic.h" + +#define ICONTROL_MCP251x_nCS1 (15) +#define ICONTROL_MCP251x_nCS2 (16) +#define ICONTROL_MCP251x_nCS3 (17) +#define ICONTROL_MCP251x_nCS4 (24) + +#define ICONTROL_MCP251x_nIRQ1 (74) +#define ICONTROL_MCP251x_nIRQ2 (75) +#define ICONTROL_MCP251x_nIRQ3 (76) +#define ICONTROL_MCP251x_nIRQ4 (77) + +static struct pxa2xx_spi_chip mcp251x_chip_info1 = { + .tx_threshold = 8, + .rx_threshold = 128, + .dma_burst_size = 8, + .timeout = 235, + .gpio_cs = ICONTROL_MCP251x_nCS1 +}; + +static struct pxa2xx_spi_chip mcp251x_chip_info2 = { + .tx_threshold = 8, + .rx_threshold = 128, + .dma_burst_size = 8, + .timeout = 235, + .gpio_cs = ICONTROL_MCP251x_nCS2 +}; + +static struct pxa2xx_spi_chip mcp251x_chip_info3 = { + .tx_threshold = 8, + .rx_threshold = 128, + .dma_burst_size = 8, + .timeout = 235, + .gpio_cs = ICONTROL_MCP251x_nCS3 +}; + +static struct pxa2xx_spi_chip mcp251x_chip_info4 = { + .tx_threshold = 8, + .rx_threshold = 128, + .dma_burst_size = 8, + .timeout = 235, + .gpio_cs = ICONTROL_MCP251x_nCS4 +}; + +static struct mcp251x_platform_data mcp251x_info = { + .oscillator_frequency = 16E6, + .model = CAN_MCP251X_MCP2515, + .board_specific_setup = NULL, + .power_enable = NULL, + .transceiver_enable = NULL +}; + +static struct spi_board_info mcp251x_board_info[] = { + { + .modalias = "mcp251x", + .max_speed_hz = 6500000, + .bus_num = 3, + .chip_select = 0, + .platform_data = &mcp251x_info, + .controller_data = &mcp251x_chip_info1, + .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ1) + }, + { + .modalias = "mcp251x", + .max_speed_hz = 6500000, + .bus_num = 3, + .chip_select = 1, + .platform_data = &mcp251x_info, + .controller_data = &mcp251x_chip_info2, + .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ2) + }, + { + .modalias = "mcp251x", + .max_speed_hz = 6500000, + .bus_num = 4, + .chip_select = 0, + .platform_data = &mcp251x_info, + .controller_data = &mcp251x_chip_info3, + .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ3) + }, + { + .modalias = "mcp251x", + .max_speed_hz = 6500000, + .bus_num = 4, + .chip_select = 1, + .platform_data = &mcp251x_info, + .controller_data = &mcp251x_chip_info4, + .irq = gpio_to_irq(ICONTROL_MCP251x_nIRQ4) + } +}; + +static struct pxa2xx_spi_master pxa_ssp3_spi_master_info = { + .clock_enable = CKEN_SSP3, + .num_chipselect = 2, + .enable_dma = 1 +}; + +static struct pxa2xx_spi_master pxa_ssp4_spi_master_info = { + .clock_enable = CKEN_SSP4, + .num_chipselect = 2, + .enable_dma = 1 +}; + +struct platform_device pxa_spi_ssp3 = { + .name = "pxa2xx-spi", + .id = 3, + .dev = { + .platform_data = &pxa_ssp3_spi_master_info, + } +}; + +struct platform_device pxa_spi_ssp4 = { + .name = "pxa2xx-spi", + .id = 4, + .dev = { + .platform_data = &pxa_ssp4_spi_master_info, + } +}; + +static struct platform_device *icontrol_spi_devices[] __initdata = { + &pxa_spi_ssp3, + &pxa_spi_ssp4, +}; + +static mfp_cfg_t mfp_can_cfg[] __initdata = { + /* CAN CS lines */ + GPIO15_GPIO, + GPIO16_GPIO, + GPIO17_GPIO, + GPIO24_GPIO, + + /* SPI (SSP3) lines */ + GPIO89_SSP3_SCLK, + GPIO91_SSP3_TXD, + GPIO92_SSP3_RXD, + + /* SPI (SSP4) lines */ + GPIO93_SSP4_SCLK, + GPIO95_SSP4_TXD, + GPIO96_SSP4_RXD, + + /* CAN nIRQ lines */ + GPIO74_GPIO | MFP_LPM_EDGE_RISE, + GPIO75_GPIO | MFP_LPM_EDGE_RISE, + GPIO76_GPIO | MFP_LPM_EDGE_RISE, + GPIO77_GPIO | MFP_LPM_EDGE_RISE +}; + +static void __init icontrol_can_init(void) +{ + pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_can_cfg)); + platform_add_devices(ARRAY_AND_SIZE(icontrol_spi_devices)); + spi_register_board_info(ARRAY_AND_SIZE(mcp251x_board_info)); +} + +static void __init icontrol_init(void) +{ + mxm_8x10_barebones_init(); + mxm_8x10_usb_host_init(); + mxm_8x10_mmc_init(); + + icontrol_can_init(); +} + +MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM") + .phys_io = 0x40000000, + .boot_params = 0xa0000100, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, + .init_machine = icontrol_init +MACHINE_END diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index 5c9e11d74f49..bc78c4dc0c66 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c @@ -47,25 +47,7 @@ static unsigned long idp_pin_config[] __initdata = { /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, + GPIOxx_LCD_DSTN_16BPP, /* BTUART */ GPIO42_BTUART_RXD, diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c index 5b0862df61ab..b2f878bd460b 100644 --- a/arch/arm/mach-pxa/imote2.c +++ b/arch/arm/mach-pxa/imote2.c @@ -64,7 +64,6 @@ static unsigned long imote2_pin_config[] __initdata = { GPIO116_GPIO, /* CC_CCA */ GPIO0_GPIO, /* CC_FIFOP */ GPIO16_GPIO, /* CCSFD */ - GPIO39_GPIO, /* CSn */ GPIO115_GPIO, /* Power enable */ /* I2C */ @@ -72,7 +71,7 @@ static unsigned long imote2_pin_config[] __initdata = { GPIO118_I2C_SDA, /* SSP 3 - 802.15.4 radio */ - GPIO39_GPIO, /* Chip Select */ + GPIO39_GPIO, /* Chip Select */ GPIO34_SSP3_SCLK, GPIO35_SSP3_TXD, GPIO41_SSP3_RXD, diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h index bfec09b1814b..1a741065045f 100644 --- a/arch/arm/mach-pxa/include/mach/balloon3.h +++ b/arch/arm/mach-pxa/include/mach/balloon3.h @@ -129,6 +129,16 @@ enum balloon3_features { #define CPLD_AROUTING_LOONR2INT_BIT 6 #define CPLD_AROUTING_LOONR2EXT_BIT 7 +/* Balloon3 Interrupts */ +#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) + +#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) +#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) + +#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ) +#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) +#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) + extern int balloon3_has(enum balloon3_features feature); #endif diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h index 3677a9af9c87..ffc8314520f2 100644 --- a/arch/arm/mach-pxa/include/mach/irqs.h +++ b/arch/arm/mach-pxa/include/mach/irqs.h @@ -135,82 +135,6 @@ #define IRQ_BOARD_END (IRQ_BOARD_START + 16) #endif -#define IRQ_SA1111_START (IRQ_BOARD_END) -#define IRQ_GPAIN0 (IRQ_BOARD_END + 0) -#define IRQ_GPAIN1 (IRQ_BOARD_END + 1) -#define IRQ_GPAIN2 (IRQ_BOARD_END + 2) -#define IRQ_GPAIN3 (IRQ_BOARD_END + 3) -#define IRQ_GPBIN0 (IRQ_BOARD_END + 4) -#define IRQ_GPBIN1 (IRQ_BOARD_END + 5) -#define IRQ_GPBIN2 (IRQ_BOARD_END + 6) -#define IRQ_GPBIN3 (IRQ_BOARD_END + 7) -#define IRQ_GPBIN4 (IRQ_BOARD_END + 8) -#define IRQ_GPBIN5 (IRQ_BOARD_END + 9) -#define IRQ_GPCIN0 (IRQ_BOARD_END + 10) -#define IRQ_GPCIN1 (IRQ_BOARD_END + 11) -#define IRQ_GPCIN2 (IRQ_BOARD_END + 12) -#define IRQ_GPCIN3 (IRQ_BOARD_END + 13) -#define IRQ_GPCIN4 (IRQ_BOARD_END + 14) -#define IRQ_GPCIN5 (IRQ_BOARD_END + 15) -#define IRQ_GPCIN6 (IRQ_BOARD_END + 16) -#define IRQ_GPCIN7 (IRQ_BOARD_END + 17) -#define IRQ_MSTXINT (IRQ_BOARD_END + 18) -#define IRQ_MSRXINT (IRQ_BOARD_END + 19) -#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) -#define IRQ_TPTXINT (IRQ_BOARD_END + 21) -#define IRQ_TPRXINT (IRQ_BOARD_END + 22) -#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) -#define SSPXMTINT (IRQ_BOARD_END + 24) -#define SSPRCVINT (IRQ_BOARD_END + 25) -#define SSPROR (IRQ_BOARD_END + 26) -#define AUDXMTDMADONEA (IRQ_BOARD_END + 32) -#define AUDRCVDMADONEA (IRQ_BOARD_END + 33) -#define AUDXMTDMADONEB (IRQ_BOARD_END + 34) -#define AUDRCVDMADONEB (IRQ_BOARD_END + 35) -#define AUDTFSR (IRQ_BOARD_END + 36) -#define AUDRFSR (IRQ_BOARD_END + 37) -#define AUDTUR (IRQ_BOARD_END + 38) -#define AUDROR (IRQ_BOARD_END + 39) -#define AUDDTS (IRQ_BOARD_END + 40) -#define AUDRDD (IRQ_BOARD_END + 41) -#define AUDSTO (IRQ_BOARD_END + 42) -#define IRQ_USBPWR (IRQ_BOARD_END + 43) -#define IRQ_HCIM (IRQ_BOARD_END + 44) -#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45) -#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46) -#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47) -#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48) -#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49) -#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50) -#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51) -#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52) -#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53) -#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) - -#define IRQ_LOCOMO_START (IRQ_BOARD_END) -#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) -#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) -#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) -#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) -#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4) -#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5) -#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6) -#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7) -#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8) -#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9) -#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10) -#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11) -#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12) -#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13) -#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14) -#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15) -#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16) -#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) -#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) -#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) -#define IRQ_LOCOMO_SPI_OVRN (IRQ_BOARD_END + 20) -#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) - /* * Figure out the MAX IRQ number. * @@ -219,89 +143,16 @@ * Otherwise, we have the standard IRQs only. */ #ifdef CONFIG_SA1111 -#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) -#elif defined(CONFIG_SHARP_LOCOMO) -#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) +#define NR_IRQS (IRQ_BOARD_END + 55) #elif defined(CONFIG_PXA_HAVE_BOARD_IRQS) #define NR_IRQS (IRQ_BOARD_END) #else #define NR_IRQS (IRQ_BOARD_START) #endif -/* - * Board specific IRQs. Define them here. - * Do not surround them with ifdefs. - */ -#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) -#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) -#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) -#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ -#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) -#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) -#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) -#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ -#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) - -#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) -#define LPD270_USBC_IRQ LPD270_IRQ(2) -#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) -#define LPD270_AC97_IRQ LPD270_IRQ(4) - -#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) -#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) -#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) -#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) -#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) -#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) -#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) -#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) -#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) -#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) -#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) -#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) -#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) -#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) -#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) - -/* Balloon3 Interrupts */ -#define BALLOON3_IRQ(x) (IRQ_BOARD_START + (x)) - -#define BALLOON3_BP_CF_NRDY_IRQ BALLOON3_IRQ(0) -#define BALLOON3_BP_NSTSCHG_IRQ BALLOON3_IRQ(1) - -#define BALLOON3_AUX_NIRQ IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ) -#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) -#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) - -/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ -#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) -#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) -#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) -#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) - -/* phyCORE-PXA270 (PCM027) Interrupts */ -#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) -#define PCM027_BTDET_IRQ PCM027_IRQ(0) -#define PCM027_FF_RI_IRQ PCM027_IRQ(1) -#define PCM027_MMCDET_IRQ PCM027_IRQ(2) -#define PCM027_PM_5V_IRQ PCM027_IRQ(3) - -/* ITE8152 irqs */ /* add IT8152 IRQs beyond BOARD_END */ #ifdef CONFIG_PCI_HOST_ITE8152 -#define IT8152_IRQ(x) (IRQ_BOARD_END + (x)) - -/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ -#define IT8152_LD_IRQ_COUNT 9 -#define IT8152_LP_IRQ_COUNT 16 -#define IT8152_PD_IRQ_COUNT 15 - -/* Priorities: */ -#define IT8152_PD_IRQ(i) IT8152_IRQ(i) -#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) -#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) - -#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1) +#define IT8152_LAST_IRQ (IRQ_BOARD_END + 40) #if NR_IRQS < (IT8152_LAST_IRQ+1) #undef NR_IRQS diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h index f89fb715266b..0e6440c81683 100644 --- a/arch/arm/mach-pxa/include/mach/lpd270.h +++ b/arch/arm/mach-pxa/include/mach/lpd270.h @@ -34,5 +34,9 @@ #define LPD270_INT_ETHERNET (1 << 3) /* Ethernet controller IRQ */ #define LPD270_INT_USBC (1 << 2) /* USB client cable detection IRQ */ +#define LPD270_IRQ(x) (IRQ_BOARD_START + (x)) +#define LPD270_USBC_IRQ LPD270_IRQ(2) +#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) +#define LPD270_AC97_IRQ LPD270_IRQ(4) #endif diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h index 751b74811d0f..a0d4247f08fc 100644 --- a/arch/arm/mach-pxa/include/mach/lubbock.h +++ b/arch/arm/mach-pxa/include/mach/lubbock.h @@ -34,6 +34,17 @@ #define LUB_IRQ_SET_CLR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0) #define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100) +/* Board specific IRQs */ +#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x)) +#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0) +#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1) +#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */ +#define LUBBOCK_ETH_IRQ LUBBOCK_IRQ(3) +#define LUBBOCK_UCB1400_IRQ LUBBOCK_IRQ(4) +#define LUBBOCK_BB_IRQ LUBBOCK_IRQ(5) +#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ +#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) + #ifndef __ASSEMBLY__ extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); #endif diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h index 3461c4302ff4..86e623abd64d 100644 --- a/arch/arm/mach-pxa/include/mach/mainstone.h +++ b/arch/arm/mach-pxa/include/mach/mainstone.h @@ -117,4 +117,21 @@ #define MST_PCMCIA_PWR_VCC_33 0x8 /* voltage VCC = 3.3V */ #define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */ +/* board specific IRQs */ +#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x)) +#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0) +#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1) +#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2) +#define MAINSTONE_ETHERNET_IRQ MAINSTONE_IRQ(3) +#define MAINSTONE_AC97_IRQ MAINSTONE_IRQ(4) +#define MAINSTONE_PEN_IRQ MAINSTONE_IRQ(5) +#define MAINSTONE_MSINS_IRQ MAINSTONE_IRQ(6) +#define MAINSTONE_EXBRD_IRQ MAINSTONE_IRQ(7) +#define MAINSTONE_S0_CD_IRQ MAINSTONE_IRQ(9) +#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10) +#define MAINSTONE_S0_IRQ MAINSTONE_IRQ(11) +#define MAINSTONE_S1_CD_IRQ MAINSTONE_IRQ(13) +#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) +#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) + #endif diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h index 9c787855cf24..cafadc33dfd8 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h @@ -190,4 +190,36 @@ #define GPIO89_AC97_nRESET MFP_CFG_OUT(GPIO89, AF0, DRIVE_HIGH) #endif /* CONFIG_CPU_PXA26x */ +/* commonly used pin configurations */ +#define GPIOxx_LCD_16BPP \ + GPIO58_LCD_LDD_0, \ + GPIO59_LCD_LDD_1, \ + GPIO60_LCD_LDD_2, \ + GPIO61_LCD_LDD_3, \ + GPIO62_LCD_LDD_4, \ + GPIO63_LCD_LDD_5, \ + GPIO64_LCD_LDD_6, \ + GPIO65_LCD_LDD_7, \ + GPIO66_LCD_LDD_8, \ + GPIO67_LCD_LDD_9, \ + GPIO68_LCD_LDD_10, \ + GPIO69_LCD_LDD_11, \ + GPIO70_LCD_LDD_12, \ + GPIO71_LCD_LDD_13, \ + GPIO72_LCD_LDD_14, \ + GPIO73_LCD_LDD_15 + +#define GPIOxx_LCD_DSTN_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK + +#define GPIOxx_LCD_TFT_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK, \ + GPIO77_LCD_BIAS + #endif /* __ASM_ARCH_MFP_PXA25X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h index 6543c05f47ed..ec0f0b0b6744 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h @@ -434,5 +434,32 @@ #define GPIO112_nMSINS MFP_CFG_IN(GPIO112, AF2) #define GPIO32_MSSCLK MFP_CFG_OUT(GPIO32, AF1, DRIVE_LOW) +/* commonly used pin configurations */ +#define GPIOxx_LCD_16BPP \ + GPIO58_LCD_LDD_0, \ + GPIO59_LCD_LDD_1, \ + GPIO60_LCD_LDD_2, \ + GPIO61_LCD_LDD_3, \ + GPIO62_LCD_LDD_4, \ + GPIO63_LCD_LDD_5, \ + GPIO64_LCD_LDD_6, \ + GPIO65_LCD_LDD_7, \ + GPIO66_LCD_LDD_8, \ + GPIO67_LCD_LDD_9, \ + GPIO68_LCD_LDD_10, \ + GPIO69_LCD_LDD_11, \ + GPIO70_LCD_LDD_12, \ + GPIO71_LCD_LDD_13, \ + GPIO72_LCD_LDD_14, \ + GPIO73_LCD_LDD_15 + +#define GPIOxx_LCD_TFT_16BPP \ + GPIOxx_LCD_16BPP, \ + GPIO74_LCD_FCLK, \ + GPIO75_LCD_LCLK, \ + GPIO76_LCD_PCLK, \ + GPIO77_LCD_BIAS + + extern int keypad_set_wake(unsigned int on); #endif /* __ASM_ARCH_MFP_PXA27X_H */ diff --git a/arch/arm/mach-pxa/include/mach/mxm8x10.h b/arch/arm/mach-pxa/include/mach/mxm8x10.h new file mode 100644 index 000000000000..ffa15665a418 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/mxm8x10.h @@ -0,0 +1,21 @@ +#ifndef __MACH_MXM_8X10_H +#define __MACH_MXM_8X10_H + +#define MXM_8X10_ETH_PHYS 0x13000000 + +#if defined(CONFIG_MMC) + +#define MXM_8X10_SD_nCD (72) +#define MXM_8X10_SD_WP (84) + +extern void mxm_8x10_mmc_init(void); +#else +static inline void mxm_8x10_mmc_init(void) {} +#endif + +extern void mxm_8x10_usb_host_init(void); +extern void mxm_8x10_ac97_init(void); + +extern void mxm_8x10_barebones_init(void); + +#endif /* __MACH_MXM_8X10_H */ diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h index 4dcd2e8baa61..04083263167e 100644 --- a/arch/arm/mach-pxa/include/mach/pcm027.h +++ b/arch/arm/mach-pxa/include/mach/pcm027.h @@ -23,6 +23,13 @@ * Definitions of CPU card resources only */ +/* phyCORE-PXA270 (PCM027) Interrupts */ +#define PCM027_IRQ(x) (IRQ_BOARD_START + (x)) +#define PCM027_BTDET_IRQ PCM027_IRQ(0) +#define PCM027_FF_RI_IRQ PCM027_IRQ(1) +#define PCM027_MMCDET_IRQ PCM027_IRQ(2) +#define PCM027_PM_5V_IRQ PCM027_IRQ(3) + /* I2C RTC */ #define PCM027_RTC_IRQ_GPIO 0 #define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) diff --git a/arch/arm/mach-pxa/include/mach/ssp.h b/arch/arm/mach-pxa/include/mach/ssp.h index cb5cb766f0f1..be1be5b6db51 100644 --- a/arch/arm/mach-pxa/include/mach/ssp.h +++ b/arch/arm/mach-pxa/include/mach/ssp.h @@ -46,6 +46,7 @@ struct ssp_device { int drcmr_tx; }; +#ifdef CONFIG_PXA_SSP_LEGACY /* * SSP initialisation flags */ @@ -78,6 +79,7 @@ void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp); int ssp_init(struct ssp_dev *dev, u32 port, u32 init_flags); int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed); void ssp_exit(struct ssp_dev *dev); +#endif /* CONFIG_PXA_SSP_LEGACY */ /** * ssp_write_reg - Write to a SSP register diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index 237734b5b1be..5ef91d9d17e4 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h @@ -10,20 +10,41 @@ */ #include <linux/serial_reg.h> -#include <mach/regs-uart.h> #include <asm/mach-types.h> -#define __REG(x) ((volatile unsigned long *)x) +#define FFUART_BASE (0x40100000) +#define BTUART_BASE (0x40200000) +#define STUART_BASE (0x40700000) -static volatile unsigned long *UART = FFUART; +static unsigned long uart_base = FFUART_BASE; +static unsigned int uart_shift = 2; +static unsigned int uart_is_pxa = 1; + +static inline unsigned char uart_read(int offset) +{ + return *(volatile unsigned char *)(uart_base + (offset << uart_shift)); +} + +static inline void uart_write(unsigned char val, int offset) +{ + *(volatile unsigned char *)(uart_base + (offset << uart_shift)) = val; +} + +static inline int uart_is_enabled(void) +{ + /* assume enabled by default for non-PXA uarts */ + return uart_is_pxa ? uart_read(UART_IER) & UART_IER_UUE : 1; +} static inline void putc(char c) { - if (!(UART[UART_IER] & IER_UUE)) + if (!uart_is_enabled()) return; - while (!(UART[UART_LSR] & LSR_TDRQ)) + + while (!(uart_read(UART_LSR) & UART_LSR_THRE)) barrier(); - UART[UART_TX] = c; + + uart_write(c, UART_TX); } /* @@ -38,7 +59,13 @@ static inline void arch_decomp_setup(void) if (machine_is_littleton() || machine_is_intelmote2() || machine_is_csb726() || machine_is_stargate2() || machine_is_cm_x300() || machine_is_balloon3()) - UART = STUART; + uart_base = STUART_BASE; + + if (machine_is_arcom_zeus()) { + uart_base = 0x10000000; /* nCS4 */ + uart_shift = 1; + uart_is_pxa = 0; + } } /* diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h index c387046d2f28..6e119976003e 100644 --- a/arch/arm/mach-pxa/include/mach/zeus.h +++ b/arch/arm/mach-pxa/include/mach/zeus.h @@ -58,6 +58,8 @@ #define ZEUS_EXT1_GPIO(x) (ZEUS_EXT1_GPIO_BASE + (x)) #define ZEUS_USER_GPIO(x) (ZEUS_USER_GPIO_BASE + (x)) +#define ZEUS_CAN_SHDN_GPIO ZEUS_EXT1_GPIO(2) + /* * CPLD registers: * Only 4 registers, but spreaded over a 32MB address space. @@ -68,7 +70,6 @@ #define ZEUS_CPLD_VERSION (ZEUS_CPLD + 0x0000) #define ZEUS_CPLD_ISA_IRQ (ZEUS_CPLD + 0x1000) #define ZEUS_CPLD_CONTROL (ZEUS_CPLD + 0x2000) -#define ZEUS_CPLD_EXTWDOG (ZEUS_CPLD + 0x3000) /* CPLD register bits */ #define ZEUS_CPLD_CONTROL_CF_RST 0x01 diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index 1373c22dbb83..d279507fc748 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c @@ -83,6 +83,10 @@ static unsigned long lpd270_pin_config[] __initdata = { GPIO89_USBH1_PEN, /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, GPIO45_AC97_SYSCLK, GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, @@ -121,7 +125,7 @@ static void lpd270_irq_handler(unsigned int irq, struct irq_desc *desc) pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled; do { - GEDR(0) = GPIO_bit(0); /* clear useless edge notification */ + desc->chip->ack(irq); /* clear useless edge notification */ if (likely(pending)) { irq = LPD270_IRQ(0) + __ffs(pending); generic_handle_irq(irq); diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index 98ee7e590299..63d65a2a0387 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c @@ -66,26 +66,14 @@ static unsigned long lubbock_pin_config[] __initdata = { GPIO25_SSP1_TXD, GPIO26_SSP1_RXD, + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + /* LCD - 16bpp DSTN */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, + GPIOxx_LCD_DSTN_16BPP, /* BTUART */ GPIO42_BTUART_RXD, @@ -158,7 +146,7 @@ static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled; do { - GEDR(0) = GPIO_bit(0); /* clear our parent irq */ + desc->chip->ack(irq); /* clear our parent irq */ if (likely(pending)) { irq = LUBBOCK_IRQ(0) + __ffs(pending); generic_handle_irq(irq); @@ -240,11 +228,18 @@ static struct resource sa1111_resources[] = { }, }; +static struct sa1111_platform_data sa1111_info = { + .irq_base = IRQ_BOARD_END, +}; + static struct platform_device sa1111_device = { .name = "sa1111", .id = -1, .num_resources = ARRAY_SIZE(sa1111_resources), .resource = sa1111_resources, + .dev = { + .platform_data = &sa1111_info, + }, }; /* ADS7846 is connected through SSP ... and if your board has J5 populated, diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 189f330719a2..e81dd0c8e40d 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -88,26 +88,7 @@ static unsigned long magician_pin_config[] __initdata = { GPIO112_MMC_CMD, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* QCI */ GPIO12_CIF_DD_7, diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 851ee0fc32e2..5543c64da9ef 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -60,26 +60,7 @@ static unsigned long mainstone_pin_config[] = { GPIO15_nCS_1, /* LCD - 16bpp Active TFT */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, GPIO16_PWM0_OUT, /* Backlight */ /* MMC */ @@ -107,6 +88,10 @@ static unsigned long mainstone_pin_config[] = { GPIO57_nIOIS16, /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, GPIO45_AC97_SYSCLK, /* Keypad */ @@ -162,7 +147,7 @@ static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc) { unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled; do { - GEDR(0) = GPIO_bit(0); /* clear useless edge notification */ + desc->chip->ack(irq); /* clear useless edge notification */ if (likely(pending)) { irq = MAINSTONE_IRQ(0) + __ffs(pending); generic_handle_irq(irq); diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 2466a44d8fda..843fcca76e26 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c @@ -86,25 +86,7 @@ static unsigned long mioa701_pin_config[] = { MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW), /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, + GPIOxx_LCD_TFT_16BPP, /* QCI */ GPIO12_CIF_DD_7, @@ -155,6 +137,10 @@ static unsigned long mioa701_pin_config[] = { GPIO41_FFUART_RTS, /* Sound */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, GPIO89_AC97_SYSCLK, MIO_CFG_IN(GPIO12_HPJACK_INSERT, AF0), diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c new file mode 100644 index 000000000000..8c9c6f0d56bb --- /dev/null +++ b/arch/arm/mach-pxa/mxm8x10.c @@ -0,0 +1,474 @@ +/* + * linux/arch/arm/mach-pxa/mxm8x10.c + * + * Support for the Embedian MXM-8x10 Computer on Module + * + * Copyright (C) 2006 Marvell International Ltd. + * Copyright (C) 2009 Embedian Inc. + * Copyright (C) 2009 TMT Services & Supplies (Pty) Ltd. + * + * 2007-09-04: eric miao <[email protected]> + * rewrite to align with latest kernel + * + * 2010-01-09: Edwin Peer <[email protected]> + * Hennie van der Merwe <[email protected]> + * rework for upstream merge + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/serial_8250.h> +#include <linux/dm9000.h> +#include <linux/gpio.h> + +#include <plat/i2c.h> +#include <plat/pxa3xx_nand.h> + +#include <mach/pxafb.h> +#include <mach/mmc.h> +#include <mach/ohci.h> +#include <mach/pxa320.h> + +#include <mach/mxm8x10.h> + +#include "devices.h" +#include "generic.h" + +/* GPIO pin definition + +External device stuff - Leave unconfigured for now... +--------------------- +GPIO0 - DREQ (External DMA Request) +GPIO3 - nGCS2 (External Chip Select) Where is nGCS0; nGCS1; nGCS4; nGCS5 ? +GPIO4 - nGCS3 +GPIO15 - EXT_GPIO1 +GPIO16 - EXT_GPIO2 +GPIO17 - EXT_GPIO3 +GPIO24 - EXT_GPIO4 +GPIO25 - EXT_GPIO5 +GPIO26 - EXT_GPIO6 +GPIO27 - EXT_GPIO7 +GPIO28 - EXT_GPIO8 +GPIO29 - EXT_GPIO9 +GPIO30 - EXT_GPIO10 +GPIO31 - EXT_GPIO11 +GPIO57 - EXT_GPIO12 +GPIO74 - EXT_IRQ1 +GPIO75 - EXT_IRQ2 +GPIO76 - EXT_IRQ3 +GPIO77 - EXT_IRQ4 +GPIO78 - EXT_IRQ5 +GPIO79 - EXT_IRQ6 +GPIO80 - EXT_IRQ7 +GPIO81 - EXT_IRQ8 +GPIO87 - VCCIO_PWREN (External Device PWREN) + +Dallas 1-Wire - Leave unconfigured for now... +------------- +GPIO0_2 - DS - 1Wire + +Ethernet +-------- +GPIO1 - DM9000 PWR +GPIO9 - DM9K_nIRQ +GPIO36 - DM9K_RESET + +Keypad - Leave unconfigured by for now... +------ +GPIO1_2 - KP_DKIN0 +GPIO5_2 - KP_MKOUT7 +GPIO82 - KP_DKIN1 +GPIO85 - KP_DKIN2 +GPIO86 - KP_DKIN3 +GPIO113 - KP_MKIN0 +GPIO114 - KP_MKIN1 +GPIO115 - KP_MKIN2 +GPIO116 - KP_MKIN3 +GPIO117 - KP_MKIN4 +GPIO118 - KP_MKIN5 +GPIO119 - KP_MKIN6 +GPIO120 - KP_MKIN7 +GPIO121 - KP_MKOUT0 +GPIO122 - KP_MKOUT1 +GPIO122 - KP_MKOUT2 +GPIO123 - KP_MKOUT3 +GPIO124 - KP_MKOUT4 +GPIO125 - KP_MKOUT5 +GPIO127 - KP_MKOUT6 + +Data Bus - Leave unconfigured for now... +-------- +GPIO2 - nWait (Data Bus) + +USB Device +---------- +GPIO4_2 - USBD_PULLUP +GPIO10 - UTM_CLK (USB Device UTM Clk) +GPIO49 - USB 2.0 Device UTM_DATA0 +GPIO50 - USB 2.0 Device UTM_DATA1 +GPIO51 - USB 2.0 Device UTM_DATA2 +GPIO52 - USB 2.0 Device UTM_DATA3 +GPIO53 - USB 2.0 Device UTM_DATA4 +GPIO54 - USB 2.0 Device UTM_DATA5 +GPIO55 - USB 2.0 Device UTM_DATA6 +GPIO56 - USB 2.0 Device UTM_DATA7 +GPIO58 - UTM_RXVALID (USB 2.0 Device) +GPIO59 - UTM_RXACTIVE (USB 2.0 Device) +GPIO60 - UTM_RXERROR +GPIO61 - UTM_OPMODE0 +GPIO62 - UTM_OPMODE1 +GPIO71 - USBD_INT (USB Device?) +GPIO73 - UTM_TXREADY (USB 2.0 Device) +GPIO83 - UTM_TXVALID (USB 2.0 Device) +GPIO98 - UTM_RESET (USB 2.0 device) +GPIO99 - UTM_XCVR_SELECT +GPIO100 - UTM_TERM_SELECT +GPIO101 - UTM_SUSPENDM_X +GPIO102 - UTM_LINESTATE0 +GPIO103 - UTM_LINESTATE1 + +Card-Bus Interface - Leave unconfigured for now... +------------------ +GPIO5 - nPIOR (I/O space output enable) +GPIO6 - nPIOW (I/O space write enable) +GPIO7 - nIOS16 (Input from I/O space telling size of data bus) +GPIO8 - nPWAIT (Input for inserting wait states) + +LCD +--- +GPIO6_2 - LDD0 +GPIO7_2 - LDD1 +GPIO8_2 - LDD2 +GPIO9_2 - LDD3 +GPIO11_2 - LDD5 +GPIO12_2 - LDD6 +GPIO13_2 - LDD7 +GPIO14_2 - VSYNC +GPIO15_2 - HSYNC +GPIO16_2 - VCLK +GPIO17_2 - HCLK +GPIO18_2 - VDEN +GPIO63 - LDD8 (CPU LCD) +GPIO64 - LDD9 (CPU LCD) +GPIO65 - LDD10 (CPU LCD) +GPIO66 - LDD11 (CPU LCD) +GPIO67 - LDD12 (CPU LCD) +GPIO68 - LDD13 (CPU LCD) +GPIO69 - LDD14 (CPU LCD) +GPIO70 - LDD15 (CPU LCD) +GPIO88 - VCCLCD_PWREN (LCD Panel PWREN) +GPIO97 - BACKLIGHT_EN +GPIO104 - LCD_PWREN + +PWM - Leave unconfigured for now... +--- +GPIO11 - PWM0 +GPIO12 - PWM1 +GPIO13 - PWM2 +GPIO14 - PWM3 + +SD-CARD +------- +GPIO18 - SDDATA0 +GPIO19 - SDDATA1 +GPIO20 - SDDATA2 +GPIO21 - SDDATA3 +GPIO22 - SDCLK +GPIO23 - SDCMD +GPIO72 - SD_WP +GPIO84 - SD_nIRQ_CD (SD-Card) + +I2C +--- +GPIO32 - I2CSCL +GPIO33 - I2CSDA + +AC97 +---- +GPIO35 - AC97_SDATA_IN +GPIO37 - AC97_SDATA_OUT +GPIO38 - AC97_SYNC +GPIO39 - AC97_BITCLK +GPIO40 - AC97_nRESET + +UART1 +----- +GPIO41 - UART_RXD1 +GPIO42 - UART_TXD1 +GPIO43 - UART_CTS1 +GPIO44 - UART_DCD1 +GPIO45 - UART_DSR1 +GPIO46 - UART_nRI1 +GPIO47 - UART_DTR1 +GPIO48 - UART_RTS1 + +UART2 +----- +GPIO109 - RTS2 +GPIO110 - RXD2 +GPIO111 - TXD2 +GPIO112 - nCTS2 + +UART3 +----- +GPIO105 - nCTS3 +GPIO106 - nRTS3 +GPIO107 - TXD3 +GPIO108 - RXD3 + +SSP3 - Leave unconfigured for now... +---- +GPIO89 - SSP3_CLK +GPIO90 - SSP3_SFRM +GPIO91 - SSP3_TXD +GPIO92 - SSP3_RXD + +SSP4 +GPIO93 - SSP4_CLK +GPIO94 - SSP4_SFRM +GPIO95 - SSP4_TXD +GPIO96 - SSP4_RXD +*/ + +static mfp_cfg_t mfp_cfg[] __initdata = { + /* USB */ + GPIO10_UTM_CLK, + GPIO49_U2D_PHYDATA_0, + GPIO50_U2D_PHYDATA_1, + GPIO51_U2D_PHYDATA_2, + GPIO52_U2D_PHYDATA_3, + GPIO53_U2D_PHYDATA_4, + GPIO54_U2D_PHYDATA_5, + GPIO55_U2D_PHYDATA_6, + GPIO56_U2D_PHYDATA_7, + GPIO58_UTM_RXVALID, + GPIO59_UTM_RXACTIVE, + GPIO60_U2D_RXERROR, + GPIO61_U2D_OPMODE0, + GPIO62_U2D_OPMODE1, + GPIO71_GPIO, /* USBD_INT */ + GPIO73_UTM_TXREADY, + GPIO83_U2D_TXVALID, + GPIO98_U2D_RESET, + GPIO99_U2D_XCVR_SEL, + GPIO100_U2D_TERM_SEL, + GPIO101_U2D_SUSPEND, + GPIO102_UTM_LINESTATE_0, + GPIO103_UTM_LINESTATE_1, + GPIO4_2_GPIO | MFP_PULL_HIGH, /* UTM_PULLUP */ + + /* DM9000 */ + GPIO1_GPIO, + GPIO9_GPIO, + GPIO36_GPIO, + + /* AC97 */ + GPIO35_AC97_SDATA_IN_0, + GPIO37_AC97_SDATA_OUT, + GPIO38_AC97_SYNC, + GPIO39_AC97_BITCLK, + GPIO40_AC97_nACRESET, + + /* UARTS */ + GPIO41_UART1_RXD, + GPIO42_UART1_TXD, + GPIO43_UART1_CTS, + GPIO44_UART1_DCD, + GPIO45_UART1_DSR, + GPIO46_UART1_RI, + GPIO47_UART1_DTR, + GPIO48_UART1_RTS, + + GPIO109_UART2_RTS, + GPIO110_UART2_RXD, + GPIO111_UART2_TXD, + GPIO112_UART2_CTS, + + GPIO105_UART3_CTS, + GPIO106_UART3_RTS, + GPIO107_UART3_TXD, + GPIO108_UART3_RXD, + + GPIO78_GPIO, + GPIO79_GPIO, + GPIO80_GPIO, + GPIO81_GPIO, + + /* I2C */ + GPIO32_I2C_SCL, + GPIO33_I2C_SDA, + + /* MMC */ + GPIO18_MMC1_DAT0, + GPIO19_MMC1_DAT1, + GPIO20_MMC1_DAT2, + GPIO21_MMC1_DAT3, + GPIO22_MMC1_CLK, + GPIO23_MMC1_CMD, + GPIO72_GPIO | MFP_PULL_HIGH, /* Card Detect */ + GPIO84_GPIO | MFP_PULL_LOW, /* Write Protect */ + + /* IRQ */ + GPIO74_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ1 */ + GPIO75_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ2 */ + GPIO76_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ3 */ + GPIO77_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ4 */ + GPIO78_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ5 */ + GPIO79_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ6 */ + GPIO80_GPIO | MFP_LPM_EDGE_RISE, /* EXT_IRQ7 */ + GPIO81_GPIO | MFP_LPM_EDGE_RISE /* EXT_IRQ8 */ +}; + +/* MMC/MCI Support */ +#if defined(CONFIG_MMC) +static struct pxamci_platform_data mxm_8x10_mci_platform_data = { + .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, + .detect_delay = 1, + .gpio_card_detect = MXM_8X10_SD_nCD, + .gpio_card_ro = MXM_8X10_SD_WP, + .gpio_power = -1 +}; + +void __init mxm_8x10_mmc_init(void) +{ + pxa_set_mci_info(&mxm_8x10_mci_platform_data); +} +#endif + +/* USB Open Host Controler Interface */ +static struct pxaohci_platform_data mxm_8x10_ohci_platform_data = { + .port_mode = PMM_NPS_MODE, + .flags = ENABLE_PORT_ALL +}; + +void __init mxm_8x10_usb_host_init(void) +{ + pxa_set_ohci_info(&mxm_8x10_ohci_platform_data); +} + +/* AC97 Sound Support */ +static struct platform_device mxm_8x10_ac97_device = { + .name = "pxa2xx-ac97" +}; + +void __init mxm_8x10_ac97_init(void) +{ + platform_device_register(&mxm_8x10_ac97_device); +} + +/* NAND flash Support */ +#if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) +#define NAND_BLOCK_SIZE SZ_128K +#define NB(x) (NAND_BLOCK_SIZE * (x)) +static struct mtd_partition mxm_8x10_nand_partitions[] = { + [0] = { + .name = "boot", + .size = NB(0x002), + .offset = NB(0x000), + .mask_flags = MTD_WRITEABLE + }, + [1] = { + .name = "kernel", + .size = NB(0x010), + .offset = NB(0x002), + .mask_flags = MTD_WRITEABLE + }, + [2] = { + .name = "root", + .size = NB(0x36c), + .offset = NB(0x012) + }, + [3] = { + .name = "bbt", + .size = NB(0x082), + .offset = NB(0x37e), + .mask_flags = MTD_WRITEABLE + } +}; + +static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = { + .enable_arbiter = 1, + .keep_config = 1, + .parts = mxm_8x10_nand_partitions, + .nr_parts = ARRAY_SIZE(mxm_8x10_nand_partitions) +}; + +static void __init mxm_8x10_nand_init(void) +{ + pxa3xx_set_nand_info(&mxm_8x10_nand_info); +} +#else +static inline void mxm_8x10_nand_init(void) {} +#endif /* CONFIG_MTD_NAND_PXA3xx || CONFIG_MTD_NAND_PXA3xx_MODULE */ + +/* Ethernet support: Davicom DM9000 */ +static struct resource dm9k_resources[] = { + [0] = { + .start = MXM_8X10_ETH_PHYS + 0x300, + .end = MXM_8X10_ETH_PHYS + 0x300, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = MXM_8X10_ETH_PHYS + 0x308, + .end = MXM_8X10_ETH_PHYS + 0x308, + .flags = IORESOURCE_MEM + }, + [2] = { + .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), + .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)), + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE + } +}; + +static struct dm9000_plat_data dm9k_plat_data = { + .flags = DM9000_PLATF_16BITONLY +}; + +static struct platform_device dm9k_device = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(dm9k_resources), + .resource = dm9k_resources, + .dev = { + .platform_data = &dm9k_plat_data + } +}; + +static void __init mxm_8x10_ethernet_init(void) +{ + platform_device_register(&dm9k_device); +} + +/* PXA UARTs */ +static void __init mxm_8x10_uarts_init(void) +{ + pxa_set_ffuart_info(NULL); + pxa_set_btuart_info(NULL); + pxa_set_stuart_info(NULL); +} + +/* I2C and Real Time Clock */ +static struct i2c_board_info __initdata mxm_8x10_i2c_devices[] = { + { + I2C_BOARD_INFO("ds1337", 0x68) + } +}; + +static void __init mxm_8x10_i2c_init(void) +{ + i2c_register_board_info(0, mxm_8x10_i2c_devices, + ARRAY_SIZE(mxm_8x10_i2c_devices)); + pxa_set_i2c_info(NULL); +} + +void __init mxm_8x10_barebones_init(void) +{ + pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg)); + + mxm_8x10_uarts_init(); + mxm_8x10_nand_init(); + mxm_8x10_i2c_init(); + mxm_8x10_ethernet_init(); +} diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index e100af78b166..f70c75b38769 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c @@ -83,26 +83,7 @@ static unsigned long palmld_pin_config[] __initdata = { GPIO105_KP_MKOUT_2, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* PWM */ GPIO16_PWM0_OUT, diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 8fe3ec27568f..d902a813aae3 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c @@ -87,26 +87,7 @@ static unsigned long palmt5_pin_config[] __initdata = { GPIO105_KP_MKOUT_2, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* PWM */ GPIO16_PWM0_OUT, diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index b992f07ece21..717d7a638675 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c @@ -84,26 +84,7 @@ static unsigned long palmtc_pin_config[] __initdata = { GPIO36_GPIO, /* pullup */ /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* MATRIX KEYPAD */ GPIO0_GPIO | WAKEUP_ON_EDGE_BOTH, /* in 0 */ diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index dc728d6ab94e..3d284ff1a64e 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c @@ -73,26 +73,7 @@ static unsigned long palmte2_pin_config[] __initdata = { GPIO47_FICP_TXD, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* GPIO KEYS */ GPIO5_GPIO, /* notes */ diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c index b433bb496711..d8b4469607a1 100644 --- a/arch/arm/mach-pxa/palmtreo.c +++ b/arch/arm/mach-pxa/palmtreo.c @@ -99,25 +99,7 @@ static unsigned long treo_pin_config[] __initdata = { GPIO93_KP_DKIN_0 | WAKEUP_ON_LEVEL_HIGH, /* Hotsync button */ /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, + GPIOxx_LCD_TFT_16BPP, /* Quick Capture Interface */ GPIO84_CIF_FV, diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index b37a025c0b7b..007b58c11f8d 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c @@ -110,26 +110,7 @@ static unsigned long palmtx_pin_config[] __initdata = { GPIO105_KP_MKOUT_2, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* FFUART */ GPIO34_FFUART_RXD, diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 1c5d68a94511..3a7925ca3944 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c @@ -95,26 +95,8 @@ static unsigned long palmz72_pin_config[] __initdata = { GPIO105_KP_MKOUT_2, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, + GPIO20_GPIO, /* bl power */ GPIO21_GPIO, /* LCD border switch */ GPIO22_GPIO, /* LCD border color */ diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index d5255ae74fe3..9d0ecea1760c 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -58,6 +58,12 @@ static unsigned long pcm990_pin_config[] __initdata = { /* I2C */ GPIO117_I2C_SCL, GPIO118_I2C_SDA, + + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, }; /* @@ -259,8 +265,7 @@ static void pcm990_irq_handler(unsigned int irq, struct irq_desc *desc) unsigned long pending = (~PCM990_INTSETCLR) & pcm990_irq_enabled; do { - GEDR(PCM990_CTRL_INT_IRQ_GPIO) = - GPIO_bit(PCM990_CTRL_INT_IRQ_GPIO); + desc->chip->ack(irq); /* clear our parent IRQ */ if (likely(pending)) { irq = PCM027_IRQ(0) + __ffs(pending); generic_handle_irq(irq); diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index c2b938a4d5c9..d58a52415d75 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -91,26 +91,7 @@ static unsigned long poodle_pin_config[] __initdata = { GPIO35_FFUART_CTS, /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* PC Card */ GPIO48_nPOE, @@ -193,11 +174,18 @@ static struct resource locomo_resources[] = { }, }; +static struct locomo_platform_data locomo_info = { + .irq_base = IRQ_BOARD_START, +}; + struct platform_device poodle_locomo_device = { .name = "locomo", .id = 0, .num_resources = ARRAY_SIZE(locomo_resources), .resource = locomo_resources, + .dev = { + .platform_data = &locomo_info, + }, }; EXPORT_SYMBOL(poodle_locomo_device); diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 6a0b73167e03..7c53543ba2de 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -40,6 +40,25 @@ void pxa27x_clear_otgph(void) } EXPORT_SYMBOL(pxa27x_clear_otgph); +static unsigned long ac97_reset_config[] = { + GPIO95_AC97_nRESET, + GPIO95_GPIO, + GPIO113_AC97_nRESET, + GPIO113_GPIO, +}; + +void pxa27x_assert_ac97reset(int reset_gpio, int on) +{ + if (reset_gpio == 113) + pxa2xx_mfp_config(on ? &ac97_reset_config[0] : + &ac97_reset_config[1], 1); + + if (reset_gpio == 95) + pxa2xx_mfp_config(on ? &ac97_reset_config[2] : + &ac97_reset_config[3], 1); +} +EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset); + /* Crystal clock: 13MHz */ #define BASE_CLK 13000000 diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c new file mode 100644 index 000000000000..3184bdc14526 --- /dev/null +++ b/arch/arm/mach-pxa/raumfeld.c @@ -0,0 +1,1108 @@ +/* + * arch/arm/mach-pxa/raumfeld.c + * + * Support for the following Raumfeld devices: + * + * * Controller + * * Connector + * * Speaker S/M + * + * See http://www.raumfeld.com for details. + * + * Copyright (c) 2009 Daniel Mack <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/sysdev.h> +#include <linux/platform_device.h> +#include <linux/interrupt.h> +#include <linux/gpio.h> +#include <linux/smsc911x.h> +#include <linux/input.h> +#include <linux/rotary_encoder.h> +#include <linux/gpio_keys.h> +#include <linux/input/eeti_ts.h> +#include <linux/leds.h> +#include <linux/w1-gpio.h> +#include <linux/sched.h> +#include <linux/pwm_backlight.h> +#include <linux/i2c.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi_gpio.h> +#include <linux/lis3lv02d.h> +#include <linux/pda_power.h> +#include <linux/power_supply.h> +#include <linux/pda_power.h> +#include <linux/power_supply.h> +#include <linux/regulator/max8660.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/consumer.h> +#include <linux/delay.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> + +#include <mach/hardware.h> +#include <mach/pxa3xx-regs.h> +#include <mach/mfp-pxa3xx.h> +#include <mach/mfp-pxa300.h> +#include <mach/ohci.h> +#include <mach/pxafb.h> +#include <mach/mmc.h> +#include <plat/i2c.h> +#include <plat/pxa3xx_nand.h> + +#include "generic.h" +#include "devices.h" +#include "clock.h" + +/* common GPIO definitions */ + +/* inputs */ +#define GPIO_ON_OFF (14) +#define GPIO_VOLENC_A (19) +#define GPIO_VOLENC_B (20) +#define GPIO_CHARGE_DONE (23) +#define GPIO_CHARGE_IND (27) +#define GPIO_TOUCH_IRQ (32) +#define GPIO_ETH_IRQ (40) +#define GPIO_SPI_MISO (98) +#define GPIO_ACCEL_IRQ (104) +#define GPIO_RESCUE_BOOT (115) +#define GPIO_DOCK_DETECT (116) +#define GPIO_KEY1 (117) +#define GPIO_KEY2 (118) +#define GPIO_KEY3 (119) +#define GPIO_CHARGE_USB_OK (112) +#define GPIO_CHARGE_DC_OK (101) +#define GPIO_CHARGE_USB_SUSP (102) + +/* outputs */ +#define GPIO_SHUTDOWN_SUPPLY (16) +#define GPIO_SHUTDOWN_BATT (18) +#define GPIO_CHRG_PEN2 (31) +#define GPIO_TFT_VA_EN (33) +#define GPIO_SPDIF_CS (34) +#define GPIO_LED2 (35) +#define GPIO_LED1 (36) +#define GPIO_SPDIF_RESET (38) +#define GPIO_SPI_CLK (95) +#define GPIO_MCLK_DAC_CS (96) +#define GPIO_SPI_MOSI (97) +#define GPIO_W1_PULLUP_ENABLE (105) +#define GPIO_DISPLAY_ENABLE (106) +#define GPIO_MCLK_RESET (111) +#define GPIO_W2W_RESET (113) +#define GPIO_W2W_PDN (114) +#define GPIO_CODEC_RESET (120) +#define GPIO_AUDIO_VA_ENABLE (124) +#define GPIO_ACCEL_CS (125) +#define GPIO_ONE_WIRE (126) + +/* + * GPIO configurations + */ +static mfp_cfg_t raumfeld_controller_pin_config[] __initdata = { + /* UART1 */ + GPIO77_UART1_RXD, + GPIO78_UART1_TXD, + GPIO79_UART1_CTS, + GPIO81_UART1_DSR, + GPIO83_UART1_DTR, + GPIO84_UART1_RTS, + + /* UART3 */ + GPIO110_UART3_RXD, + + /* USB Host */ + GPIO0_2_USBH_PEN, + GPIO1_2_USBH_PWR, + + /* I2C */ + GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + + /* SPI */ + GPIO34_GPIO, /* SPDIF_CS */ + GPIO96_GPIO, /* MCLK_CS */ + GPIO125_GPIO, /* ACCEL_CS */ + + /* MMC */ + GPIO3_MMC1_DAT0, + GPIO4_MMC1_DAT1, + GPIO5_MMC1_DAT2, + GPIO6_MMC1_DAT3, + GPIO7_MMC1_CLK, + GPIO8_MMC1_CMD, + + /* One-wire */ + GPIO126_GPIO | MFP_LPM_FLOAT, + GPIO105_GPIO | MFP_PULL_LOW | MFP_LPM_PULL_LOW, + + /* CHRG_USB_OK */ + GPIO101_GPIO | MFP_PULL_HIGH, + /* CHRG_USB_OK */ + GPIO112_GPIO | MFP_PULL_HIGH, + /* CHRG_USB_SUSP */ + GPIO102_GPIO, + /* DISPLAY_ENABLE */ + GPIO106_GPIO, + /* DOCK_DETECT */ + GPIO116_GPIO | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + + /* LCD */ + GPIO54_LCD_LDD_0, + GPIO55_LCD_LDD_1, + GPIO56_LCD_LDD_2, + GPIO57_LCD_LDD_3, + GPIO58_LCD_LDD_4, + GPIO59_LCD_LDD_5, + GPIO60_LCD_LDD_6, + GPIO61_LCD_LDD_7, + GPIO62_LCD_LDD_8, + GPIO63_LCD_LDD_9, + GPIO64_LCD_LDD_10, + GPIO65_LCD_LDD_11, + GPIO66_LCD_LDD_12, + GPIO67_LCD_LDD_13, + GPIO68_LCD_LDD_14, + GPIO69_LCD_LDD_15, + GPIO70_LCD_LDD_16, + GPIO71_LCD_LDD_17, + GPIO72_LCD_FCLK, + GPIO73_LCD_LCLK, + GPIO74_LCD_PCLK, + GPIO75_LCD_BIAS, +}; + +static mfp_cfg_t raumfeld_connector_pin_config[] __initdata = { + /* UART1 */ + GPIO77_UART1_RXD, + GPIO78_UART1_TXD, + GPIO79_UART1_CTS, + GPIO81_UART1_DSR, + GPIO83_UART1_DTR, + GPIO84_UART1_RTS, + + /* UART3 */ + GPIO110_UART3_RXD, + + /* USB Host */ + GPIO0_2_USBH_PEN, + GPIO1_2_USBH_PWR, + + /* I2C */ + GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + + /* SPI */ + GPIO34_GPIO, /* SPDIF_CS */ + GPIO96_GPIO, /* MCLK_CS */ + GPIO125_GPIO, /* ACCEL_CS */ + + /* MMC */ + GPIO3_MMC1_DAT0, + GPIO4_MMC1_DAT1, + GPIO5_MMC1_DAT2, + GPIO6_MMC1_DAT3, + GPIO7_MMC1_CLK, + GPIO8_MMC1_CMD, + + /* Ethernet */ + GPIO1_nCS2, /* CS */ + GPIO40_GPIO | MFP_PULL_HIGH, /* IRQ */ + + /* SSP for I2S */ + GPIO85_SSP1_SCLK, + GPIO89_SSP1_EXTCLK, + GPIO86_SSP1_FRM, + GPIO87_SSP1_TXD, + GPIO88_SSP1_RXD, + GPIO90_SSP1_SYSCLK, + + /* SSP2 for S/PDIF */ + GPIO25_SSP2_SCLK, + GPIO26_SSP2_FRM, + GPIO27_SSP2_TXD, + GPIO29_SSP2_EXTCLK, + + /* LEDs */ + GPIO35_GPIO | MFP_LPM_PULL_LOW, + GPIO36_GPIO | MFP_LPM_DRIVE_HIGH, +}; + +static mfp_cfg_t raumfeld_speaker_pin_config[] __initdata = { + /* UART1 */ + GPIO77_UART1_RXD, + GPIO78_UART1_TXD, + GPIO79_UART1_CTS, + GPIO81_UART1_DSR, + GPIO83_UART1_DTR, + GPIO84_UART1_RTS, + + /* UART3 */ + GPIO110_UART3_RXD, + + /* USB Host */ + GPIO0_2_USBH_PEN, + GPIO1_2_USBH_PWR, + + /* I2C */ + GPIO21_I2C_SCL | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + GPIO22_I2C_SDA | MFP_LPM_FLOAT | MFP_PULL_FLOAT, + + /* SPI */ + GPIO34_GPIO, /* SPDIF_CS */ + GPIO96_GPIO, /* MCLK_CS */ + GPIO125_GPIO, /* ACCEL_CS */ + + /* MMC */ + GPIO3_MMC1_DAT0, + GPIO4_MMC1_DAT1, + GPIO5_MMC1_DAT2, + GPIO6_MMC1_DAT3, + GPIO7_MMC1_CLK, + GPIO8_MMC1_CMD, + + /* Ethernet */ + GPIO1_nCS2, /* CS */ + GPIO40_GPIO | MFP_PULL_HIGH, /* IRQ */ + + /* SSP for I2S */ + GPIO85_SSP1_SCLK, + GPIO89_SSP1_EXTCLK, + GPIO86_SSP1_FRM, + GPIO87_SSP1_TXD, + GPIO88_SSP1_RXD, + GPIO90_SSP1_SYSCLK, + + /* LEDs */ + GPIO35_GPIO | MFP_LPM_PULL_LOW, + GPIO36_GPIO | MFP_LPM_DRIVE_HIGH, +}; + +/* + * SMSC LAN9220 Ethernet + */ + +static struct resource smc91x_resources[] = { + { + .start = PXA3xx_CS2_PHYS, + .end = PXA3xx_CS2_PHYS + 0xfffff, + .flags = IORESOURCE_MEM, + }, + { + .start = gpio_to_irq(GPIO_ETH_IRQ), + .end = gpio_to_irq(GPIO_ETH_IRQ), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING, + } +}; + +static struct smsc911x_platform_config raumfeld_smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, +}; + +static struct platform_device smc91x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, + .dev = { + .platform_data = &raumfeld_smsc911x_config, + } +}; + +/** + * NAND + */ + +static struct mtd_partition raumfeld_nand_partitions[] = { + { + .name = "Bootloader", + .offset = 0, + .size = 0xa0000, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "BootloaderEnvironment", + .offset = 0xa0000, + .size = 0x20000, + }, + { + .name = "BootloaderSplashScreen", + .offset = 0xc0000, + .size = 0x60000, + }, + { + .name = "UBI", + .offset = 0x120000, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct pxa3xx_nand_platform_data raumfeld_nand_info = { + .enable_arbiter = 1, + .keep_config = 1, + .parts = raumfeld_nand_partitions, + .nr_parts = ARRAY_SIZE(raumfeld_nand_partitions), +}; + +/** + * USB (OHCI) support + */ + +static struct pxaohci_platform_data raumfeld_ohci_info = { + .port_mode = PMM_GLOBAL_MODE, + .flags = ENABLE_PORT1, +}; + +/** + * Rotary encoder input device + */ + +static struct rotary_encoder_platform_data raumfeld_rotary_encoder_info = { + .steps = 24, + .axis = REL_X, + .relative_axis = 1, + .gpio_a = GPIO_VOLENC_A, + .gpio_b = GPIO_VOLENC_B, + .inverted_a = 1, + .inverted_b = 0, +}; + +static struct platform_device rotary_encoder_device = { + .name = "rotary-encoder", + .id = 0, + .dev = { + .platform_data = &raumfeld_rotary_encoder_info, + } +}; + +/** + * GPIO buttons + */ + +static struct gpio_keys_button gpio_keys_button[] = { + { + .code = KEY_F1, + .type = EV_KEY, + .gpio = GPIO_KEY1, + .active_low = 1, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "Button 1", + }, + { + .code = KEY_F2, + .type = EV_KEY, + .gpio = GPIO_KEY2, + .active_low = 1, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "Button 2", + }, + { + .code = KEY_F3, + .type = EV_KEY, + .gpio = GPIO_KEY3, + .active_low = 1, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "Button 3", + }, + { + .code = KEY_F4, + .type = EV_KEY, + .gpio = GPIO_RESCUE_BOOT, + .active_low = 0, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "rescue boot button", + }, + { + .code = KEY_F5, + .type = EV_KEY, + .gpio = GPIO_DOCK_DETECT, + .active_low = 1, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "dock detect", + }, + { + .code = KEY_F6, + .type = EV_KEY, + .gpio = GPIO_ON_OFF, + .active_low = 0, + .wakeup = 0, + .debounce_interval = 5, /* ms */ + .desc = "on/off button", + }, +}; + +static struct gpio_keys_platform_data gpio_keys_platform_data = { + .buttons = gpio_keys_button, + .nbuttons = ARRAY_SIZE(gpio_keys_button), + .rep = 0, +}; + +static struct platform_device raumfeld_gpio_keys_device = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &gpio_keys_platform_data, + } +}; + +/** + * GPIO LEDs + */ + +static struct gpio_led raumfeld_leds[] = { + { + .name = "raumfeld:1", + .gpio = GPIO_LED1, + .active_low = 1, + .default_state = LEDS_GPIO_DEFSTATE_ON, + }, + { + .name = "raumfeld:2", + .gpio = GPIO_LED2, + .active_low = 0, + .default_state = LEDS_GPIO_DEFSTATE_OFF, + } +}; + +static struct gpio_led_platform_data raumfeld_led_platform_data = { + .leds = raumfeld_leds, + .num_leds = ARRAY_SIZE(raumfeld_leds), +}; + +static struct platform_device raumfeld_led_device = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &raumfeld_led_platform_data, + }, +}; + +/** + * One-wire (W1 bus) support + */ + +static void w1_enable_external_pullup(int enable) +{ + gpio_set_value(GPIO_W1_PULLUP_ENABLE, enable); + msleep(100); +} + +static struct w1_gpio_platform_data w1_gpio_platform_data = { + .pin = GPIO_ONE_WIRE, + .is_open_drain = 0, + .enable_external_pullup = w1_enable_external_pullup, +}; + +struct platform_device raumfeld_w1_gpio_device = { + .name = "w1-gpio", + .dev = { + .platform_data = &w1_gpio_platform_data + } +}; + +static void __init raumfeld_w1_init(void) +{ + int ret = gpio_request(GPIO_W1_PULLUP_ENABLE, + "W1 external pullup enable"); + + if (ret < 0) + pr_warning("Unable to request GPIO_W1_PULLUP_ENABLE\n"); + else + gpio_direction_output(GPIO_W1_PULLUP_ENABLE, 0); + + platform_device_register(&raumfeld_w1_gpio_device); +} + +/** + * Framebuffer device + */ + +/* PWM controlled backlight */ +static struct platform_pwm_backlight_data raumfeld_pwm_backlight_data = { + .pwm_id = 0, + .max_brightness = 100, + .dft_brightness = 100, + /* 10000 ns = 10 ms ^= 100 kHz */ + .pwm_period_ns = 10000, +}; + +static struct platform_device raumfeld_pwm_backlight_device = { + .name = "pwm-backlight", + .dev = { + .parent = &pxa27x_device_pwm0.dev, + .platform_data = &raumfeld_pwm_backlight_data, + } +}; + +/* LT3593 controlled backlight */ +static struct gpio_led raumfeld_lt3593_led = { + .name = "backlight", + .gpio = mfp_to_gpio(MFP_PIN_GPIO17), + .default_state = LEDS_GPIO_DEFSTATE_ON, +}; + +static struct gpio_led_platform_data raumfeld_lt3593_platform_data = { + .leds = &raumfeld_lt3593_led, + .num_leds = 1, +}; + +static struct platform_device raumfeld_lt3593_device = { + .name = "leds-lt3593", + .id = -1, + .dev = { + .platform_data = &raumfeld_lt3593_platform_data, + }, +}; + +static struct pxafb_mode_info sharp_lq043t3dx02_mode = { + .pixclock = 111000, + .xres = 480, + .yres = 272, + .bpp = 16, + .hsync_len = 4, + .left_margin = 2, + .right_margin = 1, + .vsync_len = 1, + .upper_margin = 3, + .lower_margin = 1, + .sync = 0, +}; + +static struct pxafb_mach_info raumfeld_sharp_lcd_info = { + .modes = &sharp_lq043t3dx02_mode, + .num_modes = 1, + .video_mem_size = 0x400000, + .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, +}; + +static void __init raumfeld_lcd_init(void) +{ + int ret; + + set_pxa_fb_info(&raumfeld_sharp_lcd_info); + + /* Earlier devices had the backlight regulator controlled + * via PWM, later versions use another controller for that */ + if ((system_rev & 0xff) < 2) { + mfp_cfg_t raumfeld_pwm_pin_config = GPIO17_PWM0_OUT; + pxa3xx_mfp_config(&raumfeld_pwm_pin_config, 1); + platform_device_register(&raumfeld_pwm_backlight_device); + } else + platform_device_register(&raumfeld_lt3593_device); + + ret = gpio_request(GPIO_TFT_VA_EN, "display VA enable"); + if (ret < 0) + pr_warning("Unable to request GPIO_TFT_VA_EN\n"); + else + gpio_direction_output(GPIO_TFT_VA_EN, 1); + + ret = gpio_request(GPIO_DISPLAY_ENABLE, "display enable"); + if (ret < 0) + pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n"); + else + gpio_direction_output(GPIO_DISPLAY_ENABLE, 1); +} + +/** + * SPI devices + */ + +struct spi_gpio_platform_data raumfeld_spi_platform_data = { + .sck = GPIO_SPI_CLK, + .mosi = GPIO_SPI_MOSI, + .miso = GPIO_SPI_MISO, + .num_chipselect = 3, +}; + +static struct platform_device raumfeld_spi_device = { + .name = "spi_gpio", + .id = 0, + .dev = { + .platform_data = &raumfeld_spi_platform_data, + } +}; + +static struct lis3lv02d_platform_data lis3_pdata = { + .click_flags = LIS3_CLICK_SINGLE_X | + LIS3_CLICK_SINGLE_Y | + LIS3_CLICK_SINGLE_Z, + .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK, + .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI | + LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI | + LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI, + .wakeup_thresh = 10, + .click_thresh_x = 10, + .click_thresh_y = 10, + .click_thresh_z = 10, +}; + +#define SPI_AK4104 \ +{ \ + .modalias = "ak4104", \ + .max_speed_hz = 10000, \ + .bus_num = 0, \ + .chip_select = 0, \ + .controller_data = (void *) GPIO_SPDIF_CS, \ +} + +#define SPI_LIS3 \ +{ \ + .modalias = "lis3lv02d_spi", \ + .max_speed_hz = 1000000, \ + .bus_num = 0, \ + .chip_select = 1, \ + .controller_data = (void *) GPIO_ACCEL_CS, \ + .platform_data = &lis3_pdata, \ + .irq = gpio_to_irq(GPIO_ACCEL_IRQ), \ +} + +#define SPI_DAC7512 \ +{ \ + .modalias = "dac7512", \ + .max_speed_hz = 1000000, \ + .bus_num = 0, \ + .chip_select = 2, \ + .controller_data = (void *) GPIO_MCLK_DAC_CS, \ +} + +static struct spi_board_info connector_spi_devices[] __initdata = { + SPI_AK4104, + SPI_DAC7512, +}; + +static struct spi_board_info speaker_spi_devices[] __initdata = { + SPI_DAC7512, +}; + +static struct spi_board_info controller_spi_devices[] __initdata = { + SPI_LIS3, +}; + +/** + * MMC for Marvell Libertas 8688 via SDIO + */ + +static int raumfeld_mci_init(struct device *dev, irq_handler_t isr, void *data) +{ + gpio_set_value(GPIO_W2W_RESET, 1); + gpio_set_value(GPIO_W2W_PDN, 1); + + return 0; +} + +static void raumfeld_mci_exit(struct device *dev, void *data) +{ + gpio_set_value(GPIO_W2W_RESET, 0); + gpio_set_value(GPIO_W2W_PDN, 0); +} + +static struct pxamci_platform_data raumfeld_mci_platform_data = { + .init = raumfeld_mci_init, + .exit = raumfeld_mci_exit, + .detect_delay = 20, + .gpio_card_detect = -1, + .gpio_card_ro = -1, + .gpio_power = -1, +}; + +/* + * External power / charge logic + */ + +static int power_supply_init(struct device *dev) +{ + return 0; +} + +static void power_supply_exit(struct device *dev) +{ +} + +static int raumfeld_is_ac_online(void) +{ + return !gpio_get_value(GPIO_CHARGE_DC_OK); +} + +static int raumfeld_is_usb_online(void) +{ + return 0; +} + +static char *raumfeld_power_supplicants[] = { "ds2760-battery.0" }; + +static struct pda_power_pdata power_supply_info = { + .init = power_supply_init, + .is_ac_online = raumfeld_is_ac_online, + .is_usb_online = raumfeld_is_usb_online, + .exit = power_supply_exit, + .supplied_to = raumfeld_power_supplicants, + .num_supplicants = ARRAY_SIZE(raumfeld_power_supplicants) +}; + +static struct resource power_supply_resources[] = { + { + .name = "ac", + .flags = IORESOURCE_IRQ | + IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE, + .start = GPIO_CHARGE_DC_OK, + .end = GPIO_CHARGE_DC_OK, + }, +}; + +static irqreturn_t charge_done_irq(int irq, void *dev_id) +{ + struct power_supply *psy; + + psy = power_supply_get_by_name("ds2760-battery.0"); + + if (psy) + power_supply_set_battery_charged(psy); + + return IRQ_HANDLED; +} + +static struct platform_device raumfeld_power_supply = { + .name = "pda-power", + .id = -1, + .dev = { + .platform_data = &power_supply_info, + }, + .resource = power_supply_resources, + .num_resources = ARRAY_SIZE(power_supply_resources), +}; + +static void __init raumfeld_power_init(void) +{ + int ret; + + /* Set PEN2 high to enable maximum charge current */ + ret = gpio_request(GPIO_CHRG_PEN2, "CHRG_PEN2"); + if (ret < 0) + pr_warning("Unable to request GPIO_CHRG_PEN2\n"); + else + gpio_direction_output(GPIO_CHRG_PEN2, 1); + + ret = gpio_request(GPIO_CHARGE_DC_OK, "CABLE_DC_OK"); + if (ret < 0) + pr_warning("Unable to request GPIO_CHARGE_DC_OK\n"); + + ret = gpio_request(GPIO_CHARGE_USB_SUSP, "CHARGE_USB_SUSP"); + if (ret < 0) + pr_warning("Unable to request GPIO_CHARGE_USB_SUSP\n"); + else + gpio_direction_output(GPIO_CHARGE_USB_SUSP, 0); + + power_supply_resources[0].start = gpio_to_irq(GPIO_CHARGE_DC_OK); + power_supply_resources[0].end = gpio_to_irq(GPIO_CHARGE_DC_OK); + + ret = request_irq(gpio_to_irq(GPIO_CHARGE_DONE), + &charge_done_irq, IORESOURCE_IRQ_LOWEDGE, + "charge_done", NULL); + + if (ret < 0) + printk(KERN_ERR "%s: unable to register irq %d\n", __func__, + GPIO_CHARGE_DONE); + else + platform_device_register(&raumfeld_power_supply); +} + +/* Fixed regulator for AUDIO_VA, 0-0048 maps to the cs4270 codec device */ + +static struct regulator_consumer_supply audio_va_consumer_supply = + REGULATOR_SUPPLY("va", "0-0048"); + +struct regulator_init_data audio_va_initdata = { + .consumer_supplies = &audio_va_consumer_supply, + .num_consumer_supplies = 1, + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +static struct fixed_voltage_config audio_va_config = { + .supply_name = "audio_va", + .microvolts = 5000000, + .gpio = GPIO_AUDIO_VA_ENABLE, + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &audio_va_initdata, +}; + +static struct platform_device audio_va_device = { + .name = "reg-fixed-voltage", + .id = 0, + .dev = { + .platform_data = &audio_va_config, + }, +}; + +/* Dummy supplies for Codec's VD/VLC */ + +static struct regulator_consumer_supply audio_dummy_supplies[] = { + REGULATOR_SUPPLY("vd", "0-0048"), + REGULATOR_SUPPLY("vlc", "0-0048"), +}; + +struct regulator_init_data audio_dummy_initdata = { + .consumer_supplies = audio_dummy_supplies, + .num_consumer_supplies = ARRAY_SIZE(audio_dummy_supplies), + .constraints = { + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, +}; + +static struct fixed_voltage_config audio_dummy_config = { + .supply_name = "audio_vd", + .microvolts = 3300000, + .gpio = -1, + .init_data = &audio_dummy_initdata, +}; + +static struct platform_device audio_supply_dummy_device = { + .name = "reg-fixed-voltage", + .id = 1, + .dev = { + .platform_data = &audio_dummy_config, + }, +}; + +static struct platform_device *audio_regulator_devices[] = { + &audio_va_device, + &audio_supply_dummy_device, +}; + +/** + * Regulator support via MAX8660 + */ + +static struct regulator_consumer_supply vcc_mmc_supply = + REGULATOR_SUPPLY("vmmc", "pxa2xx-mci.0"); + +static struct regulator_init_data vcc_mmc_init_data = { + .constraints = { + .min_uV = 3300000, + .max_uV = 3300000, + .valid_modes_mask = REGULATOR_MODE_NORMAL, + .valid_ops_mask = REGULATOR_CHANGE_STATUS | + REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_MODE, + }, + .consumer_supplies = &vcc_mmc_supply, + .num_consumer_supplies = 1, +}; + +struct max8660_subdev_data max8660_v6_subdev_data = { + .id = MAX8660_V6, + .name = "vmmc", + .platform_data = &vcc_mmc_init_data, +}; + +static struct max8660_platform_data max8660_pdata = { + .subdevs = &max8660_v6_subdev_data, + .num_subdevs = 1, +}; + +/** + * I2C devices + */ + +static struct i2c_board_info raumfeld_pwri2c_board_info = { + .type = "max8660", + .addr = 0x34, + .platform_data = &max8660_pdata, +}; + +static struct i2c_board_info raumfeld_connector_i2c_board_info __initdata = { + .type = "cs4270", + .addr = 0x48, +}; + +static struct eeti_ts_platform_data eeti_ts_pdata = { + .irq_active_high = 1, +}; + +static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = { + .type = "eeti_ts", + .addr = 0x0a, + .irq = gpio_to_irq(GPIO_TOUCH_IRQ), + .platform_data = &eeti_ts_pdata, +}; + +static struct platform_device *raumfeld_common_devices[] = { + &raumfeld_gpio_keys_device, + &raumfeld_led_device, + &raumfeld_spi_device, +}; + +static void __init raumfeld_audio_init(void) +{ + int ret; + + ret = gpio_request(GPIO_CODEC_RESET, "cs4270 reset"); + if (ret < 0) + pr_warning("unable to request GPIO_CODEC_RESET\n"); + else + gpio_direction_output(GPIO_CODEC_RESET, 1); + + ret = gpio_request(GPIO_SPDIF_RESET, "ak4104 s/pdif reset"); + if (ret < 0) + pr_warning("unable to request GPIO_SPDIF_RESET\n"); + else + gpio_direction_output(GPIO_SPDIF_RESET, 1); + + ret = gpio_request(GPIO_MCLK_RESET, "MCLK reset"); + if (ret < 0) + pr_warning("unable to request GPIO_MCLK_RESET\n"); + else + gpio_direction_output(GPIO_MCLK_RESET, 1); + + platform_add_devices(ARRAY_AND_SIZE(audio_regulator_devices)); +} + +static void __init raumfeld_common_init(void) +{ + int ret; + + /* The on/off button polarity has changed after revision 1 */ + if ((system_rev & 0xff) > 1) { + int i; + + for (i = 0; i < ARRAY_SIZE(gpio_keys_button); i++) + if (!strcmp(gpio_keys_button[i].desc, "on/off button")) + gpio_keys_button[i].active_low = 1; + } + + enable_irq_wake(IRQ_WAKEUP0); + + pxa3xx_set_nand_info(&raumfeld_nand_info); + pxa3xx_set_i2c_power_info(NULL); + pxa_set_ohci_info(&raumfeld_ohci_info); + pxa_set_mci_info(&raumfeld_mci_platform_data); + pxa_set_i2c_info(NULL); + pxa_set_ffuart_info(NULL); + + ret = gpio_request(GPIO_W2W_RESET, "Wi2Wi reset"); + if (ret < 0) + pr_warning("Unable to request GPIO_W2W_RESET\n"); + else + gpio_direction_output(GPIO_W2W_RESET, 0); + + ret = gpio_request(GPIO_W2W_PDN, "Wi2Wi powerup"); + if (ret < 0) + pr_warning("Unable to request GPIO_W2W_PDN\n"); + else + gpio_direction_output(GPIO_W2W_PDN, 0); + + /* this can be used to switch off the device */ + ret = gpio_request(GPIO_SHUTDOWN_SUPPLY, + "supply shutdown"); + if (ret < 0) + pr_warning("Unable to request GPIO_SHUTDOWN_SUPPLY\n"); + else + gpio_direction_output(GPIO_SHUTDOWN_SUPPLY, 0); + + platform_add_devices(ARRAY_AND_SIZE(raumfeld_common_devices)); + i2c_register_board_info(1, &raumfeld_pwri2c_board_info, 1); +} + +static void __init raumfeld_controller_init(void) +{ + int ret; + + pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_controller_pin_config)); + platform_device_register(&rotary_encoder_device); + spi_register_board_info(ARRAY_AND_SIZE(controller_spi_devices)); + i2c_register_board_info(0, &raumfeld_controller_i2c_board_info, 1); + + ret = gpio_request(GPIO_SHUTDOWN_BATT, "battery shutdown"); + if (ret < 0) + pr_warning("Unable to request GPIO_SHUTDOWN_BATT\n"); + else + gpio_direction_output(GPIO_SHUTDOWN_BATT, 0); + + raumfeld_common_init(); + raumfeld_power_init(); + raumfeld_lcd_init(); + raumfeld_w1_init(); +} + +static void __init raumfeld_connector_init(void) +{ + pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_connector_pin_config)); + spi_register_board_info(ARRAY_AND_SIZE(connector_spi_devices)); + i2c_register_board_info(0, &raumfeld_connector_i2c_board_info, 1); + + platform_device_register(&smc91x_device); + + raumfeld_audio_init(); + raumfeld_common_init(); +} + +static void __init raumfeld_speaker_init(void) +{ + pxa3xx_mfp_config(ARRAY_AND_SIZE(raumfeld_speaker_pin_config)); + spi_register_board_info(ARRAY_AND_SIZE(speaker_spi_devices)); + i2c_register_board_info(0, &raumfeld_connector_i2c_board_info, 1); + + platform_device_register(&smc91x_device); + platform_device_register(&rotary_encoder_device); + + raumfeld_audio_init(); + raumfeld_common_init(); +} + +/* physical memory regions */ +#define RAUMFELD_SDRAM_BASE 0xa0000000 /* SDRAM region */ + +#ifdef CONFIG_MACH_RAUMFELD_RC +MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = RAUMFELD_SDRAM_BASE + 0x100, + .init_machine = raumfeld_controller_init, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR +MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = RAUMFELD_SDRAM_BASE + 0x100, + .init_machine = raumfeld_connector_init, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, +MACHINE_END +#endif + +#ifdef CONFIG_MACH_RAUMFELD_SPEAKER +MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") + .phys_io = 0x40000000, + .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, + .boot_params = RAUMFELD_SDRAM_BASE + 0x100, + .init_machine = raumfeld_speaker_init, + .map_io = pxa_map_io, + .init_irq = pxa3xx_init_irq, + .timer = &pxa_timer, +MACHINE_END +#endif diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 28352c0b8c34..19b5109d9808 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -56,25 +56,7 @@ static unsigned long spitz_pin_config[] __initdata = { GPIO80_nCS_4, /* SCOOP #1 */ /* LCD - 16bpp Active TFT */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, + GPIOxx_LCD_TFT_16BPP, /* PC Card */ GPIO48_nPOE, diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 9ebe658590fa..a81d6dbf662d 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c @@ -35,6 +35,8 @@ #include <mach/ssp.h> #include <mach/regs-ssp.h> +#ifdef CONFIG_PXA_SSP_LEGACY + #define TIMEOUT 100000 static irqreturn_t ssp_interrupt(int irq, void *dev_id) @@ -303,6 +305,7 @@ void ssp_exit(struct ssp_dev *dev) clk_disable(ssp->clk); ssp_free(ssp); } +#endif /* CONFIG_PXA_SSP_LEGACY */ static DEFINE_MUTEX(ssp_lock); static LIST_HEAD(ssp_list); @@ -488,6 +491,7 @@ static void __exit pxa_ssp_exit(void) arch_initcall(pxa_ssp_init); module_exit(pxa_ssp_exit); +#ifdef CONFIG_PXA_SSP_LEGACY EXPORT_SYMBOL(ssp_write_word); EXPORT_SYMBOL(ssp_read_word); EXPORT_SYMBOL(ssp_flush); @@ -498,6 +502,7 @@ EXPORT_SYMBOL(ssp_restore_state); EXPORT_SYMBOL(ssp_init); EXPORT_SYMBOL(ssp_exit); EXPORT_SYMBOL(ssp_config); +#endif MODULE_DESCRIPTION("PXA SSP driver"); MODULE_AUTHOR("Liam Girdwood"); diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 750c448db672..293e40aeaf29 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -76,14 +76,12 @@ pxa_ost0_interrupt(int irq, void *dev_id) static int pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev) { - unsigned long flags, next, oscr; + unsigned long next, oscr; - raw_local_irq_save(flags); OIER |= OIER_E0; next = OSCR + delta; OSMR0 = next; oscr = OSCR; - raw_local_irq_restore(flags); return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; } @@ -91,23 +89,17 @@ pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev) static void pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) { - unsigned long irqflags; - switch (mode) { case CLOCK_EVT_MODE_ONESHOT: - raw_local_irq_save(irqflags); OIER &= ~OIER_E0; OSSR = OSSR_M0; - raw_local_irq_restore(irqflags); break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: /* initializing, released, or preparing for suspend */ - raw_local_irq_save(irqflags); OIER &= ~OIER_E0; OSSR = OSSR_M0; - raw_local_irq_restore(irqflags); break; case CLOCK_EVT_MODE_RESUME: diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index c854c168a451..ad552791c4ce 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c @@ -32,6 +32,7 @@ #include <linux/gpio.h> #include <linux/pda_power.h> #include <linux/spi/spi.h> +#include <linux/input/matrix_keypad.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -131,24 +132,24 @@ static unsigned long tosa_pin_config[] = { GPIO45_BTUART_RTS, /* Keybd */ - GPIO58_GPIO | MFP_LPM_DRIVE_LOW, - GPIO59_GPIO | MFP_LPM_DRIVE_LOW, - GPIO60_GPIO | MFP_LPM_DRIVE_LOW, - GPIO61_GPIO | MFP_LPM_DRIVE_LOW, - GPIO62_GPIO | MFP_LPM_DRIVE_LOW, - GPIO63_GPIO | MFP_LPM_DRIVE_LOW, - GPIO64_GPIO | MFP_LPM_DRIVE_LOW, - GPIO65_GPIO | MFP_LPM_DRIVE_LOW, - GPIO66_GPIO | MFP_LPM_DRIVE_LOW, - GPIO67_GPIO | MFP_LPM_DRIVE_LOW, - GPIO68_GPIO | MFP_LPM_DRIVE_LOW, - GPIO69_GPIO | MFP_LPM_DRIVE_LOW, - GPIO70_GPIO | MFP_LPM_DRIVE_LOW, - GPIO71_GPIO | MFP_LPM_DRIVE_LOW, - GPIO72_GPIO | MFP_LPM_DRIVE_LOW, - GPIO73_GPIO | MFP_LPM_DRIVE_LOW, - GPIO74_GPIO | MFP_LPM_DRIVE_LOW, - GPIO75_GPIO | MFP_LPM_DRIVE_LOW, + GPIO58_GPIO | MFP_LPM_DRIVE_LOW, /* Column 0 */ + GPIO59_GPIO | MFP_LPM_DRIVE_LOW, /* Column 1 */ + GPIO60_GPIO | MFP_LPM_DRIVE_LOW, /* Column 2 */ + GPIO61_GPIO | MFP_LPM_DRIVE_LOW, /* Column 3 */ + GPIO62_GPIO | MFP_LPM_DRIVE_LOW, /* Column 4 */ + GPIO63_GPIO | MFP_LPM_DRIVE_LOW, /* Column 5 */ + GPIO64_GPIO | MFP_LPM_DRIVE_LOW, /* Column 6 */ + GPIO65_GPIO | MFP_LPM_DRIVE_LOW, /* Column 7 */ + GPIO66_GPIO | MFP_LPM_DRIVE_LOW, /* Column 8 */ + GPIO67_GPIO | MFP_LPM_DRIVE_LOW, /* Column 9 */ + GPIO68_GPIO | MFP_LPM_DRIVE_LOW, /* Column 10 */ + GPIO69_GPIO | MFP_LPM_DRIVE_LOW, /* Row 0 */ + GPIO70_GPIO | MFP_LPM_DRIVE_LOW, /* Row 1 */ + GPIO71_GPIO | MFP_LPM_DRIVE_LOW, /* Row 2 */ + GPIO72_GPIO | MFP_LPM_DRIVE_LOW, /* Row 3 */ + GPIO73_GPIO | MFP_LPM_DRIVE_LOW, /* Row 4 */ + GPIO74_GPIO | MFP_LPM_DRIVE_LOW, /* Row 5 */ + GPIO75_GPIO | MFP_LPM_DRIVE_LOW, /* Row 6 */ /* SPI */ GPIO81_SSP2_CLK_OUT, @@ -411,9 +412,87 @@ static struct platform_device tosa_power_device = { /* * Tosa Keyboard */ +static const uint32_t tosakbd_keymap[] = { + KEY(0, 2, KEY_W), + KEY(0, 6, KEY_K), + KEY(0, 7, KEY_BACKSPACE), + KEY(0, 8, KEY_P), + KEY(1, 1, KEY_Q), + KEY(1, 2, KEY_E), + KEY(1, 3, KEY_T), + KEY(1, 4, KEY_Y), + KEY(1, 6, KEY_O), + KEY(1, 7, KEY_I), + KEY(1, 8, KEY_COMMA), + KEY(2, 1, KEY_A), + KEY(2, 2, KEY_D), + KEY(2, 3, KEY_G), + KEY(2, 4, KEY_U), + KEY(2, 6, KEY_L), + KEY(2, 7, KEY_ENTER), + KEY(2, 8, KEY_DOT), + KEY(3, 1, KEY_Z), + KEY(3, 2, KEY_C), + KEY(3, 3, KEY_V), + KEY(3, 4, KEY_J), + KEY(3, 5, TOSA_KEY_ADDRESSBOOK), + KEY(3, 6, TOSA_KEY_CANCEL), + KEY(3, 7, TOSA_KEY_CENTER), + KEY(3, 8, TOSA_KEY_OK), + KEY(3, 9, KEY_LEFTSHIFT), + KEY(4, 1, KEY_S), + KEY(4, 2, KEY_R), + KEY(4, 3, KEY_B), + KEY(4, 4, KEY_N), + KEY(4, 5, TOSA_KEY_CALENDAR), + KEY(4, 6, TOSA_KEY_HOMEPAGE), + KEY(4, 7, KEY_LEFTCTRL), + KEY(4, 8, TOSA_KEY_LIGHT), + KEY(4, 10, KEY_RIGHTSHIFT), + KEY(5, 1, KEY_TAB), + KEY(5, 2, KEY_SLASH), + KEY(5, 3, KEY_H), + KEY(5, 4, KEY_M), + KEY(5, 5, TOSA_KEY_MENU), + KEY(5, 7, KEY_UP), + KEY(5, 11, TOSA_KEY_FN), + KEY(6, 1, KEY_X), + KEY(6, 2, KEY_F), + KEY(6, 3, KEY_SPACE), + KEY(6, 4, KEY_APOSTROPHE), + KEY(6, 5, TOSA_KEY_MAIL), + KEY(6, 6, KEY_LEFT), + KEY(6, 7, KEY_DOWN), + KEY(6, 8, KEY_RIGHT), +}; + +static struct matrix_keymap_data tosakbd_keymap_data = { + .keymap = tosakbd_keymap, + .keymap_size = ARRAY_SIZE(tosakbd_keymap), +}; + +static const int tosakbd_col_gpios[] = + { 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68 }; +static const int tosakbd_row_gpios[] = + { 69, 70, 71, 72, 73, 74, 75 }; + +static struct matrix_keypad_platform_data tosakbd_pdata = { + .keymap_data = &tosakbd_keymap_data, + .row_gpios = tosakbd_row_gpios, + .col_gpios = tosakbd_col_gpios, + .num_row_gpios = ARRAY_SIZE(tosakbd_row_gpios), + .num_col_gpios = ARRAY_SIZE(tosakbd_col_gpios), + .col_scan_delay_us = 10, + .debounce_ms = 10, + .wakeup = 1, +}; + static struct platform_device tosakbd_device = { - .name = "tosa-keyboard", + .name = "matrix-keypad", .id = -1, + .dev = { + .platform_data = &tosakbd_pdata, + }, }; static struct gpio_keys_button tosa_gpio_keys[] = { diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 0aa858ebc573..797f2544d0ce 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -72,27 +72,14 @@ static unsigned long trizeps4_pin_config[] __initdata = { GPIO79_nCS_3, /* Logic CS */ GPIO0_GPIO | WAKEUP_ON_EDGE_RISE, /* Logic irq */ + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + /* LCD - 16bpp Active TFT */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, + GPIOxx_LCD_TFT_16BPP, /* UART */ GPIO9_FFUART_CTS, diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 89f258c9e126..1dd13346f977 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c @@ -281,7 +281,7 @@ static void viper_irq_handler(unsigned int irq, struct irq_desc *desc) do { /* we're in a chained irq handler, * so ack the interrupt by hand */ - GEDR(VIPER_CPLD_GPIO) = GPIO_bit(VIPER_CPLD_GPIO); + desc->chip->ack(irq); if (likely(pending)) { irq = viper_bit_to_irq(__ffs(pending)); @@ -711,6 +711,12 @@ static mfp_cfg_t viper_pin_config[] __initdata = { GPIO80_nCS_4, GPIO33_nCS_5, + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + /* FP Backlight */ GPIO9_GPIO, /* VIPER_BCKLIGHT_EN_GPIO */ GPIO10_GPIO, /* VIPER_LCD_EN_GPIO */ diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c index 75f2a37f945d..39896d883584 100644 --- a/arch/arm/mach-pxa/zeus.c +++ b/arch/arm/mach-pxa/zeus.c @@ -26,6 +26,7 @@ #include <linux/i2c.h> #include <linux/i2c/pca953x.h> #include <linux/apm-emulation.h> +#include <linux/can/platform/mcp251x.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> @@ -387,11 +388,47 @@ static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = { .enable_dma = 1, }; -static struct platform_device pxa2xx_spi_ssp3_device = { - .name = "pxa2xx-spi", - .id = 3, - .dev = { - .platform_data = &pxa2xx_spi_ssp3_master_info, +/* CAN bus on SPI */ +static int zeus_mcp2515_setup(struct spi_device *sdev) +{ + int err; + + err = gpio_request(ZEUS_CAN_SHDN_GPIO, "CAN shutdown"); + if (err) + return err; + + err = gpio_direction_output(ZEUS_CAN_SHDN_GPIO, 1); + if (err) { + gpio_free(ZEUS_CAN_SHDN_GPIO); + return err; + } + + return 0; +} + +static int zeus_mcp2515_transceiver_enable(int enable) +{ + gpio_set_value(ZEUS_CAN_SHDN_GPIO, !enable); + return 0; +} + +static struct mcp251x_platform_data zeus_mcp2515_pdata = { + .oscillator_frequency = 16*1000*1000, + .model = CAN_MCP251X_MCP2515, + .board_specific_setup = zeus_mcp2515_setup, + .transceiver_enable = zeus_mcp2515_transceiver_enable, + .power_enable = zeus_mcp2515_transceiver_enable, +}; + +static struct spi_board_info zeus_spi_board_info[] = { + [0] = { + .modalias = "mcp251x", + .platform_data = &zeus_mcp2515_pdata, + .irq = gpio_to_irq(ZEUS_CAN_GPIO), + .max_speed_hz = 1*1000*1000, + .bus_num = 3, + .mode = SPI_MODE_0, + .chip_select = 0, }, }; @@ -457,15 +494,28 @@ static struct platform_device zeus_pcmcia_device = { }, }; +static struct resource zeus_max6369_resource = { + .start = ZEUS_CPLD_EXTWDOG_PHYS, + .end = ZEUS_CPLD_EXTWDOG_PHYS, + .flags = IORESOURCE_MEM, +}; + +struct platform_device zeus_max6369_device = { + .name = "max6369_wdt", + .id = -1, + .resource = &zeus_max6369_resource, + .num_resources = 1, +}; + static struct platform_device *zeus_devices[] __initdata = { &zeus_serial_device, &zeus_mtd_devices[0], &zeus_dm9k0_device, &zeus_dm9k1_device, &zeus_sram_device, - &pxa2xx_spi_ssp3_device, &zeus_leds_device, &zeus_pcmcia_device, + &zeus_max6369_device, }; /* AC'97 */ @@ -509,7 +559,9 @@ static void zeus_ohci_exit(struct device *dev) static struct pxaohci_platform_data zeus_ohci_platform_data = { .port_mode = PMM_NPS_MODE, - .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW, + /* Clear Power Control Polarity Low and set Power Sense + * Polarity Low. Supply power to USB ports. */ + .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW, .init = zeus_ohci_init, .exit = zeus_ohci_exit, }; @@ -621,11 +673,15 @@ static struct pxa2xx_udc_mach_info zeus_udc_info = { .udc_command = zeus_udc_command, }; +#ifdef CONFIG_PM static void zeus_power_off(void) { local_irq_disable(); pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP); } +#else +#define zeus_power_off NULL +#endif #ifdef CONFIG_APM_EMULATION static void zeus_get_power_status(struct apm_power_info *info) @@ -706,6 +762,12 @@ static struct i2c_board_info __initdata zeus_i2c_devices[] = { }; static mfp_cfg_t zeus_pin_config[] __initdata = { + /* AC97 */ + GPIO28_AC97_BITCLK, + GPIO29_AC97_SDATA_IN_0, + GPIO30_AC97_SDATA_OUT, + GPIO31_AC97_SYNC, + GPIO15_nCS_1, GPIO78_nCS_2, GPIO80_nCS_4, @@ -731,6 +793,11 @@ static mfp_cfg_t zeus_pin_config[] __initdata = { GPIO104_CIF_DD_2, GPIO105_CIF_DD_1, + GPIO81_SSP3_TXD, + GPIO82_SSP3_RXD, + GPIO83_SSP3_SFRM, + GPIO84_SSP3_SCLK, + GPIO48_nPOE, GPIO49_nPWE, GPIO50_nPIOR, @@ -785,6 +852,8 @@ static void __init zeus_init(void) pxa_set_ac97_info(&zeus_ac97_info); pxa_set_i2c_info(NULL); i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices)); + pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info); + spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info)); } static struct map_desc zeus_io_desc[] __initdata = { @@ -807,12 +876,6 @@ static struct map_desc zeus_io_desc[] __initdata = { .type = MT_DEVICE, }, { - .virtual = ZEUS_CPLD_EXTWDOG, - .pfn = __phys_to_pfn(ZEUS_CPLD_EXTWDOG_PHYS), - .length = 0x1000, - .type = MT_DEVICE, - }, - { .virtual = ZEUS_PC104IO, .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS), .length = 0x00800000, @@ -837,7 +900,7 @@ static void __init zeus_map_io(void) PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP; } -MACHINE_START(ARCOM_ZEUS, "Arcom ZEUS") +MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS") /* Maintainer: Marc Zyngier <[email protected]> */ .phys_io = 0x40000000, .io_pg_offst = ((io_p2v(0x40000000) >> 18) & 0xfffc), diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h index f8b879a7973c..acb259103808 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-core.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h @@ -15,7 +15,6 @@ #ifndef __ASM_ARCH_GPIO_CORE_H #define __ASM_ARCH_GPIO_CORE_H __FILE__ -#include <plat/gpio-core.h> #include <mach/regs-gpio.h> extern struct s3c_gpio_chip s3c24xx_gpios[]; diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index 06a84adfb13f..7047317ed7f4 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c @@ -153,7 +153,7 @@ static struct platform_device *amlm5900_devices[] __initdata = { &s3c_device_adc, &s3c_device_wdt, &s3c_device_i2c0, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_rtc, &s3c_device_usbgadget, &s3c_device_sdi, diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 97162fdd0590..02b1b6220cba 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c @@ -584,7 +584,7 @@ static struct s3c_hwmon_pdata bast_hwmon_info = { // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0 static struct platform_device *bast_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 1e34abe1a19e..fbedd0760941 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c @@ -196,7 +196,7 @@ static struct platform_device h1940_device_bluetooth = { .id = -1, }; -static struct s3c24xx_mci_pdata h1940_mmc_cfg = { +static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = { .gpio_detect = S3C2410_GPF(5), .gpio_wprotect = S3C2410_GPH(8), .set_power = NULL, @@ -272,7 +272,7 @@ static struct platform_device h1940_lcd_powerdev = { static struct platform_device *h1940_devices[] __initdata = { &s3c_device_ts, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, @@ -311,12 +311,11 @@ static void __init h1940_init(void) u32 tmp; s3c24xx_fb_set_platdata(&h1940_fb_info); + s3c24xx_mci_set_platdata(&h1940_mmc_cfg); s3c24xx_udc_set_platdata(&h1940_udc_cfg); s3c24xx_ts_set_platdata(&h1940_ts_cfg); s3c_i2c0_set_platdata(NULL); - s3c_device_sdi.dev.platform_data = &h1940_mmc_cfg; - /* Turn off suspend on both USB ports, and switch the * selectable USB port to USB device mode. */ diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 0405712c2263..684710f88142 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c @@ -322,7 +322,7 @@ static struct platform_device *n30_devices[] __initdata = { &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_iis, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_usbgadget, &n30_button_device, &n30_blue_led, diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c index f6c7261a4a12..d8c7f2efc1a7 100644 --- a/arch/arm/mach-s3c2410/mach-otom.c +++ b/arch/arm/mach-s3c2410/mach-otom.c @@ -92,7 +92,7 @@ static struct platform_device otom_device_nor = { /* Standard OTOM devices */ static struct platform_device *otom11_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index ab092bcda393..92a4ec375d82 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c @@ -246,7 +246,7 @@ static struct platform_device qt2410_spi = { /* Board devices */ static struct platform_device *qt2410_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c index c49126ccb1d5..452223042201 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c @@ -87,7 +87,7 @@ static struct s3c2410_uartcfg smdk2410_uartcfgs[] __initdata = { }; static struct platform_device *smdk2410_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c index 8fdb0430bd48..929164a8e9b1 100644 --- a/arch/arm/mach-s3c2410/mach-tct_hammer.c +++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c @@ -129,7 +129,7 @@ static struct platform_device *tct_hammer_devices[] __initdata = { &s3c_device_adc, &s3c_device_wdt, &s3c_device_i2c0, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_rtc, &s3c_device_usbgadget, &s3c_device_sdi, diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 0d61fb577170..9051f0d31123 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c @@ -334,7 +334,7 @@ static struct i2c_board_info vr1000_i2c_devs[] __initdata = { /* devices for this board */ static struct platform_device *vr1000_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index 6b9d0d83a6f9..29bd3d987bec 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c @@ -91,7 +91,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on) } } -static struct s3c2410_hcd_info usb_simtec_info = { +static struct s3c2410_hcd_info usb_simtec_info __initdata = { .port[0] = { .flags = S3C_HCDFLG_USED }, @@ -127,6 +127,6 @@ int usb_simtec_init(void) gpio_direction_output(S3C2410_GPB(4), 1); gpio_direction_input(S3C2410_GPG(10)); - s3c_device_usb.dev.platform_data = &usb_simtec_info; + s3c_ohci_set_platdata(&usb_simtec_info); return 0; } diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index a037df5e1c2d..0c0505b025cb 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c @@ -124,7 +124,9 @@ static struct clk clk_usysclk = { .name = "usysclk", .id = -1, .parent = &clk_xtal, - .set_parent = s3c2412_setparent_usysclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2412_setparent_usysclk, + }, }; static struct clk clk_mrefclk = { @@ -199,10 +201,12 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) static struct clk clk_usbsrc = { .name = "usbsrc", .id = -1, - .get_rate = s3c2412_getrate_usbsrc, - .set_rate = s3c2412_setrate_usbsrc, - .round_rate = s3c2412_roundrate_usbsrc, - .set_parent = s3c2412_setparent_usbsrc, + .ops = &(struct clk_ops) { + .get_rate = s3c2412_getrate_usbsrc, + .set_rate = s3c2412_setrate_usbsrc, + .round_rate = s3c2412_roundrate_usbsrc, + .set_parent = s3c2412_setparent_usbsrc, + }, }; static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) @@ -225,7 +229,9 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) static struct clk clk_msysclk = { .name = "msysclk", .id = -1, - .set_parent = s3c2412_setparent_msysclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2412_setparent_msysclk, + }, }; static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) @@ -264,7 +270,9 @@ static struct clk clk_armclk = { .name = "armclk", .id = -1, .parent = &clk_msysclk, - .set_parent = s3c2412_setparent_armclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2412_setparent_armclk, + }, }; /* these next clocks have an divider immediately after them, @@ -337,10 +345,12 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) static struct clk clk_uart = { .name = "uartclk", .id = -1, - .get_rate = s3c2412_getrate_uart, - .set_rate = s3c2412_setrate_uart, - .set_parent = s3c2412_setparent_uart, - .round_rate = s3c2412_roundrate_clksrc, + .ops = &(struct clk_ops) { + .get_rate = s3c2412_getrate_uart, + .set_rate = s3c2412_setrate_uart, + .set_parent = s3c2412_setparent_uart, + .round_rate = s3c2412_roundrate_clksrc, + }, }; static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent) @@ -388,10 +398,12 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) static struct clk clk_i2s = { .name = "i2sclk", .id = -1, - .get_rate = s3c2412_getrate_i2s, - .set_rate = s3c2412_setrate_i2s, - .set_parent = s3c2412_setparent_i2s, - .round_rate = s3c2412_roundrate_clksrc, + .ops = &(struct clk_ops) { + .get_rate = s3c2412_getrate_i2s, + .set_rate = s3c2412_setrate_i2s, + .set_parent = s3c2412_setparent_i2s, + .round_rate = s3c2412_roundrate_clksrc, + }, }; static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent) @@ -438,10 +450,12 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) static struct clk clk_cam = { .name = "camif-upll", /* same as 2440 name */ .id = -1, - .get_rate = s3c2412_getrate_cam, - .set_rate = s3c2412_setrate_cam, - .set_parent = s3c2412_setparent_cam, - .round_rate = s3c2412_roundrate_clksrc, + .ops = &(struct clk_ops) { + .get_rate = s3c2412_getrate_cam, + .set_rate = s3c2412_setrate_cam, + .set_parent = s3c2412_setparent_cam, + .round_rate = s3c2412_roundrate_clksrc, + }, }; /* standard clock definitions */ diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index c9fa3fca486c..14f4798291aa 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c @@ -468,7 +468,7 @@ static struct i2c_board_info jive_i2c_devs[] __initdata = { /* The platform devices being used. */ static struct platform_device *jive_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_rtc, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index 9a5e43419722..0392065af1af 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c @@ -104,8 +104,7 @@ static struct s3c2410_udc_mach_info smdk2413_udc_cfg __initdata = { static struct platform_device *smdk2413_devices[] __initdata = { - &s3c_device_usb, - //&s3c_device_lcd, + &s3c_device_ohci, &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_iis, diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c index a6ba591b26bb..3ca9265b6997 100644 --- a/arch/arm/mach-s3c2412/mach-vstms.c +++ b/arch/arm/mach-s3c2412/mach-vstms.c @@ -121,7 +121,7 @@ static struct s3c2410_platform_nand __initdata vstms_nand_info = { }; static struct platform_device *vstms_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, &s3c_device_i2c0, &s3c_device_iis, diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c index d1c29b2537cd..3dc2426e2345 100644 --- a/arch/arm/mach-s3c2440/clock.c +++ b/arch/arm/mach-s3c2440/clock.c @@ -98,8 +98,10 @@ static struct clk s3c2440_clk_cam = { static struct clk s3c2440_clk_cam_upll = { .name = "camif-upll", .id = -1, - .set_rate = s3c2440_camif_upll_setrate, - .round_rate = s3c2440_camif_upll_round, + .ops = &(struct clk_ops) { + .set_rate = s3c2440_camif_upll_setrate, + .round_rate = s3c2440_camif_upll_round, + }, }; static struct clk s3c2440_clk_ac97 = { diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 62a4c3eba97f..b73f78a9da5c 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c @@ -409,7 +409,7 @@ static struct platform_device anubis_device_sm501 = { /* Standard Anubis devices */ static struct platform_device *anubis_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, &s3c_device_adc, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index aa69290e04c6..84725791e6bf 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c @@ -165,7 +165,7 @@ static struct platform_device at2440evb_device_eth = { }, }; -static struct s3c24xx_mci_pdata at2440evb_mci_pdata = { +static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = { .gpio_detect = S3C2410_GPG(10), }; @@ -203,7 +203,7 @@ static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = { }; static struct platform_device *at2440evb_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, &s3c_device_adc, &s3c_device_i2c0, @@ -216,8 +216,6 @@ static struct platform_device *at2440evb_devices[] __initdata = { static void __init at2440evb_map_io(void) { - s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata; - s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); s3c24xx_init_clocks(16934400); s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs)); @@ -226,6 +224,7 @@ static void __init at2440evb_map_io(void) static void __init at2440evb_init(void) { s3c24xx_fb_set_platdata(&at2440evb_fb_info); + s3c24xx_mci_set_platdata(&at2440evb_mci_pdata); s3c_nand_set_platdata(&at2440evb_nand_info); s3c_i2c0_set_platdata(NULL); diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index 2068e9096a43..571b17683d96 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c @@ -506,9 +506,8 @@ static struct i2c_board_info mini2440_i2c_devs[] __initdata = { }; static struct platform_device *mini2440_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, -/* &s3c_device_adc,*/ /* ADC doesn't like living with touchscreen ! */ &s3c_device_i2c0, &s3c_device_rtc, &s3c_device_usbgadget, @@ -522,8 +521,6 @@ static struct platform_device *mini2440_devices[] __initdata = { &s3c_device_sdi, &s3c_device_iis, &mini2440_audio, -/* &s3c_device_timer[0],*/ /* buzzer pwm, no API for it */ - /* remaining devices are optional */ }; static void __init mini2440_map_io(void) @@ -531,8 +528,6 @@ static void __init mini2440_map_io(void) s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc)); s3c24xx_init_clocks(12000000); s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); - - s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg; } /* @@ -678,6 +673,7 @@ static void __init mini2440_init(void) } s3c24xx_udc_set_platdata(&mini2440_udc_cfg); + s3c24xx_mci_set_platdata(&mini2440_mmc_cfg); s3c_nand_set_platdata(&mini2440_nand_info); s3c_i2c0_set_platdata(NULL); diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c index d43edede590e..86a243b3e37d 100644 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c @@ -106,7 +106,7 @@ static struct platform_device nexcoder_device_nor = { /* Standard Nexcoder devices */ static struct platform_device *nexcoder_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index a952a13afb1f..1e836e506f8b 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c @@ -176,7 +176,7 @@ static struct s3c2410_platform_nand __initdata rx3715_nand_info = { }; static struct platform_device *rx3715_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index ec13e748ccc5..df3e9a3be82f 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c @@ -150,7 +150,7 @@ static struct s3c2410fb_mach_info smdk2440_fb_info __initdata = { }; static struct platform_device *smdk2440_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c0, diff --git a/arch/arm/mach-s3c2442/clock.c b/arch/arm/mach-s3c2442/clock.c index ea1aa1f5157a..d9b692a12480 100644 --- a/arch/arm/mach-s3c2442/clock.c +++ b/arch/arm/mach-s3c2442/clock.c @@ -109,8 +109,10 @@ static struct clk s3c2442_clk_cam = { static struct clk s3c2442_clk_cam_upll = { .name = "camif-upll", .id = -1, - .set_rate = s3c2442_camif_upll_setrate, - .round_rate = s3c2442_camif_upll_round, + .ops = &(struct clk_ops) { + .set_rate = s3c2442_camif_upll_setrate, + .round_rate = s3c2442_camif_upll_round, + }, }; static int s3c2442_clk_add(struct sys_device *sysdev) diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c index 0b4a3a03071f..45799c608d8f 100644 --- a/arch/arm/mach-s3c2442/mach-gta02.c +++ b/arch/arm/mach-s3c2442/mach-gta02.c @@ -544,7 +544,7 @@ static struct platform_device gta02_bl_dev = { /* USB */ -static struct s3c2410_hcd_info gta02_usb_info = { +static struct s3c2410_hcd_info gta02_usb_info __initdata = { .port[0] = { .flags = S3C_HCDFLG_USED, }, @@ -565,7 +565,7 @@ static void __init gta02_map_io(void) /* These are the guys that don't need to be children of PMU. */ static struct platform_device *gta02_devices[] __initdata = { - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_wdt, &s3c_device_sdi, &s3c_device_usbgadget, @@ -623,9 +623,8 @@ static void __init gta02_machine_init(void) INIT_DELAYED_WORK(>a02_charger_work, gta02_charger_worker); #endif - s3c_device_usb.dev.platform_data = >a02_usb_info; - s3c24xx_udc_set_platdata(>a02_udc_cfg); + s3c_ohci_set_platdata(>a02_usb_info); s3c_nand_set_platdata(>a02_nand_info); s3c_i2c0_set_platdata(NULL); diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index 2785d69c95b0..3eb8b935d64c 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c @@ -187,7 +187,9 @@ static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent) static struct clk clk_epllref = { .name = "epllref", .id = -1, - .set_parent = s3c2443_setparent_epllref, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_epllref, + }, }; static unsigned long s3c2443_getrate_mdivclk(struct clk *clk) @@ -205,7 +207,9 @@ static struct clk clk_mdivclk = { .name = "mdivclk", .parent = &clk_mpllref, .id = -1, - .get_rate = s3c2443_getrate_mdivclk, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_mdivclk, + }, }; static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) @@ -232,7 +236,9 @@ static struct clk clk_msysclk = { .name = "msysclk", .parent = &clk_xtal, .id = -1, - .set_parent = s3c2443_setparent_msysclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_msysclk, + }, }; /* armdiv @@ -273,7 +279,9 @@ static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent) static struct clk clk_arm = { .name = "armclk", .id = -1, - .set_parent = s3c2443_setparent_armclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_armclk, + }, }; /* esysclk @@ -302,7 +310,9 @@ static struct clk clk_esysclk = { .name = "esysclk", .parent = &clk_epll, .id = -1, - .set_parent = s3c2443_setparent_esysclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_esysclk, + }, }; /* uartclk @@ -341,9 +351,11 @@ static struct clk clk_uart = { .name = "uartclk", .id = -1, .parent = &clk_esysclk, - .get_rate = s3c2443_getrate_uart, - .set_rate = s3c2443_setrate_uart, - .round_rate = s3c2443_roundrate_clksrc16, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_uart, + .set_rate = s3c2443_setrate_uart, + .round_rate = s3c2443_roundrate_clksrc16, + }, }; /* hsspi @@ -384,9 +396,11 @@ static struct clk clk_hsspi = { .parent = &clk_esysclk, .ctrlbit = S3C2443_SCLKCON_HSSPICLK, .enable = s3c2443_clkcon_enable_s, - .get_rate = s3c2443_getrate_hsspi, - .set_rate = s3c2443_setrate_hsspi, - .round_rate = s3c2443_roundrate_clksrc4, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_hsspi, + .set_rate = s3c2443_setrate_hsspi, + .round_rate = s3c2443_roundrate_clksrc4, + }, }; /* usbhost @@ -426,9 +440,11 @@ static struct clk clk_usb_bus_host = { .parent = &clk_esysclk, .ctrlbit = S3C2443_SCLKCON_USBHOST, .enable = s3c2443_clkcon_enable_s, - .get_rate = s3c2443_getrate_usbhost, - .set_rate = s3c2443_setrate_usbhost, - .round_rate = s3c2443_roundrate_clksrc4, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_usbhost, + .set_rate = s3c2443_setrate_usbhost, + .round_rate = s3c2443_roundrate_clksrc4, + }, }; /* clk_hsmcc_div @@ -468,9 +484,11 @@ static struct clk clk_hsmmc_div = { .name = "hsmmc-div", .id = -1, .parent = &clk_esysclk, - .get_rate = s3c2443_getrate_hsmmc_div, - .set_rate = s3c2443_setrate_hsmmc_div, - .round_rate = s3c2443_roundrate_clksrc4, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_hsmmc_div, + .set_rate = s3c2443_setrate_hsmmc_div, + .round_rate = s3c2443_roundrate_clksrc4, + }, }; static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) @@ -505,7 +523,9 @@ static struct clk clk_hsmmc = { .id = -1, .parent = &clk_hsmmc_div, .enable = s3c2443_enable_hsmmc, - .set_parent = s3c2443_setparent_hsmmc, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_hsmmc, + }, }; /* i2s_eplldiv @@ -543,9 +563,11 @@ static struct clk clk_i2s_eplldiv = { .name = "i2s-eplldiv", .id = -1, .parent = &clk_esysclk, - .get_rate = s3c2443_getrate_i2s_eplldiv, - .set_rate = s3c2443_setrate_i2s_eplldiv, - .round_rate = s3c2443_roundrate_clksrc16, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_i2s_eplldiv, + .set_rate = s3c2443_setrate_i2s_eplldiv, + .round_rate = s3c2443_roundrate_clksrc16, + }, }; /* i2s-ref @@ -578,7 +600,9 @@ static struct clk clk_i2s = { .parent = &clk_i2s_eplldiv, .ctrlbit = S3C2443_SCLKCON_I2SCLK, .enable = s3c2443_clkcon_enable_s, - .set_parent = s3c2443_setparent_i2s, + .ops = &(struct clk_ops) { + .set_parent = s3c2443_setparent_i2s, + }, }; /* cam-if @@ -618,9 +642,11 @@ static struct clk clk_cam = { .parent = &clk_esysclk, .ctrlbit = S3C2443_SCLKCON_CAMCLK, .enable = s3c2443_clkcon_enable_s, - .get_rate = s3c2443_getrate_cam, - .set_rate = s3c2443_setrate_cam, - .round_rate = s3c2443_roundrate_clksrc16, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_cam, + .set_rate = s3c2443_setrate_cam, + .round_rate = s3c2443_roundrate_clksrc16, + }, }; /* display-if @@ -660,9 +686,11 @@ static struct clk clk_display = { .parent = &clk_esysclk, .ctrlbit = S3C2443_SCLKCON_DISPCLK, .enable = s3c2443_clkcon_enable_s, - .get_rate = s3c2443_getrate_display, - .set_rate = s3c2443_setrate_display, - .round_rate = s3c2443_roundrate_clksrc256, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_getrate_display, + .set_rate = s3c2443_setrate_display, + .round_rate = s3c2443_roundrate_clksrc256, + }, }; /* prediv @@ -685,7 +713,9 @@ static struct clk clk_prediv = { .name = "prediv", .id = -1, .parent = &clk_msysclk, - .get_rate = s3c2443_prediv_getrate, + .ops = &(struct clk_ops) { + .get_rate = s3c2443_prediv_getrate, + }, }; /* standard clock definitions */ @@ -1074,14 +1104,7 @@ void __init s3c2443_init_clocks(int xtal) /* register clocks from clock array */ - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); /* We must be careful disabling the clocks we are not intending to * be using at boot time, as subsystems such as the LCD which do diff --git a/arch/arm/mach-s3c6400/include/mach/entry-macro.S b/arch/arm/mach-s3c6400/include/mach/entry-macro.S index fbd90d2cf355..33a8fe240882 100644 --- a/arch/arm/mach-s3c6400/include/mach/entry-macro.S +++ b/arch/arm/mach-s3c6400/include/mach/entry-macro.S @@ -12,33 +12,7 @@ * warranty of any kind, whether express or implied. */ -#include <asm/hardware/vic.h> #include <mach/map.h> #include <plat/irqs.h> - .macro disable_fiq - .endm - - .macro get_irqnr_preamble, base, tmp - ldr \base, =S3C_VA_VIC0 - .endm - - .macro arch_ret_to_user, tmp1, tmp2 - .endm - - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - - @ check the vic0 - mov \irqnr, # S3C_IRQ_OFFSET + 31 - ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] - teq \irqstat, #0 - - @ otherwise try vic1 - addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) - addeq \irqnr, \irqnr, #32 - ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] - teqeq \irqstat, #0 - - clzne \irqstat, \irqstat - subne \irqnr, \irqnr, \irqstat - .endm +#include <asm/entry-macro-vic2.S> diff --git a/arch/arm/mach-s3c6400/include/mach/gpio-core.h b/arch/arm/mach-s3c6400/include/mach/gpio-core.h deleted file mode 100644 index d89aae68b0a5..000000000000 --- a/arch/arm/mach-s3c6400/include/mach/gpio-core.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-s3c6400/include/mach/gpio-core.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <[email protected]> - * http://armlinux.simtec.co.uk/ - * - * S3C64XX - GPIO core support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_CORE_H -#define __ASM_ARCH_GPIO_CORE_H __FILE__ - -/* currently we just include the platform support */ -#include <plat/gpio-core.h> - -#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index 106ee13581e2..801c1c0f3a95 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h @@ -17,6 +17,18 @@ #include <plat/map-base.h> +/* + * Post-mux Chip Select Regions Xm0CSn_ + * These may be used by SROM, NAND or CF depending on settings + */ + +#define S3C64XX_PA_XM0CSN0 (0x10000000) +#define S3C64XX_PA_XM0CSN1 (0x18000000) +#define S3C64XX_PA_XM0CSN2 (0x20000000) +#define S3C64XX_PA_XM0CSN3 (0x28000000) +#define S3C64XX_PA_XM0CSN4 (0x30000000) +#define S3C64XX_PA_XM0CSN5 (0x38000000) + /* HSMMC units */ #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) @@ -38,16 +50,22 @@ #define S3C_VA_UART2 S3C_VA_UARTx(2) #define S3C_VA_UART3 S3C_VA_UARTx(3) +#define S3C64XX_PA_SROM (0x70000000) + #define S3C64XX_PA_NAND (0x70200000) #define S3C64XX_PA_FB (0x77100000) #define S3C64XX_PA_USB_HSOTG (0x7C000000) #define S3C64XX_PA_WATCHDOG (0x7E004000) +#define S3C64XX_PA_RTC (0x7E005000) +#define S3C64XX_PA_ADC (0x7E00B000) #define S3C64XX_PA_SYSCON (0x7E00F000) #define S3C64XX_PA_AC97 (0x7F001000) #define S3C64XX_PA_IIS0 (0x7F002000) #define S3C64XX_PA_IIS1 (0x7F003000) #define S3C64XX_PA_TIMER (0x7F006000) #define S3C64XX_PA_IIC0 (0x7F004000) +#define S3C64XX_PA_SPI0 (0x7F00B000) +#define S3C64XX_PA_SPI1 (0x7F00C000) #define S3C64XX_PA_PCM0 (0x7F009000) #define S3C64XX_PA_PCM1 (0x7F00A000) #define S3C64XX_PA_IISV4 (0x7F00D000) @@ -70,8 +88,8 @@ #define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000) /* place VICs close together */ -#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) -#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) +#define VA_VIC0 (S3C_VA_IRQ + 0x00) +#define VA_VIC1 (S3C_VA_IRQ + 0x10000) /* compatibiltiy defines. */ #define S3C_PA_TIMER S3C64XX_PA_TIMER diff --git a/arch/arm/mach-s3c6400/include/mach/tick.h b/arch/arm/mach-s3c6400/include/mach/tick.h index d9c0dc7014ec..ebe18a9469b8 100644 --- a/arch/arm/mach-s3c6400/include/mach/tick.h +++ b/arch/arm/mach-s3c6400/include/mach/tick.h @@ -20,7 +20,7 @@ */ static inline u32 s3c24xx_ostimer_pending(void) { - u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); + u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0)); } diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c index 7619456f2ae8..f05d95784d72 100644 --- a/arch/arm/mach-s3c6410/mach-hmt.c +++ b/arch/arm/mach-s3c6410/mach-hmt.c @@ -233,7 +233,7 @@ static struct platform_device *hmt_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_nand, &s3c_device_fb, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_timer[1], &hmt_backlight_device, &hmt_leds_device, diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c index 8969fe73b83f..eba345fadffe 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c @@ -49,6 +49,7 @@ #include <plat/regs-modem.h> #include <plat/regs-gpio.h> #include <plat/regs-sys.h> +#include <plat/regs-srom.h> #include <plat/iic.h> #include <plat/fb.h> #include <plat/gpio-cfg.h> @@ -154,10 +155,20 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, }; +/* + * Configuring Ethernet on SMDK6410 + * + * Both CS8900A and LAN9115 chips share one chip select mediated by CFG6. + * The constant address below corresponds to nCS1 + * + * 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet" + * 2) CFG6 needs to be switched to "LAN9115" side + */ + static struct resource smdk6410_smsc911x_resources[] = { [0] = { - .start = 0x18000000, - .end = 0x18000000 + SZ_64K - 1, + .start = S3C64XX_PA_XM0CSN1, + .end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -235,7 +246,7 @@ static struct platform_device *smdk6410_devices[] __initdata = { &s3c_device_i2c0, &s3c_device_i2c1, &s3c_device_fb, - &s3c_device_usb, + &s3c_device_ohci, &s3c_device_usb_hsotg, #ifdef CONFIG_REGULATOR @@ -388,6 +399,7 @@ static int __init smdk6410_wm8350_init(struct wm8350 *wm8350) static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = { .init = smdk6410_wm8350_init, .irq_high = 1, + .irq_base = IRQ_BOARD_START, }; #endif @@ -430,10 +442,32 @@ static void __init smdk6410_map_io(void) static void __init smdk6410_machine_init(void) { + u32 cs1; + s3c_i2c0_set_platdata(NULL); s3c_i2c1_set_platdata(NULL); s3c_fb_set_platdata(&smdk6410_lcd_pdata); + /* configure nCS1 width to 16 bits */ + + cs1 = __raw_readl(S3C64XX_SROM_BW) & + ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT); + cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) | + (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) | + (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) << + S3C64XX_SROM_BW__NCS1__SHIFT; + __raw_writel(cs1, S3C64XX_SROM_BW); + + /* set timing for nCS1 suitable for ethernet chip */ + + __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | + (6 << S3C64XX_SROM_BCX__TACP__SHIFT) | + (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | + (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | + (0xe << S3C64XX_SROM_BCX__TACC__SHIFT) | + (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | + (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); + gpio_request(S3C64XX_GPN(5), "LCD power"); gpio_request(S3C64XX_GPF(13), "LCD power"); gpio_request(S3C64XX_GPF(15), "LCD power"); diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig new file mode 100644 index 000000000000..3aa246244dcf --- /dev/null +++ b/arch/arm/mach-s5p6440/Kconfig @@ -0,0 +1,23 @@ +# arch/arm/mach-s5p6440/Kconfig +# +# Copyright (c) 2009 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +if ARCH_S5P6440 + +config CPU_S5P6440 + bool + select CPU_S5P6440_INIT + select CPU_S5P6440_CLOCK + help + Enable S5P6440 CPU support + +config MACH_SMDK6440 + bool "SMDK6440" + select CPU_S5P6440 + help + Machine support for the Samsung SMDK6440 + +endif diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile new file mode 100644 index 000000000000..a79b13011edc --- /dev/null +++ b/arch/arm/mach-s5p6440/Makefile @@ -0,0 +1,19 @@ +# arch/arm/mach-s5p6440/Makefile +# +# Copyright (c) 2009 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := +obj- := + +# Core support for S5P6440 system + +obj-$(CONFIG_CPU_S5P6440) += cpu.o s5p6440-gpio.o + +# machine support + +obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o diff --git a/arch/arm/mach-s5p6440/Makefile.boot b/arch/arm/mach-s5p6440/Makefile.boot new file mode 100644 index 000000000000..ff90aa13bd67 --- /dev/null +++ b/arch/arm/mach-s5p6440/Makefile.boot @@ -0,0 +1,2 @@ + zreladdr-y := 0x20008000 +params_phys-y := 0x20000100 diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c new file mode 100644 index 000000000000..1794131aeacb --- /dev/null +++ b/arch/arm/mach-s5p6440/cpu.c @@ -0,0 +1,114 @@ +/* linux/arch/arm/mach-s5p6440/cpu.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/init.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/sysdev.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> + +#include <asm/proc-fns.h> + +#include <mach/hardware.h> +#include <mach/map.h> +#include <asm/irq.h> + +#include <plat/regs-serial.h> +#include <mach/regs-clock.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/clock.h> +#include <plat/s5p6440.h> + +static void s5p6440_idle(void) +{ + unsigned long val; + + if (!need_resched()) { + val = __raw_readl(S5P_PWR_CFG); + val &= ~(0x3<<5); + val |= (0x1<<5); + __raw_writel(val, S5P_PWR_CFG); + + cpu_do_idle(); + } + local_irq_enable(); +} + +/* s5p6440_map_io + * + * register the standard cpu IO areas +*/ + +void __init s5p6440_map_io(void) +{ + /* initialize any device information early */ +} + +void __init s5p6440_init_clocks(int xtal) +{ + printk(KERN_DEBUG "%s: initializing clocks\n", __func__); + + s3c24xx_register_baseclocks(xtal); + s5p_register_clocks(xtal); + s5p6440_register_clocks(); + s5p6440_setup_clocks(); +} + +void __init s5p6440_init_irq(void) +{ + /* S5P6440 supports only 2 VIC */ + u32 vic[2]; + + /* + * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)] + * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22] + */ + vic[0] = 0xff800ae7; + vic[1] = 0xffbf23e5; + + s5p_init_irq(vic, ARRAY_SIZE(vic)); +} + +static struct sysdev_class s5p6440_sysclass = { + .name = "s5p6440-core", +}; + +static struct sys_device s5p6440_sysdev = { + .cls = &s5p6440_sysclass, +}; + +static int __init s5p6440_core_init(void) +{ + return sysdev_class_register(&s5p6440_sysclass); +} + +core_initcall(s5p6440_core_init); + +int __init s5p6440_init(void) +{ + printk(KERN_INFO "S5P6440: Initializing architecture\n"); + + /* set idle function */ + pm_idle = s5p6440_idle; + + return sysdev_register(&s5p6440_sysdev); +} diff --git a/arch/arm/mach-s5p6440/include/mach/debug-macro.S b/arch/arm/mach-s5p6440/include/mach/debug-macro.S new file mode 100644 index 000000000000..f3a5d1635be5 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/debug-macro.S @@ -0,0 +1,37 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +#include <mach/map.h> +#include <plat/regs-serial.h> + + /* note, for the boot process to work we have to keep the UART + * virtual address aligned to an 1MiB boundary for the L1 + * mapping the head code makes. We keep the UART virtual address + * aligned and add in the offset when we load the value here. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 + ldreq \rx, = S5P_PA_UART + ldrne \rx, = (S5P_VA_UART + S5P_PA_UART & 0xfffff) +#if CONFIG_DEBUG_S3C_UART != 0 + add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) +#endif + .endm + +/* include the reset of the code which will do the work, we're only + * compiling for a single cpu processor type so the default of s3c2440 + * will be fine with us. + */ + +#include <plat/debug-macro.S> diff --git a/arch/arm/mach-s5p6440/include/mach/entry-macro.S b/arch/arm/mach-s5p6440/include/mach/entry-macro.S new file mode 100644 index 000000000000..e65f1b967262 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/entry-macro.S @@ -0,0 +1,16 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Low-level IRQ helper macros for the Samsung S5P6440 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <mach/map.h> +#include <plat/irqs.h> + +#include <asm/entry-macro-vic2.S> diff --git a/arch/arm/mach-s5p6440/include/mach/gpio.h b/arch/arm/mach-s5p6440/include/mach/gpio.h new file mode 100644 index 000000000000..21783834f2a2 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/gpio.h @@ -0,0 +1,80 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - GPIO lib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H __FILE__ + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + +/* GPIO bank sizes */ +#define S5P6440_GPIO_A_NR (6) +#define S5P6440_GPIO_B_NR (7) +#define S5P6440_GPIO_C_NR (8) +#define S5P6440_GPIO_F_NR (2) +#define S5P6440_GPIO_G_NR (7) +#define S5P6440_GPIO_H_NR (10) +#define S5P6440_GPIO_I_NR (16) +#define S5P6440_GPIO_J_NR (12) +#define S5P6440_GPIO_N_NR (16) +#define S5P6440_GPIO_P_NR (8) +#define S5P6440_GPIO_R_NR (15) + +/* GPIO bank numbers */ + +/* CONFIG_S3C_GPIO_SPACE allows the user to select extra + * space for debugging purposes so that any accidental + * change from one gpio bank to another can be caught. +*/ +#define S5P6440_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) + +enum s5p_gpio_number { + S5P6440_GPIO_A_START = 0, + S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A), + S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B), + S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C), + S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F), + S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G), + S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H), + S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I), + S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J), + S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N), + S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P), +}; + +/* S5P6440 GPIO number definitions. */ +#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr)) +#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr)) +#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr)) +#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr)) +#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr)) +#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr)) +#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr)) +#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr)) +#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr)) +#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr)) +#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr)) + +/* the end of the S5P6440 specific gpios */ +#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1) +#define S3C_GPIO_END S5P6440_GPIO_END + +/* define the number of gpios we need to the one after the GPR() range */ +#define ARCH_NR_GPIOS (S5P6440_GPR(S5P6440_GPIO_R_NR) + \ + CONFIG_SAMSUNG_GPIO_EXTRA + 1) + +#include <asm-generic/gpio.h> + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/hardware.h b/arch/arm/mach-s5p6440/include/mach/hardware.h new file mode 100644 index 000000000000..be8b26e875db --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/hardware.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/hardware.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Hardware support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H __FILE__ + +/* currently nothing here, placeholder */ + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p6440/include/mach/irqs.h new file mode 100644 index 000000000000..a4b9b40d18f2 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/irqs.h @@ -0,0 +1,111 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h + * + * Copyright 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - IRQ definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_S5P_IRQS_H +#define __ASM_ARCH_S5P_IRQS_H __FILE__ + +#include <plat/irqs.h> + +/* VIC0 */ + +#define IRQ_EINT0_3 S5P_IRQ_VIC0(0) +#define IRQ_EINT4_11 S5P_IRQ_VIC0(1) +#define IRQ_RTC_TIC S5P_IRQ_VIC0(2) +#define IRQ_IIC1 S5P_IRQ_VIC0(5) +#define IRQ_I2SV40 S5P_IRQ_VIC0(6) +#define IRQ_GPS S5P_IRQ_VIC0(7) +#define IRQ_POST0 S5P_IRQ_VIC0(9) +#define IRQ_2D S5P_IRQ_VIC0(11) +#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23) +#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24) +#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25) +#define IRQ_WDT S5P_IRQ_VIC0(26) +#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27) +#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28) +#define IRQ_DISPCON0 S5P_IRQ_VIC0(29) +#define IRQ_DISPCON1 S5P_IRQ_VIC0(30) +#define IRQ_DISPCON2 S5P_IRQ_VIC0(31) + +/* VIC1 */ + +#define IRQ_EINT12_15 S5P_IRQ_VIC1(0) +#define IRQ_PCM0 S5P_IRQ_VIC1(2) +#define IRQ_UART0 S5P_IRQ_VIC1(5) +#define IRQ_UART1 S5P_IRQ_VIC1(6) +#define IRQ_UART2 S5P_IRQ_VIC1(7) +#define IRQ_UART3 S5P_IRQ_VIC1(8) +#define IRQ_DMA0 S5P_IRQ_VIC1(9) +#define IRQ_NFC S5P_IRQ_VIC1(13) +#define IRQ_SPI0 S5P_IRQ_VIC1(16) +#define IRQ_SPI1 S5P_IRQ_VIC1(17) +#define IRQ_IIC S5P_IRQ_VIC1(18) +#define IRQ_DISPCON3 S5P_IRQ_VIC1(19) +#define IRQ_FIMGVG S5P_IRQ_VIC1(20) +#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) +#define IRQ_PMUIRQ S5P_IRQ_VIC1(23) +#define IRQ_HSMMC0 S5P_IRQ_VIC1(24) +#define IRQ_HSMMC1 S5P_IRQ_VIC1(25) +#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ +#define IRQ_OTG S5P_IRQ_VIC1(26) +#define IRQ_DSI S5P_IRQ_VIC1(27) +#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28) +#define IRQ_TSI S5P_IRQ_VIC1(29) +#define IRQ_PENDN S5P_IRQ_VIC1(30) +#define IRQ_TC IRQ_PENDN +#define IRQ_ADC S5P_IRQ_VIC1(31) + +/* + * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined + * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place + * after the pair of VICs. + */ + +#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6) + +#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) +#define IRQ_EINT(x) S5P_EINT(x) + +/* + * Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ + +/* Actually, #6 and #7 are missing in the EINT_GROUP1 */ +#define IRQ_EINT_GROUP1_NR (15) +#define IRQ_EINT_GROUP2_NR (8) +#define IRQ_EINT_GROUP5_NR (7) +#define IRQ_EINT_GROUP6_NR (10) +/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */ +#define IRQ_EINT_GROUP8_NR (11) + +#define IRQ_EINT_GROUP_BASE S5P_EINT(16) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) + +#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) + +/* Set the default NR_IRQS */ + +#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) + +#endif /* __ASM_ARCH_S5P_IRQS_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h new file mode 100644 index 000000000000..4a73e73c9428 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/map.h @@ -0,0 +1,107 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/map.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MAP_H +#define __ASM_ARCH_MAP_H __FILE__ + +#include <plat/map-base.h> + +/* Chip ID */ +#define S5P6440_PA_CHIPID (0xE0000000) +#define S5P_PA_CHIPID S5P6440_PA_CHIPID +#define S5P_VA_CHIPID S3C_ADDR(0x00700000) + +/* SYSCON */ +#define S5P6440_PA_SYSCON (0xE0100000) +#define S5P_PA_SYSCON S5P6440_PA_SYSCON +#define S5P_VA_SYSCON S3C_VA_SYS + +#define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0) +#define S5P_PA_CLK S5P6440_PA_CLK +#define S5P_VA_CLK (S5P_VA_SYSCON + 0x0) + +/* GPIO */ +#define S5P6440_PA_GPIO (0xE0308000) +#define S5P_PA_GPIO S5P6440_PA_GPIO +#define S5P_VA_GPIO S3C_ADDR(0x00500000) + +/* VIC0 */ +#define S5P6440_PA_VIC0 (0xE4000000) +#define S5P_PA_VIC0 S5P6440_PA_VIC0 +#define S5P_VA_VIC0 (S3C_VA_IRQ + 0x0) +#define VA_VIC0 S5P_VA_VIC0 + +/* VIC1 */ +#define S5P6440_PA_VIC1 (0xE4100000) +#define S5P_PA_VIC1 S5P6440_PA_VIC1 +#define S5P_VA_VIC1 (S3C_VA_IRQ + 0x10000) +#define VA_VIC1 S5P_VA_VIC1 + +/* Timer */ +#define S5P6440_PA_TIMER (0xEA000000) +#define S5P_PA_TIMER S5P6440_PA_TIMER +#define S5P_VA_TIMER S3C_VA_TIMER + +/* RTC */ +#define S5P6440_PA_RTC (0xEA100000) +#define S5P_PA_RTC S5P6440_PA_RTC +#define S5P_VA_RTC S3C_ADDR(0x00600000) + +/* WDT */ +#define S5P6440_PA_WDT (0xEA200000) +#define S5P_PA_WDT S5P6440_PA_WDT +#define S5p_VA_WDT S3C_VA_WATCHDOG + +/* UART */ +#define S5P6440_PA_UART (0xEC000000) +#define S5P_PA_UART S5P6440_PA_UART +#define S5P_VA_UART S3C_VA_UART + +/* HS USB OtG */ +#define S5P6440_PA_HSOTG (0xED100000) + +/* HSMMC */ +#define S5P6440_PA_HSMMC0 (0xED800000) +#define S5P6440_PA_HSMMC1 (0xED900000) +#define S5P6440_PA_HSMMC2 (0xEDA00000) + +#define S5P_PA_UART0 (S5P_PA_UART + 0x0) +#define S5P_PA_UART1 (S5P_PA_UART + 0x400) +#define S5P_PA_UART2 (S5P_PA_UART + 0x800) +#define S5P_PA_UART3 (S5P_PA_UART + 0xC00) +#define S5P_UART_OFFSET (0x400) + +#define S5P_VA_UARTx(x) (S5P_VA_UART + (S5P_PA_UART & 0xfffff) \ + + ((x) * S5P_UART_OFFSET)) + +#define S5P_VA_UART0 S5P_VA_UARTx(0) +#define S5P_VA_UART1 S5P_VA_UARTx(1) +#define S5P_VA_UART2 S5P_VA_UARTx(2) +#define S5P_VA_UART3 S5P_VA_UARTx(3) +#define S5P_SZ_UART SZ_256 + +/* I2C */ +#define S5P6440_PA_IIC0 (0xEC104000) +#define S5P_PA_IIC0 S5P6440_PA_IIC0 +#define S5p_VA_IIC0 S3C_ADDR(0x00700000) + +/* SDRAM */ +#define S5P6440_PA_SDRAM (0x20000000) +#define S5P_PA_SDRAM S5P6440_PA_SDRAM + +/* compatibiltiy defines. */ +#define S3C_PA_UART S5P_PA_UART +#define S3C_UART_OFFSET S5P_UART_OFFSET +#define S3C_PA_TIMER S5P_PA_TIMER +#define S3C_PA_IIC S5P_PA_IIC0 + +#endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/memory.h b/arch/arm/mach-s5p6440/include/mach/memory.h new file mode 100644 index 000000000000..d62910c71b56 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/memory.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/memory.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Memory definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PHYS_OFFSET UL(0x20000000) +#define CONSISTENT_DMA_SIZE SZ_8M + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h new file mode 100644 index 000000000000..c4bb7c555477 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h @@ -0,0 +1,62 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <[email protected]> + * http://armlinux.simtec.co.uk/ + * + * Copyright 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - pwm clock and timer support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/** + * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk + * @cfg: The timer TCFG1 register bits shifted down to 0. + * + * Return true if the given configuration from TCFG1 is a TCLK instead + * any of the TDIV clocks. + */ +static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) +{ + return tcfg == S3C2410_TCFG1_MUX_TCLK; +} + +/** + * tcfg_to_divisor() - convert tcfg1 setting to a divisor + * @tcfg1: The tcfg1 setting, shifted down. + * + * Get the divisor value for the given tcfg1 setting. We assume the + * caller has already checked to see if this is not a TCLK source. + */ +static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) +{ + return 1 << (1 + tcfg1); +} + +/** + * pwm_tdiv_has_div1() - does the tdiv setting have a /1 + * + * Return true if we have a /1 in the tdiv setting. + */ +static inline unsigned int pwm_tdiv_has_div1(void) +{ + return 0; +} + +/** + * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. + * @div: The divisor to calculate the bit information for. + * + * Turn a divisor into the necessary bit field for TCFG1. + */ +static inline unsigned long pwm_tdiv_div_bits(unsigned int div) +{ + return ilog2(div) - 1; +} + +#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK diff --git a/arch/arm/mach-s5p6440/include/mach/regs-clock.h b/arch/arm/mach-s5p6440/include/mach/regs-clock.h new file mode 100644 index 000000000000..b7af28342bc4 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/regs-clock.h @@ -0,0 +1,130 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Clock register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_CLOCK_H +#define __ASM_ARCH_REGS_CLOCK_H __FILE__ + +#include <mach/map.h> + +#define S5P_CLKREG(x) (S5P_VA_CLK + (x)) + +#define S5P_APLL_LOCK S5P_CLKREG(0x00) +#define S5P_MPLL_LOCK S5P_CLKREG(0x04) +#define S5P_EPLL_LOCK S5P_CLKREG(0x08) +#define S5P_APLL_CON S5P_CLKREG(0x0C) +#define S5P_MPLL_CON S5P_CLKREG(0x10) +#define S5P_EPLL_CON S5P_CLKREG(0x14) +#define S5P_EPLL_CON_K S5P_CLKREG(0x18) +#define S5P_CLK_SRC0 S5P_CLKREG(0x1C) +#define S5P_CLK_DIV0 S5P_CLKREG(0x20) +#define S5P_CLK_DIV1 S5P_CLKREG(0x24) +#define S5P_CLK_DIV2 S5P_CLKREG(0x28) +#define S5P_CLK_OUT S5P_CLKREG(0x2C) +#define S5P_CLK_GATE_HCLK0 S5P_CLKREG(0x30) +#define S5P_CLK_GATE_PCLK S5P_CLKREG(0x34) +#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x38) +#define S5P_CLK_GATE_MEM0 S5P_CLKREG(0x3C) +#define S5P_CLK_DIV3 S5P_CLKREG(0x40) +#define S5P_CLK_GATE_HCLK1 S5P_CLKREG(0x44) +#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x48) +#define S5P_AHB_CON0 S5P_CLKREG(0x100) +#define S5P_CLK_SRC1 S5P_CLKREG(0x10C) +#define S5P_SWRESET S5P_CLKREG(0x114) +#define S5P_SYS_ID S5P_CLKREG(0x118) +#define S5P_SYS_OTHERS S5P_CLKREG(0x11C) +#define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C) +#define S5P_PWR_CFG S5P_CLKREG(0x804) +#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x808) +#define S5P_NORMAL_CFG S5P_CLKREG(0x810) +#define S5P_STOP_CFG S5P_CLKREG(0x814) +#define S5P_SLEEP_CFG S5P_CLKREG(0x818) +#define S5P_OSC_FREQ S5P_CLKREG(0x820) +#define S5P_OSC_STABLE S5P_CLKREG(0x824) +#define S5P_PWR_STABLE S5P_CLKREG(0x828) +#define S5P_MTC_STABLE S5P_CLKREG(0x830) +#define S5P_OTHERS S5P_CLKREG(0x900) +#define S5P_RST_STAT S5P_CLKREG(0x904) +#define S5P_WAKEUP_STAT S5P_CLKREG(0x908) +#define S5P_SLPEN S5P_CLKREG(0x930) +#define S5P_INFORM0 S5P_CLKREG(0xA00) +#define S5P_INFORM1 S5P_CLKREG(0xA04) +#define S5P_INFORM2 S5P_CLKREG(0xA08) +#define S5P_INFORM3 S5P_CLKREG(0xA0C) + +/* CLKDIV0 */ +#define S5P_CLKDIV0_PCLK_MASK (0xf << 12) +#define S5P_CLKDIV0_PCLK_SHIFT (12) +#define S5P_CLKDIV0_HCLK_MASK (0xf << 8) +#define S5P_CLKDIV0_HCLK_SHIFT (8) +#define S5P_CLKDIV0_MPLL_MASK (0x1 << 4) +#define S5P_CLKDIV0_ARM_MASK (0xf << 0) +#define S5P_CLKDIV0_ARM_SHIFT (0) + +/* CLKDIV3 */ +#define S5P_CLKDIV3_PCLK_LOW_MASK (0xf << 12) +#define S5P_CLKDIV3_PCLK_LOW_SHIFT (12) +#define S5P_CLKDIV3_HCLK_LOW_MASK (0xf << 8) +#define S5P_CLKDIV3_HCLK_LOW_SHIFT (8) + +/* HCLK0 GATE Registers */ +#define S5P_CLKCON_HCLK0_USB (1<<20) +#define S5P_CLKCON_HCLK0_HSMMC2 (1<<19) +#define S5P_CLKCON_HCLK0_HSMMC1 (1<<18) +#define S5P_CLKCON_HCLK0_HSMMC0 (1<<17) +#define S5P_CLKCON_HCLK0_POST0 (1<<5) + +/* HCLK1 GATE Registers */ +#define S5P_CLKCON_HCLK1_DISPCON (1<<1) + +/* PCLK GATE Registers */ +#define S5P_CLKCON_PCLK_IIS2 (1<<26) +#define S5P_CLKCON_PCLK_SPI1 (1<<22) +#define S5P_CLKCON_PCLK_SPI0 (1<<21) +#define S5P_CLKCON_PCLK_GPIO (1<<18) +#define S5P_CLKCON_PCLK_IIC0 (1<<17) +#define S5P_CLKCON_PCLK_TSADC (1<<12) +#define S5P_CLKCON_PCLK_PWM (1<<7) +#define S5P_CLKCON_PCLK_RTC (1<<6) +#define S5P_CLKCON_PCLK_WDT (1<<5) +#define S5P_CLKCON_PCLK_UART3 (1<<4) +#define S5P_CLKCON_PCLK_UART2 (1<<3) +#define S5P_CLKCON_PCLK_UART1 (1<<2) +#define S5P_CLKCON_PCLK_UART0 (1<<1) + +/* SCLK0 GATE Registers */ +#define S5P_CLKCON_SCLK0_MMC2_48 (1<<29) +#define S5P_CLKCON_SCLK0_MMC1_48 (1<<28) +#define S5P_CLKCON_SCLK0_MMC0_48 (1<<27) +#define S5P_CLKCON_SCLK0_MMC2 (1<<26) +#define S5P_CLKCON_SCLK0_MMC1 (1<<25) +#define S5P_CLKCON_SCLK0_MMC0 (1<<24) +#define S5P_CLKCON_SCLK0_SPI1_48 (1<<23) +#define S5P_CLKCON_SCLK0_SPI0_48 (1<<22) +#define S5P_CLKCON_SCLK0_SPI1 (1<<21) +#define S5P_CLKCON_SCLK0_SPI0 (1<<20) +#define S5P_CLKCON_SCLK0_UART (1<<5) + +/* SCLK1 GATE Registers */ + +/* MEM0 GATE Registers */ +#define S5P_CLKCON_MEM0_HCLK_NFCON (1<<2) + +/*OTHERS Resgister */ +#define S5P_OTHERS_USB_SIG_MASK (1<<16) +#define S5P_OTHERS_HCLK_LOW_SEL_MPLL (1<<6) + +/* Compatibility defines */ +#define ARM_CLK_DIV S5P_CLK_DIV0 +#define ARM_DIV_RATIO_SHIFT 0 +#define ARM_DIV_MASK (0xf << ARM_DIV_RATIO_SHIFT) + +#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h b/arch/arm/mach-s5p6440/include/mach/regs-gpio.h new file mode 100644 index 000000000000..82ff753913da --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/regs-gpio.h @@ -0,0 +1,54 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - GPIO register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_REGS_GPIO_H +#define __ASM_ARCH_REGS_GPIO_H __FILE__ + +#include <mach/map.h> + +/* Base addresses for each of the banks */ +#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) +#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) +#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) +#define S5P6440_GPF_BASE (S5P_VA_GPIO + 0x00A0) +#define S5P6440_GPG_BASE (S5P_VA_GPIO + 0x00C0) +#define S5P6440_GPH_BASE (S5P_VA_GPIO + 0x00E0) +#define S5P6440_GPI_BASE (S5P_VA_GPIO + 0x0100) +#define S5P6440_GPJ_BASE (S5P_VA_GPIO + 0x0120) +#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) +#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) +#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) +#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) +#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) +#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) +#define S5P6440_EINT0MASK (S5P_VA_GPIO + 0x920) +#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924) + +/* for LCD */ +#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0) +#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0) + +/* These set of macros are not really useful for the + * GPF/GPI/GPJ/GPN/GPP, + * useful for others set of GPIO's (4 bit) + */ +#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +/* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit) + * */ +#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) +#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2)) +#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) + +#endif /* __ASM_ARCH_REGS_GPIO_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/regs-irq.h b/arch/arm/mach-s5p6440/include/mach/regs-irq.h new file mode 100644 index 000000000000..a961f4beeb0c --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/regs-irq.h @@ -0,0 +1,19 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - IRQ register definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_REGS_IRQ_H +#define __ASM_ARCH_REGS_IRQ_H __FILE__ + +#include <asm/hardware/vic.h> +#include <mach/map.h> + +#endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p6440/include/mach/system.h new file mode 100644 index 000000000000..d2dd817da66a --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/system.h @@ -0,0 +1,26 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/system.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - system support header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H __FILE__ + +static void arch_idle(void) +{ + /* nothing here yet */ +} + +static void arch_reset(char mode, const char *cmd) +{ + /* nothing here yet */ +} + +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/tick.h b/arch/arm/mach-s5p6440/include/mach/tick.h new file mode 100644 index 000000000000..0815aeb4f2cf --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/tick.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/tick.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Timer tick support definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_TICK_H +#define __ASM_ARCH_TICK_H __FILE__ + +static inline u32 s3c24xx_ostimer_pending(void) +{ + u32 pend = __raw_readl(S5P_VA_VIC0 + VIC_RAW_STATUS); + return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); +} + +#define TICK_MAX (0xffffffff) + +#endif /* __ASM_ARCH_TICK_H */ diff --git a/arch/arm/mach-s5p6440/include/mach/uncompress.h b/arch/arm/mach-s5p6440/include/mach/uncompress.h new file mode 100644 index 000000000000..7c1f600d65c0 --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/uncompress.h @@ -0,0 +1,24 @@ +/* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - uncompress code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include <mach/map.h> +#include <plat/uncompress.h> + +static void arch_detect_cpu(void) +{ + /* we do not need to do any cpu detection here at the moment. */ +} + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c new file mode 100644 index 000000000000..760ea5424a78 --- /dev/null +++ b/arch/arm/mach-s5p6440/mach-smdk6440.c @@ -0,0 +1,111 @@ +/* linux/arch/arm/mach-s5p6440/mach-smdk6440.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/timer.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/clk.h> + +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include <mach/hardware.h> +#include <mach/map.h> + +#include <asm/irq.h> +#include <asm/mach-types.h> + +#include <plat/regs-serial.h> + +#include <plat/s5p6440.h> +#include <plat/clock.h> +#include <mach/regs-clock.h> +#include <plat/devs.h> +#include <plat/cpu.h> +#include <plat/pll.h> + +#define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5P6440_ULCON_DEFAULT S3C2410_LCON_CS8 + +#define S5P6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S3C2440_UFCON_TXTRIG16 | \ + S3C2410_UFCON_RXTRIG8) + +static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { + [0] = { + .hwport = 0, + .flags = 0, + .ucon = S5P6440_UCON_DEFAULT, + .ulcon = S5P6440_ULCON_DEFAULT, + .ufcon = S5P6440_UFCON_DEFAULT, + }, + [1] = { + .hwport = 1, + .flags = 0, + .ucon = S5P6440_UCON_DEFAULT, + .ulcon = S5P6440_ULCON_DEFAULT, + .ufcon = S5P6440_UFCON_DEFAULT, + }, + [2] = { + .hwport = 2, + .flags = 0, + .ucon = S5P6440_UCON_DEFAULT, + .ulcon = S5P6440_ULCON_DEFAULT, + .ufcon = S5P6440_UFCON_DEFAULT, + }, + [3] = { + .hwport = 3, + .flags = 0, + .ucon = S5P6440_UCON_DEFAULT, + .ulcon = S5P6440_ULCON_DEFAULT, + .ufcon = S5P6440_UFCON_DEFAULT, + }, +}; + +static struct platform_device *smdk6440_devices[] __initdata = { +}; + +static void __init smdk6440_map_io(void) +{ + s5p_init_io(NULL, 0, S5P_SYS_ID); + s3c24xx_init_clocks(12000000); + s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs)); +} + +static void __init smdk6440_machine_init(void) +{ + platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); +} + +MACHINE_START(SMDK6440, "SMDK6440") + /* Maintainer: Kukjin Kim <[email protected]> */ + .phys_io = S5P_PA_UART & 0xfff00000, + .io_pg_offst = (((u32)S5P_VA_UART) >> 18) & 0xfffc, + .boot_params = S5P_PA_SDRAM + 0x100, + + .init_irq = s5p6440_init_irq, + .map_io = smdk6440_map_io, + .init_machine = smdk6440_machine_init, + .timer = &s3c24xx_timer, +MACHINE_END diff --git a/arch/arm/mach-s5p6440/s5p6440-gpio.c b/arch/arm/mach-s5p6440/s5p6440-gpio.c new file mode 100644 index 000000000000..742264c29f2a --- /dev/null +++ b/arch/arm/mach-s5p6440/s5p6440-gpio.c @@ -0,0 +1,322 @@ +/* arch/arm/mach-s5p6440/s5p6440-gpio.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <mach/map.h> +#include <mach/gpio.h> +#include <mach/regs-gpio.h> +#include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> + +/* GPIO bank summary: +* +* Bank GPIOs Style SlpCon ExtInt Group +* A 6 4Bit Yes 1 +* B 7 4Bit Yes 1 +* C 8 4Bit Yes 2 +* F 2 2Bit Yes 4 [1] +* G 7 4Bit Yes 5 +* H 10 4Bit[2] Yes 6 +* I 16 2Bit Yes None +* J 12 2Bit Yes None +* N 16 2Bit No IRQ_EINT +* P 8 2Bit Yes 8 +* R 15 4Bit[2] Yes 8 +* +* [1] BANKF pins 14,15 do not form part of the external interrupt sources +* [2] BANK has two control registers, GPxCON0 and GPxCON1 +*/ + +static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + + switch (offset) { + case 6: + offset += 1; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + regcon -= 4; + break; + default: + offset -= 7; + break; + } + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, regcon); + + return 0; +} + +static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + unsigned long dat; + unsigned con_offset = offset; + + switch (con_offset) { + case 6: + con_offset += 1; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + regcon -= 4; + break; + default: + con_offset -= 7; + break; + } + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(con_offset)); + con |= 0x1 << con_4bit_shift(con_offset); + + dat = __raw_readl(base + GPIODAT_OFF); + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(con, regcon); + __raw_writel(dat, base + GPIODAT_OFF); + + return 0; +} + +int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, + unsigned int off, unsigned int cfg) +{ + void __iomem *reg = chip->base; + unsigned int shift; + u32 con; + + switch (off) { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + shift = (off & 7) * 4; + reg -= 4; + break; + case 6: + shift = ((off + 1) & 7) * 4; + reg -= 4; + default: + shift = ((off + 1) & 7) * 4; + break; + } + + if (s3c_gpio_is_cfg_special(cfg)) { + cfg &= 0xf; + cfg <<= shift; + } + + con = __raw_readl(reg); + con &= ~(0xf << shift); + con |= cfg; + __raw_writel(con, reg); + + return 0; +} + +static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = { + { + .cfg_eint = 0, + }, { + .cfg_eint = 7, + }, { + .cfg_eint = 3, + .set_config = s5p6440_gpio_setcfg_4bit_rbank, + }, { + .cfg_eint = 0, + .set_config = s3c_gpio_setcfg_s3c24xx, + }, { + .cfg_eint = 2, + .set_config = s3c_gpio_setcfg_s3c24xx, + }, { + .cfg_eint = 3, + .set_config = s3c_gpio_setcfg_s3c24xx, + }, +}; + +static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { + { + .base = S5P6440_GPA_BASE, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPA(0), + .ngpio = S5P6440_GPIO_A_NR, + .label = "GPA", + }, + }, { + .base = S5P6440_GPB_BASE, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPB(0), + .ngpio = S5P6440_GPIO_B_NR, + .label = "GPB", + }, + }, { + .base = S5P6440_GPC_BASE, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPC(0), + .ngpio = S5P6440_GPIO_C_NR, + .label = "GPC", + }, + }, { + .base = S5P6440_GPG_BASE, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPG(0), + .ngpio = S5P6440_GPIO_G_NR, + .label = "GPG", + }, + }, +}; + +static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { + { + .base = S5P6440_GPH_BASE + 0x4, + .config = &s5p6440_gpio_cfgs[1], + .chip = { + .base = S5P6440_GPH(0), + .ngpio = S5P6440_GPIO_H_NR, + .label = "GPH", + }, + }, +}; + +static struct s3c_gpio_chip gpio_rbank_4bit2[] = { + { + .base = S5P6440_GPR_BASE + 0x4, + .config = &s5p6440_gpio_cfgs[2], + .chip = { + .base = S5P6440_GPR(0), + .ngpio = S5P6440_GPIO_R_NR, + .label = "GPR", + }, + }, +}; + +static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { + { + .base = S5P6440_GPF_BASE, + .config = &s5p6440_gpio_cfgs[5], + .chip = { + .base = S5P6440_GPF(0), + .ngpio = S5P6440_GPIO_F_NR, + .label = "GPF", + }, + }, { + .base = S5P6440_GPI_BASE, + .config = &s5p6440_gpio_cfgs[3], + .chip = { + .base = S5P6440_GPI(0), + .ngpio = S5P6440_GPIO_I_NR, + .label = "GPI", + }, + }, { + .base = S5P6440_GPJ_BASE, + .config = &s5p6440_gpio_cfgs[3], + .chip = { + .base = S5P6440_GPJ(0), + .ngpio = S5P6440_GPIO_J_NR, + .label = "GPJ", + }, + }, { + .base = S5P6440_GPN_BASE, + .config = &s5p6440_gpio_cfgs[4], + .chip = { + .base = S5P6440_GPN(0), + .ngpio = S5P6440_GPIO_N_NR, + .label = "GPN", + }, + }, { + .base = S5P6440_GPP_BASE, + .config = &s5p6440_gpio_cfgs[5], + .chip = { + .base = S5P6440_GPP(0), + .ngpio = S5P6440_GPIO_P_NR, + .label = "GPP", + }, + }, +}; + +void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chipcfg++) { + if (!chipcfg->set_config) + chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit; + if (!chipcfg->set_pull) + chipcfg->set_pull = s3c_gpio_setpull_updown; + if (!chipcfg->get_pull) + chipcfg->get_pull = s3c_gpio_getpull_updown; + } +} + +static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) { + chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input; + chip->chip.direction_output = + s5p6440_gpiolib_rbank_4bit2_output; + s3c_gpiolib_add(chip); + } +} + +static int __init s5p6440_gpiolib_init(void) +{ + struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; + int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); + + s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs, + ARRAY_SIZE(s5p6440_gpio_cfgs)); + + for (; nr_chips > 0; nr_chips--, chips++) + s3c_gpiolib_add(chips); + + samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, + ARRAY_SIZE(s5p6440_gpio_4bit)); + + samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, + ARRAY_SIZE(s5p6440_gpio_4bit2)); + + s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2, + ARRAY_SIZE(gpio_rbank_4bit2)); + + return 0; +} +arch_initcall(s5p6440_gpiolib_init); diff --git a/arch/arm/mach-s5pc100/include/mach/gpio-core.h b/arch/arm/mach-s5pc100/include/mach/gpio-core.h deleted file mode 100644 index ad28d8ec8a78..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/gpio-core.h +++ /dev/null @@ -1,21 +0,0 @@ -/* arch/arm/mach-s5pc100/include/mach/gpio-core.h - * - * Copyright 2009 Samsung Electronics Co. - * Byungho Min <[email protected]> - * - * S5PC100 - GPIO core support - * - * Based on mach-s3c6400/include/mach/gpio-core.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_GPIO_CORE_H -#define __ASM_ARCH_GPIO_CORE_H __FILE__ - -/* currently we just include the platform support */ -#include <plat/gpio-core.h> - -#endif /* __ASM_ARCH_GPIO_CORE_H */ diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h index d3de0f3591ae..f338c9eec717 100644 --- a/arch/arm/mach-s5pc100/include/mach/tick.h +++ b/arch/arm/mach-s5pc100/include/mach/tick.h @@ -21,7 +21,7 @@ static inline u32 s3c24xx_ostimer_pending(void) { u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); - return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0)); + return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0)); } #define TICK_MAX (0xffffffff) diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c index 051ec0f0023c..259cb2c15fff 100644 --- a/arch/arm/mach-sa1100/badge4.c +++ b/arch/arm/mach-sa1100/badge4.c @@ -51,6 +51,10 @@ static struct resource sa1111_resources[] = { }, }; +static struct sa1111_platform_data sa1111_info = { + .irq_base = IRQ_BOARD_END, +}; + static u64 sa1111_dmamask = 0xffffffffUL; static struct platform_device sa1111_device = { @@ -59,6 +63,7 @@ static struct platform_device sa1111_device = { .dev = { .dma_mask = &sa1111_dmamask, .coherent_dma_mask = 0xffffffff, + .platform_data = &sa1111_info, }, .num_resources = ARRAY_SIZE(sa1111_resources), .resource = sa1111_resources, diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 9982c5c28edf..5d5f330c5d94 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -234,6 +234,10 @@ static struct resource locomo_resources[] = { }, }; +static struct locomo_platform_data locomo_info = { + .irq_base = IRQ_BOARD_START, +}; + struct platform_device collie_locomo_device = { .name = "locomo", .id = 0, diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h index 71a0b3fdcc8c..52acda7061b7 100644 --- a/arch/arm/mach-sa1100/include/mach/collie.h +++ b/arch/arm/mach-sa1100/include/mach/collie.h @@ -72,13 +72,6 @@ #define COLLIE_IRQ_GPIO_GA_INT IRQ_GPIO25 #define COLLIE_IRQ_GPIO_MAIN_BAT_LOW IRQ_GPIO26 -#define COLLIE_LCM_IRQ_GPIO_RTS IRQ_LOCOMO_GPIO0 -#define COLLIE_LCM_IRQ_GPIO_CTS IRQ_LOCOMO_GPIO1 -#define COLLIE_LCM_IRQ_GPIO_DSR IRQ_LOCOMO_GPIO2 -#define COLLIE_LCM_IRQ_GPIO_DTR IRQ_LOCOMO_GPIO3 -#define COLLIE_LCM_IRQ_GPIO_nSD_DETECT IRQ_LOCOMO_GPIO13 -#define COLLIE_LCM_IRQ_GPIO_nSD_WP IRQ_LOCOMO_GPIO14 - /* GPIO's on the TC35143AF (Toshiba Analog Frontend) */ #define COLLIE_TC35143_GPIO_BASE (GPIO_MAX + 13) #define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h index ae81f80b0cf9..8c8845b5ae5b 100644 --- a/arch/arm/mach-sa1100/include/mach/irqs.h +++ b/arch/arm/mach-sa1100/include/mach/irqs.h @@ -68,93 +68,17 @@ #define IRQ_BOARD_START 49 #define IRQ_BOARD_END 65 -#define IRQ_SA1111_START (IRQ_BOARD_END) -#define IRQ_GPAIN0 (IRQ_BOARD_END + 0) -#define IRQ_GPAIN1 (IRQ_BOARD_END + 1) -#define IRQ_GPAIN2 (IRQ_BOARD_END + 2) -#define IRQ_GPAIN3 (IRQ_BOARD_END + 3) -#define IRQ_GPBIN0 (IRQ_BOARD_END + 4) -#define IRQ_GPBIN1 (IRQ_BOARD_END + 5) -#define IRQ_GPBIN2 (IRQ_BOARD_END + 6) -#define IRQ_GPBIN3 (IRQ_BOARD_END + 7) -#define IRQ_GPBIN4 (IRQ_BOARD_END + 8) -#define IRQ_GPBIN5 (IRQ_BOARD_END + 9) -#define IRQ_GPCIN0 (IRQ_BOARD_END + 10) -#define IRQ_GPCIN1 (IRQ_BOARD_END + 11) -#define IRQ_GPCIN2 (IRQ_BOARD_END + 12) -#define IRQ_GPCIN3 (IRQ_BOARD_END + 13) -#define IRQ_GPCIN4 (IRQ_BOARD_END + 14) -#define IRQ_GPCIN5 (IRQ_BOARD_END + 15) -#define IRQ_GPCIN6 (IRQ_BOARD_END + 16) -#define IRQ_GPCIN7 (IRQ_BOARD_END + 17) -#define IRQ_MSTXINT (IRQ_BOARD_END + 18) -#define IRQ_MSRXINT (IRQ_BOARD_END + 19) -#define IRQ_MSSTOPERRINT (IRQ_BOARD_END + 20) -#define IRQ_TPTXINT (IRQ_BOARD_END + 21) -#define IRQ_TPRXINT (IRQ_BOARD_END + 22) -#define IRQ_TPSTOPERRINT (IRQ_BOARD_END + 23) -#define SSPXMTINT (IRQ_BOARD_END + 24) -#define SSPRCVINT (IRQ_BOARD_END + 25) -#define SSPROR (IRQ_BOARD_END + 26) -#define AUDXMTDMADONEA (IRQ_BOARD_END + 32) -#define AUDRCVDMADONEA (IRQ_BOARD_END + 33) -#define AUDXMTDMADONEB (IRQ_BOARD_END + 34) -#define AUDRCVDMADONEB (IRQ_BOARD_END + 35) -#define AUDTFSR (IRQ_BOARD_END + 36) -#define AUDRFSR (IRQ_BOARD_END + 37) -#define AUDTUR (IRQ_BOARD_END + 38) -#define AUDROR (IRQ_BOARD_END + 39) -#define AUDDTS (IRQ_BOARD_END + 40) -#define AUDRDD (IRQ_BOARD_END + 41) -#define AUDSTO (IRQ_BOARD_END + 42) -#define IRQ_USBPWR (IRQ_BOARD_END + 43) -#define IRQ_HCIM (IRQ_BOARD_END + 44) -#define IRQ_HCIBUFFACC (IRQ_BOARD_END + 45) -#define IRQ_HCIRMTWKP (IRQ_BOARD_END + 46) -#define IRQ_NHCIMFCIR (IRQ_BOARD_END + 47) -#define IRQ_USB_PORT_RESUME (IRQ_BOARD_END + 48) -#define IRQ_S0_READY_NINT (IRQ_BOARD_END + 49) -#define IRQ_S1_READY_NINT (IRQ_BOARD_END + 50) -#define IRQ_S0_CD_VALID (IRQ_BOARD_END + 51) -#define IRQ_S1_CD_VALID (IRQ_BOARD_END + 52) -#define IRQ_S0_BVD1_STSCHG (IRQ_BOARD_END + 53) -#define IRQ_S1_BVD1_STSCHG (IRQ_BOARD_END + 54) - -#define IRQ_LOCOMO_START (IRQ_BOARD_END) -#define IRQ_LOCOMO_KEY (IRQ_BOARD_END + 0) -#define IRQ_LOCOMO_GPIO0 (IRQ_BOARD_END + 1) -#define IRQ_LOCOMO_GPIO1 (IRQ_BOARD_END + 2) -#define IRQ_LOCOMO_GPIO2 (IRQ_BOARD_END + 3) -#define IRQ_LOCOMO_GPIO3 (IRQ_BOARD_END + 4) -#define IRQ_LOCOMO_GPIO4 (IRQ_BOARD_END + 5) -#define IRQ_LOCOMO_GPIO5 (IRQ_BOARD_END + 6) -#define IRQ_LOCOMO_GPIO6 (IRQ_BOARD_END + 7) -#define IRQ_LOCOMO_GPIO7 (IRQ_BOARD_END + 8) -#define IRQ_LOCOMO_GPIO8 (IRQ_BOARD_END + 9) -#define IRQ_LOCOMO_GPIO9 (IRQ_BOARD_END + 10) -#define IRQ_LOCOMO_GPIO10 (IRQ_BOARD_END + 11) -#define IRQ_LOCOMO_GPIO11 (IRQ_BOARD_END + 12) -#define IRQ_LOCOMO_GPIO12 (IRQ_BOARD_END + 13) -#define IRQ_LOCOMO_GPIO13 (IRQ_BOARD_END + 14) -#define IRQ_LOCOMO_GPIO14 (IRQ_BOARD_END + 15) -#define IRQ_LOCOMO_GPIO15 (IRQ_BOARD_END + 16) -#define IRQ_LOCOMO_LT (IRQ_BOARD_END + 17) -#define IRQ_LOCOMO_SPI_RFR (IRQ_BOARD_END + 18) -#define IRQ_LOCOMO_SPI_RFW (IRQ_BOARD_END + 19) -#define IRQ_LOCOMO_SPI_REND (IRQ_BOARD_END + 20) -#define IRQ_LOCOMO_SPI_TEND (IRQ_BOARD_END + 21) - /* * Figure out the MAX IRQ number. * * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1. - * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1 + * If we have an LoCoMo, the max IRQ is IRQ_BOARD_START + 4 * Otherwise, we have the standard IRQs only. */ #ifdef CONFIG_SA1111 -#define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) -#elif defined(CONFIG_SHARP_LOCOMO) -#define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) +#define NR_IRQS (IRQ_BOARD_END + 55) +#elif defined(CONFIG_SHARPSL_LOCOMO) +#define NR_IRQS (IRQ_BOARD_START + 4) #else #define NR_IRQS (IRQ_BOARD_START) #endif @@ -166,10 +90,3 @@ #define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0) #define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1) #define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2) - -/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */ -#define IRQ_LOCOMO_KEY_BASE (IRQ_BOARD_START + 0) -#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) -#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) -#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) - diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c index 13ebd2d99bfd..d3ec620618f1 100644 --- a/arch/arm/mach-sa1100/jornada720.c +++ b/arch/arm/mach-sa1100/jornada720.c @@ -208,6 +208,10 @@ static struct resource sa1111_resources[] = { }, }; +static struct sa1111_platform_data sa1111_info = { + .irq_base = IRQ_BOARD_END, +}; + static u64 sa1111_dmamask = 0xffffffffUL; static struct platform_device sa1111_device = { @@ -216,6 +220,7 @@ static struct platform_device sa1111_device = { .dev = { .dma_mask = &sa1111_dmamask, .coherent_dma_mask = 0xffffffff, + .platform_data = &sa1111_info, }, .num_resources = ARRAY_SIZE(sa1111_resources), .resource = sa1111_resources, diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 6ccd175bc4cf..0b505d9f22d6 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -241,6 +241,10 @@ static struct resource sa1111_resources[] = { }, }; +static struct sa1111_platform_data sa1111_info = { + .irq_base = IRQ_BOARD_END, +}; + static u64 sa1111_dmamask = 0xffffffffUL; static struct platform_device sa1111_device = { @@ -249,6 +253,7 @@ static struct platform_device sa1111_device = { .dev = { .dma_mask = &sa1111_dmamask, .coherent_dma_mask = 0xffffffff, + .platform_data = &sa1111_info, }, .num_resources = ARRAY_SIZE(sa1111_resources), .resource = sa1111_resources, diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c index b9cbb56d6e9d..74b6e0e570b6 100644 --- a/arch/arm/mach-sa1100/time.c +++ b/arch/arm/mach-sa1100/time.c @@ -35,14 +35,12 @@ static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id) static int sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) { - unsigned long flags, next, oscr; + unsigned long next, oscr; - raw_local_irq_save(flags); OIER |= OIER_E0; next = OSCR + delta; OSMR0 = next; oscr = OSCR; - raw_local_irq_restore(flags); return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; } @@ -50,16 +48,12 @@ sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c) static void sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c) { - unsigned long flags; - switch (mode) { case CLOCK_EVT_MODE_ONESHOT: case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: - raw_local_irq_save(flags); OIER &= ~OIER_E0; OSSR = OSSR_M0; - raw_local_irq_restore(flags); break; case CLOCK_EVT_MODE_RESUME: diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 8b0a1ee039fa..7f7ad6f289bd 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig @@ -9,38 +9,43 @@ choice config ARCH_MX1 bool "MX1-based" select CPU_ARM920T - select COMMON_CLKDEV + select IMX_HAVE_IOMUX_V1 help This enables support for systems based on the Freescale i.MX1 family config ARCH_MX2 bool "MX2-based" select CPU_ARM926T - select COMMON_CLKDEV + select IMX_HAVE_IOMUX_V1 help This enables support for systems based on the Freescale i.MX2 family config ARCH_MX25 bool "MX25-based" select CPU_ARM926T - select COMMON_CLKDEV + select ARCH_MXC_IOMUX_V3 + select HAVE_FB_IMX help This enables support for systems based on the Freescale i.MX25 family config ARCH_MX3 bool "MX3-based" select CPU_V6 - select COMMON_CLKDEV help This enables support for systems based on the Freescale i.MX3 family config ARCH_MXC91231 bool "MXC91231-based" select CPU_V6 - select COMMON_CLKDEV help This enables support for systems based on the Freescale MXC91231 family +config ARCH_MX5 + bool "MX5-based" + select CPU_V7 + help + This enables support for systems based on the Freescale i.MX51 family + endchoice source "arch/arm/mach-mx1/Kconfig" @@ -48,12 +53,12 @@ source "arch/arm/mach-mx2/Kconfig" source "arch/arm/mach-mx3/Kconfig" source "arch/arm/mach-mx25/Kconfig" source "arch/arm/mach-mxc91231/Kconfig" +source "arch/arm/mach-mx5/Kconfig" endmenu config MXC_IRQ_PRIOR bool "Use IRQ priority" - depends on ARCH_MXC help Select this if you want to use prioritized IRQ handling. This feature prevents higher priority ISR to be interrupted @@ -62,9 +67,16 @@ config MXC_IRQ_PRIOR requirements for timing. Say N here, unless you have a specialized requirement. +config MXC_TZIC + bool "Enable TrustZone Interrupt Controller" + depends on ARCH_MX51 + help + This will be automatically selected for all processors + containing this interrupt controller. + Say N here only if you are really sure. + config MXC_PWM tristate "Enable PWM driver" - depends on ARCH_MXC select HAVE_PWM help Enable support for the i.MX PWM controller(s). @@ -74,7 +86,9 @@ config MXC_ULPI config ARCH_HAS_RNGA bool - depends on ARCH_MXC + +config IMX_HAVE_IOMUX_V1 + bool config ARCH_MXC_IOMUX_V3 bool diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index 996cbac6932c..a72a5e4ca20e 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile @@ -5,8 +5,12 @@ # Common support obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o -obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o -obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o +# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) +obj-$(CONFIG_MXC_TZIC) += tzic.o + +obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o +obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o +obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o obj-$(CONFIG_MXC_PWM) += pwm.o obj-$(CONFIG_USB_EHCI_MXC) += ehci.o diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c index da6387dcdf21..b62917ca3f95 100644 --- a/arch/arm/plat-mxc/audmux-v1.c +++ b/arch/arm/plat-mxc/audmux-v1.c @@ -50,8 +50,18 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port); static int mxc_audmux_v1_init(void) { - if (cpu_is_mx27() || cpu_is_mx21()) - audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) + audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR); + else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR); + else +#endif + (void)0; + return 0; } diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index b06954a84436..d983cd6c788c 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -190,7 +190,10 @@ static int mxc_audmux_v2_init(void) { int ret; - if (cpu_is_mx35()) { + if (cpu_is_mx31()) + audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); + + else if (cpu_is_mx35()) { audmux_clk = clk_get(NULL, "audmux"); if (IS_ERR(audmux_clk)) { ret = PTR_ERR(audmux_clk); @@ -198,11 +201,9 @@ static int mxc_audmux_v2_init(void) ret); return ret; } + audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); } - if (cpu_is_mx31() || cpu_is_mx35()) - audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); - audmux_debugfs_init(); return 0; diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 9e8fbd57495c..323ff8ccc877 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -56,6 +56,7 @@ static void __clk_disable(struct clk *clk) __clk_disable(clk->parent); __clk_disable(clk->secondary); + WARN_ON(!clk->usecount); if (!(--clk->usecount) && clk->disable) clk->disable(clk); } diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c index 9c1b3f9c4f4d..e16014b0d13c 100644 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ b/arch/arm/plat-mxc/dma-mx1-mx2.c @@ -128,6 +128,18 @@ struct imx_dma_channel { int hw_chaining; }; +static void __iomem *imx_dmav1_baseaddr; + +static void imx_dmav1_writel(unsigned val, unsigned offset) +{ + __raw_writel(val, imx_dmav1_baseaddr + offset); +} + +static unsigned imx_dmav1_readl(unsigned offset) +{ + return __raw_readl(imx_dmav1_baseaddr + offset); +} + static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; static struct clk *dma_clk; @@ -140,7 +152,6 @@ static int imx_dma_hw_chain(struct imx_dma_channel *imxdma) return 0; } - /* * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation */ @@ -160,17 +171,17 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg) imxdma->resbytes -= now; if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) - __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel)); + imx_dmav1_writel(sg->dma_address, DMA_DAR(channel)); else - __raw_writel(sg->dma_address, DMA_BASE + DMA_SAR(channel)); + imx_dmav1_writel(sg->dma_address, DMA_SAR(channel)); - __raw_writel(now, DMA_BASE + DMA_CNTR(channel)); + imx_dmav1_writel(now, DMA_CNTR(channel)); pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, " "size 0x%08x\n", channel, - __raw_readl(DMA_BASE + DMA_DAR(channel)), - __raw_readl(DMA_BASE + DMA_SAR(channel)), - __raw_readl(DMA_BASE + DMA_CNTR(channel))); + imx_dmav1_readl(DMA_DAR(channel)), + imx_dmav1_readl(DMA_SAR(channel)), + imx_dmav1_readl(DMA_CNTR(channel))); return now; } @@ -218,27 +229,26 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address, channel, __func__, (unsigned int)dma_address, dma_length, dev_addr); - __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); - __raw_writel(dma_address, DMA_BASE + DMA_DAR(channel)); - __raw_writel(imxdma->ccr_from_device, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(dev_addr, DMA_SAR(channel)); + imx_dmav1_writel(dma_address, DMA_DAR(channel)); + imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel)); } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d " "dev_addr=0x%08x for write\n", channel, __func__, (unsigned int)dma_address, dma_length, dev_addr); - __raw_writel(dma_address, DMA_BASE + DMA_SAR(channel)); - __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); - __raw_writel(imxdma->ccr_to_device, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(dma_address, DMA_SAR(channel)); + imx_dmav1_writel(dev_addr, DMA_DAR(channel)); + imx_dmav1_writel(imxdma->ccr_to_device, + DMA_CCR(channel)); } else { printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", channel); return -EINVAL; } - __raw_writel(dma_length, DMA_BASE + DMA_CNTR(channel)); + imx_dmav1_writel(dma_length, DMA_CNTR(channel)); return 0; } @@ -316,17 +326,15 @@ imx_dma_setup_sg(int channel, "dev_addr=0x%08x for read\n", channel, __func__, sg, sgcount, dma_length, dev_addr); - __raw_writel(dev_addr, DMA_BASE + DMA_SAR(channel)); - __raw_writel(imxdma->ccr_from_device, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(dev_addr, DMA_SAR(channel)); + imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel)); } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d " "dev_addr=0x%08x for write\n", channel, __func__, sg, sgcount, dma_length, dev_addr); - __raw_writel(dev_addr, DMA_BASE + DMA_DAR(channel)); - __raw_writel(imxdma->ccr_to_device, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(dev_addr, DMA_DAR(channel)); + imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel)); } else { printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", channel); @@ -360,7 +368,7 @@ imx_dma_config_channel(int channel, unsigned int config_port, imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq; imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq; - __raw_writel(dmareq, DMA_BASE + DMA_RSSR(channel)); + imx_dmav1_writel(dmareq, DMA_RSSR(channel)); return 0; } @@ -368,7 +376,7 @@ EXPORT_SYMBOL(imx_dma_config_channel); void imx_dma_config_burstlen(int channel, unsigned int burstlen) { - __raw_writel(burstlen, DMA_BASE + DMA_BLR(channel)); + imx_dmav1_writel(burstlen, DMA_BLR(channel)); } EXPORT_SYMBOL(imx_dma_config_burstlen); @@ -398,7 +406,7 @@ imx_dma_setup_handlers(int channel, } local_irq_save(flags); - __raw_writel(1 << channel, DMA_BASE + DMA_DISR); + imx_dmav1_writel(1 << channel, DMA_DISR); imxdma->irq_handler = irq_handler; imxdma->err_handler = err_handler; imxdma->data = data; @@ -462,22 +470,21 @@ void imx_dma_enable(int channel) local_irq_save(flags); - __raw_writel(1 << channel, DMA_BASE + DMA_DISR); - __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) & ~(1 << channel), - DMA_BASE + DMA_DIMR); - __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) | CCR_CEN | - CCR_ACRPT, - DMA_BASE + DMA_CCR(channel)); + imx_dmav1_writel(1 << channel, DMA_DISR); + imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR); + imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN | + CCR_ACRPT, DMA_CCR(channel)); #ifdef CONFIG_ARCH_MX2 - if (imxdma->sg && imx_dma_hw_chain(imxdma)) { + if ((cpu_is_mx21() || cpu_is_mx27()) && + imxdma->sg && imx_dma_hw_chain(imxdma)) { imxdma->sg = sg_next(imxdma->sg); if (imxdma->sg) { u32 tmp; imx_dma_sg_next(channel, imxdma->sg); - tmp = __raw_readl(DMA_BASE + DMA_CCR(channel)); - __raw_writel(tmp | CCR_RPT | CCR_ACRPT, - DMA_BASE + DMA_CCR(channel)); + tmp = imx_dmav1_readl(DMA_CCR(channel)); + imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT, + DMA_CCR(channel)); } } #endif @@ -502,11 +509,10 @@ void imx_dma_disable(int channel) del_timer(&imxdma->watchdog); local_irq_save(flags); - __raw_writel(__raw_readl(DMA_BASE + DMA_DIMR) | (1 << channel), - DMA_BASE + DMA_DIMR); - __raw_writel(__raw_readl(DMA_BASE + DMA_CCR(channel)) & ~CCR_CEN, - DMA_BASE + DMA_CCR(channel)); - __raw_writel(1 << channel, DMA_BASE + DMA_DISR); + imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR); + imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN, + DMA_CCR(channel)); + imx_dmav1_writel(1 << channel, DMA_DISR); imxdma->in_use = 0; local_irq_restore(flags); } @@ -517,7 +523,7 @@ static void imx_dma_watchdog(unsigned long chno) { struct imx_dma_channel *imxdma = &imx_dma_channels[chno]; - __raw_writel(0, DMA_BASE + DMA_CCR(chno)); + imx_dmav1_writel(0, DMA_CCR(chno)); imxdma->in_use = 0; imxdma->sg = NULL; @@ -533,17 +539,17 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id) unsigned int err_mask; int errcode; - disr = __raw_readl(DMA_BASE + DMA_DISR); + disr = imx_dmav1_readl(DMA_DISR); - err_mask = __raw_readl(DMA_BASE + DMA_DBTOSR) | - __raw_readl(DMA_BASE + DMA_DRTOSR) | - __raw_readl(DMA_BASE + DMA_DSESR) | - __raw_readl(DMA_BASE + DMA_DBOSR); + err_mask = imx_dmav1_readl(DMA_DBTOSR) | + imx_dmav1_readl(DMA_DRTOSR) | + imx_dmav1_readl(DMA_DSESR) | + imx_dmav1_readl(DMA_DBOSR); if (!err_mask) return IRQ_HANDLED; - __raw_writel(disr & err_mask, DMA_BASE + DMA_DISR); + imx_dmav1_writel(disr & err_mask, DMA_DISR); for (i = 0; i < IMX_DMA_CHANNELS; i++) { if (!(err_mask & (1 << i))) @@ -551,20 +557,20 @@ static irqreturn_t dma_err_handler(int irq, void *dev_id) imxdma = &imx_dma_channels[i]; errcode = 0; - if (__raw_readl(DMA_BASE + DMA_DBTOSR) & (1 << i)) { - __raw_writel(1 << i, DMA_BASE + DMA_DBTOSR); + if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) { + imx_dmav1_writel(1 << i, DMA_DBTOSR); errcode |= IMX_DMA_ERR_BURST; } - if (__raw_readl(DMA_BASE + DMA_DRTOSR) & (1 << i)) { - __raw_writel(1 << i, DMA_BASE + DMA_DRTOSR); + if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) { + imx_dmav1_writel(1 << i, DMA_DRTOSR); errcode |= IMX_DMA_ERR_REQUEST; } - if (__raw_readl(DMA_BASE + DMA_DSESR) & (1 << i)) { - __raw_writel(1 << i, DMA_BASE + DMA_DSESR); + if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) { + imx_dmav1_writel(1 << i, DMA_DSESR); errcode |= IMX_DMA_ERR_TRANSFER; } - if (__raw_readl(DMA_BASE + DMA_DBOSR) & (1 << i)) { - __raw_writel(1 << i, DMA_BASE + DMA_DBOSR); + if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) { + imx_dmav1_writel(1 << i, DMA_DBOSR); errcode |= IMX_DMA_ERR_BUFFER; } if (imxdma->name && imxdma->err_handler) { @@ -607,7 +613,7 @@ static void dma_irq_handle_channel(int chno) if (imxdma->sg) { imx_dma_sg_next(chno, imxdma->sg); - tmp = __raw_readl(DMA_BASE + DMA_CCR(chno)); + tmp = imx_dmav1_readl(DMA_CCR(chno)); if (imx_dma_hw_chain(imxdma)) { /* FIXME: The timeout should probably be @@ -617,15 +623,13 @@ static void dma_irq_handle_channel(int chno) jiffies + msecs_to_jiffies(500)); tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT; - __raw_writel(tmp, DMA_BASE + - DMA_CCR(chno)); + imx_dmav1_writel(tmp, DMA_CCR(chno)); } else { - __raw_writel(tmp & ~CCR_CEN, DMA_BASE + - DMA_CCR(chno)); + imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno)); tmp |= CCR_CEN; } - __raw_writel(tmp, DMA_BASE + DMA_CCR(chno)); + imx_dmav1_writel(tmp, DMA_CCR(chno)); if (imxdma->prog_handler) imxdma->prog_handler(chno, imxdma->data, @@ -640,7 +644,7 @@ static void dma_irq_handle_channel(int chno) } } - __raw_writel(0, DMA_BASE + DMA_CCR(chno)); + imx_dmav1_writel(0, DMA_CCR(chno)); imxdma->in_use = 0; if (imxdma->irq_handler) imxdma->irq_handler(chno, imxdma->data); @@ -651,15 +655,16 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) int i, disr; #ifdef CONFIG_ARCH_MX2 - dma_err_handler(irq, dev_id); + if (cpu_is_mx21() || cpu_is_mx27()) + dma_err_handler(irq, dev_id); #endif - disr = __raw_readl(DMA_BASE + DMA_DISR); + disr = imx_dmav1_readl(DMA_DISR); pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", disr); - __raw_writel(disr, DMA_BASE + DMA_DISR); + imx_dmav1_writel(disr, DMA_DISR); for (i = 0; i < IMX_DMA_CHANNELS; i++) { if (disr & (1 << i)) dma_irq_handle_channel(i); @@ -699,17 +704,19 @@ int imx_dma_request(int channel, const char *name) local_irq_restore(flags); /* request_irq() can block */ #ifdef CONFIG_ARCH_MX2 - ret = request_irq(MXC_INT_DMACH0 + channel, dma_irq_handler, 0, "DMA", - NULL); - if (ret) { - imxdma->name = NULL; - printk(KERN_CRIT "Can't register IRQ %d for DMA channel %d\n", - MXC_INT_DMACH0 + channel, channel); - return ret; + if (cpu_is_mx21() || cpu_is_mx27()) { + ret = request_irq(MX2x_INT_DMACH0 + channel, + dma_irq_handler, 0, "DMA", NULL); + if (ret) { + imxdma->name = NULL; + pr_crit("Can't register IRQ %d for DMA channel %d\n", + MX2x_INT_DMACH0 + channel, channel); + return ret; + } + init_timer(&imxdma->watchdog); + imxdma->watchdog.function = &imx_dma_watchdog; + imxdma->watchdog.data = channel; } - init_timer(&imxdma->watchdog); - imxdma->watchdog.function = &imx_dma_watchdog; - imxdma->watchdog.data = channel; #endif return ret; @@ -738,7 +745,8 @@ void imx_dma_free(int channel) imxdma->name = NULL; #ifdef CONFIG_ARCH_MX2 - free_irq(MXC_INT_DMACH0 + channel, NULL); + if (cpu_is_mx21() || cpu_is_mx27()) + free_irq(MX2x_INT_DMACH0 + channel, NULL); #endif local_irq_restore(flags); @@ -796,34 +804,53 @@ static int __init imx_dma_init(void) int ret = 0; int i; +#ifdef CONFIG_ARCH_MX1 + if (cpu_is_mx1()) + imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR); + else +#endif +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) + imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR); + else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) + imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); + else +#endif + BUG(); + dma_clk = clk_get(NULL, "dma"); clk_enable(dma_clk); /* reset DMA module */ - __raw_writel(DCR_DRST, DMA_BASE + DMA_DCR); + imx_dmav1_writel(DCR_DRST, DMA_DCR); #ifdef CONFIG_ARCH_MX1 - ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL); - if (ret) { - printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n"); - return ret; - } + if (cpu_is_mx1()) { + ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL); + if (ret) { + pr_crit("Wow! Can't register IRQ for DMA\n"); + return ret; + } - ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL); - if (ret) { - printk(KERN_CRIT "Wow! Can't register ERRIRQ for DMA\n"); - free_irq(DMA_INT, NULL); - return ret; + ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL); + if (ret) { + pr_crit("Wow! Can't register ERRIRQ for DMA\n"); + free_irq(MX1_DMA_INT, NULL); + return ret; + } } #endif /* enable DMA module */ - __raw_writel(DCR_DEN, DMA_BASE + DMA_DCR); + imx_dmav1_writel(DCR_DEN, DMA_DCR); /* clear all interrupts */ - __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DISR); + imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR); /* disable interrupts */ - __raw_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_BASE + DMA_DIMR); + imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR); for (i = 0; i < IMX_DMA_CHANNELS; i++) { imx_dma_channels[i].sg = NULL; diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index 41599be882e8..cb0b63874482 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c @@ -25,25 +25,37 @@ #define USBCTRL_OTGBASE_OFFSET 0x600 #define MX31_OTG_SIC_SHIFT 29 -#define MX31_OTG_SIC_MASK (0xf << MX31_OTG_SIC_SHIFT) +#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) #define MX31_OTG_PM_BIT (1 << 24) #define MX31_H2_SIC_SHIFT 21 -#define MX31_H2_SIC_MASK (0xf << MX31_H2_SIC_SHIFT) +#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT) #define MX31_H2_PM_BIT (1 << 16) #define MX31_H2_DT_BIT (1 << 5) #define MX31_H1_SIC_SHIFT 13 -#define MX31_H1_SIC_MASK (0xf << MX31_H1_SIC_SHIFT) +#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) #define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_DT_BIT (1 << 4) +#define MX35_OTG_SIC_SHIFT 29 +#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) +#define MX35_OTG_PM_BIT (1 << 24) + +#define MX35_H1_SIC_SHIFT 21 +#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) +#define MX35_H1_PM_BIT (1 << 8) +#define MX35_H1_IPPUE_UP_BIT (1 << 7) +#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) +#define MX35_H1_TLL_BIT (1 << 5) +#define MX35_H1_USBTE_BIT (1 << 4) + int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; - +#ifdef CONFIG_ARCH_MX3 if (cpu_is_mx31()) { - v = readl(IO_ADDRESS(MX31_OTG_BASE_ADDR + + v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { @@ -51,15 +63,15 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; - if (flags & MXC_EHCI_POWER_PINS_ENABLED) + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_OTG_PM_BIT; break; case 1: /* H1 port */ - v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT); + v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; - if (flags & MXC_EHCI_POWER_PINS_ENABLED) + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_H1_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) @@ -67,7 +79,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags) break; case 2: /* H2 port */ - v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT); + v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) @@ -77,13 +89,103 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v |= MX31_H2_DT_BIT; break; + default: + return -EINVAL; } - writel(v, IO_ADDRESS(MX31_OTG_BASE_ADDR + + writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } + if (cpu_is_mx35()) { + v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + + switch (port) { + case 0: /* OTG port */ + v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX35_OTG_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_OTG_PM_BIT; + + break; + case 1: /* H1 port */ + v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX35_H1_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX35_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX35_H1_TLL_BIT; + + if (flags & MXC_EHCI_INTERNAL_PHY) + v |= MX35_H1_USBTE_BIT; + + if (flags & MXC_EHCI_IPPUE_DOWN) + v |= MX35_H1_IPPUE_DOWN_BIT; + + if (flags & MXC_EHCI_IPPUE_UP) + v |= MX35_H1_IPPUE_UP_BIT; + + break; + default: + return -EINVAL; + } + + writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + return 0; + } +#endif /* CONFIG_ARCH_MX3 */ +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) { + /* On i.MX27 we can use the i.MX31 USBCTRL bits, they + * are identical + */ + v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + switch (port) { + case 0: /* OTG port */ + v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX31_OTG_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_OTG_PM_BIT; + break; + case 1: /* H1 port */ + v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX31_H1_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H1_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H1_DT_BIT; + + break; + case 2: /* H2 port */ + v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); + v |= (flags & MXC_EHCI_INTERFACE_MASK) + << MX31_H2_SIC_SHIFT; + if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) + v |= MX31_H2_PM_BIT; + + if (!(flags & MXC_EHCI_TTL_ENABLED)) + v |= MX31_H2_DT_BIT; + + break; + default: + return -EINVAL; + } + writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + + USBCTRL_OTGBASE_OFFSET)); + return 0; + } +#endif /* CONFIG_MACH_MX27 */ printk(KERN_WARNING "%s() unable to setup USBCONTROL for this CPU\n", __func__); return -EINVAL; diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index d65ebe303b9f..70b23893f094 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -140,16 +140,13 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) val = __raw_readl(reg); edge = (val >> (bit << 1)) & 3; val &= ~(0x3 << (bit << 1)); - switch (edge) { - case GPIO_INT_HIGH_LEV: + if (edge == GPIO_INT_HIGH_LEV) { edge = GPIO_INT_LOW_LEV; pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); - break; - case GPIO_INT_LOW_LEV: + } else if (edge == GPIO_INT_LOW_LEV) { edge = GPIO_INT_HIGH_LEV; pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); - break; - default: + } else { pr_err("mxc: invalid configuration for GPIO %d: %x\n", gpio, edge); return; @@ -157,25 +154,20 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) __raw_writel(val | (edge << (bit << 1)), reg); } -/* handle n interrupts in one status register */ +/* handle 32 interrupts in one status register */ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) { - u32 gpio_irq_no; + u32 gpio_irq_no_base = port->virtual_irq_start; - gpio_irq_no = port->virtual_irq_start; - for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) { - u32 gpio = irq_to_gpio(gpio_irq_no); - - if ((irq_stat & 1) == 0) - continue; + while (irq_stat != 0) { + int irqoffset = fls(irq_stat) - 1; - BUG_ON(!(irq_desc[gpio_irq_no].handle_irq)); + if (port->both_edges & (1 << irqoffset)) + mxc_flip_edge(port, irqoffset); - if (port->both_edges & (1 << (gpio & 31))) - mxc_flip_edge(port, gpio); + generic_handle_irq(gpio_irq_no_base + irqoffset); - irq_desc[gpio_irq_no].handle_irq(gpio_irq_no, - &irq_desc[gpio_irq_no]); + irq_stat &= ~(1 << irqoffset); } } diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h index 05ff2f31ef1f..93cc66f104c7 100644 --- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h +++ b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h @@ -21,19 +21,19 @@ /* * KZM-ARM11-01 Board Control Registers on FPGA */ -#define KZM_ARM11_CTL1 (CS4_BASE_ADDR + 0x1000) -#define KZM_ARM11_CTL2 (CS4_BASE_ADDR + 0x1001) -#define KZM_ARM11_RSW1 (CS4_BASE_ADDR + 0x1002) -#define KZM_ARM11_BACK_LIGHT (CS4_BASE_ADDR + 0x1004) -#define KZM_ARM11_FPGA_REV (CS4_BASE_ADDR + 0x1008) -#define KZM_ARM11_7SEG_LED (CS4_BASE_ADDR + 0x1010) -#define KZM_ARM11_LEDS (CS4_BASE_ADDR + 0x1020) -#define KZM_ARM11_DIPSW2 (CS4_BASE_ADDR + 0x1003) +#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000) +#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001) +#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002) +#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004) +#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008) +#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010) +#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020) +#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003) /* * External UART for touch panel on FPGA */ -#define KZM_ARM11_16550 (CS4_BASE_ADDR + 0x1050) +#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050) #endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h index 2cbfa35e82ff..095a199591c6 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h @@ -14,7 +14,7 @@ #include <mach/hardware.h> /* Base address of PBC controller */ -#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) +#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT /* Offsets for the PBC Controller register */ /* PBC Board status register offset */ diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h index d5be6b5a6acf..fc5fec9b55f0 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h @@ -25,6 +25,7 @@ enum mx31moboard_boards { MX31NOBOARD = 0, MX31DEVBOARD = 1, MX31MARXBOT = 2, + MX31SMARTBOT = 3, }; /* @@ -34,6 +35,7 @@ enum mx31moboard_boards { extern void mx31moboard_devboard_init(void); extern void mx31moboard_marxbot_init(void); +extern void mx31moboard_smartbot_init(void); #endif diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index 43a82d0c534d..753a5988d85c 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h @@ -26,13 +26,6 @@ struct module; struct clk { -#ifndef CONFIG_COMMON_CLKDEV - /* As soon as i.MX1 and i.MX31 switched to clkdev, this - * block can go away */ - struct list_head node; - struct module *owner; - const char *name; -#endif int id; /* Source clock this clk depends on */ struct clk *parent; diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 4bf1068ffad9..2941472582d2 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -20,14 +20,17 @@ extern void mx25_map_io(void); extern void mx27_map_io(void); extern void mx31_map_io(void); extern void mx35_map_io(void); +extern void mx51_map_io(void); extern void mxc91231_map_io(void); extern void mxc_init_irq(void __iomem *); +extern void tzic_init_irq(void __iomem *); extern void mx1_init_irq(void); extern void mx21_init_irq(void); extern void mx25_init_irq(void); extern void mx27_init_irq(void); extern void mx31_init_irq(void); extern void mx35_init_irq(void); +extern void mx51_init_irq(void); extern void mxc91231_init_irq(void); extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); extern int mx1_clocks_init(unsigned long fref); @@ -36,6 +39,8 @@ extern int mx25_clocks_init(void); extern int mx27_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); +extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); extern int mxc_register_device(struct platform_device *pdev, void *data); diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 15b2b148a105..133d66bfb533 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S @@ -10,6 +10,7 @@ * published by the Free Software Foundation. * */ +#define IMX_NEEDS_DEPRECATED_SYMBOLS #ifdef CONFIG_ARCH_MX1 #include <mach/mx1.h> @@ -44,13 +45,22 @@ #define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) #endif +#ifdef CONFIG_ARCH_MX5 +#ifdef UART_PADDR +#error "CONFIG_DEBUG_LL is incompatible with multiple archs" +#endif +#include <mach/mx51.h> +#define UART_PADDR MX51_UART1_BASE_ADDR +#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR) +#endif + #ifdef CONFIG_ARCH_MXC91231 #ifdef UART_PADDR #error "CONFIG_DEBUG_LL is incompatible with multiple archs" #endif #include <mach/mxc91231.h> #define UART_PADDR MXC91231_UART2_BASE_ADDR -#define UART_VADDR MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) +#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) #endif .macro addruart,rx mrc p15, 0, \rx, c1, c0 diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S index 7cf290efe768..aeb08697726b 100644 --- a/arch/arm/plat-mxc/include/mach/entry-macro.S +++ b/arch/arm/plat-mxc/include/mach/entry-macro.S @@ -1,6 +1,6 @@ /* * Copyright (C) 2007 Lennert Buytenhek <[email protected]> - * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -18,11 +18,16 @@ .endm .macro get_irqnr_preamble, base, tmp +#ifndef CONFIG_MXC_TZIC ldr \base, =avic_base ldr \base, [\base] #ifdef CONFIG_MXC_IRQ_PRIOR ldr r4, [\base, #AVIC_NIMASK] #endif +#elif defined CONFIG_MXC_TZIC + ldr \base, =tzic_base + ldr \base, [\base] +#endif /* CONFIG_MXC_TZIC */ .endm .macro arch_ret_to_user, tmp1, tmp2 @@ -32,6 +37,7 @@ @ and returns its number in irqnr @ and returns if an interrupt occured in irqstat .macro get_irqnr_and_base, irqnr, irqstat, base, tmp +#ifndef CONFIG_MXC_TZIC @ Load offset & priority of the highest priority @ interrupt pending from AVIC_NIVECSR ldr \irqstat, [\base, #0x40] @@ -45,6 +51,32 @@ strne \tmp, [\base, #AVIC_NIMASK] streq r4, [\base, #AVIC_NIMASK] #endif +#elif defined CONFIG_MXC_TZIC + @ Load offset & priority of the highest priority + @ interrupt pending. + @ 0xD80 is HIPND0 register + mov \irqnr, #0 + mov \irqstat, #0x0D80 +1000: + ldr \tmp, [\irqstat, \base] + cmp \tmp, #0 + bne 1001f + addeq \irqnr, \irqnr, #32 + addeq \irqstat, \irqstat, #4 + cmp \irqnr, #128 + blo 1000b + b 2001f +1001: mov \irqstat, #1 +1002: tst \tmp, \irqstat + bne 2002f + movs \tmp, \tmp, lsr #1 + addne \irqnr, \irqnr, #1 + bne 1002b +2001: + mov \irqnr, #0 +2002: + movs \irqnr, \irqnr +#endif .endm @ irq priority table (not used) diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index 78db75475f69..ebadf4ac43fc 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -22,6 +22,15 @@ #include <asm/sizes.h> +#define IMX_IO_ADDRESS(addr, module) \ + ((void __force __iomem *) \ + (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ + (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) + +#ifdef CONFIG_ARCH_MX5 +#include <mach/mx51.h> +#endif + #ifdef CONFIG_ARCH_MX3 #include <mach/mx3x.h> #include <mach/mx31.h> diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h index bf23305c19cc..6b1507cf378e 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h @@ -1,166 +1,155 @@ /* -* Copyright (C) 2008 by Sascha Hauer <[email protected]> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ + * Copyright (C) 2008 by Sascha Hauer <[email protected]> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX1_H__ +#define __MACH_IOMUX_MX1_H__ -#ifndef _MXC_IOMUX_MX1_H -#define _MXC_IOMUX_MX1_H +#include <mach/iomux-v1.h> -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif +#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) +#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) +#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1) +#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) +#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2) +#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) +#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) +#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) +#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) +#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) +#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) +#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) +#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) +#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) +#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) +#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) +#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) +#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) +#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) +#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) +#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) +#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) +#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) +#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) +#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) +#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) +#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) +#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) +#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) +#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) +#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) +#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) +#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) +#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) +#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) +#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) +#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) +#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) +#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) +#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) +#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) +#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) +#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) +#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) +#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) +#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) +#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) +#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) +#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) +#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) +#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) +#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) +#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) +#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) +#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) +#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) +#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) +#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16) +#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17) +#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) +#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) +#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) +#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) +#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22) +#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) +#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) +#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) +#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) +#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) +#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28) +#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29) +#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30) +#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31) +#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) +#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) +#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) +#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6) +#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) +#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) +#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) +#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10) +#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) +#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12) +#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) +#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) +#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) +#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) +#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) +#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24) +#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25) +#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26) +#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27) +#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28) +#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29) +#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) +#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31) +#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6) +#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) +#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7) +#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) +#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) +#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8) +#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) +#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) +#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9) +#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9) +#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10) +#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10) +#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10) +#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11) +#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12) +#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13) +#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14) +#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15) +#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16) +#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) +#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) +#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) +#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) +#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) +#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) +#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23) +#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) +#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) +#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) +#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) +#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) +#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) +#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30) +#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) +#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) -/* FIXME: This list is not completed. The correct directions are -* missing on some (many) pins -*/ - - -/* Primary GPIO pin functions */ - -#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) -#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) -#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1) -#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) -#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2) -#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) -#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) -#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) -#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) -#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) -#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) -#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) -#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) -#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) -#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) -#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) -#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) -#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) -#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) -#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) -#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) -#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) -#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) -#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) -#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) -#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) -#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) -#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) -#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) -#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) -#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) -#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) -#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) -#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) -#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) -#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) -#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) -#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) -#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) -#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) -#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) -#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) -#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) -#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) -#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) -#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) -#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) -#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) -#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) -#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) -#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) -#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) -#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) -#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) -#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) -#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) -#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) -#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16) -#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17) -#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) -#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) -#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) -#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) -#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22) -#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) -#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) -#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) -#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) -#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) -#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28) -#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29) -#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30) -#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31) -#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) -#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) -#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) -#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6) -#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) -#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) -#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) -#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10) -#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) -#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12) -#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) -#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) -#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) -#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) -#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) -#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24) -#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25) -#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26) -#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27) -#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28) -#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29) -#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) -#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31) -#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6) -#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) -#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7) -#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) -#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) -#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8) -#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) -#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) -#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9) -#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9) -#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10) -#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10) -#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10) -#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11) -#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12) -#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13) -#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14) -#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15) -#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16) -#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) -#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) -#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) -#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) -#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) -#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23) -#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) -#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) -#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) -#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) -#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) -#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) -#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30) -#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) -#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) - - -#endif +#endif /* ifndef __MACH_IOMUX_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h index 63aaa972e275..1495dfda7834 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx21.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h @@ -1,126 +1,122 @@ /* -* Copyright (C) 2009 by Holger Schurig <[email protected]> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ - -#ifndef _MXC_IOMUX_MX21_H -#define _MXC_IOMUX_MX21_H - -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif - + * Copyright (C) 2009 by Holger Schurig <[email protected]> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX21_H__ +#define __MACH_IOMUX_MX21_H__ + +#include <mach/iomux-mx2x.h> +#include <mach/iomux-v1.h> /* Primary GPIO pin functions */ -#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) -#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) -#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) -#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) -#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) -#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) -#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) -#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) -#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) -#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) -#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) -#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) -#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) -#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) -#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) -#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) -#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) +#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) +#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) +#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) +#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) +#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) +#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) +#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) +#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) +#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) +#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) +#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) +#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) +#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) +#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) +#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) +#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) +#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) +#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) +#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) +#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) +#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) +#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) +#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) +#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) +#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) +#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) +#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) +#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) +#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) /* Alternate GPIO pin functions */ -#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) -#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) -#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) -#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) -#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) -#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) -#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) -#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) -#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) -#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) -#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) -#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) -#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) -#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) -#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) -#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) -#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) -#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) -#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) -#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) -#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) +#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) +#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) +#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) +#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) +#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) +#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) +#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) +#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) +#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) +#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) +#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) +#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) +#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) +#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) +#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) +#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) +#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) +#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) +#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) +#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) +#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) /* AIN GPIO pin functions */ -#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) -#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) -#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) -#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) -#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) -#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) -#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) -#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) -#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) -#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) -#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) +#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) +#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) +#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) +#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) +#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) +#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) +#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) +#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) +#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) +#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) +#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) +#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) /* BIN GPIO pin functions */ -#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) -#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) +#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) +#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) /* CIN GPIO pin functions */ -#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) +#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) /* AOUT GPIO pin functions */ -#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) -#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) -#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) -#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) -#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) -#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) -#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) -#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) -#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) -#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) -#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) -#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) -#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) -#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) -#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) - - -#endif +#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) +#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) +#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) +#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) +#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) +#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) +#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) +#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) +#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) +#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) +#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) +#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) +#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) +#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) +#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) + +#endif /* ifndef __MACH_IOMUX_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h index 9af494f0ab3d..f39220d1b67a 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h @@ -7,7 +7,7 @@ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved. * and * arch/arm/plat-mxc/include/mach/iomux-mx35.h - * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <[email protected]> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <[email protected]> * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -16,24 +16,11 @@ * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ -#ifndef __IOMUX_MX25_H__ -#define __IOMUX_MX25_H__ +#ifndef __MACH_IOMUX_MX25_H__ +#define __MACH_IOMUX_MX25_H__ #include <mach/iomux-v3.h> -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif - -/* - * - * @brief MX25 I/O Pin List - * - * @ingroup GPIO_MX25 - */ - -#ifndef __ASSEMBLY__ - /* * IOMUX/PAD Bit field definitions */ @@ -462,9 +449,11 @@ #define MX25_PAD_GPIO_C__CAN2_TX IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP) #define MX25_PAD_GPIO_D__GPIO_D IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_E__LD16 IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_D__CAN2_RX IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP) #define MX25_PAD_GPIO_E__GPIO_E IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL) +#define MX25_PAD_GPIO_F__LD17 IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_E__AUD7_TXD IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL) #define MX25_PAD_GPIO_F__GPIO_F IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL) @@ -513,5 +502,4 @@ #define MX25_PAD_CTL_GRP_DVS_SDHC1 IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL) #define MX25_PAD_CTL_GRP_DVS_LCD IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL) -#endif // __ASSEMBLY__ -#endif // __IOMUX_MX25_H__ +#endif /* __MACH_IOMUX_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h index 5ac158b70f61..d9f9a6e32d80 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx27.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h @@ -1,207 +1,205 @@ /* -* Copyright (C) 2008 by Sascha Hauer <[email protected]> -* Copyright (C) 2009 by Holger Schurig <[email protected]> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ - -#ifndef _MXC_IOMUX_MX27_H -#define _MXC_IOMUX_MX27_H - -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif - + * Copyright (C) 2008 by Sascha Hauer <[email protected]> + * Copyright (C) 2009 by Holger Schurig <[email protected]> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX27_H__ +#define __MACH_IOMUX_MX27_H__ + +#include <mach/iomux-mx2x.h> +#include <mach/iomux-v1.h> /* Primary GPIO pin functions */ -#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) -#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) -#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) -#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) -#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) -#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) -#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) -#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) -#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) -#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) -#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) -#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) -#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) -#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) -#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) -#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) -#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) -#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) -#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) -#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) -#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) -#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) -#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) -#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) -#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) -#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) -#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) -#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) -#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) -#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) -#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) -#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) -#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) -#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) -#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) -#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) -#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) -#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) -#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) -#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) -#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) -#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) -#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) -#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) -#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) -#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) -#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) -#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) -#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) -#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) -#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) -#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) -#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) -#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) -#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) -#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) -#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) -#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) -#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) -#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) +#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) +#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) +#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) +#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) +#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) +#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) +#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) +#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) +#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) +#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) +#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) +#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) +#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) +#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) +#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) +#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) +#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) +#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) +#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) +#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) +#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) +#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) +#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) +#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) +#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) +#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) +#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) +#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) +#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) +#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) +#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) +#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) +#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) +#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) +#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) +#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) +#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) +#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) +#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) +#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) +#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) +#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) +#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) +#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) +#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) +#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) +#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) +#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) +#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) +#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) +#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) +#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) +#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) +#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) +#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) +#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) +#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) +#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) /* Alternate GPIO pin functions */ -#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) -#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) -#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) -#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) -#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) -#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) -#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) -#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) -#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) -#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) -#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) -#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) -#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) -#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) -#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) -#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) -#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) -#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) -#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) -#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) -#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) -#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) -#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) -#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) -#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) -#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) -#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) -#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) -#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) -#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) -#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) -#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) -#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) -#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) -#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) -#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) -#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) -#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) -#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) -#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) -#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) -#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) -#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) -#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) -#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) -#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) -#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) -#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) -#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) -#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) -#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) -#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) +#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) +#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) +#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) +#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) +#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) +#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) +#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) +#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) +#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) +#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) +#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) +#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) +#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) +#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) +#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) +#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) +#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) +#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) +#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) +#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) +#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) +#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) +#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) +#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) +#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) +#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) +#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) +#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) +#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) +#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) +#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) +#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) +#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) +#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) +#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) +#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) +#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) +#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) +#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) +#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) +#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) +#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) +#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) +#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) +#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) +#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) +#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) +#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) +#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) +#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) +#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) +#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) +#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) +#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) /* AIN GPIO pin functions */ -#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) -#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) -#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) -#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) -#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) -#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) -#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) -#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) -#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) -#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) +#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) +#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) +#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) +#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) +#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) +#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) +#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) +#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) +#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) +#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) /* BIN GPIO pin functions */ -#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) +#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) /* CIN GPIO pin functions */ -#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) -#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) -#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) -#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) -#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) -#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) -#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) -#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) -#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) -#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) -#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) -#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) -#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) -#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) -#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) -#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) -#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) +#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) +#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) +#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) +#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) +#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) +#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) +#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) +#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) +#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) +#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) +#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) +#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) +#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) +#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) +#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) +#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) +#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) /* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ /* AOUT GPIO pin functions */ -#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) -#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) -#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) -#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) -#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) -#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) -#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) -#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) -#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) -#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) -#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) - -#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) -#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) -#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) -#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) -#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) -#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) -#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) - - -#endif /* _MXC_GPIO_MX1_MX2_H */ +#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) +#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) +#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) +#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) +#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) +#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) +#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) +#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) +#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) +#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) +#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) + +/* BOUT GPIO pin functions */ + +#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) +#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) +#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) +#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) +#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) +#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) +#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) + +#endif /* __MACH_IOMUX_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h index fb5ae638e79f..c4f116d214f2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h @@ -1,237 +1,230 @@ /* -* Copyright (C) 2008 by Sascha Hauer <[email protected]> -* Copyright (C) 2009 by Holger Schurig <[email protected]> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ - -#ifndef _MXC_IOMUX_MX2x_H -#define _MXC_IOMUX_MX2x_H - -#ifndef GPIO_PORTA -#error Please include mach/iomux.h -#endif - + * Copyright (C) 2008 by Sascha Hauer <[email protected]> + * Copyright (C) 2009 by Holger Schurig <[email protected]> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_MX2x_H__ +#define __MACH_IOMUX_MX2x_H__ /* Primary GPIO pin functions */ -#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) -#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) -#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) -#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) -#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) -#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) -#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) -#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) -#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) -#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) -#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) -#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) -#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) -#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) -#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) -#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) -#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) -#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) -#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) -#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) -#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) -#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) -#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) -#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) -#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) -#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) -#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) -#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) -#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) -#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) -#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) -#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) -#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) -#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) -#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) -#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) -#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) -#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) -#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) -#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) -#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) -#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) -#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) -#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) -#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) -#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) -#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) -#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) -#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) -#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) -#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) -#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) -#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) -#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) -#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) -#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) -#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) -#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) -#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) -#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) -#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) -#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) -#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) -#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) -#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) -#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) -#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) -#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) -#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) -#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) -#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) -#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) -#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) -#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) -#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) -#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) -#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) -#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) -#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) -#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) -#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) -#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) -#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) -#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) -#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) -#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) -#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) -#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) -#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) -#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) -#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) -#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) -#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) -#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) -#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) -#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) -#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) -#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) -#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) -#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) -#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) -#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) -#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) -#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) -#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) -#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) -#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) -#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) -#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) -#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) -#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) +#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) +#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) +#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) +#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) +#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) +#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) +#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) +#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) +#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) +#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) +#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) +#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) +#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) +#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) +#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) +#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) +#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) +#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) +#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) +#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) +#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) +#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) +#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) +#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) +#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) +#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) +#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) +#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) +#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) +#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) +#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) +#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) +#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) +#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) +#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) +#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) +#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) +#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) +#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) +#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) +#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) +#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) +#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) +#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) +#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) +#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) +#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) +#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) +#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) +#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) +#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) +#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) +#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) +#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) +#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) +#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) +#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) +#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) +#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) +#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) +#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) +#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) +#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) +#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) +#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) +#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) +#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) +#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) +#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) +#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) +#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) +#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) +#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) +#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) +#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) +#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) +#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) +#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) +#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) +#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) +#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) +#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) +#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) +#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) +#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) +#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) +#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) +#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) +#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) +#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) +#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) +#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) +#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) +#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) +#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) +#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) +#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) +#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) +#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) +#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) +#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) +#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) +#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) +#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) +#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) +#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) +#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) +#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) +#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) +#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) +#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) /* Alternate GPIO pin functions */ -#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) -#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) -#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) -#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) -#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) -#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) -#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) -#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) -#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) -#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) -#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) -#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) -#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) -#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) -#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) -#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) -#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) -#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) -#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) -#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) -#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) -#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) -#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) -#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) -#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) -#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) -#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) +#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) +#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) +#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) +#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) +#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) +#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) +#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) +#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) +#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) +#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) +#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) +#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) +#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) +#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) +#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) +#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) +#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) +#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) +#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) +#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) +#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) +#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) +#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) +#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) +#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) +#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) +#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) /* AIN GPIO pin functions */ -#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) -#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) -#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) -#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) -#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) -#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) -#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) -#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) -#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) -#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) -#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) -#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) -#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) -#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) -#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) -#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) -#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) -#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) -#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) -#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) -#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) -#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) -#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) -#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) -#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) -#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) -#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) -#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) -#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) -#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) -#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) -#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) -#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) -#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) -#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) -#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) +#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) +#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) +#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) +#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) +#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) +#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) +#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) +#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) +#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) +#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) +#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) +#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) +#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) +#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) +#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) +#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) +#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) +#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) +#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) +#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) +#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) +#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) +#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) +#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) +#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) +#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) +#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) +#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) +#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) +#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) +#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) +#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) +#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) +#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) +#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) +#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) /* BIN GPIO pin functions */ -#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) +#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) /* CIN GPIO pin functions */ -#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) -#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) -#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) -#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) -#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) -#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) -#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) -#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) -#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) -#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) +#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) +#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) +#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) +#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) +#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) +#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) +#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) +#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) +#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) +#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) /* AOUT GPIO pin functions */ -#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) -#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) +#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) +#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) #define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) -#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) -#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) - +#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) +#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) -#endif +#endif /* ifndef __MACH_IOMUX_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index e1fc6da1cd10..e51465d7b224 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -16,12 +16,10 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, * MA 02110-1301, USA. */ - -#ifndef __MACH_MX31_IOMUX_H__ -#define __MACH_MX31_IOMUX_H__ +#ifndef __MACH_IOMUX_MX3_H__ +#define __MACH_IOMUX_MX3_H__ #include <linux/types.h> - /* * various IOMUX output functions */ @@ -34,7 +32,7 @@ #define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */ #define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */ #define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */ -#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ +#define IOMUX_ICONFIG_NONE 0 /* not configured for input */ #define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */ #define IOMUX_ICONFIG_FUNC 2 /* used as function */ #define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */ @@ -167,11 +165,6 @@ int mxc_iomux_mode(unsigned int pin_mode); MXC_GPIO_IRQ_START) /* - * The number of gpio devices among the pads - */ -#define GPIO_PORT_MAX 3 - -/* * This enumeration is constructed based on the Section * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated * value is constructed based on the rules described above. @@ -633,40 +626,40 @@ enum iomux_pins { #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) #define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) #define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) -#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) -#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) +#define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA3__USBOTG_DATA3 IOMUX_MODE(MX31_PIN_USBOTG_DATA3, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA4__USBOTG_DATA4 IOMUX_MODE(MX31_PIN_USBOTG_DATA4, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA5__USBOTG_DATA5 IOMUX_MODE(MX31_PIN_USBOTG_DATA5, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA6__USBOTG_DATA6 IOMUX_MODE(MX31_PIN_USBOTG_DATA6, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DATA7__USBOTG_DATA7 IOMUX_MODE(MX31_PIN_USBOTG_DATA7, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_CLK__USBOTG_CLK IOMUX_MODE(MX31_PIN_USBOTG_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_DIR__USBOTG_DIR IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_NXT__USBOTG_NXT IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBOTG_STP__USBOTG_STP IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_MISO__USBH1_RXDP IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS0__USBH1_TXDM IOMUX_MODE(MX31_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS1__USBH1_TXDP IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) +#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) #define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) #define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) #define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) -#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) #define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) #define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) #define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) #define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) #define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) #define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) -#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) +#define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) #define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) #define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) #define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) @@ -711,8 +704,8 @@ enum iomux_pins { #define MX31_PIN_DSR_DCE1__GPIO2_9 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO) #define MX31_PIN_RI_DCE1__GPIO2_10 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO) #define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) -#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) -#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) +#define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) #define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) #define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) @@ -727,13 +720,14 @@ enum iomux_pins { #define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) #define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) -/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 - * cspi1_ss1*/ +/* + * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, + * cspi2_ss1, cspi1_ss0 cspi1_ss1 + */ /* * This function configures the pad value for a IOMUX pin. */ void mxc_iomux_set_pad(enum iomux_pins, u32); -#endif - +#endif /* ifndef __MACH_IOMUX_MX3_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx35.h b/arch/arm/plat-mxc/include/mach/iomux-mx35.h index c88d40795f7a..2a24bae1b878 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx35.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx35.h @@ -1,5 +1,5 @@ /* - * Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <[email protected]> + * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <[email protected]> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h new file mode 100644 index 000000000000..b4f975e6a665 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -0,0 +1,326 @@ +/* + * Copyright (C) 2009-2010 Amit Kucheria <[email protected]> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __MACH_IOMUX_MX51_H__ +#define __MACH_IOMUX_MX51_H__ + +#include <mach/iomux-v3.h> + +/* + * various IOMUX alternate output functions (1-7) + */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, + IOMUX_CONFIG_ALT1, + IOMUX_CONFIG_ALT2, + IOMUX_CONFIG_ALT3, + IOMUX_CONFIG_ALT4, + IOMUX_CONFIG_ALT5, + IOMUX_CONFIG_ALT6, + IOMUX_CONFIG_ALT7, + IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/* Pad control groupings */ +#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH) +#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) + +/* + * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> + * If <padname> or <padmode> refers to a GPIO, it is named + * GPIO_<unit>_<num> see also iomux-v3.h + */ + +/* + * FIXME: This was converted using scripts from existing Freescale code to + * this form used upstream. Need to verify the name format. + */ + +/* PAD MUX ALT INPSE PATH PADCTRL */ + +#define MX51_PAD_GPIO_2_0__EIM_D16 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_1__EIM_D17 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_2__EIM_D18 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) + +/* Babbage UART3 */ +#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL) +#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL) + +#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_2_10__EIM_A16 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_11__EIM_A17 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_12__EIM_A18 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_13__EIM_A19 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_14__EIM_A20 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_15__EIM_A21 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_16__EIM_A22 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_17__EIM_A23 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_2_18__EIM_A24 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_19__EIM_A25 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_20__EIM_A26 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_21__EIM_A27 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_22__EIM_EB2 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_23__EIM_EB3 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_2_24__EIM_OE IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_25__EIM_CS0 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_26__EIM_CS1 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_27__EIM_CS2 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_28__EIM_CS3 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_29__EIM_CS4 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_30__EIM_CS5 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_2_31__EIM_DTACK IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_GPIO_3_1__EIM_LBA IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_2__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_3__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_4__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_5__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_6__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_7__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_8__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_9__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_10__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_11__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_12__GPIO_NAND IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) +/* REVISIT: Not sure of these values + + #define MX51_PAD_GPIO_1___NANDF_RB4 IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +*/ +#define MX51_PAD_GPIO_3_14__NANDF_RB6 IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_16__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_17__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_18__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_19__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_20__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_21__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_22__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_23__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_25__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_26__NANDF_D14 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_27__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_28__NANDF_D12 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_29__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_30__NANDF_D10 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_31__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_0__NANDF_D8 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_1__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_2__NANDF_D6 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_3__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_5__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_6__NANDF_D2 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_7__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_8__NANDF_D0 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_12__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_13__CSI1_D9 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_9__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_10__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_11__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_12__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_11__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_12__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_11__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_12__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_13__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_14__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_16__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_17__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_20__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_21__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_22__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_23__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_24__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_25__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_26__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_4_27__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) + +/* Babbage UART1 */ +#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) +#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL) +#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL) + +/* Babbage UART2 */ +#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL) +#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL) + +#define MX51_PAD_GPIO_1_22__UART3_RXD IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_23__UART3_TXD IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_24__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_3__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_4__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_19__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_29__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_30__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_31__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ + (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) +#define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) + +/* EIM */ +#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) + +#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) +#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h new file mode 100644 index 000000000000..884f5753f279 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2008 by Sascha Hauer <[email protected]> + * Copyright (C) 2009 by Holger Schurig <[email protected]> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ +#ifndef __MACH_IOMUX_V1_H__ +#define __MACH_IOMUX_V1_H__ + +/* +* GPIO Module and I/O Multiplexer +* x = 0..3 for reg_A, reg_B, reg_C, reg_D +*/ +#define MXC_DDIR(x) (0x00 + ((x) << 8)) +#define MXC_OCR1(x) (0x04 + ((x) << 8)) +#define MXC_OCR2(x) (0x08 + ((x) << 8)) +#define MXC_ICONFA1(x) (0x0c + ((x) << 8)) +#define MXC_ICONFA2(x) (0x10 + ((x) << 8)) +#define MXC_ICONFB1(x) (0x14 + ((x) << 8)) +#define MXC_ICONFB2(x) (0x18 + ((x) << 8)) +#define MXC_DR(x) (0x1c + ((x) << 8)) +#define MXC_GIUS(x) (0x20 + ((x) << 8)) +#define MXC_SSR(x) (0x24 + ((x) << 8)) +#define MXC_ICR1(x) (0x28 + ((x) << 8)) +#define MXC_ICR2(x) (0x2c + ((x) << 8)) +#define MXC_IMR(x) (0x30 + ((x) << 8)) +#define MXC_ISR(x) (0x34 + ((x) << 8)) +#define MXC_GPR(x) (0x38 + ((x) << 8)) +#define MXC_SWR(x) (0x3c + ((x) << 8)) +#define MXC_PUEN(x) (0x40 + ((x) << 8)) + +#define MX1_NUM_GPIO_PORT 4 +#define MX21_NUM_GPIO_PORT 6 +#define MX27_NUM_GPIO_PORT 6 + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) +#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) +#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) +#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) +#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) +#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) + +#define GPIO_OUT (1 << 8) +#define GPIO_IN (0 << 8) +#define GPIO_PUEN (1 << 9) + +#define GPIO_PF (1 << 10) +#define GPIO_AF (1 << 11) + +#define GPIO_OCR_SHIFT 12 +#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) +#define GPIO_AIN (0 << GPIO_OCR_SHIFT) +#define GPIO_BIN (1 << GPIO_OCR_SHIFT) +#define GPIO_CIN (2 << GPIO_OCR_SHIFT) +#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) + +#define GPIO_AOUT_SHIFT 14 +#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) + +#define GPIO_BOUT_SHIFT 16 +#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + +/* decode irq number to use with IMR(x), ISR(x) and friends */ +#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) + +#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) +#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) +#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) +#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) +#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) +#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x) + +extern int mxc_gpio_mode(int gpio_mode); +extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + const char *label); +extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); + +#endif /* __MACH_IOMUX_V1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 1deda0184892..f2f73d31d5ba 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -81,11 +81,13 @@ struct pad_desc { #define PAD_CTL_ODE (1 << 3) -#define PAD_CTL_DSE_STANDARD (0 << 1) -#define PAD_CTL_DSE_HIGH (1 << 1) -#define PAD_CTL_DSE_MAX (2 << 1) +#define PAD_CTL_DSE_LOW (0 << 1) +#define PAD_CTL_DSE_MED (1 << 1) +#define PAD_CTL_DSE_HIGH (2 << 1) +#define PAD_CTL_DSE_MAX (3 << 1) #define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW (0 << 0) /* * setups a single pad in the iomuxer diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h index 011cfcd8b820..3d226d7e7be2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux.h +++ b/arch/arm/plat-mxc/include/mach/iomux.h @@ -1,102 +1,14 @@ /* -* Copyright (C) 2008 by Sascha Hauer <[email protected]> -* Copyright (C) 2009 by Holger Schurig <[email protected]> -* -* This program is free software; you can redistribute it and/or -* modify it under the terms of the GNU General Public License -* as published by the Free Software Foundation; either version 2 -* of the License, or (at your option) any later version. -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, write to the Free Software -* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, -* MA 02110-1301, USA. -*/ - -#ifndef _MXC_IOMUX_H -#define _MXC_IOMUX_H - -/* -* GPIO Module and I/O Multiplexer -* x = 0..3 for reg_A, reg_B, reg_C, reg_D -*/ -#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR) -#define MXC_DDIR(x) (0x00 + ((x) << 8)) -#define MXC_OCR1(x) (0x04 + ((x) << 8)) -#define MXC_OCR2(x) (0x08 + ((x) << 8)) -#define MXC_ICONFA1(x) (0x0c + ((x) << 8)) -#define MXC_ICONFA2(x) (0x10 + ((x) << 8)) -#define MXC_ICONFB1(x) (0x14 + ((x) << 8)) -#define MXC_ICONFB2(x) (0x18 + ((x) << 8)) -#define MXC_DR(x) (0x1c + ((x) << 8)) -#define MXC_GIUS(x) (0x20 + ((x) << 8)) -#define MXC_SSR(x) (0x24 + ((x) << 8)) -#define MXC_ICR1(x) (0x28 + ((x) << 8)) -#define MXC_ICR2(x) (0x2c + ((x) << 8)) -#define MXC_IMR(x) (0x30 + ((x) << 8)) -#define MXC_ISR(x) (0x34 + ((x) << 8)) -#define MXC_GPR(x) (0x38 + ((x) << 8)) -#define MXC_SWR(x) (0x3c + ((x) << 8)) -#define MXC_PUEN(x) (0x40 + ((x) << 8)) - -#ifdef CONFIG_ARCH_MX1 -# define GPIO_PORT_MAX 3 -#endif -#ifdef CONFIG_ARCH_MX2 -# define GPIO_PORT_MAX 5 -#endif -#ifdef CONFIG_ARCH_MX25 -# define GPIO_PORT_MAX 3 -#endif - -#ifndef GPIO_PORT_MAX -# error "GPIO config port count unknown!" -#endif - -#define GPIO_PIN_MASK 0x1f - -#define GPIO_PORT_SHIFT 5 -#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) - -#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) -#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) -#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) -#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) -#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) -#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) - -#define GPIO_OUT (1 << 8) -#define GPIO_IN (0 << 8) -#define GPIO_PUEN (1 << 9) - -#define GPIO_PF (1 << 10) -#define GPIO_AF (1 << 11) - -#define GPIO_OCR_SHIFT 12 -#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) -#define GPIO_AIN (0 << GPIO_OCR_SHIFT) -#define GPIO_BIN (1 << GPIO_OCR_SHIFT) -#define GPIO_CIN (2 << GPIO_OCR_SHIFT) -#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) - -#define GPIO_AOUT_SHIFT 14 -#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) -#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) - -#define GPIO_BOUT_SHIFT 16 -#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) -#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ +#ifndef __MACH_IOMUX_H__ +#define __MACH_IOMUX_H__ +/* This file will go away, please include mach/iomux-mx... directly */ #ifdef CONFIG_ARCH_MX1 #include <mach/iomux-mx1.h> @@ -110,25 +22,5 @@ #include <mach/iomux-mx27.h> #endif #endif -#ifdef CONFIG_ARCH_MX25 -#include <mach/iomux-mx25.h> -#endif - -/* decode irq number to use with IMR(x), ISR(x) and friends */ -#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) - -#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) -#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) -#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) -#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) -#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) -#define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x) - - -extern void mxc_gpio_mode(int gpio_mode); -extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - const char *label); -extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); - -#endif +#endif /* __MACH_IOMUX_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 0cb347645db4..86781f7b0c0c 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -12,22 +12,29 @@ #define __ASM_ARCH_MXC_IRQS_H__ /* - * So far all i.MX SoCs have 64 internal interrupts + * SoCs with TZIC interrupt controller have 128 IRQs, those with AVIC have 64 */ +#ifdef CONFIG_MXC_TZIC +#define MXC_INTERNAL_IRQS 128 +#else #define MXC_INTERNAL_IRQS 64 +#endif #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS -#if defined CONFIG_ARCH_MX1 -#define MXC_GPIO_IRQS (32 * 4) -#elif defined CONFIG_ARCH_MX2 +/* these are ordered by size to support multi-SoC kernels */ +#if defined CONFIG_ARCH_MX2 #define MXC_GPIO_IRQS (32 * 6) -#elif defined CONFIG_ARCH_MX3 -#define MXC_GPIO_IRQS (32 * 3) +#elif defined CONFIG_ARCH_MX1 +#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MX25 #define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX5 +#define MXC_GPIO_IRQS (32 * 4) #elif defined CONFIG_ARCH_MXC91231 #define MXC_GPIO_IRQS (32 * 4) +#elif defined CONFIG_ARCH_MX3 +#define MXC_GPIO_IRQS (32 * 3) #endif /* @@ -51,6 +58,7 @@ #else #define MX3_IPU_IRQS 0 #endif +/* REVISIT: Add IPU irqs on IMX51 */ #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS) diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index d3afafdcc0e5..c4b40c35a6a1 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -11,37 +11,45 @@ #ifndef __ASM_ARCH_MXC_MEMORY_H__ #define __ASM_ARCH_MXC_MEMORY_H__ -#if defined CONFIG_ARCH_MX1 -#define PHYS_OFFSET UL(0x08000000) -#elif defined CONFIG_ARCH_MX2 -#ifdef CONFIG_MACH_MX21 -#define PHYS_OFFSET UL(0xC0000000) -#endif -#ifdef CONFIG_MACH_MX27 -#define PHYS_OFFSET UL(0xA0000000) -#endif -#elif defined CONFIG_ARCH_MX3 -#define PHYS_OFFSET UL(0x80000000) -#elif defined CONFIG_ARCH_MX25 -#define PHYS_OFFSET UL(0x80000000) -#elif defined CONFIG_ARCH_MXC91231 -#define PHYS_OFFSET UL(0x90000000) +#define MX1_PHYS_OFFSET UL(0x08000000) +#define MX21_PHYS_OFFSET UL(0xc0000000) +#define MX25_PHYS_OFFSET UL(0x80000000) +#define MX27_PHYS_OFFSET UL(0xa0000000) +#define MX3x_PHYS_OFFSET UL(0x80000000) +#define MX51_PHYS_OFFSET UL(0x90000000) +#define MXC91231_PHYS_OFFSET UL(0x90000000) + +#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) +# if defined CONFIG_ARCH_MX1 +# define PHYS_OFFSET MX1_PHYS_OFFSET +# elif defined CONFIG_MACH_MX21 +# define PHYS_OFFSET MX21_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX25 +# define PHYS_OFFSET MX25_PHYS_OFFSET +# elif defined CONFIG_MACH_MX27 +# define PHYS_OFFSET MX27_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX3 +# define PHYS_OFFSET MX3x_PHYS_OFFSET +# elif defined CONFIG_ARCH_MXC91231 +# define PHYS_OFFSET MXC91231_PHYS_OFFSET +# elif defined CONFIG_ARCH_MX5 +# define PHYS_OFFSET MX51_PHYS_OFFSET +# endif #endif -#if defined(CONFIG_MX1_VIDEO) +#if defined(CONFIG_MX3_VIDEO) /* * Increase size of DMA-consistent memory region. - * This is required for i.MX camera driver to capture at least four VGA frames. + * This is required for mx3 camera driver to capture at least two QXGA frames. */ -#define CONSISTENT_DMA_SIZE SZ_4M -#endif /* CONFIG_MX1_VIDEO */ +#define CONSISTENT_DMA_SIZE SZ_8M -#if defined(CONFIG_MX3_VIDEO) +#elif defined(CONFIG_MX1_VIDEO) /* * Increase size of DMA-consistent memory region. - * This is required for mx3 camera driver to capture at least two QXGA frames. + * This is required for i.MX camera driver to capture at least four VGA frames. */ -#define CONSISTENT_DMA_SIZE SZ_8M -#endif /* CONFIG_MX3_VIDEO */ +#define CONSISTENT_DMA_SIZE SZ_4M +#endif /* CONFIG_MX1_VIDEO */ #endif /* __ASM_ARCH_MXC_MEMORY_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mtd-xip.h b/arch/arm/plat-mxc/include/mach/mtd-xip.h deleted file mode 100644 index 1ab1bba5688d..000000000000 --- a/arch/arm/plat-mxc/include/mach/mtd-xip.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * MTD primitives for XIP support. Architecture specific functions - * - * Do not include this file directly. It's included from linux/mtd/xip.h - * - * Copyright (C) 2008 Darius Augulis <[email protected]>, Teltonika, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <mach/mxc_timer.h> - -#ifndef __ARCH_IMX_MTD_XIP_H__ -#define __ARCH_IMX_MTD_XIP_H__ - -#ifdef CONFIG_ARCH_MX1 -/* AITC registers */ -#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR) -#define NIPNDH (AITC_BASE + 0x58) -#define NIPNDL (AITC_BASE + 0x5C) -#define INTENABLEH (AITC_BASE + 0x10) -#define INTENABLEL (AITC_BASE + 0x14) -/* MTD macros */ -#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \ - || (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL))) -#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN)) -#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96) -#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0)) -#endif /* CONFIG_ARCH_MX1 */ - -#endif /* __ARCH_IMX_MTD_XIP_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h index 1b2890a5c452..5eba7e6785de 100644 --- a/arch/arm/plat-mxc/include/mach/mx1.h +++ b/arch/arm/plat-mxc/include/mach/mx1.h @@ -9,156 +9,289 @@ * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_MXC_MX1_H__ -#define __ASM_ARCH_MXC_MX1_H__ +#ifndef __MACH_MX1_H__ +#define __MACH_MX1_H__ #include <mach/vmalloc.h> /* * Memory map */ -#define IMX_IO_PHYS 0x00200000 -#define IMX_IO_SIZE 0x00100000 -#define IMX_IO_BASE VMALLOC_END +#define MX1_IO_BASE_ADDR 0x00200000 +#define MX1_IO_SIZE SZ_1M +#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END -#define IMX_CS0_PHYS 0x10000000 -#define IMX_CS0_SIZE 0x02000000 +#define MX1_CS0_PHYS 0x10000000 +#define MX1_CS0_SIZE 0x02000000 -#define IMX_CS1_PHYS 0x12000000 -#define IMX_CS1_SIZE 0x01000000 +#define MX1_CS1_PHYS 0x12000000 +#define MX1_CS1_SIZE 0x01000000 -#define IMX_CS2_PHYS 0x13000000 -#define IMX_CS2_SIZE 0x01000000 +#define MX1_CS2_PHYS 0x13000000 +#define MX1_CS2_SIZE 0x01000000 -#define IMX_CS3_PHYS 0x14000000 -#define IMX_CS3_SIZE 0x01000000 +#define MX1_CS3_PHYS 0x14000000 +#define MX1_CS3_SIZE 0x01000000 -#define IMX_CS4_PHYS 0x15000000 -#define IMX_CS4_SIZE 0x01000000 +#define MX1_CS4_PHYS 0x15000000 +#define MX1_CS4_SIZE 0x01000000 -#define IMX_CS5_PHYS 0x16000000 -#define IMX_CS5_SIZE 0x01000000 +#define MX1_CS5_PHYS 0x16000000 +#define MX1_CS5_SIZE 0x01000000 /* * Register BASEs, based on OFFSETs */ -#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS) -#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS) -#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS) -#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS) -#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS) -#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS) -#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS) -#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS) -#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS) -#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS) -#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS) -#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS) -#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS) -#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS) -#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS) -#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS) -#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS) -#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS) -#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS) -#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS) -#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS) -#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS) -#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS) -#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS) -#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS) -#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS) -#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS) -#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS) -#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS) +#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR) +#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR) +#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR) +#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR) +#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR) +#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR) +#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR) +#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR) +#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR) +#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR) +#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR) +#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR) +#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR) +#define MX1_SPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR) +#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR) +#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR) +#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR) +#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR) +#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR) +#define MX1_SPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR) +#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR) +#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) +#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) +#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) +#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) +#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) +#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) +#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR) +#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) /* macro to get at IO space when running virtually */ -#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE) - -/* define macros needed for entry-macro.S */ -#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) +#define MX1_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX1_IO)) /* fixed interrput numbers */ -#define INT_SOFTINT 0 -#define CSI_INT 6 -#define DSPA_MAC_INT 7 -#define DSPA_INT 8 -#define COMP_INT 9 -#define MSHC_XINT 10 -#define GPIO_INT_PORTA 11 -#define GPIO_INT_PORTB 12 -#define GPIO_INT_PORTC 13 -#define LCDC_INT 14 -#define SIM_INT 15 -#define SIM_DATA_INT 16 -#define RTC_INT 17 -#define RTC_SAMINT 18 -#define UART2_MINT_PFERR 19 -#define UART2_MINT_RTS 20 -#define UART2_MINT_DTR 21 -#define UART2_MINT_UARTC 22 -#define UART2_MINT_TX 23 -#define UART2_MINT_RX 24 -#define UART1_MINT_PFERR 25 -#define UART1_MINT_RTS 26 -#define UART1_MINT_DTR 27 -#define UART1_MINT_UARTC 28 -#define UART1_MINT_TX 29 -#define UART1_MINT_RX 30 -#define VOICE_DAC_INT 31 -#define VOICE_ADC_INT 32 -#define PEN_DATA_INT 33 -#define PWM_INT 34 -#define SDHC_INT 35 -#define I2C_INT 39 -#define CSPI_INT 41 -#define SSI_TX_INT 42 -#define SSI_TX_ERR_INT 43 -#define SSI_RX_INT 44 -#define SSI_RX_ERR_INT 45 -#define TOUCH_INT 46 -#define USBD_INT0 47 -#define USBD_INT1 48 -#define USBD_INT2 49 -#define USBD_INT3 50 -#define USBD_INT4 51 -#define USBD_INT5 52 -#define USBD_INT6 53 -#define BTSYS_INT 55 -#define BTTIM_INT 56 -#define BTWUI_INT 57 -#define TIM2_INT 58 -#define TIM1_INT 59 -#define DMA_ERR 60 -#define DMA_INT 61 -#define GPIO_INT_PORTD 62 -#define WDT_INT 63 +#define MX1_INT_SOFTINT 0 +#define MX1_CSI_INT 6 +#define MX1_DSPA_MAC_INT 7 +#define MX1_DSPA_INT 8 +#define MX1_COMP_INT 9 +#define MX1_MSHC_XINT 10 +#define MX1_GPIO_INT_PORTA 11 +#define MX1_GPIO_INT_PORTB 12 +#define MX1_GPIO_INT_PORTC 13 +#define MX1_LCDC_INT 14 +#define MX1_SIM_INT 15 +#define MX1_SIM_DATA_INT 16 +#define MX1_RTC_INT 17 +#define MX1_RTC_SAMINT 18 +#define MX1_UART2_MINT_PFERR 19 +#define MX1_UART2_MINT_RTS 20 +#define MX1_UART2_MINT_DTR 21 +#define MX1_UART2_MINT_UARTC 22 +#define MX1_UART2_MINT_TX 23 +#define MX1_UART2_MINT_RX 24 +#define MX1_UART1_MINT_PFERR 25 +#define MX1_UART1_MINT_RTS 26 +#define MX1_UART1_MINT_DTR 27 +#define MX1_UART1_MINT_UARTC 28 +#define MX1_UART1_MINT_TX 29 +#define MX1_UART1_MINT_RX 30 +#define MX1_VOICE_DAC_INT 31 +#define MX1_VOICE_ADC_INT 32 +#define MX1_PEN_DATA_INT 33 +#define MX1_PWM_INT 34 +#define MX1_SDHC_INT 35 +#define MX1_I2C_INT 39 +#define MX1_CSPI_INT 41 +#define MX1_SSI_TX_INT 42 +#define MX1_SSI_TX_ERR_INT 43 +#define MX1_SSI_RX_INT 44 +#define MX1_SSI_RX_ERR_INT 45 +#define MX1_TOUCH_INT 46 +#define MX1_USBD_INT0 47 +#define MX1_USBD_INT1 48 +#define MX1_USBD_INT2 49 +#define MX1_USBD_INT3 50 +#define MX1_USBD_INT4 51 +#define MX1_USBD_INT5 52 +#define MX1_USBD_INT6 53 +#define MX1_BTSYS_INT 55 +#define MX1_BTTIM_INT 56 +#define MX1_BTWUI_INT 57 +#define MX1_TIM2_INT 58 +#define MX1_TIM1_INT 59 +#define MX1_DMA_ERR 60 +#define MX1_DMA_INT 61 +#define MX1_GPIO_INT_PORTD 62 +#define MX1_WDT_INT 63 /* DMA */ -#define DMA_REQ_UART3_T 2 -#define DMA_REQ_UART3_R 3 -#define DMA_REQ_SSI2_T 4 -#define DMA_REQ_SSI2_R 5 -#define DMA_REQ_CSI_STAT 6 -#define DMA_REQ_CSI_R 7 -#define DMA_REQ_MSHC 8 -#define DMA_REQ_DSPA_DCT_DOUT 9 -#define DMA_REQ_DSPA_DCT_DIN 10 -#define DMA_REQ_DSPA_MAC 11 -#define DMA_REQ_EXT 12 -#define DMA_REQ_SDHC 13 -#define DMA_REQ_SPI1_R 14 -#define DMA_REQ_SPI1_T 15 -#define DMA_REQ_SSI_T 16 -#define DMA_REQ_SSI_R 17 -#define DMA_REQ_ASP_DAC 18 -#define DMA_REQ_ASP_ADC 19 -#define DMA_REQ_USP_EP(x) (20 + (x)) -#define DMA_REQ_SPI2_R 26 -#define DMA_REQ_SPI2_T 27 -#define DMA_REQ_UART2_T 28 -#define DMA_REQ_UART2_R 29 -#define DMA_REQ_UART1_T 30 -#define DMA_REQ_UART1_R 31 - -#endif /* __ASM_ARCH_MXC_MX1_H__ */ +#define MX1_DMA_REQ_UART3_T 2 +#define MX1_DMA_REQ_UART3_R 3 +#define MX1_DMA_REQ_SSI2_T 4 +#define MX1_DMA_REQ_SSI2_R 5 +#define MX1_DMA_REQ_CSI_STAT 6 +#define MX1_DMA_REQ_CSI_R 7 +#define MX1_DMA_REQ_MSHC 8 +#define MX1_DMA_REQ_DSPA_DCT_DOUT 9 +#define MX1_DMA_REQ_DSPA_DCT_DIN 10 +#define MX1_DMA_REQ_DSPA_MAC 11 +#define MX1_DMA_REQ_EXT 12 +#define MX1_DMA_REQ_SDHC 13 +#define MX1_DMA_REQ_SPI1_R 14 +#define MX1_DMA_REQ_SPI1_T 15 +#define MX1_DMA_REQ_SSI_T 16 +#define MX1_DMA_REQ_SSI_R 17 +#define MX1_DMA_REQ_ASP_DAC 18 +#define MX1_DMA_REQ_ASP_ADC 19 +#define MX1_DMA_REQ_USP_EP(x) (20 + (x)) +#define MX1_DMA_REQ_SPI2_R 26 +#define MX1_DMA_REQ_SPI2_T 27 +#define MX1_DMA_REQ_UART2_T 28 +#define MX1_DMA_REQ_UART2_R 29 +#define MX1_DMA_REQ_UART1_T 30 +#define MX1_DMA_REQ_UART1_R 31 + +/* + * This doesn't depend on IMX_NEEDS_DEPRECATED_SYMBOLS + * to not break drivers/usb/gadget/imx_udc. Should go + * away after this driver uses the new name. + */ +#define USBD_INT0 MX1_USBD_INT0 + +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS +/* these should go away */ +#define IMX_IO_PHYS MX1_IO_BASE_ADDR +#define IMX_IO_SIZE MX1_IO_SIZE +#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT +#define IMX_CS0_PHYS MX1_CS0_PHYS +#define IMX_CS0_SIZE MX1_CS0_SIZE +#define IMX_CS1_PHYS MX1_CS1_PHYS +#define IMX_CS1_SIZE MX1_CS1_SIZE +#define IMX_CS2_PHYS MX1_CS2_PHYS +#define IMX_CS2_SIZE MX1_CS2_SIZE +#define IMX_CS3_PHYS MX1_CS3_PHYS +#define IMX_CS3_SIZE MX1_CS3_SIZE +#define IMX_CS4_PHYS MX1_CS4_PHYS +#define IMX_CS4_SIZE MX1_CS4_SIZE +#define IMX_CS5_PHYS MX1_CS5_PHYS +#define IMX_CS5_SIZE MX1_CS5_SIZE +#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR +#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR +#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR +#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR +#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR +#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR +#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR +#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR +#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR +#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR +#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR +#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR +#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR +#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR +#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR +#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR +#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR +#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR +#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR +#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR +#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR +#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR +#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR +#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR +#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR +#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR +#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR +#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR +#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR +#define IO_ADDRESS(x) MX1_IO_ADDRESS(x) +#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x) +#define INT_SOFTINT MX1_INT_SOFTINT +#define CSI_INT MX1_CSI_INT +#define DSPA_MAC_INT MX1_DSPA_MAC_INT +#define DSPA_INT MX1_DSPA_INT +#define COMP_INT MX1_COMP_INT +#define MSHC_XINT MX1_MSHC_XINT +#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA +#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB +#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC +#define LCDC_INT MX1_LCDC_INT +#define SIM_INT MX1_SIM_INT +#define SIM_DATA_INT MX1_SIM_DATA_INT +#define RTC_INT MX1_RTC_INT +#define RTC_SAMINT MX1_RTC_SAMINT +#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR +#define UART2_MINT_RTS MX1_UART2_MINT_RTS +#define UART2_MINT_DTR MX1_UART2_MINT_DTR +#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC +#define UART2_MINT_TX MX1_UART2_MINT_TX +#define UART2_MINT_RX MX1_UART2_MINT_RX +#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR +#define UART1_MINT_RTS MX1_UART1_MINT_RTS +#define UART1_MINT_DTR MX1_UART1_MINT_DTR +#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC +#define UART1_MINT_TX MX1_UART1_MINT_TX +#define UART1_MINT_RX MX1_UART1_MINT_RX +#define VOICE_DAC_INT MX1_VOICE_DAC_INT +#define VOICE_ADC_INT MX1_VOICE_ADC_INT +#define PEN_DATA_INT MX1_PEN_DATA_INT +#define PWM_INT MX1_PWM_INT +#define SDHC_INT MX1_SDHC_INT +#define I2C_INT MX1_I2C_INT +#define CSPI_INT MX1_CSPI_INT +#define SSI_TX_INT MX1_SSI_TX_INT +#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT +#define SSI_RX_INT MX1_SSI_RX_INT +#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT +#define TOUCH_INT MX1_TOUCH_INT +#define USBD_INT1 MX1_USBD_INT1 +#define USBD_INT2 MX1_USBD_INT2 +#define USBD_INT3 MX1_USBD_INT3 +#define USBD_INT4 MX1_USBD_INT4 +#define USBD_INT5 MX1_USBD_INT5 +#define USBD_INT6 MX1_USBD_INT6 +#define BTSYS_INT MX1_BTSYS_INT +#define BTTIM_INT MX1_BTTIM_INT +#define BTWUI_INT MX1_BTWUI_INT +#define TIM2_INT MX1_TIM2_INT +#define TIM1_INT MX1_TIM1_INT +#define DMA_ERR MX1_DMA_ERR +#define DMA_INT MX1_DMA_INT +#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD +#define WDT_INT MX1_WDT_INT +#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T +#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R +#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T +#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R +#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT +#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R +#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC +#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT +#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN +#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC +#define DMA_REQ_EXT MX1_DMA_REQ_EXT +#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC +#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R +#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T +#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T +#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R +#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC +#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC +#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x) +#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R +#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T +#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T +#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R +#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T +#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R +#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */ + +#endif /* ifndef __MACH_MX1_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index bb297d8765a7..ed98b9c9f389 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h @@ -22,8 +22,8 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_MX21_H__ -#define __ASM_ARCH_MXC_MX21_H__ +#ifndef __MACH_MX21_H__ +#define __MACH_MX21_H__ #define MX21_AIPI_BASE_ADDR 0x10000000 #define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 @@ -92,6 +92,11 @@ #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ +#define MX21_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ + IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \ + IMX_IO_ADDRESS(x, MX21_X_MEMC)) + /* fixed interrupt numbers */ #define MX21_INT_CSPI3 6 #define MX21_INT_GPIO 8 @@ -179,6 +184,7 @@ #define MX21_DMA_REQ_CSI_STAT 30 #define MX21_DMA_REQ_CSI_RX 31 +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR #define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR @@ -211,5 +217,6 @@ #define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX #define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX #define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX +#endif -#endif /* __ASM_ARCH_MXC_MX21_H__ */ +#endif /* ifndef __MACH_MX21_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 854e2dc58481..4eb6e334bda5 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -22,27 +22,27 @@ #define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000) #define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000) -#define MX25_AIPS1_IO_ADDRESS(x) \ - (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT) -#define MX25_AIPS2_IO_ADDRESS(x) \ - (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT) -#define MX25_AVIC_IO_ADDRESS(x) \ - (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT) +#define MX25_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \ + IMX_IO_ADDRESS(x, MX25_AVIC)) -#define __in_range(addr, name) ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE) - -#define MX25_IO_ADDRESS(x) \ - (void __force __iomem *) \ - (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \ - __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) : \ - __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) : \ - 0xDEADBEEF) - -#define UART1_BASE_ADDR 0x43f90000 -#define UART2_BASE_ADDR 0x43f94000 +#define MX25_UART1_BASE_ADDR 0x43f90000 +#define MX25_UART2_BASE_ADDR 0x43f94000 #define MX25_FEC_BASE_ADDR 0x50038000 +#define MX25_NFC_BASE_ADDR 0xbb000000 +#define MX25_DRYICE_BASE_ADDR 0x53ffc000 +#define MX25_LCDC_BASE_ADDR 0x53fbc000 +#define MX25_INT_DRYICE 25 #define MX25_INT_FEC 57 +#define MX25_INT_NANDFC 33 +#define MX25_INT_LCDC 39 + +#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS) +#define UART1_BASE_ADDR MX25_UART1_BASE_ADDR +#define UART2_BASE_ADDR MX25_UART2_BASE_ADDR +#endif -#endif /* __MACH_MX25_H__ */ +#endif /* ifndef __MACH_MX25_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index e2ae19f51710..bae9cd75beee 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -21,8 +21,12 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_MX27_H__ -#define __ASM_ARCH_MXC_MX27_H__ +#ifndef __MACH_MX27_H__ +#define __MACH_MX27_H__ + +#ifndef __ASSEMBLER__ +#include <linux/io.h> +#endif #define MX27_AIPI_BASE_ADDR 0x10000000 #define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 @@ -109,11 +113,31 @@ #define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) #define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) +#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10) +#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs)) +#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) +#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) + #define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 /* IRAM */ #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ +#define MX27_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ + IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ + IMX_IO_ADDRESS(x, MX27_X_MEMC)) + +#ifndef __ASSEMBLER__ +static inline void mx27_setup_weimcs(size_t cs, + unsigned upper, unsigned lower, unsigned addional) +{ + __raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs))); + __raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs))); + __raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs))); +} +#endif + /* fixed interrupt numbers */ #define MX27_INT_I2C2 1 #define MX27_INT_GPT6 2 @@ -225,6 +249,7 @@ extern int mx27_revision(void); #endif +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR #define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR @@ -292,5 +317,6 @@ extern int mx27_revision(void); #define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX #define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 #define DMA_REQ_NFC MX27_DMA_REQ_NFC +#endif -#endif /* __ASM_ARCH_MXC_MX27_H__ */ +#endif /* ifndef __MACH_MX27_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index f2eaf140ed02..afb895a0b5b8 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h @@ -20,8 +20,8 @@ * MA 02110-1301, USA. */ -#ifndef __ASM_ARCH_MXC_MX2x_H__ -#define __ASM_ARCH_MXC_MX2x_H__ +#ifndef __MACH_MX2x_H__ +#define __MACH_MX2x_H__ /* The following addresses are common between i.MX21 and i.MX27 */ @@ -176,6 +176,7 @@ #define MX2x_DMA_REQ_CSI_STAT 30 #define MX2x_DMA_REQ_CSI_RX 31 +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR #define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT @@ -287,5 +288,6 @@ #define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX #define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT #define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX +#endif -#endif /* __ASM_ARCH_MXC_MX2x_H__ */ +#endif /* ifndef __MACH_MX2x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index b8b47d139eb5..fb90e119c2b5 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h @@ -1,3 +1,10 @@ +#ifndef __MACH_MX31_H__ +#define __MACH_MX31_H__ + +#ifndef __ASSEMBLER__ +#include <linux/io.h> +#endif + /* * IRAM */ @@ -107,8 +114,30 @@ #define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) #define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR +#define MX31_WEIM_CSCRx_BASE_ADDR(cs) (MX31_WEIM_BASE_ADDR + (cs) * 0x10) +#define MX31_WEIM_CSCRxU(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs)) +#define MX31_WEIM_CSCRxL(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x4) +#define MX31_WEIM_CSCRxA(cs) (MX31_WEIM_CSCRx_BASE_ADDR(cs) + 0x8) + #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 +#define MX31_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \ + IMX_IO_ADDRESS(x, MX31_AVIC) ?: \ + IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \ + IMX_IO_ADDRESS(x, MX31_SPBA0)) + +#ifndef __ASSEMBLER__ +static inline void mx31_setup_weimcs(size_t cs, + unsigned upper, unsigned lower, unsigned addional) +{ + __raw_writel(upper, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(cs))); + __raw_writel(lower, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(cs))); + __raw_writel(addional, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(cs))); +} +#endif + #define MX31_INT_I2C3 3 #define MX31_INT_I2C2 4 #define MX31_INT_MPEG4_ENCODER 5 @@ -186,6 +215,7 @@ #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 #define MX31_SYSTEM_REV_NUM 3 +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR @@ -216,3 +246,6 @@ #define MXC_INT_UART5 MX31_INT_UART5 #define MXC_INT_CCM MX31_INT_CCM #define MXC_INT_PCMCIA MX31_INT_PCMCIA +#endif + +#endif /* ifndef __MACH_MX31_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index af871bce35b6..526a55842ae5 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h @@ -1,3 +1,5 @@ +#ifndef __MACH_MX35_H__ +#define __MACH_MX35_H__ /* * IRAM */ @@ -104,6 +106,13 @@ #define MX35_NFC_BASE_ADDR 0xbb000000 #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 +#define MX35_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \ + IMX_IO_ADDRESS(x, MX35_AVIC) ?: \ + IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \ + IMX_IO_ADDRESS(x, MX35_SPBA0)) + /* * Interrupt numbers */ @@ -180,6 +189,7 @@ #define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 #define MX35_SYSTEM_REV_NUM 3 +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR #define MXC_INT_OWIRE MX35_INT_OWIRE @@ -195,3 +205,6 @@ #define MXC_INT_MLB MX35_INT_MLB #define MXC_INT_SPDIF MX35_INT_SPDIF #define MXC_INT_FEC MX35_INT_FEC +#endif + +#endif /* ifndef __MACH_MX35_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index be69272407ad..7a356de385f5 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h @@ -8,8 +8,8 @@ * published by the Free Software Foundation. */ -#ifndef __ASM_ARCH_MXC_MX31_H__ -#define __ASM_ARCH_MXC_MX31_H__ +#ifndef __MACH_MX3x_H__ +#define __MACH_MX3x_H__ /* * MX31 memory map: @@ -269,6 +269,7 @@ static inline int mx31_revision(void) } #endif +#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS /* these should go away */ #define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR #define L2CC_SIZE MX3x_L2CC_SIZE @@ -401,5 +402,6 @@ static inline int mx31_revision(void) #define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 #define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN #define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM +#endif -#endif /* __ASM_ARCH_MXC_MX31_H__ */ +#endif /* ifndef __MACH_MX3x_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h new file mode 100644 index 000000000000..771532b6b4a6 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx51.h @@ -0,0 +1,454 @@ +#ifndef __ASM_ARCH_MXC_MX51_H__ +#define __ASM_ARCH_MXC_MX51_H__ + +/* + * MX51 memory map: + * + * + * Virt Phys Size What + * --------------------------------------------------------------------------- + * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM) + * 30000000 256M GPU + * 40000000 512M IPU + * FA200000 60000000 1M DEBUG + * FB100000 70000000 1M SPBA 0 + * FB000000 73F00000 1M AIPS 1 + * FB200000 83F00000 1M AIPS 2 + * FA100000 8FFFC000 16K TZIC (interrupt controller) + * 90000000 256M CSD0 SDRAM/DDR + * A0000000 256M CSD1 SDRAM/DDR + * B0000000 128M CS0 Flash + * B8000000 128M CS1 Flash + * C0000000 128M CS2 Flash + * C8000000 64M CS3 Flash + * CC000000 32M CS4 SRAM + * CE000000 32M CS5 SRAM + * F9000000 CFFF0000 64K NFC (NAND Flash AXI) + * + */ + +/* + * IRAM + */ +#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ +#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000 +#define MX51_IRAM_PARTITIONS 16 +#define MX51_IRAM_PARTITIONS_TO1 12 +#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ + +/* + * NFC + */ +#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ +#define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000 +#define MX51_NFC_AXI_SIZE SZ_64K + +/* + * Graphics Memory of GPU + */ +#define MX51_GPU_BASE_ADDR 0x20000000 +#define MX51_GPU2D_BASE_ADDR 0xD0000000 + +#define MX51_TZIC_BASE_ADDR 0x8FFFC000 +#define MX51_TZIC_BASE_ADDR_VIRT 0xFA100000 +#define MX51_TZIC_SIZE SZ_16K + +#define MX51_DEBUG_BASE_ADDR 0x60000000 +#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 +#define MX51_DEBUG_SIZE SZ_1M +#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000) +#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000) +#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000) +#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000) +#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000) +#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000) +#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000) +#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define MX51_SPBA0_BASE_ADDR 0x70000000 +#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000 +#define MX51_SPBA0_SIZE SZ_1M + +#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) +#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) +#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) +#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) +#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) +#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) +#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) +#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) +#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) +#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) +#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000) +#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) + +/* + * defines for SPBA modules + */ +#define MX51_SPBA_SDHC1 0x04 +#define MX51_SPBA_SDHC2 0x08 +#define MX51_SPBA_UART3 0x0C +#define MX51_SPBA_CSPI1 0x10 +#define MX51_SPBA_SSI2 0x14 +#define MX51_SPBA_SDHC3 0x20 +#define MX51_SPBA_SDHC4 0x24 +#define MX51_SPBA_SPDIF 0x28 +#define MX51_SPBA_ATA 0x30 +#define MX51_SPBA_SLIM 0x34 +#define MX51_SPBA_HSI2C 0x38 +#define MX51_SPBA_CTRL 0x3C + +/* + * AIPS 1 + */ +#define MX51_AIPS1_BASE_ADDR 0x73F00000 +#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000 +#define MX51_AIPS1_SIZE SZ_1M + +#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000) +#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000) +#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000) +#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000) +#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000) +#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000) +#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000) +#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000) +#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000) +#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000) +#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000) +#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000) +#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000) +#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000) +#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000) +#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000) +#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000) +#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000) +#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000) +#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000) + +/* + * Defines for modules using static and dynamic DMA channels + */ +#define MX51_MXC_DMA_CHANNEL_IRAM 30 +#define MX51_MXC_DMA_CHANNEL_SPDIF_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_UART3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_MMC1 MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_MMC2 MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_SSI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_SSI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_SSI2_RX MXC_DMA_DYNAMIC_CHANNEL +#ifdef CONFIG_SDMA_IRAM +#define MX51_MXC_DMA_CHANNEL_SSI2_TX (MX51_MXC_DMA_CHANNEL_IRAM + 1) +#else /*CONFIG_SDMA_IRAM */ +#define MX51_MXC_DMA_CHANNEL_SSI2_TX MXC_DMA_DYNAMIC_CHANNEL +#endif /*CONFIG_SDMA_IRAM */ +#define MX51_MXC_DMA_CHANNEL_CSPI1_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI1_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI2_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI2_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI3_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_CSPI3_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_ATA_RX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL +#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL + +/* + * AIPS 2 + */ +#define MX51_AIPS2_BASE_ADDR 0x83F00000 +#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000 +#define MX51_AIPS2_SIZE SZ_1M + +#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000) +#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000) +#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000) +#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000) +#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000) +#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000) +#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000) +#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000) +#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000) +#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000) +#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000) +#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000) +#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000) +#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000) +#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000) +#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000) +#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000) +#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000) +#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000) +#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000) +#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000) +#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000) +#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000) +#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00) +#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000) +#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000) +#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000) +#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000) +#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000) +#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000) +#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000) +#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000) + +/* + * Memory regions and CS + */ +#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 +#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 +#define MX51_CSD0_BASE_ADDR 0x90000000 +#define MX51_CSD1_BASE_ADDR 0xA0000000 +#define MX51_CS0_BASE_ADDR 0xB0000000 +#define MX51_CS1_BASE_ADDR 0xB8000000 +#define MX51_CS2_BASE_ADDR 0xC0000000 +#define MX51_CS3_BASE_ADDR 0xC8000000 +#define MX51_CS4_BASE_ADDR 0xCC000000 +#define MX51_CS5_BASE_ADDR 0xCE000000 + +/* Does given address belongs to the specified memory region? */ +#define ADDRESS_IN_REGION(addr, start, size) \ + (((addr) >= (start)) && ((addr) < (start)+(size))) + +/* Does given address belongs to the specified named `module'? */ +#define MX51_IS_MODULE(addr, module) \ + ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \ + MX51_ ## module ## _SIZE) +/* + * This macro defines the physical to virtual address mapping for all the + * peripheral modules. It is used by passing in the physical address as x + * and returning the virtual address. If the physical address is not mapped, + * it returns 0xDEADBEEF + */ + +#define MX51_IO_ADDRESS(x) \ + (void __iomem *) \ + (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, TZIC) ? MX51_TZIC_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ + MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \ + 0xDEADBEEF) + +/* + * define the address mapping macros: in physical address order + */ +#define MX51_IRAM_IO_ADDRESS(x) \ + (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT) + +#define MX51_TZIC_IO_ADDRESS(x) \ + (((x) - MX51_TZIC_BASE_ADDR) + MX51_TZIC_BASE_ADDR_VIRT) + +#define MX51_DEBUG_IO_ADDRESS(x) \ + (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT) + +#define MX51_SPBA0_IO_ADDRESS(x) \ + (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT) + +#define MX51_AIPS1_IO_ADDRESS(x) \ + (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT) + +#define MX51_AIPS2_IO_ADDRESS(x) \ + (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT) + +#define MX51_NFC_AXI_IO_ADDRESS(x) \ + (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT) + +#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 + +/* + * DMA request assignments + */ +#define MX51_DMA_REQ_SSI3_TX1 47 +#define MX51_DMA_REQ_SSI3_RX1 46 +#define MX51_DMA_REQ_SPDIF 45 +#define MX51_DMA_REQ_UART3_TX 44 +#define MX51_DMA_REQ_UART3_RX 43 +#define MX51_DMA_REQ_SLIM_B_TX 42 +#define MX51_DMA_REQ_SDHC4 41 +#define MX51_DMA_REQ_SDHC3 40 +#define MX51_DMA_REQ_CSPI_TX 39 +#define MX51_DMA_REQ_CSPI_RX 38 +#define MX51_DMA_REQ_SSI3_TX2 37 +#define MX51_DMA_REQ_IPU 36 +#define MX51_DMA_REQ_SSI3_RX2 35 +#define MX51_DMA_REQ_EPIT2 34 +#define MX51_DMA_REQ_CTI2_1 33 +#define MX51_DMA_REQ_EMI_WR 32 +#define MX51_DMA_REQ_CTI2_0 31 +#define MX51_DMA_REQ_EMI_RD 30 +#define MX51_DMA_REQ_SSI1_TX1 29 +#define MX51_DMA_REQ_SSI1_RX1 28 +#define MX51_DMA_REQ_SSI1_TX2 27 +#define MX51_DMA_REQ_SSI1_RX2 26 +#define MX51_DMA_REQ_SSI2_TX1 25 +#define MX51_DMA_REQ_SSI2_RX1 24 +#define MX51_DMA_REQ_SSI2_TX2 23 +#define MX51_DMA_REQ_SSI2_RX2 22 +#define MX51_DMA_REQ_SDHC2 21 +#define MX51_DMA_REQ_SDHC1 20 +#define MX51_DMA_REQ_UART1_TX 19 +#define MX51_DMA_REQ_UART1_RX 18 +#define MX51_DMA_REQ_UART2_TX 17 +#define MX51_DMA_REQ_UART2_RX 16 +#define MX51_DMA_REQ_GPU 15 +#define MX51_DMA_REQ_EXTREQ1 14 +#define MX51_DMA_REQ_FIRI_TX 13 +#define MX51_DMA_REQ_FIRI_RX 12 +#define MX51_DMA_REQ_HS_I2C_RX 11 +#define MX51_DMA_REQ_HS_I2C_TX 10 +#define MX51_DMA_REQ_CSPI2_TX 9 +#define MX51_DMA_REQ_CSPI2_RX 8 +#define MX51_DMA_REQ_CSPI1_TX 7 +#define MX51_DMA_REQ_CSPI1_RX 6 +#define MX51_DMA_REQ_SLIM_B 5 +#define MX51_DMA_REQ_ATA_TX_END 4 +#define MX51_DMA_REQ_ATA_TX 3 +#define MX51_DMA_REQ_ATA_RX 2 +#define MX51_DMA_REQ_GPC 1 +#define MX51_DMA_REQ_VPU 0 + +/* + * Interrupt numbers + */ +#define MX51_MXC_INT_BASE 0 +#define MX51_MXC_INT_RESV0 0 +#define MX51_MXC_INT_MMC_SDHC1 1 +#define MX51_MXC_INT_MMC_SDHC2 2 +#define MX51_MXC_INT_MMC_SDHC3 3 +#define MX51_MXC_INT_MMC_SDHC4 4 +#define MX51_MXC_INT_RESV5 5 +#define MX51_MXC_INT_SDMA 6 +#define MX51_MXC_INT_IOMUX 7 +#define MX51_MXC_INT_NFC 8 +#define MX51_MXC_INT_VPU 9 +#define MX51_MXC_INT_IPU_ERR 10 +#define MX51_MXC_INT_IPU_SYN 11 +#define MX51_MXC_INT_GPU 12 +#define MX51_MXC_INT_RESV13 13 +#define MX51_MXC_INT_USB_H1 14 +#define MX51_MXC_INT_EMI 15 +#define MX51_MXC_INT_USB_H2 16 +#define MX51_MXC_INT_USB_H3 17 +#define MX51_MXC_INT_USB_OTG 18 +#define MX51_MXC_INT_SAHARA_H0 19 +#define MX51_MXC_INT_SAHARA_H1 20 +#define MX51_MXC_INT_SCC_SMN 21 +#define MX51_MXC_INT_SCC_STZ 22 +#define MX51_MXC_INT_SCC_SCM 23 +#define MX51_MXC_INT_SRTC_NTZ 24 +#define MX51_MXC_INT_SRTC_TZ 25 +#define MX51_MXC_INT_RTIC 26 +#define MX51_MXC_INT_CSU 27 +#define MX51_MXC_INT_SLIM_B 28 +#define MX51_MXC_INT_SSI1 29 +#define MX51_MXC_INT_SSI2 30 +#define MX51_MXC_INT_UART1 31 +#define MX51_MXC_INT_UART2 32 +#define MX51_MXC_INT_UART3 33 +#define MX51_MXC_INT_RESV34 34 +#define MX51_MXC_INT_RESV35 35 +#define MX51_MXC_INT_CSPI1 36 +#define MX51_MXC_INT_CSPI2 37 +#define MX51_MXC_INT_CSPI 38 +#define MX51_MXC_INT_GPT 39 +#define MX51_MXC_INT_EPIT1 40 +#define MX51_MXC_INT_EPIT2 41 +#define MX51_MXC_INT_GPIO1_INT7 42 +#define MX51_MXC_INT_GPIO1_INT6 43 +#define MX51_MXC_INT_GPIO1_INT5 44 +#define MX51_MXC_INT_GPIO1_INT4 45 +#define MX51_MXC_INT_GPIO1_INT3 46 +#define MX51_MXC_INT_GPIO1_INT2 47 +#define MX51_MXC_INT_GPIO1_INT1 48 +#define MX51_MXC_INT_GPIO1_INT0 49 +#define MX51_MXC_INT_GPIO1_LOW 50 +#define MX51_MXC_INT_GPIO1_HIGH 51 +#define MX51_MXC_INT_GPIO2_LOW 52 +#define MX51_MXC_INT_GPIO2_HIGH 53 +#define MX51_MXC_INT_GPIO3_LOW 54 +#define MX51_MXC_INT_GPIO3_HIGH 55 +#define MX51_MXC_INT_GPIO4_LOW 56 +#define MX51_MXC_INT_GPIO4_HIGH 57 +#define MX51_MXC_INT_WDOG1 58 +#define MX51_MXC_INT_WDOG2 59 +#define MX51_MXC_INT_KPP 60 +#define MX51_MXC_INT_PWM1 61 +#define MX51_MXC_INT_I2C1 62 +#define MX51_MXC_INT_I2C2 63 +#define MX51_MXC_INT_HS_I2C 64 +#define MX51_MXC_INT_RESV65 65 +#define MX51_MXC_INT_RESV66 66 +#define MX51_MXC_INT_SIM_IPB 67 +#define MX51_MXC_INT_SIM_DAT 68 +#define MX51_MXC_INT_IIM 69 +#define MX51_MXC_INT_ATA 70 +#define MX51_MXC_INT_CCM1 71 +#define MX51_MXC_INT_CCM2 72 +#define MX51_MXC_INT_GPC1 73 +#define MX51_MXC_INT_GPC2 74 +#define MX51_MXC_INT_SRC 75 +#define MX51_MXC_INT_NM 76 +#define MX51_MXC_INT_PMU 77 +#define MX51_MXC_INT_CTI_IRQ 78 +#define MX51_MXC_INT_CTI1_TG0 79 +#define MX51_MXC_INT_CTI1_TG1 80 +#define MX51_MXC_INT_MCG_ERR 81 +#define MX51_MXC_INT_MCG_TMR 82 +#define MX51_MXC_INT_MCG_FUNC 83 +#define MX51_MXC_INT_GPU2_IRQ 84 +#define MX51_MXC_INT_GPU2_BUSY 85 +#define MX51_MXC_INT_RESV86 86 +#define MX51_MXC_INT_FEC 87 +#define MX51_MXC_INT_OWIRE 88 +#define MX51_MXC_INT_CTI1_TG2 89 +#define MX51_MXC_INT_SJC 90 +#define MX51_MXC_INT_SPDIF 91 +#define MX51_MXC_INT_TVE 92 +#define MX51_MXC_INT_FIRI 93 +#define MX51_MXC_INT_PWM2 94 +#define MX51_MXC_INT_SLIM_EXP 95 +#define MX51_MXC_INT_SSI3 96 +#define MX51_MXC_INT_EMI_BOOT 97 +#define MX51_MXC_INT_CTI1_TG3 98 +#define MX51_MXC_INT_SMC_RX 99 +#define MX51_MXC_INT_VPU_IDLE 100 +#define MX51_MXC_INT_EMI_NFC 101 +#define MX51_MXC_INT_GPU_IDLE 102 + +/* silicon revisions specific to i.MX51 */ +#define MX51_CHIP_REV_1_0 0x10 +#define MX51_CHIP_REV_1_1 0x11 +#define MX51_CHIP_REV_1_2 0x12 +#define MX51_CHIP_REV_1_3 0x13 +#define MX51_CHIP_REV_2_0 0x20 +#define MX51_CHIP_REV_2_1 0x21 +#define MX51_CHIP_REV_2_2 0x22 +#define MX51_CHIP_REV_2_3 0x23 +#define MX51_CHIP_REV_3_0 0x30 +#define MX51_CHIP_REV_3_1 0x31 +#define MX51_CHIP_REV_3_2 0x32 + +/* Mandatory defines used globally */ + +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) + +extern unsigned int system_rev; + +static inline unsigned int mx51_revision(void) +{ + return system_rev; +} +#endif + +#endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 51990536b845..a790bf212972 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -30,6 +30,7 @@ #define MXC_CPU_MX27 27 #define MXC_CPU_MX31 31 #define MXC_CPU_MX35 35 +#define MXC_CPU_MX51 51 #define MXC_CPU_MXC91231 91231 #ifndef __ASSEMBLY__ @@ -108,6 +109,18 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx35() (0) #endif +#ifdef CONFIG_ARCH_MX5 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX51 +# endif +# define cpu_is_mx51() (mxc_cpu_type == MXC_CPU_MX51) +#else +# define cpu_is_mx51() (0) +#endif + #ifdef CONFIG_ARCH_MXC91231 # ifdef mxc_cpu_type # undef mxc_cpu_type @@ -121,9 +134,10 @@ extern unsigned int __mxc_cpu_type; #endif #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) -#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10) -#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4) -#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) +/* These are deprecated, use mx[23][157]_setup_weimcs instead. */ +#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10)) +#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4)) +#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8)) #endif #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231()) diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h index 81484d1ef232..5182b986b785 100644 --- a/arch/arm/plat-mxc/include/mach/mxc91231.h +++ b/arch/arm/plat-mxc/include/mach/mxc91231.h @@ -184,60 +184,22 @@ #define MXC91231_CS4_BASE_ADDR 0xB4000000 #define MXC91231_CS5_BASE_ADDR 0xB6000000 -/* Is given address belongs to the specified memory region? */ -#define ADDRESS_IN_REGION(addr, start, size) \ - (((addr) >= (start)) && ((addr) < (start)+(size))) - -/* Is given address belongs to the specified named `module'? */ -#define MXC91231_IS_MODULE(addr, module) \ - ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \ - MXC91231_ ## module ## _SIZE) /* * This macro defines the physical to virtual address mapping for all the * peripheral modules. It is used by passing in the physical address as x * and returning the virtual address. If the physical address is not mapped, - * it returns 0xDEADBEEF - */ - -#define MXC91231_IO_ADDRESS(x) \ - (void __iomem *) \ - (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \ - MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \ - 0xDEADBEEF) - - -/* - * define the address mapping macros: in physical address order + * it returns 0. */ -#define MXC91231_L2CC_IO_ADDRESS(x) \ - (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT) - -#define MXC91231_AIPS1_IO_ADDRESS(x) \ - (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT) - -#define MXC91231_SPBA0_IO_ADDRESS(x) \ - (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT) - -#define MXC91231_SPBA1_IO_ADDRESS(x) \ - (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT) - -#define MXC91231_AIPS2_IO_ADDRESS(x) \ - (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT) - -#define MXC91231_ROMP_IO_ADDRESS(x) \ - (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT) - -#define MXC91231_AVIC_IO_ADDRESS(x) \ - (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT) -#define MXC91231_X_MEMC_IO_ADDRESS(x) \ - (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT) +#define MXC91231_IO_ADDRESS(x) ( \ + IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \ + IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \ + IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \ + IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \ + IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \ + IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \ + IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \ + IMX_IO_ADDRESS(x, MXC91231_AIPS2)) /* * Interrupt numbers diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 8f796239393e..4b9b8368c0c0 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h @@ -22,6 +22,10 @@ #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) #define MXC_EHCI_TTL_ENABLED (1 << 6) +#define MXC_EHCI_INTERNAL_PHY (1 << 7) +#define MXC_EHCI_IPPUE_DOWN (1 << 8) +#define MXC_EHCI_IPPUE_UP (1 << 9) + struct mxc_usbh_platform_data { int (*init)(struct platform_device *pdev); int (*exit)(struct platform_device *pdev); diff --git a/arch/arm/plat-mxc/include/mach/ssi.h b/arch/arm/plat-mxc/include/mach/ssi.h new file mode 100644 index 000000000000..c34ded523f10 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/ssi.h @@ -0,0 +1,18 @@ +#ifndef __MACH_SSI_H +#define __MACH_SSI_H + +struct snd_ac97; + +extern unsigned char imx_ssi_fiq_start, imx_ssi_fiq_end; +extern unsigned long imx_ssi_fiq_base, imx_ssi_fiq_tx_buffer, imx_ssi_fiq_rx_buffer; + +struct imx_ssi_platform_data { + unsigned int flags; +#define IMX_SSI_DMA (1 << 0) +#define IMX_SSI_USE_AC97 (1 << 1) + void (*ac97_reset) (struct snd_ac97 *ac97); + void (*ac97_warm_reset)(struct snd_ac97 *ac97); +}; + +#endif /* __MACH_SSI_H */ + diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h index 527a6c24788e..024416ed11cd 100644 --- a/arch/arm/plat-mxc/include/mach/timex.h +++ b/arch/arm/plat-mxc/include/mach/timex.h @@ -28,6 +28,8 @@ #define CLOCK_TICK_RATE 16625000 #elif defined CONFIG_ARCH_MX25 #define CLOCK_TICK_RATE 16000000 +#elif defined CONFIG_ARCH_MX5 +#define CLOCK_TICK_RATE 8000000 #elif defined CONFIG_ARCH_MXC91231 #define CLOCK_TICK_RATE 13000000 #endif diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index d49384cb1e97..52e476a150ca 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -1,8 +1,6 @@ /* * arch/arm/plat-mxc/include/mach/uncompress.h * - * - * * Copyright (C) 1999 ARM Limited * Copyright (C) Shane Nay ([email protected]) * @@ -25,7 +23,6 @@ #define __MXC_BOOT_UNCOMPRESS -#include <mach/hardware.h> #include <asm/mach-types.h> static unsigned long uart_base; diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c deleted file mode 100644 index a37163ce280b..000000000000 --- a/arch/arm/plat-mxc/iomux-mx1-mx2.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * arch/arm/mach-mxc/generic.c - * - * author: Sascha Hauer - * Created: april 20th, 2004 - * Copyright: Synertronixx GmbH - * - * Common code for i.MX machines - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <linux/errno.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/string.h> -#include <linux/gpio.h> - -#include <mach/hardware.h> -#include <asm/mach/map.h> -#include <mach/iomux.h> - -void mxc_gpio_mode(int gpio_mode) -{ - unsigned int pin = gpio_mode & GPIO_PIN_MASK; - unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; - unsigned int tmp; - - /* Pullup enable */ - tmp = __raw_readl(VA_GPIO_BASE + MXC_PUEN(port)); - if (gpio_mode & GPIO_PUEN) - tmp |= (1 << pin); - else - tmp &= ~(1 << pin); - __raw_writel(tmp, VA_GPIO_BASE + MXC_PUEN(port)); - - /* Data direction */ - tmp = __raw_readl(VA_GPIO_BASE + MXC_DDIR(port)); - if (gpio_mode & GPIO_OUT) - tmp |= 1 << pin; - else - tmp &= ~(1 << pin); - __raw_writel(tmp, VA_GPIO_BASE + MXC_DDIR(port)); - - /* Primary / alternate function */ - tmp = __raw_readl(VA_GPIO_BASE + MXC_GPR(port)); - if (gpio_mode & GPIO_AF) - tmp |= (1 << pin); - else - tmp &= ~(1 << pin); - __raw_writel(tmp, VA_GPIO_BASE + MXC_GPR(port)); - - /* use as gpio? */ - tmp = __raw_readl(VA_GPIO_BASE + MXC_GIUS(port)); - if (gpio_mode & (GPIO_PF | GPIO_AF)) - tmp &= ~(1 << pin); - else - tmp |= (1 << pin); - __raw_writel(tmp, VA_GPIO_BASE + MXC_GIUS(port)); - - if (pin < 16) { - tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR1(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR1(port)); - - tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA1(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2); - __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA1(port)); - - tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB1(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2); - __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB1(port)); - } else { - pin -= 16; - - tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR2(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= (ocr << (pin * 2)); - __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR2(port)); - - tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA2(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2); - __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA2(port)); - - tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB2(port)); - tmp &= ~(3 << (pin * 2)); - tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2); - __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB2(port)); - } -} -EXPORT_SYMBOL(mxc_gpio_mode); - -int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, - const char *label) -{ - const int *p = pin_list; - int i; - unsigned gpio; - unsigned mode; - int ret = -EINVAL; - - for (i = 0; i < count; i++) { - gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); - mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK); - - if (gpio >= (GPIO_PORT_MAX + 1) * 32) - goto setup_error; - - ret = gpio_request(gpio, label); - if (ret) - goto setup_error; - - mxc_gpio_mode(gpio | mode); - - p++; - } - return 0; - -setup_error: - mxc_gpio_release_multiple_pins(pin_list, i); - return ret; -} -EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); - -void mxc_gpio_release_multiple_pins(const int *pin_list, int count) -{ - const int *p = pin_list; - int i; - - for (i = 0; i < count; i++) { - unsigned gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK); - gpio_free(gpio); - p++; - } - -} -EXPORT_SYMBOL(mxc_gpio_release_multiple_pins); - diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c new file mode 100644 index 000000000000..960a02cbcbaf --- /dev/null +++ b/arch/arm/plat-mxc/iomux-v1.c @@ -0,0 +1,238 @@ +/* + * arch/arm/plat-mxc/iomux-v1.c + * + * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH + * Copyright (C) 2009 Uwe Kleine-Koenig, Pengutronix + * + * Common code for i.MX1, i.MX21 and i.MX27 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/errno.h> +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/string.h> +#include <linux/gpio.h> + +#include <mach/hardware.h> +#include <asm/mach/map.h> +#include <mach/iomux-v1.h> + +static void __iomem *imx_iomuxv1_baseaddr; +static unsigned imx_iomuxv1_numports; + +static inline unsigned long imx_iomuxv1_readl(unsigned offset) +{ + return __raw_readl(imx_iomuxv1_baseaddr + offset); +} + +static inline void imx_iomuxv1_writel(unsigned long val, unsigned offset) +{ + __raw_writel(val, imx_iomuxv1_baseaddr + offset); +} + +static inline void imx_iomuxv1_rmwl(unsigned offset, + unsigned long mask, unsigned long value) +{ + unsigned long reg = imx_iomuxv1_readl(offset); + + reg &= ~mask; + reg |= value; + + imx_iomuxv1_writel(reg, offset); +} + +static inline void imx_iomuxv1_set_puen( + unsigned int port, unsigned int pin, int on) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0); +} + +static inline void imx_iomuxv1_set_ddir( + unsigned int port, unsigned int pin, int out) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0); +} + +static inline void imx_iomuxv1_set_gpr( + unsigned int port, unsigned int pin, int af) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0); +} + +static inline void imx_iomuxv1_set_gius( + unsigned int port, unsigned int pin, int inuse) +{ + unsigned long mask = 1 << pin; + + imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0); +} + +static inline void imx_iomuxv1_set_ocr( + unsigned int port, unsigned int pin, unsigned int ocr) +{ + unsigned long shift = (pin & 0xf) << 1; + unsigned long mask = 3 << shift; + unsigned long value = ocr << shift; + unsigned long offset = pin < 16 ? MXC_OCR1(port) : MXC_OCR2(port); + + imx_iomuxv1_rmwl(offset, mask, value); +} + +static inline void imx_iomuxv1_set_iconfa( + unsigned int port, unsigned int pin, unsigned int aout) +{ + unsigned long shift = (pin & 0xf) << 1; + unsigned long mask = 3 << shift; + unsigned long value = aout << shift; + unsigned long offset = pin < 16 ? MXC_ICONFA1(port) : MXC_ICONFA2(port); + + imx_iomuxv1_rmwl(offset, mask, value); +} + +static inline void imx_iomuxv1_set_iconfb( + unsigned int port, unsigned int pin, unsigned int bout) +{ + unsigned long shift = (pin & 0xf) << 1; + unsigned long mask = 3 << shift; + unsigned long value = bout << shift; + unsigned long offset = pin < 16 ? MXC_ICONFB1(port) : MXC_ICONFB2(port); + + imx_iomuxv1_rmwl(offset, mask, value); +} + +int mxc_gpio_mode(int gpio_mode) +{ + unsigned int pin = gpio_mode & GPIO_PIN_MASK; + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; + unsigned int aout = (gpio_mode >> GPIO_AOUT_SHIFT) & 3; + unsigned int bout = (gpio_mode >> GPIO_BOUT_SHIFT) & 3; + + if (port >= imx_iomuxv1_numports) + return -EINVAL; + + /* Pullup enable */ + imx_iomuxv1_set_puen(port, pin, gpio_mode & GPIO_PUEN); + + /* Data direction */ + imx_iomuxv1_set_ddir(port, pin, gpio_mode & GPIO_OUT); + + /* Primary / alternate function */ + imx_iomuxv1_set_gpr(port, pin, gpio_mode & GPIO_AF); + + /* use as gpio? */ + imx_iomuxv1_set_gius(port, pin, !(gpio_mode & (GPIO_PF | GPIO_AF))); + + imx_iomuxv1_set_ocr(port, pin, ocr); + + imx_iomuxv1_set_iconfa(port, pin, aout); + + imx_iomuxv1_set_iconfb(port, pin, bout); + + return 0; +} +EXPORT_SYMBOL(mxc_gpio_mode); + +static int imx_iomuxv1_setup_multiple(const int *list, unsigned count) +{ + size_t i; + int ret; + + for (i = 0; i < count; ++i) { + ret = mxc_gpio_mode(list[i]); + + if (ret) + return ret; + } + + return ret; +} + +int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, + const char *label) +{ + size_t i; + int ret; + + for (i = 0; i < count; ++i) { + unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK); + + ret = gpio_request(gpio, label); + if (ret) + goto err_gpio_request; + } + + ret = imx_iomuxv1_setup_multiple(pin_list, count); + if (ret) + goto err_setup; + + return 0; + +err_setup: + BUG_ON(i != count); + +err_gpio_request: + mxc_gpio_release_multiple_pins(pin_list, i); + + return ret; +} +EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins); + +void mxc_gpio_release_multiple_pins(const int *pin_list, int count) +{ + size_t i; + + for (i = 0; i < count; ++i) { + unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK); + + gpio_free(gpio); + } +} +EXPORT_SYMBOL(mxc_gpio_release_multiple_pins); + +static int imx_iomuxv1_init(void) +{ +#ifdef CONFIG_ARCH_MX1 + if (cpu_is_mx1()) { + imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR); + imx_iomuxv1_numports = MX1_NUM_GPIO_PORT; + } else +#endif +#ifdef CONFIG_MACH_MX21 + if (cpu_is_mx21()) { + imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR); + imx_iomuxv1_numports = MX21_NUM_GPIO_PORT; + } else +#endif +#ifdef CONFIG_MACH_MX27 + if (cpu_is_mx27()) { + imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR); + imx_iomuxv1_numports = MX27_NUM_GPIO_PORT; + } else +#endif + return -ENODEV; + + return 0; +} +pure_initcall(imx_iomuxv1_init); diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 844567ee35fe..c1ce51abdba6 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -30,9 +30,15 @@ #include <asm/mach/time.h> #include <mach/common.h> +/* + * There are 2 versions of the timer hardware on Freescale MXC hardware. + * Version 1: MX1/MXL, MX21, MX27. + * Version 2: MX25, MX31, MX35, MX37, MX51 + */ + /* defines common for all i.MX */ #define MXC_TCTL 0x00 -#define MXC_TCTL_TEN (1 << 0) +#define MXC_TCTL_TEN (1 << 0) /* Enable module */ #define MXC_TPRER 0x04 /* MX1, MX21, MX27 */ @@ -47,8 +53,8 @@ #define MX2_TSTAT_CAPT (1 << 1) #define MX2_TSTAT_COMP (1 << 0) -/* MX31, MX35, MX25, MXC91231 */ -#define MX3_TCTL_WAITEN (1 << 3) +/* MX31, MX35, MX25, MXC91231, MX5 */ +#define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */ #define MX3_TCTL_CLK_IPG (1 << 6) #define MX3_TCTL_FRR (1 << 9) #define MX3_IR 0x0c @@ -57,6 +63,9 @@ #define MX3_TCN 0x24 #define MX3_TCMP 0x10 +#define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) +#define timer_is_v2() (!timer_is_v1()) + static struct clock_event_device clockevent_mxc; static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; @@ -66,7 +75,7 @@ static inline void gpt_irq_disable(void) { unsigned int tmp; - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) __raw_writel(0, timer_base + MX3_IR); else { tmp = __raw_readl(timer_base + MXC_TCTL); @@ -76,7 +85,7 @@ static inline void gpt_irq_disable(void) static inline void gpt_irq_enable(void) { - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) __raw_writel(1<<0, timer_base + MX3_IR); else { __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, @@ -86,11 +95,13 @@ static inline void gpt_irq_enable(void) static void gpt_irq_acknowledge(void) { - if (cpu_is_mx1()) - __raw_writel(0, timer_base + MX1_2_TSTAT); - if (cpu_is_mx2()) - __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT); - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v1()) { + if (cpu_is_mx1()) + __raw_writel(0, timer_base + MX1_2_TSTAT); + else + __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, + timer_base + MX1_2_TSTAT); + } else if (timer_is_v2()) __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); } @@ -117,7 +128,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) clocksource_mxc.read = mx3_get_cycles; clocksource_mxc.mult = clocksource_hz2mult(c, @@ -180,7 +191,7 @@ static void mxc_set_mode(enum clock_event_mode mode, if (mode != clockevent_mode) { /* Set event time into far-far future */ - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, timer_base + MX3_TCMP); else @@ -233,7 +244,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) struct clock_event_device *evt = &clockevent_mxc; uint32_t tstat; - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) tstat = __raw_readl(timer_base + MX3_TSTAT); else tstat = __raw_readl(timer_base + MX1_2_TSTAT); @@ -264,7 +275,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) clockevent_mxc.set_next_event = mx3_set_next_event; clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, @@ -296,7 +307,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ - if (cpu_is_mx3() || cpu_is_mx25()) + if (timer_is_v2()) tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; else tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c new file mode 100644 index 000000000000..afa6709db0b3 --- /dev/null +++ b/arch/arm/plat-mxc/tzic.c @@ -0,0 +1,172 @@ +/* + * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/device.h> +#include <linux/errno.h> +#include <linux/io.h> + +#include <asm/mach/irq.h> + +#include <mach/hardware.h> + +/* + ***************************************** + * TZIC Registers * + ***************************************** + */ + +#define TZIC_INTCNTL 0x0000 /* Control register */ +#define TZIC_INTTYPE 0x0004 /* Controller Type register */ +#define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */ +#define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */ +#define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */ +#define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */ +#define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */ +#define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */ +#define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */ +#define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */ +#define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */ +#define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */ +#define TZIC_PND0 0x0D00 /* Pending Register 0 */ +#define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */ +#define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */ +#define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */ +#define TZIC_ID0 0x0FD0 /* Indentification Register 0 */ + +void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ + +/** + * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC + * + * @param irq interrupt source number + */ +static void tzic_mask_irq(unsigned int irq) +{ + int index, off; + + index = irq >> 5; + off = irq & 0x1F; + __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index)); +} + +/** + * tzic_unmask_irq() - Enable interrupt number "irq" in the TZIC + * + * @param irq interrupt source number + */ +static void tzic_unmask_irq(unsigned int irq) +{ + int index, off; + + index = irq >> 5; + off = irq & 0x1F; + __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index)); +} + +static unsigned int wakeup_intr[4]; + +/** + * tzic_set_wake_irq() - Set interrupt number "irq" in the TZIC as a wake-up source. + * + * @param irq interrupt source number + * @param enable enable as wake-up if equal to non-zero + * disble as wake-up if equal to zero + * + * @return This function returns 0 on success. + */ +static int tzic_set_wake_irq(unsigned int irq, unsigned int enable) +{ + unsigned int index, off; + + index = irq >> 5; + off = irq & 0x1F; + + if (index > 3) + return -EINVAL; + + if (enable) + wakeup_intr[index] |= (1 << off); + else + wakeup_intr[index] &= ~(1 << off); + + return 0; +} + +static struct irq_chip mxc_tzic_chip = { + .name = "MXC_TZIC", + .ack = tzic_mask_irq, + .mask = tzic_mask_irq, + .unmask = tzic_unmask_irq, + .set_wake = tzic_set_wake_irq, +}; + +/* + * This function initializes the TZIC hardware and disables all the + * interrupts. It registers the interrupt enable and disable functions + * to the kernel for each interrupt source. + */ +void __init tzic_init_irq(void __iomem *irqbase) +{ + int i; + + tzic_base = irqbase; + /* put the TZIC into the reset value with + * all interrupts disabled + */ + i = __raw_readl(tzic_base + TZIC_INTCNTL); + + __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); + __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); + __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); + + for (i = 0; i < 4; i++) + __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); + + /* disable all interrupts */ + for (i = 0; i < 4; i++) + __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); + + /* all IRQ no FIQ Warning :: No selection */ + + for (i = 0; i < MXC_INTERNAL_IRQS; i++) { + set_irq_chip(i, &mxc_tzic_chip); + set_irq_handler(i, handle_level_irq); + set_irq_flags(i, IRQF_VALID); + } + + pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); +} + +/** + * tzic_enable_wake() - enable wakeup interrupt + * + * @param is_idle 1 if called in idle loop (ENSET0 register); + * 0 to be used when called from low power entry + * @return 0 if successful; non-zero otherwise + */ +int tzic_enable_wake(int is_idle) +{ + unsigned int i, v; + + __raw_writel(1, tzic_base + TZIC_DSMINT); + if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0)) + return -EAGAIN; + + for (i = 0; i < 4; i++) { + v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i]; + __raw_writel(v, TZIC_WAKEUP0(i)); + } + + return 0; +} diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c index 62f18ad43a28..fa7cb3a57cbf 100644 --- a/arch/arm/plat-nomadik/timer.c +++ b/arch/arm/plat-nomadik/timer.c @@ -49,24 +49,17 @@ static struct clocksource nmdk_clksrc = { static void nmdk_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev) { - unsigned long flags; - switch (mode) { case CLOCK_EVT_MODE_PERIODIC: - /* enable interrupts -- and count current value? */ - raw_local_irq_save(flags); + /* count current value? */ writel(readl(mtu_base + MTU_IMSC) | 1, mtu_base + MTU_IMSC); - raw_local_irq_restore(flags); break; case CLOCK_EVT_MODE_ONESHOT: BUG(); /* Not supported, yet */ /* FALLTHROUGH */ case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_UNUSED: - /* disable irq */ - raw_local_irq_save(flags); writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC); - raw_local_irq_restore(flags); break; case CLOCK_EVT_MODE_RESUME: break; diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 9e9d0286e48f..2367908c4f62 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig @@ -59,50 +59,6 @@ config S3C_BOOT_UART_FORCE_FIFO Say Y here to force the UART FIFOs on during the kernel uncompressor -comment "Power management" - -config S3C2410_PM_DEBUG - bool "S3C2410 PM Suspend debug" - depends on PM - help - Say Y here if you want verbose debugging from the PM Suspend and - Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> - for more information. - -config S3C_PM_DEBUG_LED_SMDK - bool "SMDK LED suspend/resume debugging" - depends on PM && (MACH_SMDK6410) - help - Say Y here to enable the use of the SMDK LEDs on the baseboard - for debugging of the state of the suspend and resume process. - - Note, this currently only works for S3C64XX based SMDK boards. - -config S3C2410_PM_CHECK - bool "S3C2410 PM Suspend Memory CRC" - depends on PM && CRC32 - help - Enable the PM code's memory area checksum over sleep. This option - will generate CRCs of all blocks of memory, and store them before - going to sleep. The blocks are then checked on resume for any - errors. - - Note, this can take several seconds depending on memory size - and CPU speed. - - See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> - -config S3C2410_PM_CHECK_CHUNKSIZE - int "S3C2410 PM Suspend CRC Chunksize (KiB)" - depends on PM && S3C2410_PM_CHECK - default 64 - help - Set the chunksize in Kilobytes of the CRC for checking memory - corruption over suspend and resume. A smaller value will mean that - the CRC data block will take more memory, but wil identify any - faults with better precision. - - See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> config S3C_LOWLEVEL_UART_PORT int "S3C UART to use for low-level messages" @@ -130,39 +86,6 @@ config S3C_GPIO_TRACK Internal configuration option to enable the s3c specific gpio chip tracking if the platform requires it. -config S3C_GPIO_PULL_UPDOWN - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_PULL_DOWN - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_PULL_UP - bool - help - Internal configuration to enable the correct GPIO pull helper - -config S3C_GPIO_CFG_S3C24XX - bool - help - Internal configuration to enable S3C24XX style GPIO configuration - functions. - -config S3C_GPIO_CFG_S3C64XX - bool - help - Internal configuration to enable S3C64XX style GPIO configuration - functions. - -config S5P_GPIO_CFG_S5PC1XX - bool - help - Internal configuration to enable S5PC1XX style GPIO configuration - functions. - # DMA config S3C_DMA @@ -170,46 +93,4 @@ config S3C_DMA help Internal configuration for S3C DMA core -# device definitions to compile in - -config S3C_DEV_HSMMC - bool - help - Compile in platform device definitions for HSMMC code - -config S3C_DEV_HSMMC1 - bool - help - Compile in platform device definitions for HSMMC channel 1 - -config S3C_DEV_HSMMC2 - bool - help - Compile in platform device definitions for HSMMC channel 2 - -config S3C_DEV_I2C1 - bool - help - Compile in platform device definitions for I2C channel 1 - -config S3C_DEV_FB - bool - help - Compile in platform device definition for framebuffer - -config S3C_DEV_USB_HOST - bool - help - Compile in platform device definition for USB host. - -config S3C_DEV_USB_HSOTG - bool - help - Compile in platform device definition for USB high-speed OtG - -config S3C_DEV_NAND - bool - help - Compile in platform device definition for NAND controller - endif diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 50444da98425..89dbdb0adebf 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile @@ -11,12 +11,8 @@ obj- := # Core support for all Samsung SoCs -obj-y += init.o +obj-y += init.o obj-y += time.o -obj-y += clock.o -obj-y += pwm-clock.o -obj-y += gpio.o -obj-y += gpio-config.o # DMA support @@ -25,21 +21,3 @@ obj-$(CONFIG_S3C_DMA) += dma.o # PM support obj-$(CONFIG_PM) += pm.o -obj-$(CONFIG_PM) += pm-gpio.o -obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o - -# PWM support - -obj-$(CONFIG_HAVE_PWM) += pwm.o - -# devices - -obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o -obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o -obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o -obj-y += dev-i2c0.o -obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o -obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o -obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o -obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o -obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index d1131ca11e97..676db9465674 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h @@ -48,9 +48,12 @@ extern void s3c_init_cpu(unsigned long idcode, extern void s3c24xx_init_irq(void); extern void s3c64xx_init_irq(u32 vic0, u32 vic1); +extern void s5p_init_irq(u32 *vic, u32 num_vic); extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); +extern void s5p_init_io(struct map_desc *mach_desc, + int size, void __iomem *cpuid_addr); extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index c1c20b023917..c6f9b7310490 100644 --- a/arch/arm/plat-s3c/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h @@ -18,6 +18,7 @@ struct s3c24xx_uart_resources { extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; +extern struct s3c24xx_uart_resources s5p_uart_resources[]; extern struct platform_device *s3c24xx_uart_devs[]; extern struct platform_device *s3c24xx_uart_src[]; @@ -28,12 +29,15 @@ extern struct platform_device s3c64xx_device_iis0; extern struct platform_device s3c64xx_device_iis1; extern struct platform_device s3c64xx_device_iisv4; +extern struct platform_device s3c64xx_device_spi0; +extern struct platform_device s3c64xx_device_spi1; + extern struct platform_device s3c64xx_device_pcm0; extern struct platform_device s3c64xx_device_pcm1; extern struct platform_device s3c_device_ts; extern struct platform_device s3c_device_fb; -extern struct platform_device s3c_device_usb; +extern struct platform_device s3c_device_ohci; extern struct platform_device s3c_device_lcd; extern struct platform_device s3c_device_wdt; extern struct platform_device s3c_device_i2c0; diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h index 7a797192fcf3..2543bd227f2d 100644 --- a/arch/arm/plat-s3c/include/plat/pm.h +++ b/arch/arm/plat-s3c/include/plat/pm.h @@ -111,7 +111,7 @@ extern int s3c24xx_irq_resume(struct sys_device *dev); /* PM debug functions */ -#ifdef CONFIG_S3C2410_PM_DEBUG +#ifdef CONFIG_SAMSUNG_PM_DEBUG /** * s3c_pm_dbg() - low level debug function for use in suspend/resume. * @msg: The message to print. @@ -141,7 +141,7 @@ static inline void s3c_pm_debug_smdkled(u32 set, u32 clear) { } /* suspend memory checking */ -#ifdef CONFIG_S3C2410_PM_CHECK +#ifdef CONFIG_SAMSUNG_PM_CHECK extern void s3c_pm_check_prepare(void); extern void s3c_pm_check_restore(void); extern void s3c_pm_check_cleanup(void); diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index 85d8904e7f24..60d6604185ea 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h @@ -194,6 +194,36 @@ #define S3C64XX_UINTSP 0x34 #define S3C64XX_UINTM 0x38 +/* Following are specific to S5PV210 and S5P6442 */ +#define S5PV210_UCON_CLKMASK (1<<10) +#define S5PV210_UCON_PCLK (0<<10) +#define S5PV210_UCON_UCLK (1<<10) + +#define S5PV210_UFCON_TXTRIG0 (0<<8) +#define S5PV210_UFCON_TXTRIG4 (1<<8) +#define S5PV210_UFCON_TXTRIG8 (2<<8) +#define S5PV210_UFCON_TXTRIG16 (3<<8) +#define S5PV210_UFCON_TXTRIG32 (4<<8) +#define S5PV210_UFCON_TXTRIG64 (5<<8) +#define S5PV210_UFCON_TXTRIG128 (6<<8) +#define S5PV210_UFCON_TXTRIG256 (7<<8) + +#define S5PV210_UFCON_RXTRIG1 (0<<4) +#define S5PV210_UFCON_RXTRIG4 (1<<4) +#define S5PV210_UFCON_RXTRIG8 (2<<4) +#define S5PV210_UFCON_RXTRIG16 (3<<4) +#define S5PV210_UFCON_RXTRIG32 (4<<4) +#define S5PV210_UFCON_RXTRIG64 (5<<4) +#define S5PV210_UFCON_RXTRIG128 (6<<4) +#define S5PV210_UFCON_RXTRIG256 (7<<4) + +#define S5PV210_UFSTAT_TXFULL (1<<24) +#define S5PV210_UFSTAT_RXFULL (1<<8) +#define S5PV210_UFSTAT_TXMASK (255<<16) +#define S5PV210_UFSTAT_TXSHIFT (16) +#define S5PV210_UFSTAT_RXMASK (255<<0) +#define S5PV210_UFSTAT_RXSHIFT (0) + #ifndef __ASSEMBLY__ /* struct s3c24xx_uart_clksrc diff --git a/arch/arm/plat-s3c/include/plat/usb-control.h b/arch/arm/plat-s3c/include/plat/usb-control.h index 822c87fe948e..a6a57bf796bd 100644 --- a/arch/arm/plat-s3c/include/plat/usb-control.h +++ b/arch/arm/plat-s3c/include/plat/usb-control.h @@ -38,4 +38,6 @@ static void inline s3c2410_usb_report_oc(struct s3c2410_hcd_info *info, int port } } +extern void s3c_ohci_set_platdata(struct s3c2410_hcd_info *info); + #endif /*__ASM_ARCH_USBCONTROL_H */ diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c index 767470601e5c..e5eef126791b 100644 --- a/arch/arm/plat-s3c/pm.c +++ b/arch/arm/plat-s3c/pm.c @@ -41,7 +41,7 @@ unsigned long s3c_pm_flags; * resume before the console layer is available. */ -#ifdef CONFIG_S3C2410_PM_DEBUG +#ifdef CONFIG_SAMSUNG_PM_DEBUG extern void printascii(const char *); void s3c_pm_dbg(const char *fmt, ...) @@ -65,13 +65,13 @@ static inline void s3c_pm_debug_init(void) #else #define s3c_pm_debug_init() do { } while(0) -#endif /* CONFIG_S3C2410_PM_DEBUG */ +#endif /* CONFIG_SAMSUNG_PM_DEBUG */ /* Save the UART configurations if we are configured for debug. */ unsigned char pm_uart_udivslot; -#ifdef CONFIG_S3C2410_PM_DEBUG +#ifdef CONFIG_SAMSUNG_PM_DEBUG struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 342647eb91d8..a806f359ceb6 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig @@ -117,13 +117,6 @@ config S3C2410_DMA_DEBUG Enable debugging output for the DMA code. This option sends info to the kernel log, at priority KERN_DEBUG. -config S3C24XX_ADC - bool "ADC common driver support" - help - Core support for the ADC block found in the S3C24XX SoC systems - for drivers such as the touchscreen and hwmon to use to share - this resource. - # SPI default pin configuration code config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13 diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 5dee8c12e8b4..e0100266d039 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile @@ -38,7 +38,6 @@ obj-$(CONFIG_PM) += irq-pm.o obj-$(CONFIG_PM) += sleep.o obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o obj-$(CONFIG_S3C2410_DMA) += dma.o -obj-$(CONFIG_S3C24XX_ADC) += adc.o obj-$(CONFIG_S3C2410_IOTIMING) += s3c2410-iotiming.o obj-$(CONFIG_S3C2412_IOTIMING) += s3c2412-iotiming.o obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c index ac061a1bcb37..cf97caafe56b 100644 --- a/arch/arm/plat-s3c24xx/clock-dclk.c +++ b/arch/arm/plat-s3c24xx/clock-dclk.c @@ -161,14 +161,18 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) /* external clock definitions */ +static struct clk_ops dclk_ops = { + .set_parent = s3c24xx_dclk_setparent, + .set_rate = s3c24xx_set_dclk_rate, + .round_rate = s3c24xx_round_dclk_rate, +}; + struct clk s3c24xx_dclk0 = { .name = "dclk0", .id = -1, .ctrlbit = S3C2410_DCLKCON_DCLK0EN, .enable = s3c24xx_dclk_enable, - .set_parent = s3c24xx_dclk_setparent, - .set_rate = s3c24xx_set_dclk_rate, - .round_rate = s3c24xx_round_dclk_rate, + .ops = &dclk_ops, }; struct clk s3c24xx_dclk1 = { @@ -176,19 +180,21 @@ struct clk s3c24xx_dclk1 = { .id = -1, .ctrlbit = S3C2410_DCLKCON_DCLK1EN, .enable = s3c24xx_dclk_enable, - .set_parent = s3c24xx_dclk_setparent, - .set_rate = s3c24xx_set_dclk_rate, - .round_rate = s3c24xx_round_dclk_rate, + .ops = &dclk_ops, +}; + +static struct clk_ops clkout_ops = { + .set_parent = s3c24xx_clkout_setparent, }; struct clk s3c24xx_clkout0 = { .name = "clkout0", .id = -1, - .set_parent = s3c24xx_clkout_setparent, + .ops = &clkout_ops, }; struct clk s3c24xx_clkout1 = { .name = "clkout1", .id = -1, - .set_parent = s3c24xx_clkout_setparent, + .ops = &clkout_ops, }; diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 7f686a31e672..986d4e5408f5 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -32,6 +32,7 @@ #include <plat/regs-serial.h> #include <plat/udc.h> +#include <plat/mci.h> #include <plat/devs.h> #include <plat/cpu.h> @@ -112,34 +113,6 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { }, }; -/* yart devices */ - -static struct platform_device s3c24xx_uart_device0 = { - .id = 0, -}; - -static struct platform_device s3c24xx_uart_device1 = { - .id = 1, -}; - -static struct platform_device s3c24xx_uart_device2 = { - .id = 2, -}; - -static struct platform_device s3c24xx_uart_device3 = { - .id = 3, -}; - -struct platform_device *s3c24xx_uart_src[4] = { - &s3c24xx_uart_device0, - &s3c24xx_uart_device1, - &s3c24xx_uart_device2, - &s3c24xx_uart_device3, -}; - -struct platform_device *s3c24xx_uart_devs[4] = { -}; - /* LCD Controller */ static struct resource s3c_lcd_resource[] = { @@ -379,6 +352,18 @@ struct platform_device s3c_device_sdi = { EXPORT_SYMBOL(s3c_device_sdi); +void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) +{ + struct s3c24xx_mci_pdata *npd; + + npd = kmemdup(pdata, sizeof(struct s3c24xx_mci_pdata), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory to copy pdata", __func__); + + s3c_device_sdi.dev.platform_data = npd; +} + + /* SPI (0) */ static struct resource s3c_spi0_resource[] = { diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c index 6d7a961d3269..4f0f11a6a677 100644 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ b/arch/arm/plat-s3c24xx/gpiolib.c @@ -20,7 +20,7 @@ #include <linux/io.h> #include <linux/gpio.h> -#include <mach/gpio-core.h> +#include <plat/gpio-core.h> #include <mach/hardware.h> #include <asm/irq.h> #include <plat/pm.h> diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h index 36aaa10fad06..2ac2b21ec490 100644 --- a/arch/arm/plat-s3c24xx/include/plat/mci.h +++ b/arch/arm/plat-s3c24xx/include/plat/mci.h @@ -40,4 +40,13 @@ struct s3c24xx_mci_pdata { unsigned short vdd); }; +/** + * s3c24xx_mci_set_platdata - set platform data for mmc/sdi device + * @pdata: The platform data + * + * Copy the platform data supplied by @pdata so that this can be marked + * __initdata. + */ +extern void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata); + #endif /* _ARCH_NCI_H */ diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c index 79371091aa38..f8d96130d1d1 100644 --- a/arch/arm/plat-s3c24xx/s3c244x-clock.c +++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c @@ -68,7 +68,9 @@ static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent) static struct clk clk_arm = { .name = "armclk", .id = -1, - .set_parent = s3c2440_setparent_armclk, + .ops = &(struct clk_ops) { + .set_parent = s3c2440_setparent_armclk, + }, }; static int s3c244x_clk_add(struct sys_device *sysdev) diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig index e6da87a5885c..37b4519fb832 100644 --- a/arch/arm/plat-s3c64xx/Kconfig +++ b/arch/arm/plat-s3c64xx/Kconfig @@ -13,12 +13,16 @@ config PLAT_S3C64XX select ARM_VIC select NO_IOPORT select ARCH_REQUIRE_GPIOLIB + select SAMSUNG_CLKSRC + select SAMSUNG_IRQ_VIC_TIMER + select SAMSUNG_IRQ_UART select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX select S3C_GPIO_CFG_S3C64XX select S3C_DEV_NAND select USB_ARCH_HAS_OHCI + select SAMSUNG_GPIOLIB_4BIT help Base platform code for any Samsung S3C64XX device diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile index b85b4359e935..80255a5e1789 100644 --- a/arch/arm/plat-s3c64xx/Makefile +++ b/arch/arm/plat-s3c64xx/Makefile @@ -13,6 +13,7 @@ obj- := # Core files obj-y += dev-uart.o +obj-y += dev-rtc.o obj-y += cpu.o obj-y += irq.o obj-y += irq-eint.o @@ -35,6 +36,10 @@ obj-$(CONFIG_PM) += irq-pm.o obj-$(CONFIG_S3C64XX_DMA) += dma.o +# ADC support + +obj-$(CONFIG_S3C_ADC) += dev-adc.o + # Device setup obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o @@ -42,3 +47,4 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o +obj-$(CONFIG_SPI_S3C64XX) += dev-spi.o diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c index 7a36e899360d..2989c3a2e94d 100644 --- a/arch/arm/plat-s3c64xx/clock.c +++ b/arch/arm/plat-s3c64xx/clock.c @@ -141,6 +141,18 @@ static struct clk init_clocks_disable[] = { .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_SPI1, }, { + .name = "spi_48m", + .id = 0, + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, + }, { + .name = "spi_48m", + .id = 1, + .parent = &clk_48m, + .enable = s3c64xx_sclk_ctrl, + .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, + }, { .name = "48m", .id = 0, .parent = &clk_48m, @@ -274,15 +286,7 @@ void __init s3c64xx_register_clocks(void) int ptr; s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - - clkp = init_clocks; - for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); clkp = init_clocks_disable; for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index 49796d2db86d..bc7ca1812e32 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c @@ -73,17 +73,22 @@ static struct map_desc s3c_iodesc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE, }, { + .virtual = (unsigned long)S3C_VA_MEM, + .pfn = __phys_to_pfn(S3C64XX_PA_SROM), + .length = SZ_4K, + .type = MT_DEVICE, + }, { .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), .pfn = __phys_to_pfn(S3C_PA_UART), .length = SZ_4K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S3C_VA_VIC0, + .virtual = (unsigned long)VA_VIC0, .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), .length = SZ_16K, .type = MT_DEVICE, }, { - .virtual = (unsigned long)S3C_VA_VIC1, + .virtual = (unsigned long)VA_VIC1, .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), .length = SZ_16K, .type = MT_DEVICE, diff --git a/arch/arm/plat-s3c64xx/dev-adc.c b/arch/arm/plat-s3c64xx/dev-adc.c new file mode 100644 index 000000000000..fafef9b6bcfa --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-adc.c @@ -0,0 +1,46 @@ +/* linux/arch/arm/plat-s3c64xx/dev-adc.c + * + * Copyright 2010 Maurus Cuelenaere + * + * S3C64xx series device definition for ADC device + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +#include <plat/adc.h> +#include <plat/devs.h> +#include <plat/cpu.h> + +static struct resource s3c_adc_resource[] = { + [0] = { + .start = S3C64XX_PA_ADC, + .end = S3C64XX_PA_ADC + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_TC, + .end = IRQ_TC, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_ADC, + .end = IRQ_ADC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device s3c_device_adc = { + .name = "s3c64xx-adc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_adc_resource), + .resource = s3c_adc_resource, +}; diff --git a/arch/arm/plat-s3c64xx/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c index a21a88fbb7e3..f6b7bfb519d7 100644 --- a/arch/arm/plat-s3c64xx/dev-audio.c +++ b/arch/arm/plat-s3c64xx/dev-audio.c @@ -3,7 +3,6 @@ * Copyright 2009 Wolfson Microelectronics * Mark Brown <[email protected]> * - * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. @@ -20,16 +19,69 @@ #include <plat/devs.h> #include <plat/audio.h> +#include <plat/gpio-bank-c.h> #include <plat/gpio-bank-d.h> #include <plat/gpio-bank-e.h> +#include <plat/gpio-bank-h.h> #include <plat/gpio-cfg.h> +static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C64XX_GPD0_I2S0_CLK); + s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C64XX_GPD1_I2S0_CDCLK); + s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C64XX_GPD2_I2S0_LRCLK); + s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C64XX_GPD3_I2S0_DI); + s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C64XX_GPD4_I2S0_D0); + break; + case 1: + s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C64XX_GPE0_I2S1_CLK); + s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C64XX_GPE1_I2S1_CDCLK); + s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C64XX_GPE2_I2S1_LRCLK); + s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C64XX_GPE3_I2S1_DI); + s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C64XX_GPE4_I2S1_D0); + default: + printk(KERN_DEBUG "Invalid I2S Controller number!"); + return -EINVAL; + } + + return 0; +} + +static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev) +{ + s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_I2S_V40_DO0); + s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_I2S_V40_DO1); + s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C64XX_GPC7_I2S_V40_DO2); + s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C64XX_GPH6_I2S_V40_BCLK); + s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C64XX_GPH7_I2S_V40_CDCLK); + s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C64XX_GPH8_I2S_V40_LRCLK); + s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C64XX_GPH9_I2S_V40_DI); + + return 0; +} + static struct resource s3c64xx_iis0_resource[] = { [0] = { .start = S3C64XX_PA_IIS0, .end = S3C64XX_PA_IIS0 + 0x100 - 1, .flags = IORESOURCE_MEM, }, + [1] = { + .start = DMACH_I2S0_OUT, + .end = DMACH_I2S0_OUT, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S0_IN, + .end = DMACH_I2S0_IN, + .flags = IORESOURCE_DMA, + }, +}; + +static struct s3c_audio_pdata s3c_i2s0_pdata = { + .cfg_gpio = s3c64xx_i2sv3_cfg_gpio, }; struct platform_device s3c64xx_device_iis0 = { @@ -37,6 +89,9 @@ struct platform_device s3c64xx_device_iis0 = { .id = 0, .num_resources = ARRAY_SIZE(s3c64xx_iis0_resource), .resource = s3c64xx_iis0_resource, + .dev = { + .platform_data = &s3c_i2s0_pdata, + }, }; EXPORT_SYMBOL(s3c64xx_device_iis0); @@ -46,6 +101,20 @@ static struct resource s3c64xx_iis1_resource[] = { .end = S3C64XX_PA_IIS1 + 0x100 - 1, .flags = IORESOURCE_MEM, }, + [1] = { + .start = DMACH_I2S1_OUT, + .end = DMACH_I2S1_OUT, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_I2S1_IN, + .end = DMACH_I2S1_IN, + .flags = IORESOURCE_DMA, + }, +}; + +static struct s3c_audio_pdata s3c_i2s1_pdata = { + .cfg_gpio = s3c64xx_i2sv3_cfg_gpio, }; struct platform_device s3c64xx_device_iis1 = { @@ -53,6 +122,9 @@ struct platform_device s3c64xx_device_iis1 = { .id = 1, .num_resources = ARRAY_SIZE(s3c64xx_iis1_resource), .resource = s3c64xx_iis1_resource, + .dev = { + .platform_data = &s3c_i2s1_pdata, + }, }; EXPORT_SYMBOL(s3c64xx_device_iis1); @@ -62,6 +134,20 @@ static struct resource s3c64xx_iisv4_resource[] = { .end = S3C64XX_PA_IISV4 + 0x100 - 1, .flags = IORESOURCE_MEM, }, + [1] = { + .start = DMACH_HSI_I2SV40_TX, + .end = DMACH_HSI_I2SV40_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_HSI_I2SV40_RX, + .end = DMACH_HSI_I2SV40_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct s3c_audio_pdata s3c_i2sv4_pdata = { + .cfg_gpio = s3c64xx_i2sv4_cfg_gpio, }; struct platform_device s3c64xx_device_iisv4 = { @@ -69,6 +155,9 @@ struct platform_device s3c64xx_device_iisv4 = { .id = -1, .num_resources = ARRAY_SIZE(s3c64xx_iisv4_resource), .resource = s3c64xx_iisv4_resource, + .dev = { + .platform_data = &s3c_i2sv4_pdata, + }, }; EXPORT_SYMBOL(s3c64xx_device_iisv4); diff --git a/arch/arm/plat-s3c64xx/dev-rtc.c b/arch/arm/plat-s3c64xx/dev-rtc.c new file mode 100644 index 000000000000..b9e7a05f0129 --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-rtc.c @@ -0,0 +1,43 @@ +/* linux/arch/arm/plat-s3c64xx/dev-rtc.c + * + * Copyright 2009 by Maurus Cuelenaere <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> + +#include <mach/irqs.h> +#include <mach/map.h> + +#include <plat/devs.h> + +static struct resource s3c_rtc_resource[] = { + [0] = { + .start = S3C64XX_PA_RTC, + .end = S3C64XX_PA_RTC + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_RTC_ALARM, + .end = IRQ_RTC_ALARM, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_RTC_TIC, + .end = IRQ_RTC_TIC, + .flags = IORESOURCE_IRQ + } +}; + +struct platform_device s3c_device_rtc = { + .name = "s3c64xx-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(s3c_rtc_resource), + .resource = s3c_rtc_resource, +}; +EXPORT_SYMBOL(s3c_device_rtc); diff --git a/arch/arm/plat-s3c64xx/dev-spi.c b/arch/arm/plat-s3c64xx/dev-spi.c new file mode 100644 index 000000000000..ca10388d7ed1 --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-spi.c @@ -0,0 +1,183 @@ +/* linux/arch/arm/plat-s3c64xx/dev-spi.c + * + * Copyright (C) 2009 Samsung Electronics Ltd. + * Jaswinder Singh <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <linux/platform_device.h> +#include <linux/dma-mapping.h> + +#include <mach/dma.h> +#include <mach/map.h> +#include <mach/gpio.h> + +#include <plat/spi-clocks.h> + +#include <plat/s3c64xx-spi.h> +#include <plat/gpio-bank-c.h> +#include <plat/gpio-cfg.h> +#include <plat/irqs.h> + +static char *spi_src_clks[] = { + [S3C64XX_SPI_SRCCLK_PCLK] = "pclk", + [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus", + [S3C64XX_SPI_SRCCLK_48M] = "spi_48m", +}; + +/* SPI Controller platform_devices */ + +/* Since we emulate multi-cs capability, we do not touch the GPC-3,7. + * The emulated CS is toggled by board specific mechanism, as it can + * be either some immediate GPIO or some signal out of some other + * chip in between ... or some yet another way. + * We simply do not assume anything about CS. + */ +static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev) +{ + switch (pdev->id) { + case 0: + s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0); + s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO); + s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO); + s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP); + break; + + case 1: + s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1); + s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1); + s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1); + s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP); + s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP); + break; + + default: + dev_err(&pdev->dev, "Invalid SPI Controller number!"); + return -EINVAL; + } + + return 0; +} + +static struct resource s3c64xx_spi0_resource[] = { + [0] = { + .start = S3C64XX_PA_SPI0, + .end = S3C64XX_PA_SPI0 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI0_TX, + .end = DMACH_SPI0_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI0_RX, + .end = DMACH_SPI0_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI0, + .end = IRQ_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s3c64xx_spi0_pdata = { + .cfg_gpio = s3c64xx_spi_cfg_gpio, + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, +}; + +static u64 spi_dmamask = DMA_BIT_MASK(32); + +struct platform_device s3c64xx_device_spi0 = { + .name = "s3c64xx-spi", + .id = 0, + .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), + .resource = s3c64xx_spi0_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s3c64xx_spi0_pdata, + }, +}; +EXPORT_SYMBOL(s3c64xx_device_spi0); + +static struct resource s3c64xx_spi1_resource[] = { + [0] = { + .start = S3C64XX_PA_SPI1, + .end = S3C64XX_PA_SPI1 + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DMACH_SPI1_TX, + .end = DMACH_SPI1_TX, + .flags = IORESOURCE_DMA, + }, + [2] = { + .start = DMACH_SPI1_RX, + .end = DMACH_SPI1_RX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = IRQ_SPI1, + .end = IRQ_SPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct s3c64xx_spi_info s3c64xx_spi1_pdata = { + .cfg_gpio = s3c64xx_spi_cfg_gpio, + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, +}; + +struct platform_device s3c64xx_device_spi1 = { + .name = "s3c64xx-spi", + .id = 1, + .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), + .resource = s3c64xx_spi1_resource, + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &s3c64xx_spi1_pdata, + }, +}; +EXPORT_SYMBOL(s3c64xx_device_spi1); + +void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) +{ + struct s3c64xx_spi_info *pd; + + /* Reject invalid configuration */ + if (!num_cs || src_clk_nr < 0 + || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) { + printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); + return; + } + + switch (cntrlr) { + case 0: + pd = &s3c64xx_spi0_pdata; + break; + case 1: + pd = &s3c64xx_spi1_pdata; + break; + default: + printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", + __func__, cntrlr); + return; + } + + pd->num_cs = num_cs; + pd->src_clk_nr = src_clk_nr; + pd->src_clk_name = spi_src_clks[src_clk_nr]; +} diff --git a/arch/arm/plat-s3c64xx/dev-uart.c b/arch/arm/plat-s3c64xx/dev-uart.c index 62c11a6fc7ba..f797f748b999 100644 --- a/arch/arm/plat-s3c64xx/dev-uart.c +++ b/arch/arm/plat-s3c64xx/dev-uart.c @@ -145,32 +145,3 @@ struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = { .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource), }, }; - -/* uart devices */ - -static struct platform_device s3c24xx_uart_device0 = { - .id = 0, -}; - -static struct platform_device s3c24xx_uart_device1 = { - .id = 1, -}; - -static struct platform_device s3c24xx_uart_device2 = { - .id = 2, -}; - -static struct platform_device s3c24xx_uart_device3 = { - .id = 3, -}; - -struct platform_device *s3c24xx_uart_src[4] = { - &s3c24xx_uart_device0, - &s3c24xx_uart_device1, - &s3c24xx_uart_device2, - &s3c24xx_uart_device3, -}; - -struct platform_device *s3c24xx_uart_devs[4] = { -}; - diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index 778560457277..b6e3f55321fa 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c @@ -18,8 +18,8 @@ #include <mach/map.h> #include <mach/gpio.h> -#include <mach/gpio-core.h> +#include <plat/gpio-core.h> #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> #include <plat/regs-gpio.h> @@ -49,150 +49,6 @@ * [2] BANK has two control registers, GPxCON0 and GPxCON1 */ -#define OFF_GPCON (0x00) -#define OFF_GPDAT (0x04) - -#define con_4bit_shift(__off) ((__off) * 4) - -#if 1 -#define gpio_dbg(x...) do { } while(0) -#else -#define gpio_dbg(x...) printk(KERN_DEBUG x) -#endif - -/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where - * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the - * following example: - * - * base + 0x00: Control register, 4 bits per gpio - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Data register, 1 bit per gpio - * bit n: data bit n - * - * Note, since the data register is one bit per gpio and is at base + 0x4 - * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of - * the output. -*/ - -static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - - con = __raw_readl(base + OFF_GPCON); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, base + OFF_GPCON); - - gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); - - return 0; -} - -static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - unsigned long con; - unsigned long dat; - - con = __raw_readl(base + OFF_GPCON); - con &= ~(0xf << con_4bit_shift(offset)); - con |= 0x1 << con_4bit_shift(offset); - - dat = __raw_readl(base + OFF_GPDAT); - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + OFF_GPDAT); - __raw_writel(con, base + OFF_GPCON); - __raw_writel(dat, base + OFF_GPDAT); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - -/* The next set of routines are for the case where the GPIO configuration - * registers are 4 bits per GPIO but there is more than one register (the - * bank has more than 8 GPIOs. - * - * This case is the similar to the 4 bit case, but the registers are as - * follows: - * - * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) - * gpio n: 4 bits starting at (4*n) - * 0000 = input, 0001 = output, others mean special-function - * base + 0x08: Data register, 1 bit per gpio - * bit n: data bit n - * - * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we - * store the 'base + 0x4' address so that these routines see the data - * register at ourchip->base + 0x04. -*/ - -static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - - if (offset > 7) - offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(offset)); - __raw_writel(con, regcon); - - gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); - - return 0; - -} - -static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); - void __iomem *base = ourchip->base; - void __iomem *regcon = base; - unsigned long con; - unsigned long dat; - - if (offset > 7) - offset -= 8; - else - regcon -= 4; - - con = __raw_readl(regcon); - con &= ~(0xf << con_4bit_shift(offset)); - con |= 0x1 << con_4bit_shift(offset); - - dat = __raw_readl(base + OFF_GPDAT); - if (value) - dat |= 1 << offset; - else - dat &= ~(1 << offset); - - __raw_writel(dat, base + OFF_GPDAT); - __raw_writel(con, regcon); - __raw_writel(dat, base + OFF_GPDAT); - - gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); - - return 0; -} - static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { .set_config = s3c_gpio_setcfg_s3c64xx_4bit, .set_pull = s3c_gpio_setpull_updown, @@ -399,20 +255,6 @@ static struct s3c_gpio_chip gpio_2bit[] = { }, }; -static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; - chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - -static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) -{ - chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; - chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; - chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); -} - static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip) { chip->pm = __gpio_pm(&s3c_gpio_pm_2bit); @@ -432,10 +274,10 @@ static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, static __init int s3c64xx_gpiolib_init(void) { s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), - s3c64xx_gpiolib_add_4bit); + samsung_gpiolib_add_4bit); s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), - s3c64xx_gpiolib_add_4bit2); + samsung_gpiolib_add_4bit2); s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), s3c64xx_gpiolib_add_2bit); diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h index 7956fd3bb194..a22758194e6d 100644 --- a/arch/arm/plat-s3c64xx/include/plat/irqs.h +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h @@ -24,8 +24,8 @@ #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) -#define S3C_VIC0_BASE S3C_IRQ(0) -#define S3C_VIC1_BASE S3C_IRQ(32) +#define IRQ_VIC0_BASE S3C_IRQ(0) +#define IRQ_VIC1_BASE S3C_IRQ(32) /* UART interrupts, each UART has 4 intterupts per channel so * use the space between the ISA and S3C main interrupts. Note, these @@ -59,8 +59,8 @@ /* VIC based IRQs */ -#define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) -#define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) +#define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) +#define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) /* VIC0 */ @@ -198,7 +198,11 @@ * interrupt controllers). */ #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) +#ifdef CONFIG_SMDK6410_WM1190_EV1 +#define IRQ_BOARD_NR 64 +#else #define IRQ_BOARD_NR 16 +#endif #define IRQ_BOARD_END (IRQ_BOARD_START + IRQ_BOARD_NR) diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h index ff46e7fa957a..3ef62741e5d1 100644 --- a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h @@ -35,14 +35,6 @@ #define S3C_MEM0_GATE S3C_CLKREG(0x3C) /* CLKDIV0 */ -#define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) -#define S3C6400_CLKDIV0_MFC_SHIFT (28) -#define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24) -#define S3C6400_CLKDIV0_JPEG_SHIFT (24) -#define S3C6400_CLKDIV0_CAM_MASK (0xf << 20) -#define S3C6400_CLKDIV0_CAM_SHIFT (20) -#define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18) -#define S3C6400_CLKDIV0_SECURITY_SHIFT (18) #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) #define S3C6400_CLKDIV0_PCLK_SHIFT (12) #define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) @@ -51,42 +43,11 @@ #define S3C6400_CLKDIV0_HCLK_SHIFT (8) #define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) #define S3C6400_CLKDIV0_MPLL_SHIFT (4) + #define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0) #define S3C6410_CLKDIV0_ARM_MASK (0xf << 0) #define S3C6400_CLKDIV0_ARM_SHIFT (0) -/* CLKDIV1 */ -#define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24) -#define S3C6410_CLKDIV1_FIMC_SHIFT (24) -#define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20) -#define S3C6400_CLKDIV1_UHOST_SHIFT (20) -#define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16) -#define S3C6400_CLKDIV1_SCALER_SHIFT (16) -#define S3C6400_CLKDIV1_LCD_MASK (0xf << 12) -#define S3C6400_CLKDIV1_LCD_SHIFT (12) -#define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8) -#define S3C6400_CLKDIV1_MMC2_SHIFT (8) -#define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4) -#define S3C6400_CLKDIV1_MMC1_SHIFT (4) -#define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0) -#define S3C6400_CLKDIV1_MMC0_SHIFT (0) - -/* CLKDIV2 */ -#define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24) -#define S3C6410_CLKDIV2_AUDIO2_SHIFT (24) -#define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20) -#define S3C6400_CLKDIV2_IRDA_SHIFT (20) -#define S3C6400_CLKDIV2_UART_MASK (0xf << 16) -#define S3C6400_CLKDIV2_UART_SHIFT (16) -#define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12) -#define S3C6400_CLKDIV2_AUDIO1_SHIFT (12) -#define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8) -#define S3C6400_CLKDIV2_AUDIO0_SHIFT (8) -#define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4) -#define S3C6400_CLKDIV2_SPI1_SHIFT (4) -#define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0) -#define S3C6400_CLKDIV2_SPI0_SHIFT (0) - /* HCLK GATE Registers */ #define S3C_CLKCON_HCLK_3DSE (1<<31) #define S3C_CLKCON_HCLK_UHOST (1<<29) @@ -192,34 +153,4 @@ #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) #define S3C6400_CLKSRC_MFC (1 << 4) -#define S3C6410_CLKSRC_TV27_MASK (0x1 << 31) -#define S3C6410_CLKSRC_TV27_SHIFT (31) -#define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30) -#define S3C6410_CLKSRC_DAC27_SHIFT (30) -#define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28) -#define S3C6400_CLKSRC_SCALER_SHIFT (28) -#define S3C6400_CLKSRC_LCD_MASK (0x3 << 26) -#define S3C6400_CLKSRC_LCD_SHIFT (26) -#define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24) -#define S3C6400_CLKSRC_IRDA_SHIFT (24) -#define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22) -#define S3C6400_CLKSRC_MMC2_SHIFT (22) -#define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20) -#define S3C6400_CLKSRC_MMC1_SHIFT (20) -#define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18) -#define S3C6400_CLKSRC_MMC0_SHIFT (18) -#define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16) -#define S3C6400_CLKSRC_SPI1_SHIFT (16) -#define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14) -#define S3C6400_CLKSRC_SPI0_SHIFT (14) -#define S3C6400_CLKSRC_UART_MASK (0x1 << 13) -#define S3C6400_CLKSRC_UART_SHIFT (13) -#define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10) -#define S3C6400_CLKSRC_AUDIO1_SHIFT (10) -#define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7) -#define S3C6400_CLKSRC_AUDIO0_SHIFT (7) -#define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5) -#define S3C6400_CLKSRC_UHOST_SHIFT (5) - - #endif /* _PLAT_REGS_CLOCK_H */ diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-srom.h b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h new file mode 100644 index 000000000000..756731b36297 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-srom.h @@ -0,0 +1,59 @@ +/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h + * + * Copyright 2009 Andy Green <[email protected]> + * + * S3C64XX SROM definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __PLAT_REGS_SROM_H +#define __PLAT_REGS_SROM_H __FILE__ + +#define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x)) + +#define S3C64XX_SROM_BW S3C64XX_SROMREG(0) +#define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4) +#define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8) +#define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc) +#define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10) +#define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14) +#define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18) + +/* + * one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4 + */ + +#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0 +#define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2 +#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3 +#define S3C64XX_SROM_BW__CS_MASK 0xf + +#define S3C64XX_SROM_BW__NCS0__SHIFT 0 +#define S3C64XX_SROM_BW__NCS1__SHIFT 4 +#define S3C64XX_SROM_BW__NCS2__SHIFT 8 +#define S3C64XX_SROM_BW__NCS3__SHIFT 0xc +#define S3C64XX_SROM_BW__NCS4__SHIFT 0x10 + +/* + * applies to same to BCS0 - BCS4 + */ + +#define S3C64XX_SROM_BCX__PMC__SHIFT 0 +#define S3C64XX_SROM_BCX__PMC__MASK 3 +#define S3C64XX_SROM_BCX__TACP__SHIFT 4 +#define S3C64XX_SROM_BCX__TACP__MASK 0xf +#define S3C64XX_SROM_BCX__TCAH__SHIFT 8 +#define S3C64XX_SROM_BCX__TCAH__MASK 0xf +#define S3C64XX_SROM_BCX__TCOH__SHIFT 12 +#define S3C64XX_SROM_BCX__TCOH__MASK 0xf +#define S3C64XX_SROM_BCX__TACC__SHIFT 16 +#define S3C64XX_SROM_BCX__TACC__MASK 0x1f +#define S3C64XX_SROM_BCX__TCOS__SHIFT 24 +#define S3C64XX_SROM_BCX__TCOS__MASK 0xf +#define S3C64XX_SROM_BCX__TACS__SHIFT 28 +#define S3C64XX_SROM_BCX__TACS__MASK 0xf + +#endif /* _PLAT_REGS_SROM_H */ diff --git a/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h new file mode 100644 index 000000000000..524bdae3f625 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h @@ -0,0 +1,18 @@ +/* linux/arch/arm/plat-s3c64xx/include/plat/spi-clocks.h + * + * Copyright (C) 2009 Samsung Electronics Ltd. + * Jaswinder Singh <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __S3C64XX_PLAT_SPI_CLKS_H +#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__ + +#define S3C64XX_SPI_SRCCLK_PCLK 0 +#define S3C64XX_SPI_SRCCLK_SPIBUS 1 +#define S3C64XX_SPI_SRCCLK_48M 2 + +#endif /* __S3C64XX_PLAT_SPI_CLKS_H */ diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c index 8dc5b6da9789..67a145d440f3 100644 --- a/arch/arm/plat-s3c64xx/irq.c +++ b/arch/arm/plat-s3c64xx/irq.c @@ -21,88 +21,11 @@ #include <asm/hardware/vic.h> #include <mach/map.h> -#include <plat/regs-serial.h> -#include <plat/regs-timer.h> +#include <plat/irq-vic-timer.h> +#include <plat/irq-uart.h> #include <plat/cpu.h> -/* Timer interrupt handling */ - -static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) -{ - generic_handle_irq(sub_irq); -} - -static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER0); -} - -static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER1); -} - -static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER2); -} - -static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER3); -} - -static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER4); -} - -/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ - -static void s3c_irq_timer_mask(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg &= ~(1 << (irq - IRQ_TIMER0)); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_unmask(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg |= 1 << (irq - IRQ_TIMER0); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_ack(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; - reg |= (1 << 5) << (irq - IRQ_TIMER0); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static struct irq_chip s3c_irq_timer = { - .name = "s3c-timer", - .mask = s3c_irq_timer_mask, - .unmask = s3c_irq_timer_unmask, - .ack = s3c_irq_timer_ack, -}; - -struct uart_irq { - void __iomem *regs; - unsigned int base_irq; - unsigned int parent_irq; -}; - -/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] - * are consecutive when looking up the interrupt in the demux routines. - */ -static struct uart_irq uart_irqs[] = { +static struct s3c_uart_irq uart_irqs[] = { [0] = { .regs = S3C_VA_UART0, .base_irq = IRQ_S3CUART_BASE0, @@ -125,132 +48,22 @@ static struct uart_irq uart_irqs[] = { }, }; -static inline void __iomem *s3c_irq_uart_base(unsigned int irq) -{ - struct uart_irq *uirq = get_irq_chip_data(irq); - return uirq->regs; -} - -static inline unsigned int s3c_irq_uart_bit(unsigned int irq) -{ - return irq & 3; -} - -/* UART interrupt registers, not worth adding to seperate include header */ - -static void s3c_irq_uart_mask(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_maskack(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_uart_unmask(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg &= ~(1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_ack(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) -{ - struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; - u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); - int base = uirq->base_irq; - - if (pend & (1 << 0)) - generic_handle_irq(base); - if (pend & (1 << 1)) - generic_handle_irq(base + 1); - if (pend & (1 << 2)) - generic_handle_irq(base + 2); - if (pend & (1 << 3)) - generic_handle_irq(base + 3); -} - -static struct irq_chip s3c_irq_uart = { - .name = "s3c-uart", - .mask = s3c_irq_uart_mask, - .unmask = s3c_irq_uart_unmask, - .mask_ack = s3c_irq_uart_maskack, - .ack = s3c_irq_uart_ack, -}; - -static void __init s3c64xx_uart_irq(struct uart_irq *uirq) -{ - void __iomem *reg_base = uirq->regs; - unsigned int irq; - int offs; - - /* mask all interrupts at the start. */ - __raw_writel(0xf, reg_base + S3C64XX_UINTM); - - for (offs = 0; offs < 3; offs++) { - irq = uirq->base_irq + offs; - - set_irq_chip(irq, &s3c_irq_uart); - set_irq_chip_data(irq, uirq); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); -} void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) { - int uart, irq; - printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); /* initialise the pair of VICs */ - vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid, 0); - vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid, 0); + vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0); + vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0); /* add the timer sub-irqs */ - set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0); - set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1); - set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2); - set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3); - set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4); - - for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { - set_irq_chip(irq, &s3c_irq_timer); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } + s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); + s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); + s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); + s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); + s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); - for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) - s3c64xx_uart_irq(&uart_irqs[uart]); + s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } - - diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c index ffd56deb9e81..cb2bf4bff051 100644 --- a/arch/arm/plat-s3c64xx/s3c6400-clock.c +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c @@ -29,6 +29,7 @@ #include <plat/regs-clock.h> #include <plat/clock.h> +#include <plat/clock-clksrc.h> #include <plat/cpu.h> #include <plat/pll.h> @@ -48,22 +49,6 @@ static struct clk clk_ext_xtal_mux = { #define clk_fout_mpll clk_mpll #define clk_fout_epll clk_epll -struct clk_sources { - unsigned int nr_sources; - struct clk **sources; -}; - -struct clksrc_clk { - struct clk clk; - unsigned int mask; - unsigned int shift; - - struct clk_sources *sources; - - unsigned int divider_shift; - void __iomem *reg_divider; -}; - static struct clk clk_fout_apll = { .name = "fout_apll", .id = -1, @@ -74,7 +59,7 @@ static struct clk *clk_src_apll_list[] = { [1] = &clk_fout_apll, }; -static struct clk_sources clk_src_apll = { +static struct clksrc_sources clk_src_apll = { .sources = clk_src_apll_list, .nr_sources = ARRAY_SIZE(clk_src_apll_list), }; @@ -84,8 +69,7 @@ static struct clksrc_clk clk_mout_apll = { .name = "mout_apll", .id = -1, }, - .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT, - .mask = S3C6400_CLKSRC_APLL_MOUT, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 }, .sources = &clk_src_apll, }; @@ -94,7 +78,7 @@ static struct clk *clk_src_epll_list[] = { [1] = &clk_fout_epll, }; -static struct clk_sources clk_src_epll = { +static struct clksrc_sources clk_src_epll = { .sources = clk_src_epll_list, .nr_sources = ARRAY_SIZE(clk_src_epll_list), }; @@ -104,8 +88,7 @@ static struct clksrc_clk clk_mout_epll = { .name = "mout_epll", .id = -1, }, - .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT, - .mask = S3C6400_CLKSRC_EPLL_MOUT, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 }, .sources = &clk_src_epll, }; @@ -114,7 +97,7 @@ static struct clk *clk_src_mpll_list[] = { [1] = &clk_fout_mpll, }; -static struct clk_sources clk_src_mpll = { +static struct clksrc_sources clk_src_mpll = { .sources = clk_src_mpll_list, .nr_sources = ARRAY_SIZE(clk_src_mpll_list), }; @@ -124,8 +107,7 @@ static struct clksrc_clk clk_mout_mpll = { .name = "mout_mpll", .id = -1, }, - .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT, - .mask = S3C6400_CLKSRC_MPLL_MOUT, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 }, .sources = &clk_src_mpll, }; @@ -183,9 +165,11 @@ static struct clk clk_arm = { .name = "armclk", .id = -1, .parent = &clk_mout_apll.clk, - .get_rate = s3c64xx_clk_arm_get_rate, - .set_rate = s3c64xx_clk_arm_set_rate, - .round_rate = s3c64xx_clk_arm_round_rate, + .ops = &(struct clk_ops) { + .get_rate = s3c64xx_clk_arm_get_rate, + .set_rate = s3c64xx_clk_arm_set_rate, + .round_rate = s3c64xx_clk_arm_round_rate, + }, }; static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) @@ -200,11 +184,15 @@ static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) return rate; } +static struct clk_ops clk_dout_ops = { + .get_rate = s3c64xx_clk_doutmpll_get_rate, +}; + static struct clk clk_dout_mpll = { .name = "dout_mpll", .id = -1, .parent = &clk_mout_mpll.clk, - .get_rate = s3c64xx_clk_doutmpll_get_rate, + .ops = &clk_dout_ops, }; static struct clk *clkset_spi_mmc_list[] = { @@ -214,7 +202,7 @@ static struct clk *clkset_spi_mmc_list[] = { &clk_27m, }; -static struct clk_sources clkset_spi_mmc = { +static struct clksrc_sources clkset_spi_mmc = { .sources = clkset_spi_mmc_list, .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), }; @@ -226,7 +214,7 @@ static struct clk *clkset_irda_list[] = { &clk_27m, }; -static struct clk_sources clkset_irda = { +static struct clksrc_sources clkset_irda = { .sources = clkset_irda_list, .nr_sources = ARRAY_SIZE(clkset_irda_list), }; @@ -238,7 +226,7 @@ static struct clk *clkset_uart_list[] = { NULL }; -static struct clk_sources clkset_uart = { +static struct clksrc_sources clkset_uart = { .sources = clkset_uart_list, .nr_sources = ARRAY_SIZE(clkset_uart_list), }; @@ -250,12 +238,11 @@ static struct clk *clkset_uhost_list[] = { &clk_fin_epll, }; -static struct clk_sources clkset_uhost = { +static struct clksrc_sources clkset_uhost = { .sources = clkset_uhost_list, .nr_sources = ARRAY_SIZE(clkset_uhost_list), }; - /* The peripheral clocks are all controlled via clocksource followed * by an optional divider and gate stage. We currently roll this into * one clock which hides the intermediate clock from the mux. @@ -266,221 +253,7 @@ static struct clk_sources clkset_uhost = { * have a common parent divisor so are not included here. */ -static inline struct clksrc_clk *to_clksrc(struct clk *clk) -{ - return container_of(clk, struct clksrc_clk, clk); -} - -static unsigned long s3c64xx_getrate_clksrc(struct clk *clk) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - unsigned long rate = clk_get_rate(clk->parent); - u32 clkdiv = __raw_readl(sclk->reg_divider); - - clkdiv >>= sclk->divider_shift; - clkdiv &= 0xf; - clkdiv++; - - rate /= clkdiv; - return rate; -} - -static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - void __iomem *reg = sclk->reg_divider; - unsigned int div; - u32 val; - - rate = clk_round_rate(clk, rate); - div = clk_get_rate(clk->parent) / rate; - if (div > 16) - return -EINVAL; - - val = __raw_readl(reg); - val &= ~(0xf << sclk->divider_shift); - val |= (div - 1) << sclk->divider_shift; - __raw_writel(val, reg); - - return 0; -} - -static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - struct clk_sources *srcs = sclk->sources; - u32 clksrc = __raw_readl(S3C_CLK_SRC); - int src_nr = -1; - int ptr; - - for (ptr = 0; ptr < srcs->nr_sources; ptr++) - if (srcs->sources[ptr] == parent) { - src_nr = ptr; - break; - } - - if (src_nr >= 0) { - clksrc &= ~sclk->mask; - clksrc |= src_nr << sclk->shift; - - __raw_writel(clksrc, S3C_CLK_SRC); - - clk->parent = parent; - return 0; - } - - return -EINVAL; -} - -static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - rate = parent_rate; - else { - div = parent_rate / rate; - - if (div == 0) - div = 1; - if (div > 16) - div = 16; - - rate = parent_rate / div; - } - - return rate; -} - -static struct clksrc_clk clk_mmc0 = { - .clk = { - .name = "mmc_bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_MMC0, - .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_MMC0_SHIFT, - .mask = S3C6400_CLKSRC_MMC0_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT, - .reg_divider = S3C_CLK_DIV1, -}; - -static struct clksrc_clk clk_mmc1 = { - .clk = { - .name = "mmc_bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_MMC1, - .enable = s3c64xx_sclk_ctrl, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .set_parent = s3c64xx_setparent_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_MMC1_SHIFT, - .mask = S3C6400_CLKSRC_MMC1_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT, - .reg_divider = S3C_CLK_DIV1, -}; - -static struct clksrc_clk clk_mmc2 = { - .clk = { - .name = "mmc_bus", - .id = 2, - .ctrlbit = S3C_CLKCON_SCLK_MMC2, - .enable = s3c64xx_sclk_ctrl, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .set_parent = s3c64xx_setparent_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_MMC2_SHIFT, - .mask = S3C6400_CLKSRC_MMC2_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT, - .reg_divider = S3C_CLK_DIV1, -}; - -static struct clksrc_clk clk_usbhost = { - .clk = { - .name = "usb-bus-host", - .id = -1, - .ctrlbit = S3C_CLKCON_SCLK_UHOST, - .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_UHOST_SHIFT, - .mask = S3C6400_CLKSRC_UHOST_MASK, - .sources = &clkset_uhost, - .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT, - .reg_divider = S3C_CLK_DIV1, -}; - -static struct clksrc_clk clk_uart_uclk1 = { - .clk = { - .name = "uclk1", - .id = -1, - .ctrlbit = S3C_CLKCON_SCLK_UART, - .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_UART_SHIFT, - .mask = S3C6400_CLKSRC_UART_MASK, - .sources = &clkset_uart, - .divider_shift = S3C6400_CLKDIV2_UART_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - -/* Where does UCLK0 come from? */ - -static struct clksrc_clk clk_spi0 = { - .clk = { - .name = "spi-bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_SPI0, - .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_SPI0_SHIFT, - .mask = S3C6400_CLKSRC_SPI0_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - -static struct clksrc_clk clk_spi1 = { - .clk = { - .name = "spi-bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_SPI1, - .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_SPI1_SHIFT, - .mask = S3C6400_CLKSRC_SPI1_MASK, - .sources = &clkset_spi_mmc, - .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; +/* clocks that feed other parts of the clock source tree */ static struct clk clk_iis_cd0 = { .name = "iis_cdclk0", @@ -505,29 +278,11 @@ static struct clk *clkset_audio0_list[] = { [4] = &clk_pcm_cd, }; -static struct clk_sources clkset_audio0 = { +static struct clksrc_sources clkset_audio0 = { .sources = clkset_audio0_list, .nr_sources = ARRAY_SIZE(clkset_audio0_list), }; -static struct clksrc_clk clk_audio0 = { - .clk = { - .name = "audio-bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, - .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, - .mask = S3C6400_CLKSRC_AUDIO0_MASK, - .sources = &clkset_audio0, - .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - static struct clk *clkset_audio1_list[] = { [0] = &clk_mout_epll.clk, [1] = &clk_dout_mpll, @@ -536,72 +291,133 @@ static struct clk *clkset_audio1_list[] = { [4] = &clk_pcm_cd, }; -static struct clk_sources clkset_audio1 = { +static struct clksrc_sources clkset_audio1 = { .sources = clkset_audio1_list, .nr_sources = ARRAY_SIZE(clkset_audio1_list), }; -static struct clksrc_clk clk_audio1 = { - .clk = { - .name = "audio-bus", - .id = 1, - .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, - .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, - .mask = S3C6400_CLKSRC_AUDIO1_MASK, - .sources = &clkset_audio1, - .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - -static struct clksrc_clk clk_irda = { - .clk = { - .name = "irda-bus", - .id = 0, - .ctrlbit = S3C_CLKCON_SCLK_IRDA, - .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, - }, - .shift = S3C6400_CLKSRC_IRDA_SHIFT, - .mask = S3C6400_CLKSRC_IRDA_MASK, - .sources = &clkset_irda, - .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT, - .reg_divider = S3C_CLK_DIV2, -}; - static struct clk *clkset_camif_list[] = { &clk_h2, }; -static struct clk_sources clkset_camif = { +static struct clksrc_sources clkset_camif = { .sources = clkset_camif_list, .nr_sources = ARRAY_SIZE(clkset_camif_list), }; -static struct clksrc_clk clk_camif = { - .clk = { - .name = "camera", - .id = -1, - .ctrlbit = S3C_CLKCON_SCLK_CAM, - .enable = s3c64xx_sclk_ctrl, - .set_parent = s3c64xx_setparent_clksrc, - .get_rate = s3c64xx_getrate_clksrc, - .set_rate = s3c64xx_setrate_clksrc, - .round_rate = s3c64xx_roundrate_clksrc, +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_MMC0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_MMC1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = S3C_CLKCON_SCLK_MMC2, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "usb-bus-host", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_UHOST, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 5, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 }, + .sources = &clkset_uhost, + }, { + .clk = { + .name = "uclk1", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_UART, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, + .sources = &clkset_uart, + }, { +/* Where does UCLK0 come from? */ + .clk = { + .name = "spi-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_SPI0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "spi-bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_SPI1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 }, + .sources = &clkset_spi_mmc, + }, { + .clk = { + .name = "audio-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 7, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 }, + .sources = &clkset_audio0, + }, { + .clk = { + .name = "audio-bus", + .id = 1, + .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 }, + .sources = &clkset_audio1, + }, { + .clk = { + .name = "irda-bus", + .id = 0, + .ctrlbit = S3C_CLKCON_SCLK_IRDA, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg = S3C_CLK_SRC, .shift = 24, .size = 2 }, + .reg_div = { .reg = S3C_CLK_DIV2, .shift = 20, .size = 4 }, + .sources = &clkset_irda, + }, { + .clk = { + .name = "camera", + .id = -1, + .ctrlbit = S3C_CLKCON_SCLK_CAM, + .enable = s3c64xx_sclk_ctrl, + }, + .reg_div = { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4 }, + .reg_src = { .reg = NULL, .shift = 0, .size = 0 }, + .sources = &clkset_camif, }, - .shift = 0, - .mask = 0, - .sources = &clkset_camif, - .divider_shift = S3C6400_CLKDIV0_CAM_SHIFT, - .reg_divider = S3C_CLK_DIV0, }; /* Clock initialisation code */ @@ -610,39 +426,7 @@ static struct clksrc_clk *init_parents[] = { &clk_mout_apll, &clk_mout_epll, &clk_mout_mpll, - &clk_mmc0, - &clk_mmc1, - &clk_mmc2, - &clk_usbhost, - &clk_uart_uclk1, - &clk_spi0, - &clk_spi1, - &clk_audio0, - &clk_audio1, - &clk_irda, - &clk_camif, -}; - -static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) -{ - struct clk_sources *srcs = clk->sources; - u32 clksrc = __raw_readl(S3C_CLK_SRC); - - clksrc &= clk->mask; - clksrc >>= clk->shift; - - if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { - printk(KERN_ERR "%s: bad source %d\n", - clk->clk.name, clksrc); - return; - } - - clk->clk.parent = srcs->sources[clksrc]; - - printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", - clk->clk.name, clk->clk.parent->name, clksrc, - clk_get_rate(&clk->clk)); -} +}; #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) @@ -702,7 +486,10 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) clk_f.rate = fclk; for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s3c6400_set_clksrc(init_parents[ptr]); + s3c_set_clksrc(init_parents[ptr], true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_set_clksrc(&clksrcs[ptr], true); } static struct clk *clks[] __initdata = { @@ -713,17 +500,6 @@ static struct clk *clks[] __initdata = { &clk_mout_epll.clk, &clk_mout_mpll.clk, &clk_dout_mpll, - &clk_mmc0.clk, - &clk_mmc1.clk, - &clk_mmc2.clk, - &clk_usbhost.clk, - &clk_uart_uclk1.clk, - &clk_spi0.clk, - &clk_spi1.clk, - &clk_audio0.clk, - &clk_audio1.clk, - &clk_irda.clk, - &clk_camif.clk, &clk_arm, }; @@ -755,4 +531,6 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit) clkp->name, ret); } } + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); } diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig new file mode 100644 index 000000000000..e7c31e7060e5 --- /dev/null +++ b/arch/arm/plat-s5p/Kconfig @@ -0,0 +1,42 @@ +# arch/arm/plat-s5p/Kconfig +# +# Copyright (c) 2009 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +config PLAT_S5P + bool + depends on ARCH_S5P6440 + default y + select PLAT_S3C + select ARM_VIC + select NO_IOPORT + select ARCH_REQUIRE_GPIOLIB + select S3C_GPIO_TRACK + select SAMSUNG_GPIOLIB_4BIT + select S3C_GPIO_CFG_S3C64XX + select S3C_GPIO_PULL_UPDOWN + select S3C_GPIO_CFG_S3C24XX + select PLAT_SAMSUNG + select SAMSUNG_CLKSRC + select SAMSUNG_IRQ_VIC_TIMER + select SAMSUNG_IRQ_UART + help + Base platform code for Samsung's S5P series SoC. + +if (PLAT_S5P && ARCH_S5P6440) + +# Configuration options shared by all S5P64XX implementations + +config CPU_S5P6440_INIT + bool + help + Initialisation code for the S5P6440. + +config CPU_S5P6440_CLOCK + bool + help + Clock support code for the S5P6440. + +endif diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile new file mode 100644 index 000000000000..92b647450542 --- /dev/null +++ b/arch/arm/plat-s5p/Makefile @@ -0,0 +1,24 @@ +# arch/arm/plat-s5p/Makefile +# +# Copyright (c) 2009 Samsung Electronics Co., Ltd. +# http://www.samsung.com/ +# +# Licensed under GPLv2 + +obj-y := +obj-m := +obj-n := dummy.o +obj- := + +# Core files + +obj-y += dev-uart.o +obj-y += cpu.o +obj-y += clock.o +obj-y += irq.o +obj-y += setup-i2c0.o + +# CPU support + +obj-$(CONFIG_CPU_S5P6440_INIT) += s5p6440-init.o +obj-$(CONFIG_CPU_S5P6440_CLOCK) += s5p6440-clock.o diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c new file mode 100644 index 000000000000..3d3c0f1934fc --- /dev/null +++ b/arch/arm/plat-s5p/clock.c @@ -0,0 +1,136 @@ +/* linux/arch/arm/plat-s5p/clock.c + * + * Copyright 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P - Common clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/sysdev.h> +#include <linux/io.h> +#include <asm/div64.h> + +#include <plat/clock.h> +#include <plat/clock-clksrc.h> +#include <plat/s5p-clock.h> + +/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call + * clk_ext_xtal_mux. +*/ +struct clk clk_ext_xtal_mux = { + .name = "ext_xtal", + .id = -1, +}; + +/* 48MHz USB Phy clock output */ +struct clk clk_48m = { + .name = "clk_48m", + .id = -1, + .rate = 48000000, +}; + +/* APLL clock output + * No need .ctrlbit, this is always on +*/ +struct clk clk_fout_apll = { + .name = "fout_apll", + .id = -1, +}; + +/* MPLL clock output + * No need .ctrlbit, this is always on +*/ +struct clk clk_fout_mpll = { + .name = "fout_mpll", + .id = -1, +}; + +/* EPLL clock output */ +struct clk clk_fout_epll = { + .name = "fout_epll", + .id = -1, + .ctrlbit = (1 << 31), +}; + +/* ARM clock */ +struct clk clk_arm = { + .name = "armclk", + .id = -1, + .rate = 0, + .ctrlbit = 0, +}; + +/* Possible clock sources for APLL Mux */ +static struct clk *clk_src_apll_list[] = { + [0] = &clk_fin_apll, + [1] = &clk_fout_apll, +}; + +struct clksrc_sources clk_src_apll = { + .sources = clk_src_apll_list, + .nr_sources = ARRAY_SIZE(clk_src_apll_list), +}; + +/* Possible clock sources for MPLL Mux */ +static struct clk *clk_src_mpll_list[] = { + [0] = &clk_fin_mpll, + [1] = &clk_fout_mpll, +}; + +struct clksrc_sources clk_src_mpll = { + .sources = clk_src_mpll_list, + .nr_sources = ARRAY_SIZE(clk_src_mpll_list), +}; + +/* Possible clock sources for EPLL Mux */ +static struct clk *clk_src_epll_list[] = { + [0] = &clk_fin_epll, + [1] = &clk_fout_epll, +}; + +struct clksrc_sources clk_src_epll = { + .sources = clk_src_epll_list, + .nr_sources = ARRAY_SIZE(clk_src_epll_list), +}; + +int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + u32 con; + + con = __raw_readl(reg); + con = enable ? (con | ctrlbit) : (con & ~ctrlbit); + __raw_writel(con, reg); + return 0; +} + +static struct clk *s5p_clks[] __initdata = { + &clk_ext_xtal_mux, + &clk_48m, + &clk_fout_apll, + &clk_fout_mpll, + &clk_fout_epll, + &clk_arm, +}; + +void __init s5p_register_clocks(unsigned long xtal_freq) +{ + int ret; + + clk_ext_xtal_mux.rate = xtal_freq; + + ret = s3c24xx_register_clocks(s5p_clks, ARRAY_SIZE(s5p_clks)); + if (ret > 0) + printk(KERN_ERR "Failed to register s5p clocks\n"); +} diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c new file mode 100644 index 000000000000..0895a77a2835 --- /dev/null +++ b/arch/arm/plat-s5p/cpu.c @@ -0,0 +1,90 @@ +/* linux/arch/arm/plat-s5p/cpu.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P CPU Support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <mach/map.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> +#include <mach/regs-clock.h> +#include <plat/cpu.h> +#include <plat/s5p6440.h> + +/* table of supported CPUs */ + +static const char name_s5p6440[] = "S5P6440"; + +static struct cpu_table cpu_ids[] __initdata = { + { + .idcode = 0x56440100, + .idmask = 0xffffff00, + .map_io = s5p6440_map_io, + .init_clocks = s5p6440_init_clocks, + .init_uarts = s5p6440_init_uarts, + .init = s5p6440_init, + .name = name_s5p6440, + }, +}; + +/* minimal IO mapping */ + +#define UART_OFFS (S5P_PA_UART & 0xfffff) + +static struct map_desc s5p_iodesc[] __initdata = { + { + .virtual = (unsigned long)S5P_VA_SYSCON, + .pfn = __phys_to_pfn(S5P_PA_SYSCON), + .length = SZ_64K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)(S5P_VA_UART + UART_OFFS), + .pfn = __phys_to_pfn(S5P_PA_UART), + .length = SZ_4K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_VIC0, + .pfn = __phys_to_pfn(S5P_PA_VIC0), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_VIC1, + .pfn = __phys_to_pfn(S5P_PA_VIC1), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_TIMER, + .pfn = __phys_to_pfn(S5P_PA_TIMER), + .length = SZ_16K, + .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_GPIO, + .pfn = __phys_to_pfn(S5P_PA_GPIO), + .length = SZ_4K, + .type = MT_DEVICE, + }, +}; + +/* read cpu identification code */ + +void __init s5p_init_io(struct map_desc *mach_desc, + int size, void __iomem *cpuid_addr) +{ + unsigned long idcode; + + /* initialize the io descriptors we need for initialization */ + iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc)); + if (mach_desc) + iotable_init(mach_desc, size); + + idcode = __raw_readl(cpuid_addr); + s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); +} diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c new file mode 100644 index 000000000000..23c75316d491 --- /dev/null +++ b/arch/arm/plat-s5p/dev-uart.c @@ -0,0 +1,137 @@ +/* linux/arch/arm/plat-s5p/dev-uart.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Base S5P UART resource and device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/platform_device.h> + +#include <asm/mach/arch.h> +#include <asm/mach/irq.h> +#include <mach/hardware.h> +#include <mach/map.h> + +#include <plat/devs.h> + + /* Serial port registrations */ + +static struct resource s5p_uart0_resource[] = { + [0] = { + .start = S5P_PA_UART0, + .end = S5P_PA_UART0 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX0, + .end = IRQ_S5P_UART_RX0, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX0, + .end = IRQ_S5P_UART_TX0, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR0, + .end = IRQ_S5P_UART_ERR0, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource s5p_uart1_resource[] = { + [0] = { + .start = S5P_PA_UART1, + .end = S5P_PA_UART1 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX1, + .end = IRQ_S5P_UART_RX1, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX1, + .end = IRQ_S5P_UART_TX1, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR1, + .end = IRQ_S5P_UART_ERR1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource s5p_uart2_resource[] = { + [0] = { + .start = S5P_PA_UART2, + .end = S5P_PA_UART2 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX2, + .end = IRQ_S5P_UART_RX2, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX2, + .end = IRQ_S5P_UART_TX2, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR2, + .end = IRQ_S5P_UART_ERR2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource s5p_uart3_resource[] = { + [0] = { + .start = S5P_PA_UART3, + .end = S5P_PA_UART3 + S5P_SZ_UART, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = IRQ_S5P_UART_RX3, + .end = IRQ_S5P_UART_RX3, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = IRQ_S5P_UART_TX3, + .end = IRQ_S5P_UART_TX3, + .flags = IORESOURCE_IRQ, + }, + [3] = { + .start = IRQ_S5P_UART_ERR3, + .end = IRQ_S5P_UART_ERR3, + .flags = IORESOURCE_IRQ, + }, +}; + +struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = { + [0] = { + .resources = s5p_uart0_resource, + .nr_resources = ARRAY_SIZE(s5p_uart0_resource), + }, + [1] = { + .resources = s5p_uart1_resource, + .nr_resources = ARRAY_SIZE(s5p_uart1_resource), + }, + [2] = { + .resources = s5p_uart2_resource, + .nr_resources = ARRAY_SIZE(s5p_uart2_resource), + }, + [3] = { + .resources = s5p_uart3_resource, + .nr_resources = ARRAY_SIZE(s5p_uart3_resource), + }, +}; diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h new file mode 100644 index 000000000000..5d7937dddad2 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/irqs.h @@ -0,0 +1,83 @@ +/* linux/arch/arm/plat-s5p/include/plat/irqs.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P Common IRQ support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_IRQS_H +#define __ASM_PLAT_S5P_IRQS_H __FILE__ + +/* we keep the first set of CPU IRQs out of the range of + * the ISA space, so that the PC104 has them to itself + * and we don't end up having to do horrible things to the + * standard ISA drivers.... + * + * note, since we're using the VICs, our start must be a + * mulitple of 32 to allow the common code to work + */ + +#define S5P_IRQ_OFFSET (32) + +#define S5P_IRQ(x) ((x) + S5P_IRQ_OFFSET) + +#define S5P_VIC0_BASE S5P_IRQ(0) +#define S5P_VIC1_BASE S5P_IRQ(32) + +#define IRQ_VIC0_BASE S5P_VIC0_BASE +#define IRQ_VIC1_BASE S5P_VIC1_BASE + +/* UART interrupts, each UART has 4 intterupts per channel so + * use the space between the ISA and S3C main interrupts. Note, these + * are not in the same order as the S3C24XX series! */ + +#define IRQ_S5P_UART_BASE0 (16) +#define IRQ_S5P_UART_BASE1 (20) +#define IRQ_S5P_UART_BASE2 (24) +#define IRQ_S5P_UART_BASE3 (28) + +#define UART_IRQ_RXD (0) +#define UART_IRQ_ERR (1) +#define UART_IRQ_TXD (2) + +#define IRQ_S5P_UART_RX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX0 (IRQ_S5P_UART_BASE0 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR0 (IRQ_S5P_UART_BASE0 + UART_IRQ_ERR) + +#define IRQ_S5P_UART_RX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX1 (IRQ_S5P_UART_BASE1 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR1 (IRQ_S5P_UART_BASE1 + UART_IRQ_ERR) + +#define IRQ_S5P_UART_RX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX2 (IRQ_S5P_UART_BASE2 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR2 (IRQ_S5P_UART_BASE2 + UART_IRQ_ERR) + +#define IRQ_S5P_UART_RX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_RXD) +#define IRQ_S5P_UART_TX3 (IRQ_S5P_UART_BASE3 + UART_IRQ_TXD) +#define IRQ_S5P_UART_ERR3 (IRQ_S5P_UART_BASE3 + UART_IRQ_ERR) + +/* S3C compatibilty defines */ +#define IRQ_S3CUART_RX0 IRQ_S5P_UART_RX0 +#define IRQ_S3CUART_RX1 IRQ_S5P_UART_RX1 +#define IRQ_S3CUART_RX2 IRQ_S5P_UART_RX2 +#define IRQ_S3CUART_RX3 IRQ_S5P_UART_RX3 + +/* VIC based IRQs */ + +#define S5P_IRQ_VIC0(x) (S5P_VIC0_BASE + (x)) +#define S5P_IRQ_VIC1(x) (S5P_VIC1_BASE + (x)) + +#define S5P_TIMER_IRQ(x) S5P_IRQ(64 + (x)) + +#define IRQ_TIMER0 S5P_TIMER_IRQ(0) +#define IRQ_TIMER1 S5P_TIMER_IRQ(1) +#define IRQ_TIMER2 S5P_TIMER_IRQ(2) +#define IRQ_TIMER3 S5P_TIMER_IRQ(3) +#define IRQ_TIMER4 S5P_TIMER_IRQ(4) + +#endif /* __ASM_PLAT_S5P_IRQS_H */ diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h new file mode 100644 index 000000000000..d48325bb29e2 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/pll.h @@ -0,0 +1,83 @@ +/* arch/arm/plat-s5p/include/plat/pll.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P PLL code + * + * Based on arch/arm/plat-s3c64xx/include/plat/pll.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define PLL45XX_MDIV_MASK (0x3FF) +#define PLL45XX_PDIV_MASK (0x3F) +#define PLL45XX_SDIV_MASK (0x7) +#define PLL45XX_MDIV_SHIFT (16) +#define PLL45XX_PDIV_SHIFT (8) +#define PLL45XX_SDIV_SHIFT (0) + +#include <asm/div64.h> + +enum pll45xx_type_t { + pll_4500, + pll_4502, + pll_4508 +}; + +static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con, + enum pll45xx_type_t pll_type) +{ + u32 mdiv, pdiv, sdiv; + u64 fvco = baseclk; + + mdiv = (pll_con >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; + pdiv = (pll_con >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; + sdiv = (pll_con >> PLL45XX_SDIV_SHIFT) & PLL45XX_SDIV_MASK; + + if (pll_type == pll_4508) + sdiv = sdiv - 1; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +#define PLL90XX_MDIV_MASK (0xFF) +#define PLL90XX_PDIV_MASK (0x3F) +#define PLL90XX_SDIV_MASK (0x7) +#define PLL90XX_KDIV_MASK (0xffff) +#define PLL90XX_MDIV_SHIFT (16) +#define PLL90XX_PDIV_SHIFT (8) +#define PLL90XX_SDIV_SHIFT (0) +#define PLL90XX_KDIV_SHIFT (0) + +static inline unsigned long s5p_get_pll90xx(unsigned long baseclk, + u32 pll_con, u32 pll_conk) +{ + unsigned long result; + u32 mdiv, pdiv, sdiv, kdiv; + u64 tmp; + + mdiv = (pll_con >> PLL90XX_MDIV_SHIFT) & PLL90XX_MDIV_MASK; + pdiv = (pll_con >> PLL90XX_PDIV_SHIFT) & PLL90XX_PDIV_MASK; + sdiv = (pll_con >> PLL90XX_SDIV_SHIFT) & PLL90XX_SDIV_MASK; + kdiv = pll_conk & PLL90XX_KDIV_MASK; + + /* We need to multiple baseclk by mdiv (the integer part) and kdiv + * which is in 2^16ths, so shift mdiv up (does not overflow) and + * add kdiv before multiplying. The use of tmp is to avoid any + * overflows before shifting bac down into result when multipling + * by the mdiv and kdiv pair. + */ + + tmp = baseclk; + tmp *= (mdiv << 16) + kdiv; + do_div(tmp, (pdiv << sdiv)); + result = tmp >> 16; + + return result; +} diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h new file mode 100644 index 000000000000..e1a7444b8829 --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h @@ -0,0 +1,38 @@ +/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h + * + * Copyright 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5p clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S5P_CLOCK_H +#define __ASM_PLAT_S5P_CLOCK_H __FILE__ + +#include <linux/clk.h> + +#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) + +#define clk_fin_apll clk_ext_xtal_mux +#define clk_fin_mpll clk_ext_xtal_mux +#define clk_fin_epll clk_ext_xtal_mux + +extern struct clk clk_ext_xtal_mux; +extern struct clk clk_48m; +extern struct clk clk_fout_apll; +extern struct clk clk_fout_mpll; +extern struct clk clk_fout_epll; +extern struct clk clk_arm; + +extern struct clksrc_sources clk_src_apll; +extern struct clksrc_sources clk_src_mpll; +extern struct clksrc_sources clk_src_epll; + +extern int s5p6440_clk48m_ctrl(struct clk *clk, int enable); +extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); + +#endif /* __ASM_PLAT_S5P_CLOCK_H */ diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-s5p/include/plat/s5p6440.h new file mode 100644 index 000000000000..a4cd75afeb3b --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5p6440.h @@ -0,0 +1,37 @@ +/* arch/arm/plat-s5p/include/plat/s5p6440.h + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Header file for s5p6440 cpu support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + + /* Common init code for S5P6440 related SoCs */ + +extern void s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); +extern void s5p6440_register_clocks(void); +extern void s5p6440_setup_clocks(void); + +#ifdef CONFIG_CPU_S5P6440 + +extern int s5p6440_init(void); +extern void s5p6440_init_irq(void); +extern void s5p6440_map_io(void); +extern void s5p6440_init_clocks(int xtal); + +#define s5p6440_init_uarts s5p6440_common_init_uarts + +#else +#define s5p6440_init_clocks NULL +#define s5p6440_init_uarts NULL +#define s5p6440_map_io NULL +#define s5p6440_init NULL +#endif + +/* S5P6440 timer */ + +extern struct sys_timer s5p6440_timer; diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c new file mode 100644 index 000000000000..eada40d0847d --- /dev/null +++ b/arch/arm/plat-s5p/irq.c @@ -0,0 +1,73 @@ +/* arch/arm/plat-s5p/irq.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P - Interrupt handling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <asm/hardware/vic.h> + +#include <linux/serial_core.h> +#include <mach/map.h> +#include <plat/regs-timer.h> +#include <plat/regs-serial.h> +#include <plat/cpu.h> +#include <plat/irq-vic-timer.h> +#include <plat/irq-uart.h> + +#define VIC_VAADDR(no) (S5P_VA_VIC0 + ((no)*0x10000)) +#define VIC_BASE(no) (S5P_VIC0_BASE + ((no)*32)) + +/* + * Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] + * are consecutive when looking up the interrupt in the demux routines. + */ +static struct s3c_uart_irq uart_irqs[] = { + [0] = { + .regs = S5P_VA_UART0, + .base_irq = IRQ_S5P_UART_BASE0, + .parent_irq = IRQ_UART0, + }, + [1] = { + .regs = S5P_VA_UART1, + .base_irq = IRQ_S5P_UART_BASE1, + .parent_irq = IRQ_UART1, + }, + [2] = { + .regs = S5P_VA_UART2, + .base_irq = IRQ_S5P_UART_BASE2, + .parent_irq = IRQ_UART2, + }, + [3] = { + .regs = S5P_VA_UART3, + .base_irq = IRQ_S5P_UART_BASE3, + .parent_irq = IRQ_UART3, + }, +}; + +void __init s5p_init_irq(u32 *vic, u32 num_vic) +{ + int irq; + + /* initialize the VICs */ + for (irq = 0; irq < num_vic; irq++) + vic_init(VIC_VAADDR(irq), VIC_BASE(irq), vic[irq], 0); + + s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); + s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); + s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); + s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); + s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); + + s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); +} diff --git a/arch/arm/plat-s5p/s5p6440-clock.c b/arch/arm/plat-s5p/s5p6440-clock.c new file mode 100644 index 000000000000..2f412f8c1212 --- /dev/null +++ b/arch/arm/plat-s5p/s5p6440-clock.c @@ -0,0 +1,698 @@ +/* linux/arch/arm/plat-s5p/s5p6440-clock.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * S5P6440 - Clock support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/sysdev.h> +#include <linux/io.h> + +#include <mach/hardware.h> +#include <mach/map.h> + +#include <plat/cpu-freq.h> +#include <mach/regs-clock.h> +#include <plat/clock.h> +#include <plat/cpu.h> +#include <plat/clock-clksrc.h> +#include <plat/s5p-clock.h> +#include <plat/pll.h> +#include <plat/s5p6440.h> + +/* APLL Mux output clock */ +static struct clksrc_clk clk_mout_apll = { + .clk = { + .name = "mout_apll", + .id = -1, + }, + .sources = &clk_src_apll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, +}; + +static int s5p6440_epll_enable(struct clk *clk, int enable) +{ + unsigned int ctrlbit = clk->ctrlbit; + unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; + + if (enable) + __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); + else + __raw_writel(epll_con, S5P_EPLL_CON); + + return 0; +} + +static unsigned long s5p6440_epll_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static u32 epll_div[][5] = { + { 36000000, 0, 48, 1, 4 }, + { 48000000, 0, 32, 1, 3 }, + { 60000000, 0, 40, 1, 3 }, + { 72000000, 0, 48, 1, 3 }, + { 84000000, 0, 28, 1, 2 }, + { 96000000, 0, 32, 1, 2 }, + { 32768000, 45264, 43, 1, 4 }, + { 45158000, 6903, 30, 1, 3 }, + { 49152000, 50332, 32, 1, 3 }, + { 67738000, 10398, 45, 1, 3 }, + { 73728000, 9961, 49, 1, 3 } +}; + +static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int epll_con, epll_con_k; + unsigned int i; + + if (clk->rate == rate) /* Return if nothing changed */ + return 0; + + epll_con = __raw_readl(S5P_EPLL_CON); + epll_con_k = __raw_readl(S5P_EPLL_CON_K); + + epll_con_k &= ~(PLL90XX_KDIV_MASK); + epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK); + + for (i = 0; i < ARRAY_SIZE(epll_div); i++) { + if (epll_div[i][0] == rate) { + epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT); + epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) | + (epll_div[i][3] << PLL90XX_PDIV_SHIFT) | + (epll_div[i][4] << PLL90XX_SDIV_SHIFT); + break; + } + } + + if (i == ARRAY_SIZE(epll_div)) { + printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); + return -EINVAL; + } + + __raw_writel(epll_con, S5P_EPLL_CON); + __raw_writel(epll_con_k, S5P_EPLL_CON_K); + + clk->rate = rate; + + return 0; +} + +static struct clk_ops s5p6440_epll_ops = { + .get_rate = s5p6440_epll_get_rate, + .set_rate = s5p6440_epll_set_rate, +}; + +static struct clksrc_clk clk_mout_epll = { + .clk = { + .name = "mout_epll", + .id = -1, + }, + .sources = &clk_src_epll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 }, +}; + +static struct clksrc_clk clk_mout_mpll = { + .clk = { + .name = "mout_mpll", + .id = -1, + }, + .sources = &clk_src_mpll, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, +}; + +static struct clk clk_h_low = { + .name = "hclk_low", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, + .ops = &clk_ops_def_setrate, +}; + +static struct clk clk_p_low = { + .name = "pclk_low", + .id = -1, + .rate = 0, + .parent = NULL, + .ctrlbit = 0, + .ops = &clk_ops_def_setrate, +}; + +enum perf_level { + L0 = 532*1000, + L1 = 266*1000, + L2 = 133*1000, +}; + +static const u32 clock_table[][3] = { + /*{ARM_CLK, DIVarm, DIVhclk}*/ + {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)}, + {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)}, + {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)}, +}; + +static unsigned long s5p6440_armclk_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + u32 clkdiv; + + /* divisor mask starts at bit0, so no need to shift */ + clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK; + + return rate / (clkdiv + 1); +} + +static unsigned long s5p6440_armclk_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 iter; + + for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) { + if (rate > clock_table[iter][0]) + return clock_table[iter-1][0]; + } + + return clock_table[ARRAY_SIZE(clock_table) - 1][0]; +} + +static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 round_tmp; + u32 iter; + u32 clk_div0_tmp; + u32 cur_rate = clk->ops->get_rate(clk); + unsigned long flags; + + round_tmp = clk->ops->round_rate(clk, rate); + if (round_tmp == cur_rate) + return 0; + + + for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) { + if (round_tmp == clock_table[iter][0]) + break; + } + + if (iter >= ARRAY_SIZE(clock_table)) + iter = ARRAY_SIZE(clock_table) - 1; + + local_irq_save(flags); + if (cur_rate > round_tmp) { + /* Frequency Down */ + clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); + clk_div0_tmp |= clock_table[iter][1]; + __raw_writel(clk_div0_tmp, ARM_CLK_DIV); + + clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & + ~(S5P_CLKDIV0_HCLK_MASK); + clk_div0_tmp |= clock_table[iter][2]; + __raw_writel(clk_div0_tmp, ARM_CLK_DIV); + + + } else { + /* Frequency Up */ + clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & + ~(S5P_CLKDIV0_HCLK_MASK); + clk_div0_tmp |= clock_table[iter][2]; + __raw_writel(clk_div0_tmp, ARM_CLK_DIV); + + clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); + clk_div0_tmp |= clock_table[iter][1]; + __raw_writel(clk_div0_tmp, ARM_CLK_DIV); + } + local_irq_restore(flags); + + clk->rate = clock_table[iter][0]; + + return 0; +} + +static struct clk_ops s5p6440_clkarm_ops = { + .get_rate = s5p6440_armclk_get_rate, + .set_rate = s5p6440_armclk_set_rate, + .round_rate = s5p6440_armclk_round_rate, +}; + +static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + + if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK) + rate /= 2; + + return rate; +} + +static struct clk clk_dout_mpll = { + .name = "dout_mpll", + .id = -1, + .parent = &clk_mout_mpll.clk, + .ops = &(struct clk_ops) { + .get_rate = s5p6440_clk_doutmpll_get_rate, + }, +}; + +int s5p6440_clk48m_ctrl(struct clk *clk, int enable) +{ + unsigned long flags; + u32 val; + + /* can't rely on clock lock, this register has other usages */ + local_irq_save(flags); + + val = __raw_readl(S5P_OTHERS); + if (enable) + val |= S5P_OTHERS_USB_SIG_MASK; + else + val &= ~S5P_OTHERS_USB_SIG_MASK; + + __raw_writel(val, S5P_OTHERS); + + local_irq_restore(flags); + + return 0; +} + +static int s5p6440_pclk_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable); +} + +static int s5p6440_hclk0_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable); +} + +static int s5p6440_hclk1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable); +} + +static int s5p6440_sclk_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); +} + +static int s5p6440_mem_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); +} + +/* + * The following clocks will be disabled during clock initialization. It is + * recommended to keep the following clocks disabled until the driver requests + * for enabling the clock. + */ +static struct clk init_clocks_disable[] = { + { + .name = "nand", + .id = -1, + .parent = &clk_h, + .enable = s5p6440_mem_ctrl, + .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, + }, { + .name = "adc", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_TSADC, + }, { + .name = "i2c", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_IIC0, + }, { + .name = "i2s_v40", + .id = 0, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_IIS2, + }, { + .name = "spi", + .id = 0, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_SPI0, + }, { + .name = "spi", + .id = 1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_SPI1, + }, { + .name = "sclk_spi_48", + .id = 0, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_SPI0_48, + }, { + .name = "sclk_spi_48", + .id = 1, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_SPI1_48, + }, { + .name = "mmc_48m", + .id = 0, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_MMC0_48, + }, { + .name = "mmc_48m", + .id = 1, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_MMC1_48, + }, { + .name = "mmc_48m", + .id = 2, + .parent = &clk_48m, + .enable = s5p6440_sclk_ctrl, + .ctrlbit = S5P_CLKCON_SCLK0_MMC2_48, + }, { + .name = "otg", + .id = -1, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_USB + }, { + .name = "post", + .id = -1, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_POST0 + }, { + .name = "lcd", + .id = -1, + .parent = &clk_h_low, + .enable = s5p6440_hclk1_ctrl, + .ctrlbit = S5P_CLKCON_HCLK1_DISPCON, + }, { + .name = "hsmmc", + .id = 0, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, + }, { + .name = "hsmmc", + .id = 1, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, + }, { + .name = "hsmmc", + .id = 2, + .parent = &clk_h_low, + .enable = s5p6440_hclk0_ctrl, + .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, + }, { + .name = "rtc", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_RTC, + }, { + .name = "watchdog", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_WDT, + }, { + .name = "timers", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_PWM, + } +}; + +/* + * The following clocks will be enabled during clock initialization. + */ +static struct clk init_clocks[] = { + { + .name = "gpio", + .id = -1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_GPIO, + }, { + .name = "uart", + .id = 0, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_UART0, + }, { + .name = "uart", + .id = 1, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_UART1, + }, { + .name = "uart", + .id = 2, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_UART2, + }, { + .name = "uart", + .id = 3, + .parent = &clk_p_low, + .enable = s5p6440_pclk_ctrl, + .ctrlbit = S5P_CLKCON_PCLK_UART3, + } +}; + +static struct clk clk_iis_cd_v40 = { + .name = "iis_cdclk_v40", + .id = -1, +}; + +static struct clk clk_pcm_cd = { + .name = "pcm_cdclk", + .id = -1, +}; + +static struct clk *clkset_spi_mmc_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, + &clk_fin_epll, +}; + +static struct clksrc_sources clkset_spi_mmc = { + .sources = clkset_spi_mmc_list, + .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), +}; + +static struct clk *clkset_uart_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll +}; + +static struct clksrc_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), +}; + +static struct clksrc_clk clksrcs[] = { + { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = S5P_CLKCON_SCLK0_MMC0, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = S5P_CLKCON_SCLK0_MMC1, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, + }, { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = S5P_CLKCON_SCLK0_MMC2, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, + }, { + .clk = { + .name = "uclk1", + .id = -1, + .ctrlbit = S5P_CLKCON_SCLK0_UART, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_uart, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 }, + }, { + .clk = { + .name = "spi_epll", + .id = 0, + .ctrlbit = S5P_CLKCON_SCLK0_SPI0, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "spi_epll", + .id = 1, + .ctrlbit = S5P_CLKCON_SCLK0_SPI1, + .enable = s5p6440_sclk_ctrl, + }, + .sources = &clkset_spi_mmc, + .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, + .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, + } +}; + +/* Clock initialisation code */ +static struct clksrc_clk *init_parents[] = { + &clk_mout_apll, + &clk_mout_epll, + &clk_mout_mpll, +}; + +void __init_or_cpufreq s5p6440_setup_clocks(void) +{ + struct clk *xtal_clk; + unsigned long xtal; + unsigned long fclk; + unsigned long hclk; + unsigned long hclk_low; + unsigned long pclk; + unsigned long pclk_low; + unsigned long epll; + unsigned long apll; + unsigned long mpll; + unsigned int ptr; + u32 clkdiv0; + u32 clkdiv3; + + /* Set S5P6440 functions for clk_fout_epll */ + clk_fout_epll.enable = s5p6440_epll_enable; + clk_fout_epll.ops = &s5p6440_epll_ops; + + /* Set S5P6440 functions for arm clock */ + clk_arm.parent = &clk_mout_apll.clk; + clk_arm.ops = &s5p6440_clkarm_ops; + clk_48m.enable = s5p6440_clk48m_ctrl; + + clkdiv0 = __raw_readl(S5P_CLK_DIV0); + clkdiv3 = __raw_readl(S5P_CLK_DIV3); + + xtal_clk = clk_get(NULL, "ext_xtal"); + BUG_ON(IS_ERR(xtal_clk)); + + xtal = clk_get_rate(xtal_clk); + clk_put(xtal_clk); + + epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON), + __raw_readl(S5P_EPLL_CON_K)); + mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); + apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); + + printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ + " E=%ld.%ldMHz\n", + print_mhz(apll), print_mhz(mpll), print_mhz(epll)); + + fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); + hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); + pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); + + if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { + /* Asynchronous mode */ + hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); + } else { + /* Synchronous mode */ + hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); + } + + pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW); + + printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ + " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", + print_mhz(hclk), print_mhz(hclk_low), + print_mhz(pclk), print_mhz(pclk_low)); + + clk_fout_mpll.rate = mpll; + clk_fout_epll.rate = epll; + clk_fout_apll.rate = apll; + + clk_f.rate = fclk; + clk_h.rate = hclk; + clk_p.rate = pclk; + clk_h_low.rate = hclk_low; + clk_p_low.rate = pclk_low; + + for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) + s3c_set_clksrc(init_parents[ptr], true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) + s3c_set_clksrc(&clksrcs[ptr], true); +} + +static struct clk *clks[] __initdata = { + &clk_ext, + &clk_mout_epll.clk, + &clk_mout_mpll.clk, + &clk_dout_mpll, + &clk_iis_cd_v40, + &clk_pcm_cd, + &clk_p_low, + &clk_h_low, +}; + +void __init s5p6440_register_clocks(void) +{ + struct clk *clkp; + int ret; + int ptr; + + ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); + if (ret > 0) + printk(KERN_ERR "Failed to register %u clocks\n", ret); + + s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); + s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); + + clkp = init_clocks_disable; + for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { + + ret = s3c24xx_register_clock(clkp); + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + (clkp->enable)(clkp, 0); + } + + s3c_pwmclk_init(); +} diff --git a/arch/arm/plat-s5p/s5p6440-init.c b/arch/arm/plat-s5p/s5p6440-init.c new file mode 100644 index 000000000000..90178256cc28 --- /dev/null +++ b/arch/arm/plat-s5p/s5p6440-init.c @@ -0,0 +1,50 @@ +/* linux/arch/arm/plat-s5p/s5p6440-init.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/init.h> +#include <linux/serial_core.h> + +#include <plat/cpu.h> +#include <plat/devs.h> +#include <plat/s5p6440.h> +#include <plat/regs-serial.h> + +static struct s3c24xx_uart_clksrc s5p6440_serial_clocks[] = { + [0] = { + .name = "pclk_low", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, + [1] = { + .name = "uclk1", + .divisor = 1, + .min_baud = 0, + .max_baud = 0, + }, +}; + +/* uart registration process */ +void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) +{ + struct s3c2410_uartcfg *tcfg = cfg; + u32 ucnt; + + for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { + if (!tcfg->clocks) { + tcfg->clocks = s5p6440_serial_clocks; + tcfg->clocks_size = ARRAY_SIZE(s5p6440_serial_clocks); + } + } + + s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); +} diff --git a/arch/arm/plat-s5p/setup-i2c0.c b/arch/arm/plat-s5p/setup-i2c0.c new file mode 100644 index 000000000000..67a66e02a97a --- /dev/null +++ b/arch/arm/plat-s5p/setup-i2c0.c @@ -0,0 +1,25 @@ +/* linux/arch/arm/plat-s5p/setup-i2c0.c + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * I2C0 GPIO configuration. + * + * Based on plat-s3c64xx/setup-i2c0.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/kernel.h> +#include <linux/types.h> + +struct platform_device; /* don't need the contents */ + +#include <plat/iic.h> + +void s3c_i2c0_cfg_gpio(struct platform_device *dev) +{ + /* Will be populated later */ +} diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index b7b9e91c0243..c7ccdf22eefa 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig @@ -11,6 +11,9 @@ config PLAT_S5PC1XX select ARM_VIC select NO_IOPORT select ARCH_REQUIRE_GPIOLIB + select SAMSUNG_CLKSRC + select SAMSUNG_IRQ_UART + select SAMSUNG_IRQ_VIC_TIMER select S3C_GPIO_TRACK select S3C_GPIO_PULL_UPDOWN select S3C_GPIO_CFG_S3C24XX diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c index 26c21d849790..387f23190c3c 100644 --- a/arch/arm/plat-s5pc1xx/clock.c +++ b/arch/arm/plat-s5pc1xx/clock.c @@ -64,25 +64,13 @@ struct clk clk_54m = { .rate = 54000000, }; -static int clk_default_setrate(struct clk *clk, unsigned long rate) -{ - clk->rate = rate; - return 0; -} - -static int clk_dummy_enable(struct clk *clk, int enable) -{ - return 0; -} - struct clk clk_hd0 = { .name = "hclkd0", .id = -1, .rate = 0, .parent = NULL, .ctrlbit = 0, - .set_rate = clk_default_setrate, - .enable = clk_dummy_enable, + .ops = &clk_ops_def_setrate, }; struct clk clk_pd0 = { @@ -91,8 +79,7 @@ struct clk clk_pd0 = { .rate = 0, .parent = NULL, .ctrlbit = 0, - .set_rate = clk_default_setrate, - .enable = clk_dummy_enable, + .ops = &clk_ops_def_setrate, }; static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) @@ -686,6 +673,8 @@ static struct clk s5pc100_init_clocks[] = { static struct clk *clks[] __initdata = { &clk_ext, &clk_epll, + &clk_pd0, + &clk_hd0, &clk_27m, &clk_48m, &clk_54m, @@ -700,16 +689,8 @@ void __init s5pc1xx_register_clocks(void) s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); - clkp = s5pc100_init_clocks; - size = ARRAY_SIZE(s5pc100_init_clocks); - - for (ptr = 0; ptr < size; ptr++, clkp++) { - ret = s3c24xx_register_clock(clkp); - if (ret < 0) { - printk(KERN_ERR "Failed to register clock %s (%d)\n", - clkp->name, ret); - } - } + s3c_register_clocks(s5pc100_init_clocks, + ARRAY_SIZE(s5pc100_init_clocks)); clkp = s5pc100_init_clocks_disable; size = ARRAY_SIZE(s5pc100_init_clocks_disable); diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c index f749bc5407b5..586c95c60bfe 100644 --- a/arch/arm/plat-s5pc1xx/dev-uart.c +++ b/arch/arm/plat-s5pc1xx/dev-uart.c @@ -143,32 +143,3 @@ struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = { .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource), }, }; - -/* uart devices */ - -static struct platform_device s3c24xx_uart_device0 = { - .id = 0, -}; - -static struct platform_device s3c24xx_uart_device1 = { - .id = 1, -}; - -static struct platform_device s3c24xx_uart_device2 = { - .id = 2, -}; - -static struct platform_device s3c24xx_uart_device3 = { - .id = 3, -}; - -struct platform_device *s3c24xx_uart_src[4] = { - &s3c24xx_uart_device0, - &s3c24xx_uart_device1, - &s3c24xx_uart_device2, - &s3c24xx_uart_device3, -}; - -struct platform_device *s3c24xx_uart_devs[4] = { -}; - diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c index bba675df9c75..a4f67e80a150 100644 --- a/arch/arm/plat-s5pc1xx/gpio-config.c +++ b/arch/arm/plat-s5pc1xx/gpio-config.c @@ -16,7 +16,7 @@ #include <linux/gpio.h> #include <linux/io.h> -#include <mach/gpio-core.h> +#include <plat/gpio-core.h> #include <plat/gpio-cfg-s5pc1xx.h> s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c index facb410e7a71..1ffc57ac293d 100644 --- a/arch/arm/plat-s5pc1xx/gpiolib.c +++ b/arch/arm/plat-s5pc1xx/gpiolib.c @@ -17,8 +17,8 @@ #include <linux/gpio.h> #include <mach/map.h> -#include <mach/gpio-core.h> +#include <plat/gpio-core.h> #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> #include <plat/regs-gpio.h> diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h index ef8736366f0d..409c804315e8 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h +++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h @@ -88,11 +88,11 @@ #define IRQ_MDMA S5PC1XX_IRQ_VIC0(18) #define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19) #define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20) -#define IRQ_TIMER0 S5PC1XX_IRQ_VIC0(21) -#define IRQ_TIMER1 S5PC1XX_IRQ_VIC0(22) -#define IRQ_TIMER2 S5PC1XX_IRQ_VIC0(23) -#define IRQ_TIMER3 S5PC1XX_IRQ_VIC0(24) -#define IRQ_TIMER4 S5PC1XX_IRQ_VIC0(25) +#define IRQ_TIMER0_VIC S5PC1XX_IRQ_VIC0(21) +#define IRQ_TIMER1_VIC S5PC1XX_IRQ_VIC0(22) +#define IRQ_TIMER2_VIC S5PC1XX_IRQ_VIC0(23) +#define IRQ_TIMER3_VIC S5PC1XX_IRQ_VIC0(24) +#define IRQ_TIMER4_VIC S5PC1XX_IRQ_VIC0(25) #define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26) #define IRQ_WDT S5PC1XX_IRQ_VIC0(27) #define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28) @@ -171,8 +171,15 @@ #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) +#define IRQ_TIMER(x) (IRQ_SDMFIQ + 1 + (x)) +#define IRQ_TIMER0 IRQ_TIMER(0) +#define IRQ_TIMER1 IRQ_TIMER(1) +#define IRQ_TIMER2 IRQ_TIMER(2) +#define IRQ_TIMER3 IRQ_TIMER(3) +#define IRQ_TIMER4 IRQ_TIMER(4) + /* External interrupt */ -#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) +#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 6) #define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) #define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h index c5cc86e92d65..24dec4e52538 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h @@ -61,73 +61,10 @@ #define S5PC100_EPLL_MASK 0xffffffff #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) -/* CLKSRC0 */ -#define S5PC100_CLKSRC0_APLL_MASK (0x1<<0) -#define S5PC100_CLKSRC0_APLL_SHIFT (0) -#define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4) -#define S5PC100_CLKSRC0_MPLL_SHIFT (4) -#define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8) -#define S5PC100_CLKSRC0_EPLL_SHIFT (8) -#define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) -#define S5PC100_CLKSRC0_HPLL_SHIFT (12) -#define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) -#define S5PC100_CLKSRC0_AMMUX_SHIFT (16) -#define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) -#define S5PC100_CLKSRC0_HREF_SHIFT (20) -#define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24) -#define S5PC100_CLKSRC0_ONENAND_SHIFT (24) - - -/* CLKSRC1 */ -#define S5PC100_CLKSRC1_UART_MASK (0x1<<0) -#define S5PC100_CLKSRC1_UART_SHIFT (0) -#define S5PC100_CLKSRC1_SPI0_MASK (0x3<<4) -#define S5PC100_CLKSRC1_SPI0_SHIFT (4) -#define S5PC100_CLKSRC1_SPI1_MASK (0x3<<8) -#define S5PC100_CLKSRC1_SPI1_SHIFT (8) -#define S5PC100_CLKSRC1_SPI2_MASK (0x3<<12) -#define S5PC100_CLKSRC1_SPI2_SHIFT (12) -#define S5PC100_CLKSRC1_IRDA_MASK (0x3<<16) -#define S5PC100_CLKSRC1_IRDA_SHIFT (16) -#define S5PC100_CLKSRC1_UHOST_MASK (0x3<<20) -#define S5PC100_CLKSRC1_UHOST_SHIFT (20) -#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) +/* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */ +#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) #define S5PC100_CLKSRC1_CLK48M_SHIFT (24) -/* CLKSRC2 */ -#define S5PC100_CLKSRC2_MMC0_MASK (0x3<<0) -#define S5PC100_CLKSRC2_MMC0_SHIFT (0) -#define S5PC100_CLKSRC2_MMC1_MASK (0x3<<4) -#define S5PC100_CLKSRC2_MMC1_SHIFT (4) -#define S5PC100_CLKSRC2_MMC2_MASK (0x3<<8) -#define S5PC100_CLKSRC2_MMC2_SHIFT (8) -#define S5PC100_CLKSRC2_LCD_MASK (0x3<<12) -#define S5PC100_CLKSRC2_LCD_SHIFT (12) -#define S5PC100_CLKSRC2_FIMC0_MASK (0x3<<16) -#define S5PC100_CLKSRC2_FIMC0_SHIFT (16) -#define S5PC100_CLKSRC2_FIMC1_MASK (0x3<<20) -#define S5PC100_CLKSRC2_FIMC1_SHIFT (20) -#define S5PC100_CLKSRC2_FIMC2_MASK (0x3<<24) -#define S5PC100_CLKSRC2_FIMC2_SHIFT (24) -#define S5PC100_CLKSRC2_MIXER_MASK (0x3<<28) -#define S5PC100_CLKSRC2_MIXER_SHIFT (28) - -/* CLKSRC3 */ -#define S5PC100_CLKSRC3_PWI_MASK (0x3<<0) -#define S5PC100_CLKSRC3_PWI_SHIFT (0) -#define S5PC100_CLKSRC3_HCLKD2_MASK (0x1<<4) -#define S5PC100_CLKSRC3_HCLKD2_SHIFT (4) -#define S5PC100_CLKSRC3_I2SD2_MASK (0x3<<8) -#define S5PC100_CLKSRC3_I2SD2_SHIFT (8) -#define S5PC100_CLKSRC3_AUDIO0_MASK (0x7<<12) -#define S5PC100_CLKSRC3_AUDIO0_SHIFT (12) -#define S5PC100_CLKSRC3_AUDIO1_MASK (0x7<<16) -#define S5PC100_CLKSRC3_AUDIO1_SHIFT (16) -#define S5PC100_CLKSRC3_AUDIO2_MASK (0x7<<20) -#define S5PC100_CLKSRC3_AUDIO2_SHIFT (20) -#define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) -#define S5PC100_CLKSRC3_SPDIF_SHIFT (24) - /* CLKDIV0 */ #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) #define S5PC100_CLKDIV0_APLL_SHIFT (0) @@ -140,7 +77,7 @@ #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) #define S5PC100_CLKDIV0_SECSS_SHIFT (16) -/* CLKDIV1 */ +/* CLKDIV1 (OneNAND clock only used in one place, removed) */ #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) #define S5PC100_CLKDIV1_APLL2_SHIFT (0) #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) @@ -151,56 +88,12 @@ #define S5PC100_CLKDIV1_D1_SHIFT (12) #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) -#define S5PC100_CLKDIV1_ONENAND_MASK (0x3<<20) -#define S5PC100_CLKDIV1_ONENAND_SHIFT (20) #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) #define S5PC100_CLKDIV1_CAM_SHIFT (24) -/* CLKDIV2 */ -#define S5PC100_CLKDIV2_UART_MASK (0x7<<0) -#define S5PC100_CLKDIV2_UART_SHIFT (0) -#define S5PC100_CLKDIV2_SPI0_MASK (0xf<<4) -#define S5PC100_CLKDIV2_SPI0_SHIFT (4) -#define S5PC100_CLKDIV2_SPI1_MASK (0xf<<8) -#define S5PC100_CLKDIV2_SPI1_SHIFT (8) -#define S5PC100_CLKDIV2_SPI2_MASK (0xf<<12) -#define S5PC100_CLKDIV2_SPI2_SHIFT (12) -#define S5PC100_CLKDIV2_IRDA_MASK (0xf<<16) -#define S5PC100_CLKDIV2_IRDA_SHIFT (16) -#define S5PC100_CLKDIV2_UHOST_MASK (0xf<<20) -#define S5PC100_CLKDIV2_UHOST_SHIFT (20) - -/* CLKDIV3 */ -#define S5PC100_CLKDIV3_MMC0_MASK (0xf<<0) -#define S5PC100_CLKDIV3_MMC0_SHIFT (0) -#define S5PC100_CLKDIV3_MMC1_MASK (0xf<<4) -#define S5PC100_CLKDIV3_MMC1_SHIFT (4) -#define S5PC100_CLKDIV3_MMC2_MASK (0xf<<8) -#define S5PC100_CLKDIV3_MMC2_SHIFT (8) -#define S5PC100_CLKDIV3_LCD_MASK (0xf<<12) -#define S5PC100_CLKDIV3_LCD_SHIFT (12) -#define S5PC100_CLKDIV3_FIMC0_MASK (0xf<<16) -#define S5PC100_CLKDIV3_FIMC0_SHIFT (16) -#define S5PC100_CLKDIV3_FIMC1_MASK (0xf<<20) -#define S5PC100_CLKDIV3_FIMC1_SHIFT (20) -#define S5PC100_CLKDIV3_FIMC2_MASK (0xf<<24) -#define S5PC100_CLKDIV3_FIMC2_SHIFT (24) -#define S5PC100_CLKDIV3_HDMI_MASK (0xf<<28) -#define S5PC100_CLKDIV3_HDMI_SHIFT (28) - -/* CLKDIV4 */ -#define S5PC100_CLKDIV4_PWI_MASK (0x7<<0) -#define S5PC100_CLKDIV4_PWI_SHIFT (0) -#define S5PC100_CLKDIV4_HCLKD2_MASK (0x7<<4) -#define S5PC100_CLKDIV4_HCLKD2_SHIFT (4) -#define S5PC100_CLKDIV4_I2SD2_MASK (0xf<<8) -#define S5PC100_CLKDIV4_I2SD2_SHIFT (8) -#define S5PC100_CLKDIV4_AUDIO0_MASK (0xf<<12) -#define S5PC100_CLKDIV4_AUDIO0_SHIFT (12) -#define S5PC100_CLKDIV4_AUDIO1_MASK (0xf<<16) -#define S5PC100_CLKDIV4_AUDIO1_SHIFT (16) -#define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) -#define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) +/* CLKDIV2 => removed in clksrc update */ +/* CLKDIV3 => removed in clksrc update, or not needed */ +/* CLKDIV4 => removed in clksrc update, or not needed */ /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ #define S5PC100_CLKGATE_D00_INTC (1<<0) diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c index e44fd04ef333..bfc524827819 100644 --- a/arch/arm/plat-s5pc1xx/irq.c +++ b/arch/arm/plat-s5pc1xx/irq.c @@ -20,87 +20,14 @@ #include <asm/hardware/vic.h> #include <mach/map.h> -#include <plat/regs-timer.h> +#include <plat/irq-vic-timer.h> +#include <plat/irq-uart.h> #include <plat/cpu.h> -/* Timer interrupt handling */ - -static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) -{ - generic_handle_irq(sub_irq); -} - -static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER0); -} - -static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER1); -} - -static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER2); -} - -static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER3); -} - -static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) -{ - s3c_irq_demux_timer(irq, IRQ_TIMER4); -} - -/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ - -static void s3c_irq_timer_mask(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg &= ~(1 << (irq - IRQ_TIMER0)); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_unmask(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg |= 1 << (irq - IRQ_TIMER0); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static void s3c_irq_timer_ack(unsigned int irq) -{ - u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); - - reg &= 0x1f; /* mask out pending interrupts */ - reg |= (1 << 5) << (irq - IRQ_TIMER0); - __raw_writel(reg, S3C64XX_TINT_CSTAT); -} - -static struct irq_chip s3c_irq_timer = { - .name = "s3c-timer", - .mask = s3c_irq_timer_mask, - .unmask = s3c_irq_timer_unmask, - .ack = s3c_irq_timer_ack, -}; - -struct uart_irq { - void __iomem *regs; - unsigned int base_irq; - unsigned int parent_irq; -}; - /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] * are consecutive when looking up the interrupt in the demux routines. */ -static struct uart_irq uart_irqs[] = { +static struct s3c_uart_irq uart_irqs[] = { [0] = { .regs = (void *)S3C_VA_UART0, .base_irq = IRQ_S3CUART_BASE0, @@ -123,113 +50,9 @@ static struct uart_irq uart_irqs[] = { }, }; -static inline void __iomem *s3c_irq_uart_base(unsigned int irq) -{ - struct uart_irq *uirq = get_irq_chip_data(irq); - return uirq->regs; -} - -static inline unsigned int s3c_irq_uart_bit(unsigned int irq) -{ - return irq & 3; -} - -/* UART interrupt registers, not worth adding to seperate include header */ -#define S3C64XX_UINTP 0x30 -#define S3C64XX_UINTSP 0x34 -#define S3C64XX_UINTM 0x38 - -static void s3c_irq_uart_mask(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_maskack(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg |= (1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_uart_unmask(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - u32 reg; - - reg = __raw_readl(regs + S3C64XX_UINTM); - reg &= ~(1 << bit); - __raw_writel(reg, regs + S3C64XX_UINTM); -} - -static void s3c_irq_uart_ack(unsigned int irq) -{ - void __iomem *regs = s3c_irq_uart_base(irq); - unsigned int bit = s3c_irq_uart_bit(irq); - - __raw_writel(1 << bit, regs + S3C64XX_UINTP); -} - -static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) -{ - struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; - u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); - int base = uirq->base_irq; - - if (pend & (1 << 0)) - generic_handle_irq(base); - if (pend & (1 << 1)) - generic_handle_irq(base + 1); - if (pend & (1 << 2)) - generic_handle_irq(base + 2); - if (pend & (1 << 3)) - generic_handle_irq(base + 3); -} - -static struct irq_chip s3c_irq_uart = { - .name = "s3c-uart", - .mask = s3c_irq_uart_mask, - .unmask = s3c_irq_uart_unmask, - .mask_ack = s3c_irq_uart_maskack, - .ack = s3c_irq_uart_ack, -}; - -static void __init s5pc1xx_uart_irq(struct uart_irq *uirq) -{ - void __iomem *reg_base = uirq->regs; - unsigned int irq; - int offs; - - /* mask all interrupts at the start. */ - __raw_writel(0xf, reg_base + S3C64XX_UINTM); - - for (offs = 0; offs < 3; offs++) { - irq = uirq->base_irq + offs; - - set_irq_chip(irq, &s3c_irq_uart); - set_irq_chip_data(irq, uirq); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } - - set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); -} - void __init s5pc1xx_init_irq(u32 *vic_valid, int num) { int i; - int uart, irq; printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); @@ -240,20 +63,13 @@ void __init s5pc1xx_init_irq(u32 *vic_valid, int num) /* add the timer sub-irqs */ - set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0); - set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1); - set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2); - set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3); - set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4); - - for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { - set_irq_chip(irq, &s3c_irq_timer); - set_irq_handler(irq, handle_level_irq); - set_irq_flags(irq, IRQF_VALID); - } + s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); + s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); + s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); + s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); + s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); - for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) - s5pc1xx_uart_irq(&uart_irqs[uart]); + s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); } diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c index b436d44510c8..2bf6c57a96a2 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c @@ -29,6 +29,7 @@ #include <plat/regs-clock.h> #include <plat/clock.h> +#include <plat/clock-clksrc.h> #include <plat/cpu.h> #include <plat/pll.h> #include <plat/devs.h> @@ -51,23 +52,6 @@ static struct clk clk_ext_xtal_mux = { #define clk_fout_mpll clk_mpll #define clk_vclk_54m clk_54m -struct clk_sources { - unsigned int nr_sources; - struct clk **sources; -}; - -struct clksrc_clk { - struct clk clk; - unsigned int mask; - unsigned int shift; - - struct clk_sources *sources; - - unsigned int divider_shift; - void __iomem *reg_divider; - void __iomem *reg_source; -}; - /* APLL */ static struct clk clk_fout_apll = { .name = "fout_apll", @@ -80,7 +64,7 @@ static struct clk *clk_src_apll_list[] = { [1] = &clk_fout_apll, }; -static struct clk_sources clk_src_apll = { +static struct clksrc_sources clk_src_apll = { .sources = clk_src_apll_list, .nr_sources = ARRAY_SIZE(clk_src_apll_list), }; @@ -90,10 +74,8 @@ static struct clksrc_clk clk_mout_apll = { .name = "mout_apll", .id = -1, }, - .shift = S5PC100_CLKSRC0_APLL_SHIFT, - .mask = S5PC100_CLKSRC0_APLL_MASK, .sources = &clk_src_apll, - .reg_source = S5PC100_CLKSRC0, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 0, .size = 1, }, }; static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) @@ -111,7 +93,9 @@ static struct clk clk_dout_apll = { .name = "dout_apll", .id = -1, .parent = &clk_mout_apll.clk, - .get_rate = s5pc100_clk_dout_apll_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_apll_get_rate, + }, }; static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) @@ -165,9 +149,11 @@ static struct clk clk_arm = { .name = "armclk", .id = -1, .parent = &clk_dout_apll, - .get_rate = s5pc100_clk_arm_get_rate, - .set_rate = s5pc100_clk_arm_set_rate, - .round_rate = s5pc100_clk_arm_round_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_arm_get_rate, + .set_rate = s5pc100_clk_arm_set_rate, + .round_rate = s5pc100_clk_arm_round_rate, + }, }; static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) @@ -185,7 +171,9 @@ static struct clk clk_dout_d0_bus = { .name = "dout_d0_bus", .id = -1, .parent = &clk_arm, - .get_rate = s5pc100_clk_dout_d0_bus_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_d0_bus_get_rate, + }, }; static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) @@ -203,7 +191,9 @@ static struct clk clk_dout_pclkd0 = { .name = "dout_pclkd0", .id = -1, .parent = &clk_dout_d0_bus, - .get_rate = s5pc100_clk_dout_pclkd0_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_pclkd0_get_rate, + }, }; static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) @@ -221,7 +211,9 @@ static struct clk clk_dout_apll2 = { .name = "dout_apll2", .id = -1, .parent = &clk_mout_apll.clk, - .get_rate = s5pc100_clk_dout_apll2_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_apll2_get_rate, + }, }; /* MPLL */ @@ -230,7 +222,7 @@ static struct clk *clk_src_mpll_list[] = { [1] = &clk_fout_mpll, }; -static struct clk_sources clk_src_mpll = { +static struct clksrc_sources clk_src_mpll = { .sources = clk_src_mpll_list, .nr_sources = ARRAY_SIZE(clk_src_mpll_list), }; @@ -240,10 +232,8 @@ static struct clksrc_clk clk_mout_mpll = { .name = "mout_mpll", .id = -1, }, - .shift = S5PC100_CLKSRC0_MPLL_SHIFT, - .mask = S5PC100_CLKSRC0_MPLL_MASK, .sources = &clk_src_mpll, - .reg_source = S5PC100_CLKSRC0, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 4, .size = 1, }, }; static struct clk *clkset_am_list[] = { @@ -251,7 +241,7 @@ static struct clk *clkset_am_list[] = { [1] = &clk_dout_apll2, }; -static struct clk_sources clk_src_am = { +static struct clksrc_sources clk_src_am = { .sources = clkset_am_list, .nr_sources = ARRAY_SIZE(clkset_am_list), }; @@ -261,10 +251,8 @@ static struct clksrc_clk clk_mout_am = { .name = "mout_am", .id = -1, }, - .shift = S5PC100_CLKSRC0_AMMUX_SHIFT, - .mask = S5PC100_CLKSRC0_AMMUX_MASK, .sources = &clk_src_am, - .reg_source = S5PC100_CLKSRC0, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 16, .size = 1, }, }; static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) @@ -284,7 +272,9 @@ static struct clk clk_dout_d1_bus = { .name = "dout_d1_bus", .id = -1, .parent = &clk_mout_am.clk, - .get_rate = s5pc100_clk_dout_d1_bus_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_d1_bus_get_rate, + }, }; static struct clk *clkset_onenand_list[] = { @@ -292,7 +282,7 @@ static struct clk *clkset_onenand_list[] = { [1] = &clk_dout_d1_bus, }; -static struct clk_sources clk_src_onenand = { +static struct clksrc_sources clk_src_onenand = { .sources = clkset_onenand_list, .nr_sources = ARRAY_SIZE(clkset_onenand_list), }; @@ -302,10 +292,8 @@ static struct clksrc_clk clk_mout_onenand = { .name = "mout_onenand", .id = -1, }, - .shift = S5PC100_CLKSRC0_ONENAND_SHIFT, - .mask = S5PC100_CLKSRC0_ONENAND_MASK, .sources = &clk_src_onenand, - .reg_source = S5PC100_CLKSRC0, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 24, .size = 1, }, }; static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) @@ -325,7 +313,9 @@ static struct clk clk_dout_pclkd1 = { .name = "dout_pclkd1", .id = -1, .parent = &clk_dout_d1_bus, - .get_rate = s5pc100_clk_dout_pclkd1_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_pclkd1_get_rate, + }, }; static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) @@ -345,7 +335,9 @@ static struct clk clk_dout_mpll2 = { .name = "dout_mpll2", .id = -1, .parent = &clk_mout_am.clk, - .get_rate = s5pc100_clk_dout_mpll2_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_mpll2_get_rate, + }, }; static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) @@ -365,7 +357,9 @@ static struct clk clk_dout_cam = { .name = "dout_cam", .id = -1, .parent = &clk_dout_mpll2, - .get_rate = s5pc100_clk_dout_cam_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_cam_get_rate, + }, }; static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) @@ -385,7 +379,9 @@ static struct clk clk_dout_mpll = { .name = "dout_mpll", .id = -1, .parent = &clk_mout_am.clk, - .get_rate = s5pc100_clk_dout_mpll_get_rate, + .ops = &(struct clk_ops) { + .get_rate = s5pc100_clk_dout_mpll_get_rate, + }, }; /* EPLL */ @@ -399,7 +395,7 @@ static struct clk *clk_src_epll_list[] = { [1] = &clk_fout_epll, }; -static struct clk_sources clk_src_epll = { +static struct clksrc_sources clk_src_epll = { .sources = clk_src_epll_list, .nr_sources = ARRAY_SIZE(clk_src_epll_list), }; @@ -409,10 +405,8 @@ static struct clksrc_clk clk_mout_epll = { .name = "mout_epll", .id = -1, }, - .shift = S5PC100_CLKSRC0_EPLL_SHIFT, - .mask = S5PC100_CLKSRC0_EPLL_MASK, - .sources = &clk_src_epll, - .reg_source = S5PC100_CLKSRC0, + .sources = &clk_src_epll, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 8, .size = 1, }, }; /* HPLL */ @@ -426,7 +420,7 @@ static struct clk *clk_src_hpll_list[] = { [1] = &clk_fout_hpll, }; -static struct clk_sources clk_src_hpll = { +static struct clksrc_sources clk_src_hpll = { .sources = clk_src_hpll_list, .nr_sources = ARRAY_SIZE(clk_src_hpll_list), }; @@ -436,10 +430,8 @@ static struct clksrc_clk clk_mout_hpll = { .name = "mout_hpll", .id = -1, }, - .shift = S5PC100_CLKSRC0_HPLL_SHIFT, - .mask = S5PC100_CLKSRC0_HPLL_MASK, - .sources = &clk_src_hpll, - .reg_source = S5PC100_CLKSRC0, + .sources = &clk_src_hpll, + .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 12, .size = 1, }, }; /* Peripherals */ @@ -454,190 +446,6 @@ static struct clksrc_clk clk_mout_hpll = { * have a common parent divisor so are not included here. */ -static inline struct clksrc_clk *to_clksrc(struct clk *clk) -{ - return container_of(clk, struct clksrc_clk, clk); -} - -static unsigned long s5pc100_getrate_clksrc(struct clk *clk) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - unsigned long rate = clk_get_rate(clk->parent); - u32 clkdiv = __raw_readl(sclk->reg_divider); - - clkdiv >>= sclk->divider_shift; - clkdiv &= 0xf; - clkdiv++; - - rate /= clkdiv; - return rate; -} - -static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - void __iomem *reg = sclk->reg_divider; - unsigned int div; - u32 val; - - rate = clk_round_rate(clk, rate); - div = clk_get_rate(clk->parent) / rate; - if (div > 16) - return -EINVAL; - - val = __raw_readl(reg); - val &= ~(0xf << sclk->divider_shift); - val |= (div - 1) << sclk->divider_shift; - __raw_writel(val, reg); - - return 0; -} - -static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent) -{ - struct clksrc_clk *sclk = to_clksrc(clk); - struct clk_sources *srcs = sclk->sources; - u32 clksrc = __raw_readl(sclk->reg_source); - int src_nr = -1; - int ptr; - - for (ptr = 0; ptr < srcs->nr_sources; ptr++) - if (srcs->sources[ptr] == parent) { - src_nr = ptr; - break; - } - - if (src_nr >= 0) { - clksrc &= ~sclk->mask; - clksrc |= src_nr << sclk->shift; - - __raw_writel(clksrc, sclk->reg_source); - return 0; - } - - return -EINVAL; -} - -static unsigned long s5pc100_roundrate_clksrc(struct clk *clk, - unsigned long rate) -{ - unsigned long parent_rate = clk_get_rate(clk->parent); - int div; - - if (rate > parent_rate) - rate = parent_rate; - else { - div = rate / parent_rate; - - if (div == 0) - div = 1; - if (div > 16) - div = 16; - - rate = parent_rate / div; - } - - return rate; -} - -static struct clk *clkset_spi_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll2, - &clk_fin_epll, - &clk_mout_hpll.clk, -}; - -static struct clk_sources clkset_spi = { - .sources = clkset_spi_list, - .nr_sources = ARRAY_SIZE(clkset_spi_list), -}; - -static struct clksrc_clk clk_spi0 = { - .clk = { - .name = "spi_bus", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, - .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC1_SPI0_SHIFT, - .mask = S5PC100_CLKSRC1_SPI0_MASK, - .sources = &clkset_spi, - .divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, -}; - -static struct clksrc_clk clk_spi1 = { - .clk = { - .name = "spi_bus", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, - .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC1_SPI1_SHIFT, - .mask = S5PC100_CLKSRC1_SPI1_MASK, - .sources = &clkset_spi, - .divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, -}; - -static struct clksrc_clk clk_spi2 = { - .clk = { - .name = "spi_bus", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, - .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC1_SPI2_SHIFT, - .mask = S5PC100_CLKSRC1_SPI2_MASK, - .sources = &clkset_spi, - .divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, -}; - -static struct clk *clkset_uart_list[] = { - &clk_mout_epll.clk, - &clk_dout_mpll, -}; - -static struct clk_sources clkset_uart = { - .sources = clkset_uart_list, - .nr_sources = ARRAY_SIZE(clkset_uart_list), -}; - -static struct clksrc_clk clk_uart_uclk1 = { - .clk = { - .name = "uclk1", - .id = -1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, - .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC1_UART_SHIFT, - .mask = S5PC100_CLKSRC1_UART_MASK, - .sources = &clkset_uart, - .divider_shift = S5PC100_CLKDIV2_UART_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, -}; - static struct clk clk_iis_cd0 = { .name = "iis_cdclk0", .id = -1, @@ -672,28 +480,31 @@ static struct clk *clkset_audio0_list[] = { &clk_mout_hpll.clk, }; -static struct clk_sources clkset_audio0 = { +static struct clksrc_sources clkset_audio0 = { .sources = clkset_audio0_list, .nr_sources = ARRAY_SIZE(clkset_audio0_list), }; -static struct clksrc_clk clk_audio0 = { - .clk = { - .name = "audio-bus", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, - .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, - .mask = S5PC100_CLKSRC3_AUDIO0_MASK, - .sources = &clkset_audio0, - .divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT, - .reg_divider = S5PC100_CLKDIV4, - .reg_source = S5PC100_CLKSRC3, +static struct clk *clkset_spi_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll2, + &clk_fin_epll, + &clk_mout_hpll.clk, +}; + +static struct clksrc_sources clkset_spi = { + .sources = clkset_spi_list, + .nr_sources = ARRAY_SIZE(clkset_spi_list), +}; + +static struct clk *clkset_uart_list[] = { + &clk_mout_epll.clk, + &clk_dout_mpll, +}; + +static struct clksrc_sources clkset_uart = { + .sources = clkset_uart_list, + .nr_sources = ARRAY_SIZE(clkset_uart_list), }; static struct clk *clkset_audio1_list[] = { @@ -705,30 +516,11 @@ static struct clk *clkset_audio1_list[] = { &clk_mout_hpll.clk, }; -static struct clk_sources clkset_audio1 = { +static struct clksrc_sources clkset_audio1 = { .sources = clkset_audio1_list, .nr_sources = ARRAY_SIZE(clkset_audio1_list), }; -static struct clksrc_clk clk_audio1 = { - .clk = { - .name = "audio-bus", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, - .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT, - .mask = S5PC100_CLKSRC3_AUDIO1_MASK, - .sources = &clkset_audio1, - .divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT, - .reg_divider = S5PC100_CLKDIV4, - .reg_source = S5PC100_CLKSRC3, -}; - static struct clk *clkset_audio2_list[] = { &clk_mout_epll.clk, &clk_dout_mpll, @@ -737,52 +529,56 @@ static struct clk *clkset_audio2_list[] = { &clk_mout_hpll.clk, }; -static struct clk_sources clkset_audio2 = { +static struct clksrc_sources clkset_audio2 = { .sources = clkset_audio2_list, .nr_sources = ARRAY_SIZE(clkset_audio2_list), }; -static struct clksrc_clk clk_audio2 = { - .clk = { - .name = "audio-bus", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, - .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, +static struct clksrc_clk clksrc_audio[] = { + { + .clk = { + .name = "audio-bus", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_audio0, + .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, + }, { + .clk = { + .name = "audio-bus", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_audio1, + .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, + }, { + .clk = { + .name = "audio-bus", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_audio2, + .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, }, - .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT, - .mask = S5PC100_CLKSRC3_AUDIO2_MASK, - .sources = &clkset_audio2, - .divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT, - .reg_divider = S5PC100_CLKDIV4, - .reg_source = S5PC100_CLKSRC3, }; static struct clk *clkset_spdif_list[] = { - &clk_audio0.clk, - &clk_audio1.clk, - &clk_audio2.clk, + &clksrc_audio[0].clk, + &clksrc_audio[1].clk, + &clksrc_audio[2].clk, }; -static struct clk_sources clkset_spdif = { +static struct clksrc_sources clkset_spdif = { .sources = clkset_spdif_list, .nr_sources = ARRAY_SIZE(clkset_spdif_list), }; -static struct clksrc_clk clk_spdif = { - .clk = { - .name = "spdif", - .id = -1, - }, - .shift = S5PC100_CLKSRC3_SPDIF_SHIFT, - .mask = S5PC100_CLKSRC3_SPDIF_MASK, - .sources = &clkset_spdif, - .reg_source = S5PC100_CLKSRC3, -}; - static struct clk *clkset_lcd_fimc_list[] = { &clk_mout_epll.clk, &clk_dout_mpll, @@ -790,87 +586,11 @@ static struct clk *clkset_lcd_fimc_list[] = { &clk_vclk_54m, }; -static struct clk_sources clkset_lcd_fimc = { +static struct clksrc_sources clkset_lcd_fimc = { .sources = clkset_lcd_fimc_list, .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), }; -static struct clksrc_clk clk_lcd = { - .clk = { - .name = "lcd", - .id = -1, - .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, - .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC2_LCD_SHIFT, - .mask = S5PC100_CLKSRC2_LCD_MASK, - .sources = &clkset_lcd_fimc, - .divider_shift = S5PC100_CLKDIV3_LCD_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, -}; - -static struct clksrc_clk clk_fimc0 = { - .clk = { - .name = "fimc", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, - .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC2_FIMC0_SHIFT, - .mask = S5PC100_CLKSRC2_FIMC0_MASK, - .sources = &clkset_lcd_fimc, - .divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, -}; - -static struct clksrc_clk clk_fimc1 = { - .clk = { - .name = "fimc", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, - .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC2_FIMC1_SHIFT, - .mask = S5PC100_CLKSRC2_FIMC1_MASK, - .sources = &clkset_lcd_fimc, - .divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, -}; - -static struct clksrc_clk clk_fimc2 = { - .clk = { - .name = "fimc", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, - .enable = s5pc100_sclk1_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC2_FIMC2_SHIFT, - .mask = S5PC100_CLKSRC2_FIMC2_MASK, - .sources = &clkset_lcd_fimc, - .divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, -}; - static struct clk *clkset_mmc_list[] = { &clk_mout_epll.clk, &clk_dout_mpll, @@ -878,69 +598,11 @@ static struct clk *clkset_mmc_list[] = { &clk_mout_hpll.clk , }; -static struct clk_sources clkset_mmc = { +static struct clksrc_sources clkset_mmc = { .sources = clkset_mmc_list, .nr_sources = ARRAY_SIZE(clkset_mmc_list), }; -static struct clksrc_clk clk_mmc0 = { - .clk = { - .name = "mmc_bus", - .id = 0, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, - .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC2_MMC0_SHIFT, - .mask = S5PC100_CLKSRC2_MMC0_MASK, - .sources = &clkset_mmc, - .divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, -}; - -static struct clksrc_clk clk_mmc1 = { - .clk = { - .name = "mmc_bus", - .id = 1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, - .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC2_MMC1_SHIFT, - .mask = S5PC100_CLKSRC2_MMC1_MASK, - .sources = &clkset_mmc, - .divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, -}; - -static struct clksrc_clk clk_mmc2 = { - .clk = { - .name = "mmc_bus", - .id = 2, - .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, - .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC2_MMC2_SHIFT, - .mask = S5PC100_CLKSRC2_MMC2_MASK, - .sources = &clkset_mmc, - .divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT, - .reg_divider = S5PC100_CLKDIV3, - .reg_source = S5PC100_CLKSRC2, -}; - - static struct clk *clkset_usbhost_list[] = { &clk_mout_epll.clk, &clk_dout_mpll, @@ -948,28 +610,141 @@ static struct clk *clkset_usbhost_list[] = { &clk_48m, }; -static struct clk_sources clkset_usbhost = { +static struct clksrc_sources clkset_usbhost = { .sources = clkset_usbhost_list, .nr_sources = ARRAY_SIZE(clkset_usbhost_list), }; -static struct clksrc_clk clk_usbhost = { - .clk = { - .name = "usbhost", - .id = -1, - .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, - .enable = s5pc100_sclk0_ctrl, - .set_parent = s5pc100_setparent_clksrc, - .get_rate = s5pc100_getrate_clksrc, - .set_rate = s5pc100_setrate_clksrc, - .round_rate = s5pc100_roundrate_clksrc, - }, - .shift = S5PC100_CLKSRC1_UHOST_SHIFT, - .mask = S5PC100_CLKSRC1_UHOST_MASK, - .sources = &clkset_usbhost, - .divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT, - .reg_divider = S5PC100_CLKDIV2, - .reg_source = S5PC100_CLKSRC1, +static struct clksrc_clk clksrc_clks[] = { + { + .clk = { + .name = "spi_bus", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, + .enable = s5pc100_sclk0_ctrl, + + }, + .sources = &clkset_spi, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, }, + }, { + .clk = { + .name = "spi_bus", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_spi, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, }, + }, { + .clk = { + .name = "spi_bus", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_spi, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, + }, { + .clk = { + .name = "uclk1", + .id = -1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_uart, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, + }, { + .clk = { + .name = "spdif", + .id = -1, + }, + .sources = &clkset_spdif, + .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, + }, { + .clk = { + .name = "lcd", + .id = -1, + .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, }, + }, { + .clk = { + .name = "fimc", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, }, + }, { + .clk = { + .name = "fimc", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, }, + }, { + .clk = { + .name = "fimc", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, + .enable = s5pc100_sclk1_ctrl, + }, + .sources = &clkset_lcd_fimc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, }, + }, { + .clk = { + .name = "mmc_bus", + .id = 0, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_mmc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, }, + }, { + .clk = { + .name = "mmc_bus", + .id = 1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_mmc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, }, + }, { + .clk = { + .name = "mmc_bus", + .id = 2, + .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_mmc, + .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, }, + }, { + .clk = { + .name = "usbhost", + .id = -1, + .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clkset_usbhost, + .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, }, + .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, }, + } }; /* Clock initialisation code */ @@ -981,45 +756,8 @@ static struct clksrc_clk *init_parents[] = { &clk_mout_onenand, &clk_mout_epll, &clk_mout_hpll, - &clk_spi0, - &clk_spi1, - &clk_spi2, - &clk_uart_uclk1, - &clk_audio0, - &clk_audio1, - &clk_audio2, - &clk_spdif, - &clk_lcd, - &clk_fimc0, - &clk_fimc1, - &clk_fimc2, - &clk_mmc0, - &clk_mmc1, - &clk_mmc2, - &clk_usbhost, }; -static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk) -{ - struct clk_sources *srcs = clk->sources; - u32 clksrc = __raw_readl(clk->reg_source); - - clksrc &= clk->mask; - clksrc >>= clk->shift; - - if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { - printk(KERN_ERR "%s: bad source %d\n", - clk->clk.name, clksrc); - return; - } - - clk->clk.parent = srcs->sources[clksrc]; - - printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n", - clk->clk.name, clk->clk.parent->name, clksrc, - print_mhz(clk_get_rate(&clk->clk))); -} - #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) void __init_or_cpufreq s5pc100_setup_clocks(void) @@ -1083,17 +821,25 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) clk_f.rate = armclk; for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) - s5pc100_set_clksrc(init_parents[ptr]); + s3c_set_clksrc(init_parents[ptr], true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++) + s3c_set_clksrc(clksrc_audio + ptr, true); + + for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) + s3c_set_clksrc(clksrc_clks + ptr, true); } static struct clk *clks[] __initdata = { &clk_ext_xtal_mux, - &clk_mout_apll.clk, &clk_dout_apll, &clk_dout_d0_bus, &clk_dout_pclkd0, &clk_dout_apll2, + &clk_mout_apll.clk, &clk_mout_mpll.clk, + &clk_mout_epll.clk, + &clk_mout_hpll.clk, &clk_mout_am.clk, &clk_dout_d1_bus, &clk_mout_onenand.clk, @@ -1101,29 +847,12 @@ static struct clk *clks[] __initdata = { &clk_dout_mpll2, &clk_dout_cam, &clk_dout_mpll, - &clk_mout_epll.clk, &clk_fout_epll, &clk_iis_cd0, &clk_iis_cd1, &clk_iis_cd2, &clk_pcm_cd0, &clk_pcm_cd1, - &clk_spi0.clk, - &clk_spi1.clk, - &clk_spi2.clk, - &clk_uart_uclk1.clk, - &clk_audio0.clk, - &clk_audio1.clk, - &clk_audio2.clk, - &clk_spdif.clk, - &clk_lcd.clk, - &clk_fimc0.clk, - &clk_fimc1.clk, - &clk_fimc2.clk, - &clk_mmc0.clk, - &clk_mmc1.clk, - &clk_mmc2.clk, - &clk_usbhost.clk, &clk_arm, }; @@ -1141,4 +870,7 @@ void __init s5pc100_register_clocks(void) clkp->name, ret); } } + + s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio)); + s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks)); } diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 486a0d6301e7..1c2fe91c23e9 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -13,5 +13,168 @@ config PLAT_SAMSUNG if PLAT_SAMSUNG +config SAMSUNG_CLKSRC + bool + help + Select the clock code for the clksrc implementation + used by newer systems such as the S3C64XX. + +# options for IRQ support + +config SAMSUNG_IRQ_VIC_TIMER + bool + help + Internal configuration to build the VIC timer interrupt code. + +config SAMSUNG_IRQ_UART + bool + help + Internal configuration to build the IRQ UART demux code. + +# options for gpio configuration support + +config SAMSUNG_GPIOLIB_4BIT + bool + help + GPIOlib file contains the 4 bit modification functions for gpio + configuration. GPIOlib shall be compiled only for S3C64XX and S5P + series of processors. + +config S3C_GPIO_CFG_S3C24XX + bool + help + Internal configuration to enable S3C24XX style GPIO configuration + functions. + +config S3C_GPIO_CFG_S3C64XX + bool + help + Internal configuration to enable S3C64XX style GPIO configuration + functions. + +config S5P_GPIO_CFG_S5PC1XX + bool + help + Internal configuration to enable S5PC1XX style GPIO configuration + functions. + +config S3C_GPIO_PULL_UPDOWN + bool + help + Internal configuration to enable the correct GPIO pull helper + +config S3C_GPIO_PULL_DOWN + bool + help + Internal configuration to enable the correct GPIO pull helper + +config S3C_GPIO_PULL_UP + bool + help + Internal configuration to enable the correct GPIO pull helper + +config SAMSUNG_GPIO_EXTRA + int "Number of additional GPIO pins" + default 0 + help + Use additional GPIO space in addition to the GPIO's the SOC + provides. This allows expanding the GPIO space for use with + GPIO expanders. + +# ADC driver + +config S3C_ADC + bool "ADC common driver support" + help + Core support for the ADC block found in the Samsung SoC systems + for drivers such as the touchscreen and hwmon to use to share + this resource. + +# device definitions to compile in + +config S3C_DEV_HSMMC + bool + help + Compile in platform device definitions for HSMMC code + +config S3C_DEV_HSMMC1 + bool + help + Compile in platform device definitions for HSMMC channel 1 + +config S3C_DEV_HSMMC2 + bool + help + Compile in platform device definitions for HSMMC channel 2 + +config S3C_DEV_I2C1 + bool + help + Compile in platform device definitions for I2C channel 1 + +config S3C_DEV_FB + bool + help + Compile in platform device definition for framebuffer + +config S3C_DEV_USB_HOST + bool + help + Compile in platform device definition for USB host. + +config S3C_DEV_USB_HSOTG + bool + help + Compile in platform device definition for USB high-speed OtG + +config S3C_DEV_NAND + bool + help + Compile in platform device definition for NAND controller + +comment "Power management" + +config SAMSUNG_PM_DEBUG + bool "S3C2410 PM Suspend debug" + depends on PM + help + Say Y here if you want verbose debugging from the PM Suspend and + Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> + for more information. + +config S3C_PM_DEBUG_LED_SMDK + bool "SMDK LED suspend/resume debugging" + depends on PM && (MACH_SMDK6410) + help + Say Y here to enable the use of the SMDK LEDs on the baseboard + for debugging of the state of the suspend and resume process. + + Note, this currently only works for S3C64XX based SMDK boards. + +config SAMSUNG_PM_CHECK + bool "S3C2410 PM Suspend Memory CRC" + depends on PM && CRC32 + help + Enable the PM code's memory area checksum over sleep. This option + will generate CRCs of all blocks of memory, and store them before + going to sleep. The blocks are then checked on resume for any + errors. + + Note, this can take several seconds depending on memory size + and CPU speed. + + See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> + +config SAMSUNG_PM_CHECK_CHUNKSIZE + int "S3C2410 PM Suspend CRC Chunksize (KiB)" + depends on PM && SAMSUNG_PM_CHECK + default 64 + help + Set the chunksize in Kilobytes of the CRC for checking memory + corruption over suspend and resume. A smaller value will mean that + the CRC data block will take more memory, but wil identify any + faults with better precision. + + See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> endif diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 4478b9f7dc34..c8c8caec8cde 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -9,3 +9,41 @@ obj-m := obj-n := dummy.o obj- := +# Objects we always build independent of SoC choice + +obj-y += clock.o +obj-y += pwm-clock.o +obj-y += gpio.o +obj-y += gpio-config.o + +obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT) += gpiolib.o +obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o + +obj-$(CONFIG_SAMSUNG_IRQ_UART) += irq-uart.o +obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o + +# ADC + +obj-$(CONFIG_S3C_ADC) += adc.o + +# devices + +obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o +obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o +obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o +obj-y += dev-i2c0.o +obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o +obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o +obj-y += dev-uart.o +obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o +obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o +obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o + +# PM support + +obj-$(CONFIG_PM) += pm-gpio.o +obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o + +# PWM support + +obj-$(CONFIG_HAVE_PWM) += pwm.o diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-samsung/adc.c index ce47627f3368..c7659b7378b1 100644 --- a/arch/arm/plat-s3c24xx/adc.c +++ b/arch/arm/plat-samsung/adc.c @@ -1,10 +1,10 @@ -/* arch/arm/plat-s3c24xx/adc.c +/* arch/arm/plat-samsung/adc.c * * Copyright (c) 2008 Simtec Electronics * http://armlinux.simtec.co.uk/ * Ben Dooks <[email protected]>, <[email protected]> * - * S3C24XX ADC device core + * Samsung ADC device core * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -37,6 +37,11 @@ * action is required. */ +enum s3c_cpu_type { + TYPE_S3C24XX, + TYPE_S3C64XX +}; + struct s3c_adc_client { struct platform_device *pdev; struct list_head pend; @@ -262,7 +267,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) if (!client) { dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__); - return IRQ_HANDLED; + goto exit; } data0 = readl(adc->regs + S3C2410_ADCDAT0); @@ -289,6 +294,11 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) local_irq_restore(flags); } +exit: + if (platform_get_device_id(adc->pdev)->driver_data == TYPE_S3C64XX) { + /* Clear ADC interrupt */ + writel(0, adc->regs + S3C64XX_ADCCLRINT); + } return IRQ_HANDLED; } @@ -410,9 +420,22 @@ static int s3c_adc_resume(struct platform_device *pdev) #define s3c_adc_resume NULL #endif +static struct platform_device_id s3c_adc_driver_ids[] = { + { + .name = "s3c24xx-adc", + .driver_data = TYPE_S3C24XX, + }, { + .name = "s3c64xx-adc", + .driver_data = TYPE_S3C64XX, + }, + { } +}; +MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids); + static struct platform_driver s3c_adc_driver = { + .id_table = s3c_adc_driver_ids, .driver = { - .name = "s3c24xx-adc", + .name = "s3c-adc", .owner = THIS_MODULE, }, .probe = s3c_adc_probe, diff --git a/arch/arm/plat-samsung/clock-clksrc.c b/arch/arm/plat-samsung/clock-clksrc.c new file mode 100644 index 000000000000..ae8b8507663f --- /dev/null +++ b/arch/arm/plat-samsung/clock-clksrc.c @@ -0,0 +1,212 @@ +/* linux/arch/arm/plat-samsung/clock-clksrc.c + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <[email protected]> + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/init.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/sysdev.h> +#include <linux/io.h> + +#include <plat/clock.h> +#include <plat/clock-clksrc.h> +#include <plat/cpu-freq.h> + +static inline struct clksrc_clk *to_clksrc(struct clk *clk) +{ + return container_of(clk, struct clksrc_clk, clk); +} + +static inline u32 bit_mask(u32 shift, u32 nr_bits) +{ + u32 mask = 0xffffffff >> (32 - nr_bits); + + return mask << shift; +} + +static unsigned long s3c_getrate_clksrc(struct clk *clk) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + unsigned long rate = clk_get_rate(clk->parent); + u32 clkdiv = __raw_readl(sclk->reg_div.reg); + u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); + + clkdiv &= mask; + clkdiv >>= sclk->reg_div.shift; + clkdiv++; + + rate /= clkdiv; + return rate; +} + +static int s3c_setrate_clksrc(struct clk *clk, unsigned long rate) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + void __iomem *reg = sclk->reg_div.reg; + unsigned int div; + u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size); + u32 val; + + rate = clk_round_rate(clk, rate); + div = clk_get_rate(clk->parent) / rate; + if (div > (1 << sclk->reg_div.size)) + return -EINVAL; + + val = __raw_readl(reg); + val &= ~mask; + val |= (div - 1) << sclk->reg_div.shift; + __raw_writel(val, reg); + + return 0; +} + +static int s3c_setparent_clksrc(struct clk *clk, struct clk *parent) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + struct clksrc_sources *srcs = sclk->sources; + u32 clksrc = __raw_readl(sclk->reg_src.reg); + u32 mask = bit_mask(sclk->reg_src.shift, sclk->reg_src.size); + int src_nr = -1; + int ptr; + + for (ptr = 0; ptr < srcs->nr_sources; ptr++) + if (srcs->sources[ptr] == parent) { + src_nr = ptr; + break; + } + + if (src_nr >= 0) { + clk->parent = parent; + + clksrc &= ~mask; + clksrc |= src_nr << sclk->reg_src.shift; + + __raw_writel(clksrc, sclk->reg_src.reg); + return 0; + } + + return -EINVAL; +} + +static unsigned long s3c_roundrate_clksrc(struct clk *clk, + unsigned long rate) +{ + struct clksrc_clk *sclk = to_clksrc(clk); + unsigned long parent_rate = clk_get_rate(clk->parent); + int max_div = 1 << sclk->reg_div.size; + int div; + + if (rate >= parent_rate) + rate = parent_rate; + else { + div = parent_rate / rate; + if (parent_rate % rate) + div++; + + if (div == 0) + div = 1; + if (div > max_div) + div = max_div; + + rate = parent_rate / div; + } + + return rate; +} + +/* Clock initialisation code */ + +void __init_or_cpufreq s3c_set_clksrc(struct clksrc_clk *clk, bool announce) +{ + struct clksrc_sources *srcs = clk->sources; + u32 mask = bit_mask(clk->reg_src.shift, clk->reg_src.size); + u32 clksrc; + + if (!clk->reg_src.reg) { + if (!clk->clk.parent) + printk(KERN_ERR "%s: no parent clock specified\n", + clk->clk.name); + return; + } + + clksrc = __raw_readl(clk->reg_src.reg); + clksrc &= mask; + clksrc >>= clk->reg_src.shift; + + if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { + printk(KERN_ERR "%s: bad source %d\n", + clk->clk.name, clksrc); + return; + } + + clk->clk.parent = srcs->sources[clksrc]; + + if (announce) + printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", + clk->clk.name, clk->clk.parent->name, clksrc, + clk_get_rate(&clk->clk)); +} + +static struct clk_ops clksrc_ops = { + .set_parent = s3c_setparent_clksrc, + .get_rate = s3c_getrate_clksrc, + .set_rate = s3c_setrate_clksrc, + .round_rate = s3c_roundrate_clksrc, +}; + +static struct clk_ops clksrc_ops_nodiv = { + .set_parent = s3c_setparent_clksrc, +}; + +static struct clk_ops clksrc_ops_nosrc = { + .get_rate = s3c_getrate_clksrc, + .set_rate = s3c_setrate_clksrc, + .round_rate = s3c_roundrate_clksrc, +}; + +void __init s3c_register_clksrc(struct clksrc_clk *clksrc, int size) +{ + int ret; + + for (; size > 0; size--, clksrc++) { + if (!clksrc->reg_div.reg && !clksrc->reg_src.reg) + printk(KERN_ERR "%s: clock %s has no registers set\n", + __func__, clksrc->clk.name); + + /* fill in the default functions */ + + if (!clksrc->clk.ops) { + if (!clksrc->reg_div.reg) + clksrc->clk.ops = &clksrc_ops_nodiv; + else if (!clksrc->reg_src.reg) + clksrc->clk.ops = &clksrc_ops_nosrc; + else + clksrc->clk.ops = &clksrc_ops; + } + + /* setup the clocksource, but do not announce it + * as it may be re-set by the setup routines + * called after the rest of the clocks have been + * registered + */ + s3c_set_clksrc(clksrc, false); + + ret = s3c24xx_register_clock(&clksrc->clk); + + if (ret < 0) { + printk(KERN_ERR "%s: failed to register %s (%d)\n", + __func__, clksrc->clk.name, ret); + } + } +} diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-samsung/clock.c index 619cfa82dcab..e9cdbe47beb6 100644 --- a/arch/arm/plat-s3c/clock.c +++ b/arch/arm/plat-samsung/clock.c @@ -150,8 +150,8 @@ unsigned long clk_get_rate(struct clk *clk) if (clk->rate != 0) return clk->rate; - if (clk->get_rate != NULL) - return (clk->get_rate)(clk); + if (clk->ops != NULL && clk->ops->get_rate != NULL) + return (clk->ops->get_rate)(clk); if (clk->parent != NULL) return clk_get_rate(clk->parent); @@ -161,8 +161,8 @@ unsigned long clk_get_rate(struct clk *clk) long clk_round_rate(struct clk *clk, unsigned long rate) { - if (!IS_ERR(clk) && clk->round_rate) - return (clk->round_rate)(clk, rate); + if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate) + return (clk->ops->round_rate)(clk, rate); return rate; } @@ -178,13 +178,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate) * the clock may have been made this way by choice. */ - WARN_ON(clk->set_rate == NULL); + WARN_ON(clk->ops == NULL); + WARN_ON(clk->ops && clk->ops->set_rate == NULL); - if (clk->set_rate == NULL) + if (clk->ops == NULL || clk->ops->set_rate == NULL) return -EINVAL; spin_lock(&clocks_lock); - ret = (clk->set_rate)(clk, rate); + ret = (clk->ops->set_rate)(clk, rate); spin_unlock(&clocks_lock); return ret; @@ -204,8 +205,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent) spin_lock(&clocks_lock); - if (clk->set_parent) - ret = (clk->set_parent)(clk, parent); + if (clk->ops && clk->ops->set_parent) + ret = (clk->ops->set_parent)(clk, parent); spin_unlock(&clocks_lock); @@ -224,12 +225,16 @@ EXPORT_SYMBOL(clk_set_parent); /* base clocks */ -static int clk_default_setrate(struct clk *clk, unsigned long rate) +int clk_default_setrate(struct clk *clk, unsigned long rate) { clk->rate = rate; return 0; } +struct clk_ops clk_ops_def_setrate = { + .set_rate = clk_default_setrate, +}; + struct clk clk_xtal = { .name = "xtal", .id = -1, @@ -251,7 +256,7 @@ struct clk clk_epll = { struct clk clk_mpll = { .name = "mpll", .id = -1, - .set_rate = clk_default_setrate, + .ops = &clk_ops_def_setrate, }; struct clk clk_upll = { @@ -267,7 +272,6 @@ struct clk clk_f = { .rate = 0, .parent = &clk_mpll, .ctrlbit = 0, - .set_rate = clk_default_setrate, }; struct clk clk_h = { @@ -276,7 +280,7 @@ struct clk clk_h = { .rate = 0, .parent = NULL, .ctrlbit = 0, - .set_rate = clk_default_setrate, + .ops = &clk_ops_def_setrate, }; struct clk clk_p = { @@ -285,7 +289,7 @@ struct clk clk_p = { .rate = 0, .parent = NULL, .ctrlbit = 0, - .set_rate = clk_default_setrate, + .ops = &clk_ops_def_setrate, }; struct clk clk_usb_bus = { @@ -296,7 +300,6 @@ struct clk clk_usb_bus = { }; - struct clk s3c24xx_uclk = { .name = "uclk", .id = -1, @@ -333,6 +336,28 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) return fails; } +/** + * s3c_register_clocks() - register an array of clocks + * @clkp: Pointer to the first clock in the array. + * @nr_clks: Number of clocks to register. + * + * Call s3c24xx_register_clock() on the @clkp array given, printing an + * error if it fails to register the clock (unlikely). + */ +void __init s3c_register_clocks(struct clk *clkp, int nr_clks) +{ + int ret; + + for (; nr_clks > 0; nr_clks--, clkp++) { + ret = s3c24xx_register_clock(clkp); + + if (ret < 0) { + printk(KERN_ERR "Failed to register clock %s (%d)\n", + clkp->name, ret); + } + } +} + /* initalise all the clocks */ int __init s3c24xx_register_baseclocks(unsigned long xtal) diff --git a/arch/arm/plat-s3c/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c index a90198fc4b0f..a90198fc4b0f 100644 --- a/arch/arm/plat-s3c/dev-fb.c +++ b/arch/arm/plat-samsung/dev-fb.c diff --git a/arch/arm/plat-s3c/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c index 4c05b39810e2..4c05b39810e2 100644 --- a/arch/arm/plat-s3c/dev-hsmmc.c +++ b/arch/arm/plat-samsung/dev-hsmmc.c diff --git a/arch/arm/plat-s3c/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c index e49bc4cd0ee6..e49bc4cd0ee6 100644 --- a/arch/arm/plat-s3c/dev-hsmmc1.c +++ b/arch/arm/plat-samsung/dev-hsmmc1.c diff --git a/arch/arm/plat-s3c/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c index 824580bc0e06..824580bc0e06 100644 --- a/arch/arm/plat-s3c/dev-hsmmc2.c +++ b/arch/arm/plat-samsung/dev-hsmmc2.c diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c index 4c761529b949..4c761529b949 100644 --- a/arch/arm/plat-s3c/dev-i2c0.c +++ b/arch/arm/plat-samsung/dev-i2c0.c diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c index d44f79110506..d44f79110506 100644 --- a/arch/arm/plat-s3c/dev-i2c1.c +++ b/arch/arm/plat-samsung/dev-i2c1.c diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c index a52fb6cf618f..a52fb6cf618f 100644 --- a/arch/arm/plat-s3c/dev-nand.c +++ b/arch/arm/plat-samsung/dev-nand.c diff --git a/arch/arm/plat-samsung/dev-uart.c b/arch/arm/plat-samsung/dev-uart.c new file mode 100644 index 000000000000..3776cd952450 --- /dev/null +++ b/arch/arm/plat-samsung/dev-uart.c @@ -0,0 +1,44 @@ +/* linux/arch/arm/plat-samsung/dev-uart.c + * originally from arch/arm/plat-s3c24xx/devs.c + *x + * Copyright (c) 2004 Simtec Electronics + * Ben Dooks <[email protected]> + * + * Base S3C24XX platform device definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +#include <linux/kernel.h> +#include <linux/platform_device.h> + +/* uart devices */ + +static struct platform_device s3c24xx_uart_device0 = { + .id = 0, +}; + +static struct platform_device s3c24xx_uart_device1 = { + .id = 1, +}; + +static struct platform_device s3c24xx_uart_device2 = { + .id = 2, +}; + +static struct platform_device s3c24xx_uart_device3 = { + .id = 3, +}; + +struct platform_device *s3c24xx_uart_src[4] = { + &s3c24xx_uart_device0, + &s3c24xx_uart_device1, + &s3c24xx_uart_device2, + &s3c24xx_uart_device3, +}; + +struct platform_device *s3c24xx_uart_devs[4] = { +}; diff --git a/arch/arm/plat-s3c/dev-usb-hsotg.c b/arch/arm/plat-samsung/dev-usb-hsotg.c index e2f604b51c86..e2f604b51c86 100644 --- a/arch/arm/plat-s3c/dev-usb-hsotg.c +++ b/arch/arm/plat-samsung/dev-usb-hsotg.c diff --git a/arch/arm/plat-s3c/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c index 2ee85abed6d9..88165657fa53 100644 --- a/arch/arm/plat-s3c/dev-usb.c +++ b/arch/arm/plat-samsung/dev-usb.c @@ -19,7 +19,7 @@ #include <mach/map.h> #include <plat/devs.h> - +#include <plat/usb-control.h> static struct resource s3c_usb_resource[] = { [0] = { @@ -36,7 +36,7 @@ static struct resource s3c_usb_resource[] = { static u64 s3c_device_usb_dmamask = 0xffffffffUL; -struct platform_device s3c_device_usb = { +struct platform_device s3c_device_ohci = { .name = "s3c2410-ohci", .id = -1, .num_resources = ARRAY_SIZE(s3c_usb_resource), @@ -47,4 +47,23 @@ struct platform_device s3c_device_usb = { } }; -EXPORT_SYMBOL(s3c_device_usb); +EXPORT_SYMBOL(s3c_device_ohci); + +/** + * s3c_ohci_set_platdata - initialise OHCI device platform data + * @info: The platform data. + * + * This call copies the @info passed in and sets the device .platform_data + * field to that copy. The @info is copied so that the original can be marked + * __initdata. + */ +void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info) +{ + struct s3c2410_hcd_info *npd; + + npd = kmemdup(info, sizeof(struct s3c2410_hcd_info), GFP_KERNEL); + if (!npd) + printk(KERN_ERR "%s: no memory for platform data\n", __func__); + + s3c_device_ohci.dev.platform_data = npd; +} diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c index 456969b6fa0d..44a84e896546 100644 --- a/arch/arm/plat-s3c/gpio-config.c +++ b/arch/arm/plat-samsung/gpio-config.c @@ -17,7 +17,7 @@ #include <linux/gpio.h> #include <linux/io.h> -#include <mach/gpio-core.h> +#include <plat/gpio-core.h> #include <plat/gpio-cfg.h> #include <plat/gpio-cfg-helpers.h> diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-samsung/gpio.c index 5ff24e0f9f89..28d2ab8a08db 100644 --- a/arch/arm/plat-s3c/gpio.c +++ b/arch/arm/plat-samsung/gpio.c @@ -16,7 +16,7 @@ #include <linux/io.h> #include <linux/gpio.h> -#include <mach/gpio-core.h> +#include <plat/gpio-core.h> #ifdef CONFIG_S3C_GPIO_TRACK struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c new file mode 100644 index 000000000000..8a8ba8bc1d96 --- /dev/null +++ b/arch/arm/plat-samsung/gpiolib.c @@ -0,0 +1,199 @@ +/* arch/arm/plat-samsung/gpiolib.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <[email protected]> + * http://armlinux.simtec.co.uk/ + * + * Copyright (c) 2009 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * SAMSUNG - GPIOlib support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/irq.h> +#include <linux/io.h> +#include <mach/gpio.h> +#include <plat/gpio-core.h> +#include <plat/gpio-cfg.h> +#include <plat/gpio-cfg-helpers.h> + +#ifndef DEBUG_GPIO +#define gpio_dbg(x...) do { } while (0) +#else +#define gpio_dbg(x...) printk(KERN_DEBUG x) +#endif + +/* The samsung_gpiolib_4bit routines are to control the gpio banks where + * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the + * following example: + * + * base + 0x00: Control register, 4 bits per gpio + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Data register, 1 bit per gpio + * bit n: data bit n + * + * Note, since the data register is one bit per gpio and is at base + 0x4 + * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of + * the output. +*/ + +static int samsung_gpiolib_4bit_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + + con = __raw_readl(base + GPIOCON_OFF); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, base + GPIOCON_OFF); + + gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); + + return 0; +} + +static int samsung_gpiolib_4bit_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + unsigned long con; + unsigned long dat; + + con = __raw_readl(base + GPIOCON_OFF); + con &= ~(0xf << con_4bit_shift(offset)); + con |= 0x1 << con_4bit_shift(offset); + + dat = __raw_readl(base + GPIODAT_OFF); + + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + GPIODAT_OFF); + __raw_writel(con, base + GPIOCON_OFF); + __raw_writel(dat, base + GPIODAT_OFF); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +/* The next set of routines are for the case where the GPIO configuration + * registers are 4 bits per GPIO but there is more than one register (the + * bank has more than 8 GPIOs. + * + * This case is the similar to the 4 bit case, but the registers are as + * follows: + * + * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) + * gpio n: 4 bits starting at (4*n) + * 0000 = input, 0001 = output, others mean special-function + * base + 0x08: Data register, 1 bit per gpio + * bit n: data bit n + * + * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we + * store the 'base + 0x4' address so that these routines see the data + * register at ourchip->base + 0x04. + */ + +static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + + if (offset > 7) + offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(offset)); + __raw_writel(con, regcon); + + gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); + + return 0; +} + +static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); + void __iomem *base = ourchip->base; + void __iomem *regcon = base; + unsigned long con; + unsigned long dat; + unsigned con_offset = offset; + + if (con_offset > 7) + con_offset -= 8; + else + regcon -= 4; + + con = __raw_readl(regcon); + con &= ~(0xf << con_4bit_shift(con_offset)); + con |= 0x1 << con_4bit_shift(con_offset); + + dat = __raw_readl(base + GPIODAT_OFF); + + if (value) + dat |= 1 << offset; + else + dat &= ~(1 << offset); + + __raw_writel(dat, base + GPIODAT_OFF); + __raw_writel(con, regcon); + __raw_writel(dat, base + GPIODAT_OFF); + + gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); + + return 0; +} + +void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip) +{ + chip->chip.direction_input = samsung_gpiolib_4bit_input; + chip->chip.direction_output = samsung_gpiolib_4bit_output; + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); +} + +void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) +{ + chip->chip.direction_input = samsung_gpiolib_4bit2_input; + chip->chip.direction_output = samsung_gpiolib_4bit2_output; + chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); +} + +void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) { + samsung_gpiolib_add_4bit(chip); + s3c_gpiolib_add(chip); + } +} + +void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, + int nr_chips) +{ + for (; nr_chips > 0; nr_chips--, chip++) { + samsung_gpiolib_add_4bit2(chip); + s3c_gpiolib_add(chip); + } +} diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-samsung/include/plat/adc.h index 5f3b1cd53b90..e8382c7be10b 100644 --- a/arch/arm/plat-s3c/include/plat/adc.h +++ b/arch/arm/plat-samsung/include/plat/adc.h @@ -1,10 +1,10 @@ -/* arch/arm/plat-s3c/include/plat/adc.h +/* arch/arm/plat-samsung/include/plat/adc.h * * Copyright (c) 2008 Simtec Electronics * http://armlinux.simnte.co.uk/ * Ben Dooks <[email protected]> * - * S3C24XX ADC driver information + * S3C ADC driver information * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as diff --git a/arch/arm/plat-samsung/include/plat/clock-clksrc.h b/arch/arm/plat-samsung/include/plat/clock-clksrc.h new file mode 100644 index 000000000000..50a8ca7c3760 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/clock-clksrc.h @@ -0,0 +1,83 @@ +/* linux/arch/arm/plat-samsung/include/plat/clock-clksrc.h + * + * Parts taken from arch/arm/plat-s3c64xx/clock.c + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <[email protected]> + * http://armlinux.simtec.co.uk/ + * + * Copyright 2009 Ben Dooks <[email protected]> + * Copyright 2009 Harald Welte + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/** + * struct clksrc_sources - list of sources for a given clock + * @sources: array of pointers to clocks + * @nr_sources: The size of @sources + */ +struct clksrc_sources { + unsigned int nr_sources; + struct clk **sources; +}; + +/** + * struct clksrc_reg - register definition for clock control bits + * @reg: pointer to the register in virtual memory. + * @shift: the shift in bits to where the bitfield is. + * @size: the size in bits of the bitfield. + * + * This specifies the size and position of the bits we are interested + * in within the register specified by @reg. + */ +struct clksrc_reg { + void __iomem *reg; + unsigned short shift; + unsigned short size; +}; + +/** + * struct clksrc_clk - class of clock for newer style samsung devices. + * @clk: the standard clock representation + * @sources: the sources for this clock + * @reg_src: the register definition for selecting the clock's source + * @reg_div: the register definition for the clock's output divisor + * + * This clock implements the features required by the newer SoCs where + * the standard clock block provides an input mux and a post-mux divisor + * to provide the periperhal's clock. + * + * The array of @sources provides the mapping of mux position to the + * clock, and @reg_src shows the code where to modify to change the mux + * position. The @reg_div defines how to change the divider settings on + * the output. + */ +struct clksrc_clk { + struct clk clk; + struct clksrc_sources *sources; + + struct clksrc_reg reg_src; + struct clksrc_reg reg_div; +}; + +/** + * s3c_set_clksrc() - setup the clock from the register settings + * @clk: The clock to setup. + * @announce: true to announce the setting to printk(). + * + * Setup the clock from the current register settings, for when the + * kernel boots or if it is resuming from a possibly unknown state. + */ +extern void s3c_set_clksrc(struct clksrc_clk *clk, bool announce); + +/** + * s3c_register_clksrc() register clocks from an array of clksrc clocks + * @srcs: The array of clocks to register + * @size: The size of the @srcs array. + * + * Initialise and register the array of clocks described by @srcs. + */ +extern void s3c_register_clksrc(struct clksrc_clk *srcs, int size); diff --git a/arch/arm/plat-s3c/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index d86af84b5b8c..ba9a1cdd3a28 100644 --- a/arch/arm/plat-s3c/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h @@ -11,6 +11,30 @@ #include <linux/spinlock.h> +struct clk; + +/** + * struct clk_ops - standard clock operations + * @set_rate: set the clock rate, see clk_set_rate(). + * @get_rate: get the clock rate, see clk_get_rate(). + * @round_rate: round a given clock rate, see clk_round_rate(). + * @set_parent: set the clock's parent, see clk_set_parent(). + * + * Group the common clock implementations together so that we + * don't have to keep setting the same fiels again. We leave + * enable in struct clk. + * + * Adding an extra layer of indirection into the process should + * not be a problem as it is unlikely these operations are going + * to need to be called quickly. + */ +struct clk_ops { + int (*set_rate)(struct clk *c, unsigned long rate); + unsigned long (*get_rate)(struct clk *c); + unsigned long (*round_rate)(struct clk *c, unsigned long rate); + int (*set_parent)(struct clk *c, struct clk *parent); +}; + struct clk { struct list_head list; struct module *owner; @@ -21,11 +45,8 @@ struct clk { unsigned long rate; unsigned long ctrlbit; + struct clk_ops *ops; int (*enable)(struct clk *, int enable); - int (*set_rate)(struct clk *c, unsigned long rate); - unsigned long (*get_rate)(struct clk *c); - unsigned long (*round_rate)(struct clk *c, unsigned long rate); - int (*set_parent)(struct clk *c, struct clk *parent); }; /* other clocks which may be registered by board support */ @@ -54,6 +75,9 @@ extern struct clk clk_h2; extern struct clk clk_27m; extern struct clk clk_48m; +extern int clk_default_setrate(struct clk *clk, unsigned long rate); +extern struct clk_ops clk_ops_def_setrate; + /* exports for arch/arm/mach-s3c2410 * * Please DO NOT use these outside of arch/arm/mach-s3c2410 @@ -66,9 +90,12 @@ extern int s3c2410_clkcon_enable(struct clk *clk, int enable); extern int s3c24xx_register_clock(struct clk *clk); extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); +extern void s3c_register_clocks(struct clk *clk, int nr_clks); + extern int s3c24xx_register_baseclocks(unsigned long xtal); extern void s3c64xx_register_clocks(void); +extern void s5p_register_clocks(unsigned long xtal_freq); extern void s3c24xx_setup_clocks(unsigned long fclk, unsigned long hclk, diff --git a/arch/arm/plat-s3c/include/plat/dma-core.h b/arch/arm/plat-samsung/include/plat/dma-core.h index 32ff2a92cb3c..32ff2a92cb3c 100644 --- a/arch/arm/plat-s3c/include/plat/dma-core.h +++ b/arch/arm/plat-samsung/include/plat/dma-core.h diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index 652e2bbdaa20..652e2bbdaa20 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 29cd6a86cade..29cd6a86cade 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 32af612767aa..49ff406a7066 100644 --- a/arch/arm/plat-s3c/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h @@ -11,6 +11,11 @@ * published by the Free Software Foundation. */ +#define GPIOCON_OFF (0x00) +#define GPIODAT_OFF (0x04) + +#define con_4bit_shift(__off) ((__off) * 4) + /* Define the core gpiolib support functions that the s3c platforms may * need to extend or change depending on the hardware and the s3c chip * selected at build or found at run time. @@ -80,6 +85,29 @@ extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); * and any other necessary functions. */ +/** + * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. + * @chip: The gpio chip that is being configured. + * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. + * + * This helper deal with the GPIO cases where the control register has 4 bits + * of control per GPIO, generally in the form of: + * 0000 = Input + * 0001 = Output + * others = Special functions (dependant on bank) + * + * Note, since the code to deal with the case where there are two control + * registers instead of one, we do not have a seperate set of function + * (samsung_gpiolib_add_4bit2_chips)for each case. + */ +extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, + int nr_chips); +extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, + int nr_chips); + +extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); +extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); + #ifdef CONFIG_S3C_GPIO_TRACK extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; @@ -90,6 +118,8 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) #else /* machine specific code should provide s3c_gpiolib_getchip */ +#include <mach/gpio-track.h> + static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } #endif diff --git a/arch/arm/plat-s3c/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h index 1ba88ea0aa31..1ba88ea0aa31 100644 --- a/arch/arm/plat-s3c/include/plat/hwmon.h +++ b/arch/arm/plat-samsung/include/plat/hwmon.h diff --git a/arch/arm/plat-s3c/include/plat/iic-core.h b/arch/arm/plat-samsung/include/plat/iic-core.h index 36397ca20962..36397ca20962 100644 --- a/arch/arm/plat-s3c/include/plat/iic-core.h +++ b/arch/arm/plat-samsung/include/plat/iic-core.h diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h index 3083df00dee6..3083df00dee6 100644 --- a/arch/arm/plat-s3c/include/plat/iic.h +++ b/arch/arm/plat-samsung/include/plat/iic.h diff --git a/arch/arm/plat-samsung/include/plat/irq-uart.h b/arch/arm/plat-samsung/include/plat/irq-uart.h new file mode 100644 index 000000000000..a9331e49bea3 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/irq-uart.h @@ -0,0 +1,20 @@ +/* arch/arm/plat-samsung/include/plat/irq-uart.h + * + * Copyright (c) 2010 Simtec Electronics + * Ben Dooks <[email protected]> + * + * Header file for Samsung SoC UART IRQ demux for S3C64XX and later + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +struct s3c_uart_irq { + void __iomem *regs; + unsigned int base_irq; + unsigned int parent_irq; +}; + +extern void s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs); + diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h new file mode 100644 index 000000000000..a90b53431b5b --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h @@ -0,0 +1,13 @@ +/* arch/arm/plat-samsung/include/plat/irq-vic-timer.h + * + * Copyright (c) 2010 Simtec Electronics + * Ben Dooks <[email protected]> + * + * Header file for Samsung SoC IRQ VIC timer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer); diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-samsung/include/plat/nand.h index 226147b7e026..226147b7e026 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-samsung/include/plat/nand.h diff --git a/arch/arm/plat-s3c/include/plat/regs-ac97.h b/arch/arm/plat-samsung/include/plat/regs-ac97.h index c3878f7acb83..c3878f7acb83 100644 --- a/arch/arm/plat-s3c/include/plat/regs-ac97.h +++ b/arch/arm/plat-samsung/include/plat/regs-ac97.h diff --git a/arch/arm/plat-s3c/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h index 4323cccc86cd..f43c8dab39e4 100644 --- a/arch/arm/plat-s3c/include/plat/regs-adc.h +++ b/arch/arm/plat-samsung/include/plat/regs-adc.h @@ -19,6 +19,9 @@ #define S3C2410_ADCDLY S3C2410_ADCREG(0x08) #define S3C2410_ADCDAT0 S3C2410_ADCREG(0x0C) #define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) +#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) +#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) +#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) /* ADCCON Register Bits */ diff --git a/arch/arm/plat-s3c/include/plat/regs-iic.h b/arch/arm/plat-samsung/include/plat/regs-iic.h index 2f7c17de8ac8..2f7c17de8ac8 100644 --- a/arch/arm/plat-s3c/include/plat/regs-iic.h +++ b/arch/arm/plat-samsung/include/plat/regs-iic.h diff --git a/arch/arm/plat-s3c/include/plat/regs-irqtype.h b/arch/arm/plat-samsung/include/plat/regs-irqtype.h index c63cd3fc5ad3..c63cd3fc5ad3 100644 --- a/arch/arm/plat-s3c/include/plat/regs-irqtype.h +++ b/arch/arm/plat-samsung/include/plat/regs-irqtype.h diff --git a/arch/arm/plat-s3c/include/plat/regs-nand.h b/arch/arm/plat-samsung/include/plat/regs-nand.h index 238efea7b9e4..238efea7b9e4 100644 --- a/arch/arm/plat-s3c/include/plat/regs-nand.h +++ b/arch/arm/plat-samsung/include/plat/regs-nand.h diff --git a/arch/arm/plat-s3c/include/plat/regs-rtc.h b/arch/arm/plat-samsung/include/plat/regs-rtc.h index d5837cf8e402..d5837cf8e402 100644 --- a/arch/arm/plat-s3c/include/plat/regs-rtc.h +++ b/arch/arm/plat-samsung/include/plat/regs-rtc.h diff --git a/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h index abf2fbc2eb2f..abf2fbc2eb2f 100644 --- a/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h +++ b/arch/arm/plat-samsung/include/plat/regs-s3c2412-iis.h diff --git a/arch/arm/plat-s3c/include/plat/regs-sdhci.h b/arch/arm/plat-samsung/include/plat/regs-sdhci.h index e34049ad44cc..e34049ad44cc 100644 --- a/arch/arm/plat-s3c/include/plat/regs-sdhci.h +++ b/arch/arm/plat-samsung/include/plat/regs-sdhci.h diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h index d097d92f8cc7..d097d92f8cc7 100644 --- a/arch/arm/plat-s3c/include/plat/regs-timer.h +++ b/arch/arm/plat-samsung/include/plat/regs-timer.h diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h index 36a85f5000c8..36a85f5000c8 100644 --- a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h +++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg-phy.h diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h index 8d18d9d4d148..8d18d9d4d148 100644 --- a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h +++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h diff --git a/arch/arm/plat-s3c/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h index 4938492470f7..4938492470f7 100644 --- a/arch/arm/plat-s3c/include/plat/regs-watchdog.h +++ b/arch/arm/plat-samsung/include/plat/regs-watchdog.h diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h new file mode 100644 index 000000000000..d17724149315 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h @@ -0,0 +1,67 @@ +/* linux/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h + * + * Copyright (C) 2009 Samsung Electronics Ltd. + * Jaswinder Singh <[email protected]> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __S3C64XX_PLAT_SPI_H +#define __S3C64XX_PLAT_SPI_H + +/** + * struct s3c64xx_spi_csinfo - ChipSelect description + * @fb_delay: Slave specific feedback delay. + * Refer to FB_CLK_SEL register definition in SPI chapter. + * @line: Custom 'identity' of the CS line. + * @set_level: CS line control. + * + * This is per SPI-Slave Chipselect information. + * Allocate and initialize one in machine init code and make the + * spi_board_info.controller_data point to it. + */ +struct s3c64xx_spi_csinfo { + u8 fb_delay; + unsigned line; + void (*set_level)(unsigned line_id, int lvl); +}; + +/** + * struct s3c64xx_spi_info - SPI Controller defining structure + * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. + * @src_clk_name: Platform name of the corresponding clock. + * @num_cs: Number of CS this controller emulates. + * @cfg_gpio: Configure pins for this SPI controller. + * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 + * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number + * @high_speed: If the controller supports HIGH_SPEED_EN bit + */ +struct s3c64xx_spi_info { + int src_clk_nr; + char *src_clk_name; + + int num_cs; + + int (*cfg_gpio)(struct platform_device *pdev); + + /* Following two fields are for future compatibility */ + int fifo_lvl_mask; + int rx_lvl_offset; + int high_speed; +}; + +/** + * s3c64xx_spi_set_info - SPI Controller configure callback by the board + * initialization code. + * @cntrlr: SPI controller number the configuration is for. + * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. + * @num_cs: Number of elements in the 'cs' array. + * + * Call this from machine init code for each SPI Controller that + * has some chips attached to it. + */ +extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); + +#endif /* __S3C64XX_PLAT_SPI_H */ diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 53198673b6bd..53198673b6bd 100644 --- a/arch/arm/plat-s3c/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h diff --git a/arch/arm/plat-s3c/include/plat/udc-hs.h b/arch/arm/plat-samsung/include/plat/udc-hs.h index dd04db043109..a22a4f2eea94 100644 --- a/arch/arm/plat-s3c/include/plat/udc-hs.h +++ b/arch/arm/plat-samsung/include/plat/udc-hs.h @@ -12,7 +12,7 @@ * published by the Free Software Foundation. */ -enum s3c_hostg_dmamode { +enum s3c_hsotg_dmamode { S3C_HSOTG_DMA_NONE, /* do not use DMA at-all */ S3C_HSOTG_DMA_ONLY, /* always use DMA */ S3C_HSOTG_DMA_DRV, /* DMA is chosen by driver */ @@ -24,6 +24,6 @@ enum s3c_hostg_dmamode { * @is_osc: The clock source is an oscillator, not a crystal */ struct s3c_hsotg_plat { - enum s3c_hostg_dmamode dma; + enum s3c_hsotg_dmamode dma; unsigned int is_osc : 1; }; diff --git a/arch/arm/plat-s3c/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h index 54b762acb5a0..54b762acb5a0 100644 --- a/arch/arm/plat-s3c/include/plat/watchdog-reset.h +++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c new file mode 100644 index 000000000000..4f8c102674ae --- /dev/null +++ b/arch/arm/plat-samsung/irq-uart.c @@ -0,0 +1,143 @@ +/* arch/arm/plat-samsung/irq-uart.c + * originally part of arch/arm/plat-s3c64xx/irq.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <[email protected]> + * http://armlinux.simtec.co.uk/ + * + * Samsung- UART Interrupt handling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/serial_core.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/map.h> +#include <plat/irq-uart.h> +#include <plat/regs-serial.h> +#include <plat/cpu.h> + +/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] + * are consecutive when looking up the interrupt in the demux routines. + */ + +static inline void __iomem *s3c_irq_uart_base(unsigned int irq) +{ + struct s3c_uart_irq *uirq = get_irq_chip_data(irq); + return uirq->regs; +} + +static inline unsigned int s3c_irq_uart_bit(unsigned int irq) +{ + return irq & 3; +} + +static void s3c_irq_uart_mask(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + u32 reg; + + reg = __raw_readl(regs + S3C64XX_UINTM); + reg |= (1 << bit); + __raw_writel(reg, regs + S3C64XX_UINTM); +} + +static void s3c_irq_uart_maskack(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + u32 reg; + + reg = __raw_readl(regs + S3C64XX_UINTM); + reg |= (1 << bit); + __raw_writel(reg, regs + S3C64XX_UINTM); + __raw_writel(1 << bit, regs + S3C64XX_UINTP); +} + +static void s3c_irq_uart_unmask(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + u32 reg; + + reg = __raw_readl(regs + S3C64XX_UINTM); + reg &= ~(1 << bit); + __raw_writel(reg, regs + S3C64XX_UINTM); +} + +static void s3c_irq_uart_ack(unsigned int irq) +{ + void __iomem *regs = s3c_irq_uart_base(irq); + unsigned int bit = s3c_irq_uart_bit(irq); + + __raw_writel(1 << bit, regs + S3C64XX_UINTP); +} + +static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) +{ + struct s3c_uart_irq *uirq = desc->handler_data; + u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); + int base = uirq->base_irq; + + if (pend & (1 << 0)) + generic_handle_irq(base); + if (pend & (1 << 1)) + generic_handle_irq(base + 1); + if (pend & (1 << 2)) + generic_handle_irq(base + 2); + if (pend & (1 << 3)) + generic_handle_irq(base + 3); +} + +static struct irq_chip s3c_irq_uart = { + .name = "s3c-uart", + .mask = s3c_irq_uart_mask, + .unmask = s3c_irq_uart_unmask, + .mask_ack = s3c_irq_uart_maskack, + .ack = s3c_irq_uart_ack, +}; + +static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) +{ + struct irq_desc *desc = irq_to_desc(uirq->parent_irq); + void __iomem *reg_base = uirq->regs; + unsigned int irq; + int offs; + + /* mask all interrupts at the start. */ + __raw_writel(0xf, reg_base + S3C64XX_UINTM); + + for (offs = 0; offs < 3; offs++) { + irq = uirq->base_irq + offs; + + set_irq_chip(irq, &s3c_irq_uart); + set_irq_chip_data(irq, uirq); + set_irq_handler(irq, handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + desc->handler_data = uirq; + set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); +} + +/** + * s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing + * @irq: The interrupt data for registering + * @nr_irqs: The number of interrupt descriptions in @irq. + * + * Register the UART interrupts specified by @irq including the demuxing + * routines. This supports the S3C6400 and newer style of devices. + */ +void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs) +{ + for (; nr_irqs > 0; nr_irqs--, irq++) + s3c_init_uart_irq(irq); +} diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c new file mode 100644 index 000000000000..0270519fcabc --- /dev/null +++ b/arch/arm/plat-samsung/irq-vic-timer.c @@ -0,0 +1,86 @@ +/* arch/arm/plat-samsung/irq-vic-timer.c + * originally part of arch/arm/plat-s3c64xx/irq.c + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <[email protected]> + * http://armlinux.simtec.co.uk/ + * + * S3C64XX - Interrupt handling + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/io.h> + +#include <mach/map.h> +#include <plat/irq-vic-timer.h> +#include <plat/regs-timer.h> + +static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) +{ + generic_handle_irq((int)desc->handler_data); +} + +/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ + +static void s3c_irq_timer_mask(unsigned int irq) +{ + u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + + reg &= 0x1f; /* mask out pending interrupts */ + reg &= ~(1 << (irq - IRQ_TIMER0)); + __raw_writel(reg, S3C64XX_TINT_CSTAT); +} + +static void s3c_irq_timer_unmask(unsigned int irq) +{ + u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + + reg &= 0x1f; /* mask out pending interrupts */ + reg |= 1 << (irq - IRQ_TIMER0); + __raw_writel(reg, S3C64XX_TINT_CSTAT); +} + +static void s3c_irq_timer_ack(unsigned int irq) +{ + u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); + + reg &= 0x1f; + reg |= (1 << 5) << (irq - IRQ_TIMER0); + __raw_writel(reg, S3C64XX_TINT_CSTAT); +} + +static struct irq_chip s3c_irq_timer = { + .name = "s3c-timer", + .mask = s3c_irq_timer_mask, + .unmask = s3c_irq_timer_unmask, + .ack = s3c_irq_timer_ack, +}; + +/** + * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\ + * @parent_irq: The parent IRQ on the VIC for the timer. + * @timer_irq: The IRQ to be used for the timer. + * + * Register the necessary IRQ chaining and support for the timer IRQs + * chained of the VIC. + */ +void __init s3c_init_vic_timer_irq(unsigned int parent_irq, + unsigned int timer_irq) +{ + struct irq_desc *desc = irq_to_desc(parent_irq); + + set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer); + + set_irq_chip(timer_irq, &s3c_irq_timer); + set_irq_handler(timer_irq, handle_level_irq); + set_irq_flags(timer_irq, IRQF_VALID); + + desc->handler_data = (void *)timer_irq; +} diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-samsung/pm-check.c index 8eb1f439861c..0b5bb774192a 100644 --- a/arch/arm/plat-s3c/pm-check.c +++ b/arch/arm/plat-samsung/pm-check.c @@ -20,8 +20,8 @@ #include <plat/pm.h> -#if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1 -#error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value +#if CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE < 1 +#error CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE must be a positive non-zero value #endif /* suspend checking code... @@ -29,12 +29,12 @@ * this next area does a set of crc checks over all the installed * memory, so the system can verify if the resume was ok. * - * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, + * CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, * increasing it will mean that the area corrupted will be less easy to spot, * and reducing the size will cause the CRC save area to grow */ -#define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) +#define CHECK_CHUNKSIZE (CONFIG_SAMSUNG_PM_CHECK_CHUNKSIZE * 1024) static u32 crc_size; /* size needed for the crc block */ static u32 *crcs; /* allocated over suspend/resume */ diff --git a/arch/arm/plat-s3c/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index cfd326a8b693..69a4c7f02e25 100644 --- a/arch/arm/plat-s3c/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c @@ -19,7 +19,7 @@ #include <linux/io.h> #include <linux/gpio.h> -#include <mach/gpio-core.h> +#include <plat/gpio-core.h> #include <plat/pm.h> /* PM GPIO helpers */ diff --git a/arch/arm/plat-s3c/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c index a318215ab535..46c9381e083b 100644 --- a/arch/arm/plat-s3c/pwm-clock.c +++ b/arch/arm/plat-samsung/pwm-clock.c @@ -130,20 +130,22 @@ static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate) return 0; } +static struct clk_ops clk_pwm_scaler_ops = { + .get_rate = clk_pwm_scaler_get_rate, + .set_rate = clk_pwm_scaler_set_rate, + .round_rate = clk_pwm_scaler_round_rate, +}; + static struct clk clk_timer_scaler[] = { [0] = { .name = "pwm-scaler0", .id = -1, - .get_rate = clk_pwm_scaler_get_rate, - .set_rate = clk_pwm_scaler_set_rate, - .round_rate = clk_pwm_scaler_round_rate, + .ops = &clk_pwm_scaler_ops, }, [1] = { .name = "pwm-scaler1", .id = -1, - .get_rate = clk_pwm_scaler_get_rate, - .set_rate = clk_pwm_scaler_set_rate, - .round_rate = clk_pwm_scaler_round_rate, + .ops = &clk_pwm_scaler_ops, }, }; @@ -256,50 +258,46 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) return 0; } +static struct clk_ops clk_tdiv_ops = { + .get_rate = clk_pwm_tdiv_get_rate, + .set_rate = clk_pwm_tdiv_set_rate, + .round_rate = clk_pwm_tdiv_round_rate, +}; + static struct pwm_tdiv_clk clk_timer_tdiv[] = { [0] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[0], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[0], }, }, [1] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[0], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[0], } }, [2] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[1], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[1], }, }, [3] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[1], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[1], }, }, [4] = { .clk = { - .name = "pwm-tdiv", - .parent = &clk_timer_scaler[1], - .get_rate = clk_pwm_tdiv_get_rate, - .set_rate = clk_pwm_tdiv_set_rate, - .round_rate = clk_pwm_tdiv_round_rate, + .name = "pwm-tdiv", + .ops = &clk_tdiv_ops, + .parent = &clk_timer_scaler[1], }, }, }; @@ -356,31 +354,35 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) return 0; } +static struct clk_ops clk_tin_ops = { + .set_parent = clk_pwm_tin_set_parent, +}; + static struct clk clk_tin[] = { [0] = { - .name = "pwm-tin", - .id = 0, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 0, + .ops = &clk_tin_ops, }, [1] = { - .name = "pwm-tin", - .id = 1, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 1, + .ops = &clk_tin_ops, }, [2] = { - .name = "pwm-tin", - .id = 2, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 2, + .ops = &clk_tin_ops, }, [3] = { - .name = "pwm-tin", - .id = 3, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 3, + .ops = &clk_tin_ops, }, [4] = { - .name = "pwm-tin", - .id = 4, - .set_parent = clk_pwm_tin_set_parent, + .name = "pwm-tin", + .id = 4, + .ops = &clk_tin_ops, }, }; @@ -428,25 +430,15 @@ __init void s3c_pwmclk_init(void) return; } - for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) { + for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) clk_timer_scaler[clk].parent = clk_timers; - ret = s3c24xx_register_clock(&clk_timer_scaler[clk]); - if (ret < 0) { - printk(KERN_ERR "error adding pwm scaler%d clock\n", clk); - return; - } - } - for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) { - ret = s3c24xx_register_clock(&clk_timer_tclk[clk]); - if (ret < 0) { - printk(KERN_ERR "error adding pww tclk%d\n", clk); - return; - } - } + s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler)); + s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk)); for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) { ret = clk_pwm_tdiv_register(clk); + if (ret < 0) { printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); return; diff --git a/arch/arm/plat-s3c/pwm.c b/arch/arm/plat-samsung/pwm.c index ef019f27b67d..ef019f27b67d 100644 --- a/arch/arm/plat-s3c/pwm.c +++ b/arch/arm/plat-samsung/pwm.c diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 5a79fc6ee818..31c2f4c30a95 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -12,7 +12,7 @@ # # http://www.arm.linux.org.uk/developer/machines/?action=new # -# Last update: Thu Jan 28 22:15:54 2010 +# Last update: Sat Feb 20 14:16:15 2010 # # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number # @@ -2257,7 +2257,7 @@ oratisalog MACH_ORATISALOG ORATISALOG 2268 oratismadi MACH_ORATISMADI ORATISMADI 2269 oratisot16 MACH_ORATISOT16 ORATISOT16 2270 oratisdesk MACH_ORATISDESK ORATISDESK 2271 -v2_ca9 MACH_V2P_CA9 V2P_CA9 2272 +vexpress MACH_VEXPRESS VEXPRESS 2272 sintexo MACH_SINTEXO SINTEXO 2273 cm3389 MACH_CM3389 CM3389 2274 omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 @@ -2636,3 +2636,45 @@ hw90240 MACH_HW90240 HW90240 2648 dm365_leopard MACH_DM365_LEOPARD DM365_LEOPARD 2649 mityomapl138 MACH_MITYOMAPL138 MITYOMAPL138 2650 scat110 MACH_SCAT110 SCAT110 2651 +acer_a1 MACH_ACER_A1 ACER_A1 2652 +cmcontrol MACH_CMCONTROL CMCONTROL 2653 +pelco_lamar MACH_PELCO_LAMAR PELCO_LAMAR 2654 +rfp43 MACH_RFP43 RFP43 2655 +sk86r0301 MACH_SK86R0301 SK86R0301 2656 +ctpxa MACH_CTPXA CTPXA 2657 +epb_arm9_a MACH_EPB_ARM9_A EPB_ARM9_A 2658 +guruplug MACH_GURUPLUG GURUPLUG 2659 +spear310 MACH_SPEAR310 SPEAR310 2660 +spear320 MACH_SPEAR320 SPEAR320 2661 +robotx MACH_ROBOTX ROBOTX 2662 +lsxhl MACH_LSXHL LSXHL 2663 +smartlite MACH_SMARTLITE SMARTLITE 2664 +cws2 MACH_CWS2 CWS2 2665 +m619 MACH_M619 M619 2666 +smartview MACH_SMARTVIEW SMARTVIEW 2667 +lsa_salsa MACH_LSA_SALSA LSA_SALSA 2668 +kizbox MACH_KIZBOX KIZBOX 2669 +htccharmer MACH_HTCCHARMER HTCCHARMER 2670 +guf_neso_lt MACH_GUF_NESO_LT GUF_NESO_LT 2671 +pm9g45 MACH_PM9G45 PM9G45 2672 +htcpanther MACH_HTCPANTHER HTCPANTHER 2673 +htcpanther_cdma MACH_HTCPANTHER_CDMA HTCPANTHER_CDMA 2674 +reb01 MACH_REB01 REB01 2675 +aquila MACH_AQUILA AQUILA 2676 +spark_sls_hw2 MACH_SPARK_SLS_HW2 SPARK_SLS_HW2 2677 +sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678 +surf7x30 MACH_SURF7X30 SURF7X30 2679 +micro2440 MACH_MICRO2440 MICRO2440 2680 +am2440 MACH_AM2440 AM2440 2681 +tq2440 MACH_TQ2440 TQ2440 2682 +lpc2478oem MACH_LPC2478OEM LPC2478OEM 2683 +ak880x MACH_AK880X AK880X 2684 +cobra3530 MACH_COBRA3530 COBRA3530 2685 +pmppb MACH_PMPPB PMPPB 2686 +u6715 MACH_U6715 U6715 2687 +axar1500_sender MACH_AXAR1500_SENDER AXAR1500_SENDER 2688 +g30_dvb MACH_G30_DVB G30_DVB 2689 +vc088x MACH_VC088X VC088X 2690 +mioa702 MACH_MIOA702 MIOA702 2691 +hpmin MACH_HPMIN HPMIN 2692 +ak880xak MACH_AK880XAK AK880XAK 2693 diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c index 1aa1ea5e9212..b13d1879e51b 100644 --- a/arch/avr32/mach-at32ap/at32ap700x.c +++ b/arch/avr32/mach-at32ap/at32ap700x.c @@ -1325,7 +1325,7 @@ struct platform_device *__init at32_add_device_mci(unsigned int id, struct mci_platform_data *data) { struct platform_device *pdev; - struct mci_dma_slave *slave; + struct mci_dma_data *slave; u32 pioa_mask; u32 piob_mask; @@ -1344,7 +1344,9 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data) ARRAY_SIZE(atmel_mci0_resource))) goto fail; - slave = kzalloc(sizeof(struct mci_dma_slave), GFP_KERNEL); + slave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL); + if (!slave) + goto fail; slave->sdata.dma_dev = &dw_dmac0_device.dev; slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT; @@ -1357,7 +1359,7 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data) if (platform_device_add_data(pdev, data, sizeof(struct mci_platform_data))) - goto fail; + goto fail_free; /* CLK line is common to both slots */ pioa_mask = 1 << 10; @@ -1381,7 +1383,7 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data) /* Slot is unused */ break; default: - goto fail; + goto fail_free; } select_peripheral(PIOA, pioa_mask, PERIPH_A, 0); @@ -1408,7 +1410,7 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data) break; default: if (!data->slot[0].bus_width) - goto fail; + goto fail_free; data->slot[1].bus_width = 0; break; @@ -1419,9 +1421,10 @@ at32_add_device_mci(unsigned int id, struct mci_platform_data *data) platform_device_add(pdev); return pdev; +fail_free: + kfree(slave); fail: data->dma_slave = NULL; - kfree(slave); platform_device_put(pdev); return NULL; } diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h index 7ae58892ba8d..e97b255d97bc 100644 --- a/arch/ia64/include/asm/acpi.h +++ b/arch/ia64/include/asm/acpi.h @@ -94,6 +94,7 @@ ia64_acpi_release_global_lock (unsigned int *lock) #define acpi_noirq 0 /* ACPI always enabled on IA64 */ #define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */ #define acpi_strict 1 /* no ACPI spec workarounds on IA64 */ +#define acpi_ht 0 /* no HT-only mode on IA64 */ #endif #define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */ static inline void disable_acpi(void) { } diff --git a/arch/ia64/include/asm/elf.h b/arch/ia64/include/asm/elf.h index e14108b19c09..4c41656ede87 100644 --- a/arch/ia64/include/asm/elf.h +++ b/arch/ia64/include/asm/elf.h @@ -201,7 +201,9 @@ extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst); relevant until we have real hardware to play with... */ #define ELF_PLATFORM NULL -#define SET_PERSONALITY(ex) set_personality(PER_LINUX) +#define SET_PERSONALITY(ex) \ + set_personality((current->personality & ~PER_MASK) | PER_LINUX) + #define elf_read_implies_exec(ex, executable_stack) \ ((executable_stack!=EXSTACK_DISABLE_X) && ((ex).e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK) != 0) diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c index 5372b24ad049..bb8c4b9ccb80 100644 --- a/arch/microblaze/kernel/setup.c +++ b/arch/microblaze/kernel/setup.c @@ -54,6 +54,7 @@ void __init setup_arch(char **cmdline_p) microblaze_cache_init(); + invalidate_dcache(); enable_dcache(); invalidate_icache(); diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index ed84b4cb3c8d..84b6503f10b9 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.23-rc2 -# Tue Aug 7 13:04:24 2007 +# Linux kernel version: 2.6.33-rc6 +# Wed Feb 3 18:12:31 2010 # CONFIG_MIPS=y @@ -9,20 +9,28 @@ CONFIG_MIPS=y # Machine selection # # CONFIG_MACH_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set -# CONFIG_LEMOTE_FULONG is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MARKEINS is not set +# CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set +# CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set CONFIG_SGI_IP27=y +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set @@ -33,32 +41,39 @@ CONFIG_SGI_IP27=y # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set CONFIG_SGI_SN_M_MODE=y # CONFIG_SGI_SN_N_MODE is not set # CONFIG_MAPPED_KERNEL is not set # CONFIG_REPLICATE_KTEXT is not set # CONFIG_REPLICATE_EXHANDLERS is not set +CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_ARC=y CONFIG_DMA_COHERENT=y -CONFIG_EARLY_PRINTK=y CONFIG_SYS_HAS_EARLY_PRINTK=y # CONFIG_NO_IOPORT is not set CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_DEFAULT_SGI_PARTITION=y CONFIG_MIPS_L1_CACHE_SHIFT=7 CONFIG_ARC64=y CONFIG_BOOT_ELF64=y @@ -66,7 +81,8 @@ CONFIG_BOOT_ELF64=y # # CPU selection # -# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_LOONGSON2E is not set +# CONFIG_CPU_LOONGSON2F is not set # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -79,6 +95,7 @@ CONFIG_BOOT_ELF64=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -86,6 +103,7 @@ CONFIG_CPU_R10000=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_R10000=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y @@ -99,6 +117,7 @@ CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y @@ -110,6 +129,7 @@ CONFIG_GENERIC_IRQ_PROBE=y CONFIG_IRQ_PER_CPU=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_DISCONTIGMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_NUMA=y CONFIG_SYS_SUPPORTS_NUMA=y CONFIG_NODES_SHIFT=6 @@ -120,16 +140,22 @@ CONFIG_DISCONTIGMEM_MANUAL=y CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y -CONFIG_RESOURCES_64BIT=y +CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 CONFIG_SMP=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_NR_CPUS_DEFAULT_64=y CONFIG_NR_CPUS=64 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -142,13 +168,13 @@ CONFIG_HZ=1000 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set -CONFIG_PREEMPT_BKL=y # CONFIG_MIPS_INSANE_LARGE is not set # CONFIG_KEXEC is not set CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # # General setup @@ -162,20 +188,41 @@ CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set # CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_TINY_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=64 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_GROUP_SCHED is not set CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set CONFIG_CPUSETS=y -CONFIG_SYSFS_DEPRECATED=y +CONFIG_PROC_PID_CPUSET=y +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set # CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y @@ -184,44 +231,92 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y -CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_SYSCALL_WRAPPERS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y + +# +# GCOV-based kernel profiling +# +CONFIG_SLOW_WORK=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set # CONFIG_MODVERSIONS is not set CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y -# CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CGROUP is not set +CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y +# CONFIG_CFQ_GROUP_IOSCHED is not set # CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_INLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +CONFIG_INLINE_READ_UNLOCK=y +# CONFIG_INLINE_READ_UNLOCK_BH is not set +CONFIG_INLINE_READ_UNLOCK_IRQ=y +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +CONFIG_INLINE_WRITE_UNLOCK=y +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -230,11 +325,10 @@ CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_LEGACY is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set @@ -242,8 +336,9 @@ CONFIG_MMU=y # Executable file formats # CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set -# CONFIG_BUILD_ELF64 is not set CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y @@ -255,13 +350,10 @@ CONFIG_BINFMT_ELF32=y # Power management options # CONFIG_PM=y -# CONFIG_PM_LEGACY is not set # CONFIG_PM_DEBUG is not set - -# -# Networking -# +# CONFIG_PM_RUNTIME is not set CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y # # Networking options @@ -273,6 +365,8 @@ CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=m CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y @@ -292,19 +386,40 @@ CONFIG_IP_PNP=y # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set +CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y -# CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_PIMSM_V2=y CONFIG_NETWORK_SECMARK=y # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -314,9 +429,11 @@ CONFIG_IP_SCTP=m # CONFIG_SCTP_HMAC_NONE is not set # CONFIG_SCTP_HMAC_SHA1 is not set CONFIG_SCTP_HMAC_MD5=y +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -326,12 +443,9 @@ CONFIG_SCTP_HMAC_MD5=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y -CONFIG_NET_SCH_FIFO=y # # Queueing/Scheduling @@ -340,7 +454,7 @@ CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m CONFIG_NET_SCH_HFSC=m CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_RR=m +CONFIG_NET_SCH_MULTIQ=y CONFIG_NET_SCH_RED=m CONFIG_NET_SCH_SFQ=m CONFIG_NET_SCH_TEQL=m @@ -348,6 +462,7 @@ CONFIG_NET_SCH_TBF=m CONFIG_NET_SCH_GRED=m CONFIG_NET_SCH_DSMARK=m CONFIG_NET_SCH_NETEM=m +# CONFIG_NET_SCH_DRR is not set CONFIG_NET_SCH_INGRESS=m # @@ -364,41 +479,63 @@ CONFIG_NET_CLS_U32=m CONFIG_CLS_U32_MARK=y CONFIG_NET_CLS_RSVP=m CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=y # CONFIG_NET_EMATCH is not set CONFIG_NET_CLS_ACT=y CONFIG_NET_ACT_POLICE=y CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m # CONFIG_NET_ACT_SIMP is not set -CONFIG_NET_CLS_POLICE=y +CONFIG_NET_ACT_SKBEDIT=m # CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set - -# -# Wireless -# -CONFIG_CFG80211=m +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_WIRELESS_OLD_REGULATORY is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=m +CONFIG_LIB80211_CRYPT_WEP=m +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +# CONFIG_LIB80211_DEBUG is not set CONFIG_MAC80211=m -# CONFIG_MAC80211_DEBUG is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_CRYPT_TKIP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set +CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_RC_MINSTREL=y +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel" +# CONFIG_MAC80211_MESH is not set +CONFIG_MAC80211_LEDS=y +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y # CONFIG_NET_9P is not set # @@ -408,9 +545,13 @@ CONFIG_RFKILL=m # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=m # CONFIG_MTD is not set @@ -423,14 +564,19 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_OSD=m # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set CONFIG_ATA_OVER_ETH=m +# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set +CONFIG_EEPROM_93CX6=m +CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # @@ -453,10 +599,6 @@ CONFIG_BLK_DEV_SR=m CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=m CONFIG_CHR_DEV_SCH=m - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# # CONFIG_SCSI_MULTI_LUN is not set CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y @@ -471,11 +613,18 @@ CONFIG_SCSI_FC_ATTRS=y CONFIG_SCSI_ISCSI_ATTRS=m CONFIG_SCSI_SAS_ATTRS=m CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SAS_HOST_SMP=y # CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set +# CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_BE2ISCSI=m # CONFIG_BLK_DEV_3W_XXXX_RAID is not set +CONFIG_SCSI_HPSA=m # CONFIG_SCSI_3W_9XXX is not set +CONFIG_SCSI_3W_SAS=m # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set @@ -483,11 +632,21 @@ CONFIG_SCSI_LOWLEVEL=y # CONFIG_SCSI_AIC79XX is not set CONFIG_SCSI_AIC94XX=m # CONFIG_AIC94XX_DEBUG is not set +CONFIG_SCSI_MVSAS=m +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_DPT_I2O=m +# CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +# CONFIG_SCSI_MPT2SAS_LOGGING is not set # CONFIG_SCSI_HPTIOP is not set +CONFIG_LIBFC=m +# CONFIG_LIBFCOE is not set +# CONFIG_FCOE is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set @@ -502,16 +661,31 @@ CONFIG_SCSI_QLOGIC_1280=y # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set +CONFIG_SCSI_PMCRAID=m +# CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_DH=m +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_OSD_INITIATOR=m +CONFIG_SCSI_OSD_ULD=m +CONFIG_SCSI_OSD_DPRINT_SENSE=1 +# CONFIG_SCSI_OSD_DEBUG is not set # CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=y CONFIG_MD_RAID1=y CONFIG_MD_RAID10=m CONFIG_MD_RAID456=y -CONFIG_MD_RAID5_RESHAPE=y +# CONFIG_MULTICORE_RAID456 is not set +CONFIG_MD_RAID6_PQ=y +# CONFIG_ASYNC_RAID6_TEST is not set CONFIG_MD_MULTIPATH=m CONFIG_MD_FAULTY=m CONFIG_BLK_DEV_DM=m @@ -519,36 +693,39 @@ CONFIG_BLK_DEV_DM=m CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_EMC=m -CONFIG_DM_MULTIPATH_RDAC=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m # CONFIG_DM_DELAY is not set +CONFIG_DM_UEVENT=y +# CONFIG_FUSION is not set # -# Fusion MPT device support +# IEEE 1394 (FireWire) support # -# CONFIG_FUSION is not set -# CONFIG_FUSION_SPI is not set -# CONFIG_FUSION_FC is not set -# CONFIG_FUSION_SAS is not set # -# IEEE 1394 (FireWire) support +# You can enable one or both FireWire driver stacks. +# + +# +# The newer stack is recommended. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -CONFIG_NETDEVICES_MULTIQUEUE=y CONFIG_IFB=m # CONFIG_DUMMY is not set # CONFIG_BONDING is not set CONFIG_MACVLAN=m # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +CONFIG_VETH=m # CONFIG_ARCNET is not set -CONFIG_PHYLIB=m +CONFIG_PHYLIB=y # # MII PHY device drivers @@ -562,23 +739,51 @@ CONFIG_VITESSE_PHY=m CONFIG_SMSC_PHY=m # CONFIG_BROADCOM_PHY is not set CONFIG_ICPLUS_PHY=m +CONFIG_REALTEK_PHY=m +CONFIG_NATIONAL_PHY=m +CONFIG_STE10XP=m +CONFIG_LSI_ET1011C_PHY=m # CONFIG_FIXED_PHY is not set +CONFIG_MDIO_BITBANG=m CONFIG_NET_ETHERNET=y CONFIG_MII=y CONFIG_AX88796=m +CONFIG_AX88796_93CX6=y CONFIG_SGI_IOC3_ETH=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set +CONFIG_SMC91X=m # CONFIG_DM9000 is not set +CONFIG_ETHOC=m +CONFIG_SMSC911X=m +CONFIG_DNET=m # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set +CONFIG_B44=m +CONFIG_B44_PCI_AUTOSELECT=y +CONFIG_B44_PCICORE_AUTOSELECT=y +CONFIG_B44_PCI=y +CONFIG_KS8842=m +CONFIG_KS8851_MLL=m +CONFIG_ATL2=m CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set +CONFIG_E1000E=m +CONFIG_IP1000=m +CONFIG_IGB=m +CONFIG_IGBVF=m # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -588,24 +793,75 @@ CONFIG_NETDEV_1000=y # CONFIG_SKY2 is not set CONFIG_VIA_VELOCITY=m # CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set +CONFIG_BNX2=m +CONFIG_CNIC=m CONFIG_QLA3XXX=m # CONFIG_ATL1 is not set +CONFIG_ATL1E=m +CONFIG_ATL1C=m +CONFIG_JME=m CONFIG_NETDEV_10000=y +CONFIG_MDIO=m # CONFIG_CHELSIO_T1 is not set +CONFIG_CHELSIO_T3_DEPENDS=y CONFIG_CHELSIO_T3=m +CONFIG_ENIC=m +CONFIG_IXGBE=m # CONFIG_IXGB is not set # CONFIG_S2IO is not set +CONFIG_VXGE=m +# CONFIG_VXGE_DEBUG_TRACE_ALL is not set # CONFIG_MYRI10GE is not set CONFIG_NETXEN_NIC=m -# CONFIG_MLX4_CORE is not set +CONFIG_NIU=m +CONFIG_MLX4_EN=m +CONFIG_MLX4_CORE=m +# CONFIG_MLX4_DEBUG is not set +CONFIG_TEHUTI=m +CONFIG_BNX2X=m +CONFIG_QLGE=m +CONFIG_SFC=m +CONFIG_BE2NET=m # CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -CONFIG_WLAN_80211=y +CONFIG_WLAN=y +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_ATMEL=m +CONFIG_PCI_ATMEL=m +CONFIG_PRISM54=m +CONFIG_RTL8180=m +CONFIG_ADM8211=m +# CONFIG_MAC80211_HWSIM is not set +CONFIG_MWL8K=m +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH5K=m +# CONFIG_ATH5K_DEBUG is not set +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K=m +CONFIG_B43=m +CONFIG_B43_PCI_AUTOSELECT=y +CONFIG_B43_PCICORE_AUTOSELECT=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_LEDS=y +CONFIG_B43_HWRNG=y +# CONFIG_B43_DEBUG is not set +CONFIG_B43LEGACY=m +CONFIG_B43LEGACY_PCI_AUTOSELECT=y +CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y +CONFIG_B43LEGACY_LEDS=y +CONFIG_B43LEGACY_HWRNG=y +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY_PIO=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_HOSTAP_PLX=m +CONFIG_HOSTAP_PCI=m CONFIG_IPW2100=m CONFIG_IPW2100_MONITOR=y CONFIG_IPW2100_DEBUG=y @@ -615,38 +871,57 @@ CONFIG_IPW2200_RADIOTAP=y CONFIG_IPW2200_PROMISCUOUS=y CONFIG_IPW2200_QOS=y CONFIG_IPW2200_DEBUG=y +CONFIG_LIBIPW=m +# CONFIG_LIBIPW_DEBUG is not set +CONFIG_IWLWIFI=m +CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT=y +# CONFIG_IWLWIFI_DEBUG is not set +CONFIG_IWLAGN=m +CONFIG_IWL4965=y +CONFIG_IWL5000=y +CONFIG_IWL3945=m +CONFIG_IWL3945_SPECTRUM_MEASUREMENT=y CONFIG_LIBERTAS=m # CONFIG_LIBERTAS_DEBUG is not set CONFIG_HERMES=m +# CONFIG_HERMES_CACHE_FW_ON_INIT is not set CONFIG_PLX_HERMES=m CONFIG_TMD_HERMES=m CONFIG_NORTEL_HERMES=m CONFIG_PCI_HERMES=m -CONFIG_ATMEL=m -CONFIG_PCI_ATMEL=m -CONFIG_PRISM54=m -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -CONFIG_HOSTAP_PLX=m -CONFIG_HOSTAP_PCI=m -CONFIG_BCM43XX=m -CONFIG_BCM43XX_DEBUG=y -CONFIG_BCM43XX_DMA=y -CONFIG_BCM43XX_PIO=y -CONFIG_BCM43XX_DMA_AND_PIO_MODE=y -# CONFIG_BCM43XX_DMA_MODE is not set -# CONFIG_BCM43XX_PIO_MODE is not set +CONFIG_P54_COMMON=m +CONFIG_P54_PCI=m +CONFIG_P54_LEDS=y +CONFIG_RT2X00=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT61PCI=m +CONFIG_RT2800PCI_PCI=m +CONFIG_RT2800PCI=m +CONFIG_RT2800_LIB=m +CONFIG_RT2X00_LIB_PCI=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_HT=y +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_DEBUG is not set +CONFIG_WL12XX=m +CONFIG_WL1251=m + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set @@ -664,13 +939,16 @@ CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=m CONFIG_SERIO_RAW=m +CONFIG_SERIO_ALTERA_PS2=m # CONFIG_GAMEPORT is not set # # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_NOZOMI=m # # Serial drivers @@ -693,95 +971,258 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set CONFIG_HW_RANDOM=m -# CONFIG_RTC is not set +CONFIG_HW_RANDOM_TIMERIOMEM=m # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_DRM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y -# CONFIG_I2C is not set +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +CONFIG_I2C_ALI1535=m +CONFIG_I2C_ALI1563=m +CONFIG_I2C_ALI15X3=m +CONFIG_I2C_AMD756=m +CONFIG_I2C_AMD8111=m +CONFIG_I2C_I801=m +CONFIG_I2C_ISCH=m +CONFIG_I2C_PIIX4=m +CONFIG_I2C_NFORCE2=m +CONFIG_I2C_SIS5595=m +CONFIG_I2C_SIS630=m +CONFIG_I2C_SIS96X=m +CONFIG_I2C_VIA=m +CONFIG_I2C_VIAPRO=m # -# SPI support +# I2C system bus drivers (mostly embedded / system-on-chip) # +CONFIG_I2C_OCORES=m +CONFIG_I2C_SIMTEC=m + +# +# External I2C/SMBus adapter drivers +# +CONFIG_I2C_PARPORT_LIGHT=m +CONFIG_I2C_TAOS_EVM=m + +# +# Other I2C/SMBus bus drivers +# +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_STUB=m + +# +# Miscellaneous I2C Chip support +# +CONFIG_SENSORS_TSL2550=m +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set + +# +# PPS support +# +CONFIG_PPS=m +# CONFIG_PPS_DEBUG is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set +CONFIG_THERMAL=m +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y # -# Multifunction device drivers -# -# CONFIG_MFD_SM501 is not set +# Sonics Silicon Backplane +# +CONFIG_SSB=m +CONFIG_SSB_SPROM=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_B43_PCI_BRIDGE=y +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +CONFIG_SSB_DRIVER_PCICORE=y +# CONFIG_SSB_DRIVER_MIPS is not set # -# Multimedia devices +# Multifunction device drivers # -# CONFIG_VIDEO_DEV is not set -# CONFIG_DVB_CORE is not set -# CONFIG_DAB is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +CONFIG_MFD_WM8350=m +CONFIG_MFD_WM8350_I2C=m +CONFIG_MFD_PCF50633=m +CONFIG_PCF50633_ADC=m +CONFIG_PCF50633_GPIO=m +CONFIG_AB3100_CORE=m +CONFIG_AB3100_OTP=m +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support # -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # -# Sound +# Display device support # +# CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# Enable Host or Gadget support to see Inventra options # # -# USB Gadget Support +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_UWB is not set # CONFIG_MMC is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_INFINIBAND is not set -# CONFIG_RTC_CLASS is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=m + +# +# LED drivers +# +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_PCA955X=m +CONFIG_LEDS_WM8350=m +CONFIG_LEDS_BD2802=m + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m # -# DMA Engine support +# iptables trigger is under Netfilter config (LED target) # -# CONFIG_DMA_ENGINE is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set # -# DMA Clients +# RTC interfaces # +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set # -# DMA Devices +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# + # +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +CONFIG_RTC_DRV_M48T35=y +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_WM8350 is not set +# CONFIG_RTC_DRV_PCF50633 is not set +CONFIG_RTC_DRV_AB3100=m # -# Userspace I/O +# on-CPU RTC drivers # +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set CONFIG_UIO=y # CONFIG_UIO_CIF is not set +# CONFIG_UIO_PDRV is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +CONFIG_UIO_SMX=m +CONFIG_UIO_AEC=m +CONFIG_UIO_SERCOS3=m +CONFIG_UIO_PCI_GENERIC=m + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set # # File systems @@ -792,36 +1233,58 @@ CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set CONFIG_JBD=y -CONFIG_JBD_DEBUG=y +CONFIG_JBD2=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=m CONFIG_XFS_QUOTA=y -CONFIG_XFS_SECURITY=y CONFIG_XFS_POSIX_ACL=y # CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_BTRFS_FS=m +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set +CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QUOTACTL=y -CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m # CONFIG_AUTOFS4_FS is not set CONFIG_FUSE_FS=m +CONFIG_CUSE=m CONFIG_GENERIC_ACL=y # +# Caches +# +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +CONFIG_CACHEFILES=m +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_HISTOGRAM is not set + +# # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set @@ -840,16 +1303,13 @@ CONFIG_GENERIC_ACL=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set @@ -859,28 +1319,32 @@ CONFIG_CONFIGFS_FS=m # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=m +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +CONFIG_OMFS_FS=m # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_EXOFS_FS=m +# CONFIG_EXOFS_DEBUG is not set +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set # CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_BIND34 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set @@ -910,35 +1374,37 @@ CONFIG_SGI_PARTITION=y # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set - -# -# Native Language Support -# # CONFIG_NLS is not set - -# -# Distributed Lock Manager -# CONFIG_DLM=m # CONFIG_DLM_DEBUG is not set # -# Profiling support -# -# CONFIG_PROFILING is not set - -# # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 # CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_EARLY_PRINTK=y # CONFIG_CMDLINE_BOOL is not set # @@ -947,65 +1413,140 @@ CONFIG_CROSSCOMPILE=y CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set -CONFIG_XOR_BLOCKS=m -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m +CONFIG_SECURITYFS=y +# CONFIG_DEFAULT_SECURITY_SELINUX is not set +# CONFIG_DEFAULT_SECURITY_SMACK is not set +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_XOR_BLOCKS=y +CONFIG_ASYNC_CORE=y +CONFIG_ASYNC_MEMCPY=y +CONFIG_ASYNC_XOR=y +CONFIG_ASYNC_PQ=y +CONFIG_ASYNC_RAID6_RECOV=y CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_FIPS=y CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ABLKCIPHER=m +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_VMAC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_GHASH=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set +CONFIG_CRYPTO_ZLIB=m +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_HIFN_795X=m +# CONFIG_CRYPTO_DEV_HIFN_795X_RNG is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y CONFIG_CRC_CCITT=m -# CONFIG_CRC16 is not set -# CONFIG_CRC_ITU_T is not set +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=m +CONFIG_CRC_ITU_T=m CONFIG_CRC32=y -# CONFIG_CRC7 is not set +CONFIG_CRC7=m CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m -CONFIG_PLIST=y +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9c187a64649b..758ad426c57f 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -287,9 +287,9 @@ static inline int __cpu_has_fpu(void) static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) { #ifdef __NEED_VMBITS_PROBE - write_c0_entryhi(0x3ffffffffffff000ULL); + write_c0_entryhi(0x3fffffffffffe000ULL); back_to_back_c0_hazard(); - c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); + c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); #endif } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 338dfe8ed002..31b204b26ba0 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1501,6 +1501,7 @@ void __cpuinit per_cpu_trap_init(void) cp0_perfcount_irq = -1; } else { cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; + cp0_compare_irq_shift = cp0_compare_irq; cp0_perfcount_irq = -1; } diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index 94e05e5733c1..e06f1af760a7 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -174,7 +174,7 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma, * Probe Octeon's caches * */ -static void __devinit probe_octeon(void) +static void __cpuinit probe_octeon(void) { unsigned long icache_size; unsigned long dcache_size; @@ -235,7 +235,7 @@ static void __devinit probe_octeon(void) * Setup the Octeon cache flush routines * */ -void __devinit octeon_cache_init(void) +void __cpuinit octeon_cache_init(void) { extern unsigned long ebase; extern char except_vec2_octeon; diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 102b2dfa542a..e716cafc346d 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -155,7 +155,7 @@ static inline void setup_protection_map(void) protection_map[15] = PAGE_SHARED; } -void __devinit cpu_cache_init(void) +void __cpuinit cpu_cache_init(void) { if (cpu_has_3k_cache) { extern void __weak r3k_cache_init(void); diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index 46f00691f448..31e2583ec622 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c @@ -404,7 +404,7 @@ void __init sni_rm200_i8259_irqs(void) if (!rm200_pic_master) return; rm200_pic_slave = ioremap_nocache(0x160000a0, 4); - if (!rm200_pic_master) { + if (!rm200_pic_slave) { iounmap(rm200_pic_master); return; } diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c index fb37ac52e46c..35c827e94e31 100644 --- a/arch/parisc/kernel/signal.c +++ b/arch/parisc/kernel/signal.c @@ -468,7 +468,9 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, recalc_sigpending(); spin_unlock_irq(¤t->sighand->siglock); - tracehook_signal_handler(sig, info, ka, regs, 0); + tracehook_signal_handler(sig, info, ka, regs, + test_thread_flag(TIF_SINGLESTEP) || + test_thread_flag(TIF_BLOCKSTEP)); return 1; } diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c index 282d9306361f..1ec06576f619 100644 --- a/arch/powerpc/mm/tlb_hash64.c +++ b/arch/powerpc/mm/tlb_hash64.c @@ -63,15 +63,21 @@ void hpte_need_flush(struct mm_struct *mm, unsigned long addr, if (huge) { #ifdef CONFIG_HUGETLB_PAGE psize = get_slice_psize(mm, addr); + /* Mask the address for the correct page size */ + addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1); #else BUG(); psize = pte_pagesize_index(mm, addr, pte); /* shutup gcc */ #endif - } else + } else { psize = pte_pagesize_index(mm, addr, pte); + /* Mask the address for the standard page size. If we + * have a 64k page kernel, but the hardware does not + * support 64k pages, this might be different from the + * hardware page size encoded in the slice table. */ + addr &= PAGE_MASK; + } - /* Mask the address for the correct page size */ - addr &= ~((1UL << mmu_psize_defs[psize].shift) - 1); /* Build full vaddr */ if (!is_kernel_addr(addr)) { diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 21f61b8c445b..cc29c0f5300d 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -338,7 +338,8 @@ static void __init mpc85xx_mds_pic_init(void) } mpic = mpic_alloc(np, r.start, - MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, + MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | + MPIC_BROKEN_FRR_NIRQS, 0, 256, " OpenPIC "); BUG_ON(mpic == NULL); of_node_put(np); diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c index 04160a4cc699..a15f582300d8 100644 --- a/arch/powerpc/platforms/85xx/smp.c +++ b/arch/powerpc/platforms/85xx/smp.c @@ -46,6 +46,7 @@ smp_85xx_kick_cpu(int nr) __iomem u32 *bptr_vaddr; struct device_node *np; int n = 0; + int ioremappable; WARN_ON (nr < 0 || nr >= NR_CPUS); @@ -59,21 +60,37 @@ smp_85xx_kick_cpu(int nr) return; } + /* + * A secondary core could be in a spinloop in the bootpage + * (0xfffff000), somewhere in highmem, or somewhere in lowmem. + * The bootpage and highmem can be accessed via ioremap(), but + * we need to directly access the spinloop if its in lowmem. + */ + ioremappable = *cpu_rel_addr > virt_to_phys(high_memory); + /* Map the spin table */ - bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); + if (ioremappable) + bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY); + else + bptr_vaddr = phys_to_virt(*cpu_rel_addr); local_irq_save(flags); out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr); out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start)); + if (!ioremappable) + flush_dcache_range((ulong)bptr_vaddr, + (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY)); + /* Wait a bit for the CPU to ack. */ while ((__secondary_hold_acknowledge != nr) && (++n < 1000)) mdelay(1); local_irq_restore(flags); - iounmap(bptr_vaddr); + if (ioremappable) + iounmap(bptr_vaddr); pr_debug("waited %d msecs for CPU #%d.\n", n, nr); } diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c index 1ee66db003be..f5f79196721c 100644 --- a/arch/powerpc/platforms/pseries/xics.c +++ b/arch/powerpc/platforms/pseries/xics.c @@ -784,9 +784,13 @@ static void xics_set_cpu_priority(unsigned char cppr) { struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); - BUG_ON(os_cppr->index != 0); + /* + * we only really want to set the priority when there's + * just one cppr value on the stack + */ + WARN_ON(os_cppr->index != 0); - os_cppr->stack[os_cppr->index] = cppr; + os_cppr->stack[0] = cppr; if (firmware_has_feature(FW_FEATURE_LPAR)) lpar_cppr_info(cppr); @@ -821,8 +825,14 @@ void xics_setup_cpu(void) void xics_teardown_cpu(void) { + struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr); int cpu = smp_processor_id(); + /* + * we have to reset the cppr index to 0 because we're + * not going to return from the IPI + */ + os_cppr->index = 0; xics_set_cpu_priority(0); /* Clear any pending IPI request */ diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h index f2ef4b619ce1..c25dfac7dd76 100644 --- a/arch/s390/include/asm/lowcore.h +++ b/arch/s390/include/asm/lowcore.h @@ -293,12 +293,12 @@ struct _lowcore __u64 clock_comparator; /* 0x02d0 */ __u32 machine_flags; /* 0x02d8 */ __u32 ftrace_func; /* 0x02dc */ - __u8 pad_0x02f0[0x0300-0x02f0]; /* 0x02f0 */ + __u8 pad_0x02e0[0x0300-0x02e0]; /* 0x02e0 */ /* Interrupt response block */ __u8 irb[64]; /* 0x0300 */ - __u8 pad_0x0400[0x0e00-0x0400]; /* 0x0400 */ + __u8 pad_0x0340[0x0e00-0x0340]; /* 0x0340 */ /* * 0xe00 contains the address of the IPL Parameter Information diff --git a/arch/sh/kernel/cpu/sh3/entry.S b/arch/sh/kernel/cpu/sh3/entry.S index 3f7e2a22c7c2..f6a389c996cb 100644 --- a/arch/sh/kernel/cpu/sh3/entry.S +++ b/arch/sh/kernel/cpu/sh3/entry.S @@ -132,7 +132,6 @@ ENTRY(tlb_protection_violation_store) mov #1, r5 call_handle_tlbmiss: - setup_frame_reg mov.l 1f, r0 mov r5, r8 mov.l @r0, r6 @@ -365,6 +364,8 @@ handle_exception: mov.l @k2, k2 ! read out vector and keep in k2 handle_exception_special: + setup_frame_reg + ! Setup return address and jump to exception handler mov.l 7f, r9 ! fetch return address stc r2_bank, r0 ! k2 (vector) diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c index 88d28ec3780a..e51168064e56 100644 --- a/arch/sh/kernel/dwarf.c +++ b/arch/sh/kernel/dwarf.c @@ -540,6 +540,8 @@ void dwarf_free_frame(struct dwarf_frame *frame) mempool_free(frame, dwarf_frame_pool); } +extern void ret_from_irq(void); + /** * dwarf_unwind_stack - unwind the stack * @@ -678,6 +680,24 @@ struct dwarf_frame * dwarf_unwind_stack(unsigned long pc, addr = frame->cfa + reg->addr; frame->return_addr = __raw_readl(addr); + /* + * Ah, the joys of unwinding through interrupts. + * + * Interrupts are tricky - the DWARF info needs to be _really_ + * accurate and unfortunately I'm seeing a lot of bogus DWARF + * info. For example, I've seen interrupts occur in epilogues + * just after the frame pointer (r14) had been restored. The + * problem was that the DWARF info claimed that the CFA could be + * reached by using the value of the frame pointer before it was + * restored. + * + * So until the compiler can be trusted to produce reliable + * DWARF info when it really matters, let's stop unwinding once + * we've calculated the function that was interrupted. + */ + if (prev && prev->pc == (unsigned long)ret_from_irq) + frame->return_addr = 0; + return frame; bail: diff --git a/arch/sh/kernel/entry-common.S b/arch/sh/kernel/entry-common.S index f0abd58c3a69..2b15ae60c3a0 100644 --- a/arch/sh/kernel/entry-common.S +++ b/arch/sh/kernel/entry-common.S @@ -70,8 +70,14 @@ ret_from_exception: CFI_STARTPROC simple CFI_DEF_CFA r14, 0 CFI_REL_OFFSET 17, 64 - CFI_REL_OFFSET 15, 0 + CFI_REL_OFFSET 15, 60 CFI_REL_OFFSET 14, 56 + CFI_REL_OFFSET 13, 52 + CFI_REL_OFFSET 12, 48 + CFI_REL_OFFSET 11, 44 + CFI_REL_OFFSET 10, 40 + CFI_REL_OFFSET 9, 36 + CFI_REL_OFFSET 8, 32 preempt_stop() ENTRY(ret_from_irq) ! diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c index 873ebdc4f98e..b063eb8b18e3 100644 --- a/arch/sh/kernel/ptrace_64.c +++ b/arch/sh/kernel/ptrace_64.c @@ -133,6 +133,8 @@ void user_enable_single_step(struct task_struct *child) struct pt_regs *regs = child->thread.uregs; regs->sr |= SR_SSTEP; /* auto-resetting upon exception */ + + set_tsk_thread_flag(child, TIF_SINGLESTEP); } void user_disable_single_step(struct task_struct *child) @@ -140,6 +142,8 @@ void user_disable_single_step(struct task_struct *child) struct pt_regs *regs = child->thread.uregs; regs->sr &= ~SR_SSTEP; + + clear_tsk_thread_flag(child, TIF_SINGLESTEP); } static int genregs_get(struct task_struct *target, @@ -454,6 +458,8 @@ asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs) asmlinkage void do_syscall_trace_leave(struct pt_regs *regs) { + int step; + if (unlikely(current->audit_context)) audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]), regs->regs[9]); @@ -461,8 +467,9 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs) if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT))) trace_sys_exit(regs, regs->regs[9]); - if (test_thread_flag(TIF_SYSCALL_TRACE)) - tracehook_report_syscall_exit(regs, 0); + step = test_thread_flag(TIF_SINGLESTEP); + if (step || test_thread_flag(TIF_SYSCALL_TRACE)) + tracehook_report_syscall_exit(regs, step); } /* Called with interrupts disabled */ diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c index ce76dbdef294..580e97d46ca5 100644 --- a/arch/sh/kernel/signal_64.c +++ b/arch/sh/kernel/signal_64.c @@ -118,7 +118,9 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset) * clear the TS_RESTORE_SIGMASK flag. */ current_thread_info()->status &= ~TS_RESTORE_SIGMASK; - tracehook_signal_handler(signr, &info, &ka, regs, 0); + + tracehook_signal_handler(signr, &info, &ka, regs, + test_thread_flag(TIF_SINGLESTEP)); return 1; } } diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c index 2830b415e214..c49865b30719 100644 --- a/arch/sparc/kernel/process_32.c +++ b/arch/sparc/kernel/process_32.c @@ -526,7 +526,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp, * Set some valid stack frames to give to the child. */ childstack = (struct sparc_stackf __user *) - (sp & ~0x7UL); + (sp & ~0xfUL); parentstack = (struct sparc_stackf __user *) regs->u_regs[UREG_FP]; diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c index c3f1cce0e95e..cb70476bd8f5 100644 --- a/arch/sparc/kernel/process_64.c +++ b/arch/sparc/kernel/process_64.c @@ -398,11 +398,11 @@ static unsigned long clone_stackframe(unsigned long csp, unsigned long psp) } else __get_user(fp, &(((struct reg_window32 __user *)psp)->ins[6])); - /* Now 8-byte align the stack as this is mandatory in the - * Sparc ABI due to how register windows work. This hides - * the restriction from thread libraries etc. -DaveM + /* Now align the stack as this is mandatory in the Sparc ABI + * due to how register windows work. This hides the + * restriction from thread libraries etc. */ - csp &= ~7UL; + csp &= ~15UL; distance = fp - psp; rval = (csp - distance); diff --git a/arch/sparc/kernel/signal32.c b/arch/sparc/kernel/signal32.c index ba5b09ad6666..ea22cd373c64 100644 --- a/arch/sparc/kernel/signal32.c +++ b/arch/sparc/kernel/signal32.c @@ -120,8 +120,8 @@ struct rt_signal_frame32 { }; /* Align macros */ -#define SF_ALIGNEDSZ (((sizeof(struct signal_frame32) + 7) & (~7))) -#define RT_ALIGNEDSZ (((sizeof(struct rt_signal_frame32) + 7) & (~7))) +#define SF_ALIGNEDSZ (((sizeof(struct signal_frame32) + 15) & (~15))) +#define RT_ALIGNEDSZ (((sizeof(struct rt_signal_frame32) + 15) & (~15))) int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from) { @@ -420,15 +420,17 @@ static void __user *get_sigframe(struct sigaction *sa, struct pt_regs *regs, uns sp = current->sas_ss_sp + current->sas_ss_size; } + sp -= framesize; + /* Always align the stack frame. This handles two cases. First, * sigaltstack need not be mindful of platform specific stack * alignment. Second, if we took this signal because the stack * is not aligned properly, we'd like to take the signal cleanly * and report that. */ - sp &= ~7UL; + sp &= ~15UL; - return (void __user *)(sp - framesize); + return (void __user *) sp; } static int save_fpu_state32(struct pt_regs *regs, __siginfo_fpu_t __user *fpu) diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c index 7ce1a1005b1d..9882df92ba0a 100644 --- a/arch/sparc/kernel/signal_32.c +++ b/arch/sparc/kernel/signal_32.c @@ -267,15 +267,17 @@ static inline void __user *get_sigframe(struct sigaction *sa, struct pt_regs *re sp = current->sas_ss_sp + current->sas_ss_size; } + sp -= framesize; + /* Always align the stack frame. This handles two cases. First, * sigaltstack need not be mindful of platform specific stack * alignment. Second, if we took this signal because the stack * is not aligned properly, we'd like to take the signal cleanly * and report that. */ - sp &= ~7UL; + sp &= ~15UL; - return (void __user *)(sp - framesize); + return (void __user *) sp; } static inline int diff --git a/arch/sparc/kernel/signal_64.c b/arch/sparc/kernel/signal_64.c index 647afbda7ae1..9fa48c30037e 100644 --- a/arch/sparc/kernel/signal_64.c +++ b/arch/sparc/kernel/signal_64.c @@ -353,7 +353,7 @@ segv: /* Checks if the fp is valid */ static int invalid_frame_pointer(void __user *fp, int fplen) { - if (((unsigned long) fp) & 7) + if (((unsigned long) fp) & 15) return 1; return 0; } @@ -396,15 +396,17 @@ static inline void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs * sp = current->sas_ss_sp + current->sas_ss_size; } + sp -= framesize; + /* Always align the stack frame. This handles two cases. First, * sigaltstack need not be mindful of platform specific stack * alignment. Second, if we took this signal because the stack * is not aligned properly, we'd like to take the signal cleanly * and report that. */ - sp &= ~7UL; + sp &= ~15UL; - return (void __user *)(sp - framesize); + return (void __user *) sp; } static inline void diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h index 1994d3f58443..f2ad2163109d 100644 --- a/arch/x86/include/asm/elf.h +++ b/arch/x86/include/asm/elf.h @@ -170,10 +170,7 @@ static inline void elf_common_init(struct thread_struct *t, } #define ELF_PLAT_INIT(_r, load_addr) \ -do { \ - elf_common_init(¤t->thread, _r, 0); \ - clear_thread_flag(TIF_IA32); \ -} while (0) + elf_common_init(¤t->thread, _r, 0) #define COMPAT_ELF_PLAT_INIT(regs, load_addr) \ elf_common_init(¤t->thread, regs, __USER_DS) diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h index ecb544e65382..e04740f7a0bb 100644 --- a/arch/x86/include/asm/system.h +++ b/arch/x86/include/asm/system.h @@ -11,9 +11,9 @@ #include <linux/irqflags.h> /* entries in ARCH_DLINFO: */ -#ifdef CONFIG_IA32_EMULATION +#if defined(CONFIG_IA32_EMULATION) || !defined(CONFIG_X86_64) # define AT_VECTOR_SIZE_ARCH 2 -#else +#else /* else it's non-compat x86-64 */ # define AT_VECTOR_SIZE_ARCH 1 #endif diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 036d28adf59d..af1c5833ff23 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -1185,9 +1185,6 @@ static void __init acpi_process_madt(void) if (!error) { acpi_lapic = 1; -#ifdef CONFIG_X86_BIGSMP - generic_bigsmp_probe(); -#endif /* * Parse MADT IO-APIC entries */ @@ -1197,8 +1194,6 @@ static void __init acpi_process_madt(void) acpi_ioapic = 1; smp_found_config = 1; - if (apic->setup_apic_routing) - apic->setup_apic_routing(); } } if (error == -EINVAL) { @@ -1349,14 +1344,6 @@ static struct dmi_system_id __initdata acpi_dmi_table[] = { }, { .callback = force_acpi_ht, - .ident = "ASUS P2B-DS", - .matches = { - DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), - DMI_MATCH(DMI_BOARD_NAME, "P2B-DS"), - }, - }, - { - .callback = force_acpi_ht, .ident = "ASUS CUR-DLS", .matches = { DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 3987e4408f75..dfca210f6a10 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -1641,9 +1641,7 @@ int __init APIC_init_uniprocessor(void) #endif enable_IR_x2apic(); -#ifdef CONFIG_X86_64 default_setup_apic_routing(); -#endif verify_local_APIC(); connect_bsp_APIC(); @@ -1891,21 +1889,6 @@ void __cpuinit generic_processor_info(int apicid, int version) if (apicid > max_physical_apicid) max_physical_apicid = apicid; -#ifdef CONFIG_X86_32 - if (num_processors > 8) { - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - if (!APIC_XAPIC(version)) { - def_to_bigsmp = 0; - break; - } - /* If P4 and above fall through */ - case X86_VENDOR_AMD: - def_to_bigsmp = 1; - } - } -#endif - #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c index 1a6559f6768c..99d2fe016084 100644 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c @@ -52,7 +52,32 @@ static int __init print_ipi_mode(void) } late_initcall(print_ipi_mode); -void default_setup_apic_routing(void) +void __init default_setup_apic_routing(void) +{ + int version = apic_version[boot_cpu_physical_apicid]; + + if (num_possible_cpus() > 8) { + switch (boot_cpu_data.x86_vendor) { + case X86_VENDOR_INTEL: + if (!APIC_XAPIC(version)) { + def_to_bigsmp = 0; + break; + } + /* If P4 and above fall through */ + case X86_VENDOR_AMD: + def_to_bigsmp = 1; + } + } + +#ifdef CONFIG_X86_BIGSMP + generic_bigsmp_probe(); +#endif + + if (apic->setup_apic_routing) + apic->setup_apic_routing(); +} + +static void setup_apic_flat_routing(void) { #ifdef CONFIG_X86_IO_APIC printk(KERN_INFO @@ -103,7 +128,7 @@ struct apic apic_default = { .init_apic_ldr = default_init_apic_ldr, .ioapic_phys_id_map = default_ioapic_phys_id_map, - .setup_apic_routing = default_setup_apic_routing, + .setup_apic_routing = setup_apic_flat_routing, .multi_timer_check = NULL, .apicid_to_node = default_apicid_to_node, .cpu_to_logical_apicid = default_cpu_to_logical_apicid, diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c index 450fe2064a14..83e9be4778e2 100644 --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c @@ -67,7 +67,7 @@ void __init default_setup_apic_routing(void) } #endif - if (apic == &apic_flat && num_processors > 8) + if (apic == &apic_flat && num_possible_cpus() > 8) apic = &apic_physflat; printk(KERN_INFO "Setting APIC routing to %s\n", apic->name); diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c index f125e5c551c0..6e44519960c8 100644 --- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c +++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c @@ -1356,6 +1356,7 @@ static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol) kfree(data->powernow_table); kfree(data); + per_cpu(powernow_data, pol->cpu) = NULL; return 0; } @@ -1375,7 +1376,7 @@ static unsigned int powernowk8_get(unsigned int cpu) int err; if (!data) - return -EINVAL; + return 0; smp_call_function_single(cpu, query_values_on_cpu, &err, true); if (err) diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index 40b54ceb68b5..a2c1edd2d3ac 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -359,13 +359,6 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early) x86_init.mpparse.mpc_record(1); } -#ifdef CONFIG_X86_BIGSMP - generic_bigsmp_probe(); -#endif - - if (apic->setup_apic_routing) - apic->setup_apic_routing(); - if (!num_processors) printk(KERN_ERR "MPTABLE: no processors registered!\n"); return num_processors; diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 41a26a82470a..126f0b493d04 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -527,6 +527,7 @@ void set_personality_ia32(void) /* Make sure to be in 32bit mode */ set_thread_flag(TIF_IA32); + current->personality |= force_personality32; /* Prepare the first "return" to user space */ current_thread_info()->status |= TS_COMPAT; diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 678d0b8c26f3..b4e870cbdc60 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -1083,9 +1083,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) set_cpu_sibling_map(0); enable_IR_x2apic(); -#ifdef CONFIG_X86_64 default_setup_apic_routing(); -#endif if (smp_sanity_check(max_cpus) < 0) { printk(KERN_INFO "SMP disabled\n"); diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c index 296aba49472a..15578f180e59 100644 --- a/arch/x86/kvm/i8254.c +++ b/arch/x86/kvm/i8254.c @@ -467,6 +467,9 @@ static int pit_ioport_read(struct kvm_io_device *this, return -EOPNOTSUPP; addr &= KVM_PIT_CHANNEL_MASK; + if (addr == 3) + return 0; + s = &pit_state->channels[addr]; mutex_lock(&pit_state->lock); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 1ddcad452add..a1e1bc9d412d 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -670,7 +670,7 @@ static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) { static int version; struct pvclock_wall_clock wc; - struct timespec now, sys, boot; + struct timespec boot; if (!wall_clock) return; @@ -685,9 +685,7 @@ static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock) * wall clock specified here. guest system time equals host * system time for us, thus we must fill in host boot time here. */ - now = current_kernel_time(); - ktime_get_ts(&sys); - boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys)); + getboottime(&boot); wc.sec = boot.tv_sec; wc.nsec = boot.tv_nsec; @@ -762,6 +760,7 @@ static void kvm_write_guest_time(struct kvm_vcpu *v) local_irq_save(flags); kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp); ktime_get_ts(&ts); + monotonic_to_bootbased(&ts); local_irq_restore(flags); /* With all the info we got, fill in the values */ diff --git a/arch/x86/mm/gup.c b/arch/x86/mm/gup.c index 71da1bca13cb..738e6593799d 100644 --- a/arch/x86/mm/gup.c +++ b/arch/x86/mm/gup.c @@ -18,7 +18,7 @@ static inline pte_t gup_get_pte(pte_t *ptep) #else /* * With get_user_pages_fast, we walk down the pagetables without taking - * any locks. For this we would like to load the pointers atoimcally, + * any locks. For this we would like to load the pointers atomically, * but that is not possible (without expensive cmpxchg8b) on PAE. What * we do have is the guarantee that a pte will only either go from not * present to present, or present to not present or both -- it will not diff --git a/block/cfq-iosched.c b/block/cfq-iosched.c index 17b768d0d42f..023f4e69a337 100644 --- a/block/cfq-iosched.c +++ b/block/cfq-iosched.c @@ -42,16 +42,13 @@ static const int cfq_hist_divisor = 4; */ #define CFQ_MIN_TT (2) -/* - * Allow merged cfqqs to perform this amount of seeky I/O before - * deciding to break the queues up again. - */ -#define CFQQ_COOP_TOUT (HZ) - #define CFQ_SLICE_SCALE (5) #define CFQ_HW_QUEUE_MIN (5) #define CFQ_SERVICE_SHIFT 12 +#define CFQQ_SEEK_THR 8 * 1024 +#define CFQQ_SEEKY(cfqq) ((cfqq)->seek_mean > CFQQ_SEEK_THR) + #define RQ_CIC(rq) \ ((struct cfq_io_context *) (rq)->elevator_private) #define RQ_CFQQ(rq) (struct cfq_queue *) ((rq)->elevator_private2) @@ -137,7 +134,6 @@ struct cfq_queue { u64 seek_total; sector_t seek_mean; sector_t last_request_pos; - unsigned long seeky_start; pid_t pid; @@ -314,6 +310,7 @@ enum cfqq_state_flags { CFQ_CFQQ_FLAG_slice_new, /* no requests dispatched in slice */ CFQ_CFQQ_FLAG_sync, /* synchronous queue */ CFQ_CFQQ_FLAG_coop, /* cfqq is shared */ + CFQ_CFQQ_FLAG_split_coop, /* shared cfqq will be splitted */ CFQ_CFQQ_FLAG_deep, /* sync cfqq experienced large depth */ CFQ_CFQQ_FLAG_wait_busy, /* Waiting for next request */ }; @@ -342,6 +339,7 @@ CFQ_CFQQ_FNS(prio_changed); CFQ_CFQQ_FNS(slice_new); CFQ_CFQQ_FNS(sync); CFQ_CFQQ_FNS(coop); +CFQ_CFQQ_FNS(split_coop); CFQ_CFQQ_FNS(deep); CFQ_CFQQ_FNS(wait_busy); #undef CFQ_CFQQ_FNS @@ -1566,6 +1564,15 @@ __cfq_slice_expired(struct cfq_data *cfqd, struct cfq_queue *cfqq, cfq_clear_cfqq_wait_busy(cfqq); /* + * If this cfqq is shared between multiple processes, check to + * make sure that those processes are still issuing I/Os within + * the mean seek distance. If not, it may be time to break the + * queues apart again. + */ + if (cfq_cfqq_coop(cfqq) && CFQQ_SEEKY(cfqq)) + cfq_mark_cfqq_split_coop(cfqq); + + /* * store what was left of this slice, if the queue idled/timed out */ if (timed_out && !cfq_cfqq_slice_new(cfqq)) { @@ -1663,9 +1670,6 @@ static inline sector_t cfq_dist_from_last(struct cfq_data *cfqd, return cfqd->last_position - blk_rq_pos(rq); } -#define CFQQ_SEEK_THR 8 * 1024 -#define CFQQ_SEEKY(cfqq) ((cfqq)->seek_mean > CFQQ_SEEK_THR) - static inline int cfq_rq_close(struct cfq_data *cfqd, struct cfq_queue *cfqq, struct request *rq, bool for_preempt) { @@ -3000,19 +3004,6 @@ cfq_update_io_seektime(struct cfq_data *cfqd, struct cfq_queue *cfqq, total = cfqq->seek_total + (cfqq->seek_samples/2); do_div(total, cfqq->seek_samples); cfqq->seek_mean = (sector_t)total; - - /* - * If this cfqq is shared between multiple processes, check to - * make sure that those processes are still issuing I/Os within - * the mean seek distance. If not, it may be time to break the - * queues apart again. - */ - if (cfq_cfqq_coop(cfqq)) { - if (CFQQ_SEEKY(cfqq) && !cfqq->seeky_start) - cfqq->seeky_start = jiffies; - else if (!CFQQ_SEEKY(cfqq)) - cfqq->seeky_start = 0; - } } /* @@ -3453,14 +3444,6 @@ cfq_merge_cfqqs(struct cfq_data *cfqd, struct cfq_io_context *cic, return cic_to_cfqq(cic, 1); } -static int should_split_cfqq(struct cfq_queue *cfqq) -{ - if (cfqq->seeky_start && - time_after(jiffies, cfqq->seeky_start + CFQQ_COOP_TOUT)) - return 1; - return 0; -} - /* * Returns NULL if a new cfqq should be allocated, or the old cfqq if this * was the last process referring to said cfqq. @@ -3469,9 +3452,9 @@ static struct cfq_queue * split_cfqq(struct cfq_io_context *cic, struct cfq_queue *cfqq) { if (cfqq_process_refs(cfqq) == 1) { - cfqq->seeky_start = 0; cfqq->pid = current->pid; cfq_clear_cfqq_coop(cfqq); + cfq_clear_cfqq_split_coop(cfqq); return cfqq; } @@ -3510,7 +3493,7 @@ new_queue: /* * If the queue was seeky for too long, break it apart. */ - if (cfq_cfqq_coop(cfqq) && should_split_cfqq(cfqq)) { + if (cfq_cfqq_coop(cfqq) && cfq_cfqq_split_coop(cfqq)) { cfq_log_cfqq(cfqd, cfqq, "breaking apart cfqq"); cfqq = split_cfqq(cic, cfqq); if (!cfqq) diff --git a/drivers/acpi/dock.c b/drivers/acpi/dock.c index bbc2c1315c47..b2586f57e1f5 100644 --- a/drivers/acpi/dock.c +++ b/drivers/acpi/dock.c @@ -935,6 +935,7 @@ static int dock_add(acpi_handle handle) struct platform_device *dd; id = dock_station_count; + memset(&ds, 0, sizeof(ds)); dd = platform_device_register_data(NULL, "dock", id, &ds, sizeof(ds)); if (IS_ERR(dd)) return PTR_ERR(dd); diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 7c0441f63b39..e88e8ae04fdb 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -110,6 +110,14 @@ static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, (void *)2}, + { set_max_cstate, "Pavilion zv5000", { + DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), + DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")}, + (void *)1}, + { set_max_cstate, "Asus L8400B", { + DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."), + DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")}, + (void *)1}, {}, }; diff --git a/drivers/acpi/processor_pdc.c b/drivers/acpi/processor_pdc.c index 7247819dbd80..e306ba9aa34e 100644 --- a/drivers/acpi/processor_pdc.c +++ b/drivers/acpi/processor_pdc.c @@ -125,6 +125,8 @@ acpi_processor_eval_pdc(acpi_handle handle, struct acpi_object_list *pdc_in) return status; } +static int early_pdc_done; + void acpi_processor_set_pdc(acpi_handle handle) { struct acpi_object_list *obj_list; @@ -132,6 +134,9 @@ void acpi_processor_set_pdc(acpi_handle handle) if (arch_has_acpi_pdc() == false) return; + if (early_pdc_done) + return; + obj_list = acpi_processor_alloc_pdc(); if (!obj_list) return; @@ -151,6 +156,13 @@ static int set_early_pdc_optin(const struct dmi_system_id *id) return 0; } +static int param_early_pdc_optin(char *s) +{ + early_pdc_optin = 1; + return 1; +} +__setup("acpi_early_pdc_eval", param_early_pdc_optin); + static struct dmi_system_id __cpuinitdata early_pdc_optin_table[] = { { set_early_pdc_optin, "HP Envy", { @@ -192,4 +204,6 @@ void __init acpi_early_processor_set_pdc(void) acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX, early_init_pdc, NULL, NULL, NULL); + + early_pdc_done = 1; } diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index ff9f6226085d..3e009674f333 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -1336,9 +1336,25 @@ static int acpi_bus_scan(acpi_handle handle, struct acpi_bus_ops *ops, if (child) *child = device; - return 0; + + if (device) + return 0; + else + return -ENODEV; } +/* + * acpi_bus_add and acpi_bus_start + * + * scan a given ACPI tree and (probably recently hot-plugged) + * create and add or starts found devices. + * + * If no devices were found -ENODEV is returned which does not + * mean that this is a real error, there just have been no suitable + * ACPI objects in the table trunk from which the kernel could create + * a device and add/start an appropriate driver. + */ + int acpi_bus_add(struct acpi_device **child, struct acpi_device *parent, acpi_handle handle, int type) @@ -1348,8 +1364,7 @@ acpi_bus_add(struct acpi_device **child, memset(&ops, 0, sizeof(ops)); ops.acpi_op_add = 1; - acpi_bus_scan(handle, &ops, child); - return 0; + return acpi_bus_scan(handle, &ops, child); } EXPORT_SYMBOL(acpi_bus_add); @@ -1357,11 +1372,13 @@ int acpi_bus_start(struct acpi_device *device) { struct acpi_bus_ops ops; + if (!device) + return -EINVAL; + memset(&ops, 0, sizeof(ops)); ops.acpi_op_start = 1; - acpi_bus_scan(device->handle, &ops, NULL); - return 0; + return acpi_bus_scan(device->handle, &ops, NULL); } EXPORT_SYMBOL(acpi_bus_start); diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index f336bca7c450..8a0ed2800e63 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -213,7 +213,7 @@ acpi_table_parse_entries(char *id, unsigned long table_end; acpi_size tbl_size; - if (acpi_disabled) + if (acpi_disabled && !acpi_ht) return -ENODEV; if (!handler) @@ -280,7 +280,7 @@ int __init acpi_table_parse(char *id, acpi_table_handler handler) struct acpi_table_header *table = NULL; acpi_size tbl_size; - if (acpi_disabled) + if (acpi_disabled && !acpi_ht) return -ENODEV; if (!handler) diff --git a/drivers/base/class.c b/drivers/base/class.c index 161746deab4b..6e2c3b064f53 100644 --- a/drivers/base/class.c +++ b/drivers/base/class.c @@ -59,6 +59,8 @@ static void class_release(struct kobject *kobj) else pr_debug("class '%s' does not have a release() function, " "be careful\n", class->name); + + kfree(cp); } static struct sysfs_ops class_sysfs_ops = { diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index 873e594860d3..9291614ac6b7 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c @@ -337,6 +337,9 @@ static int cciss_seq_show(struct seq_file *seq, void *v) if (*pos > h->highest_lun) return 0; + if (drv == NULL) /* it's possible for h->drv[] to have holes. */ + return 0; + if (drv->heads == 0) return 0; diff --git a/drivers/bluetooth/btmrvl_sdio.c b/drivers/bluetooth/btmrvl_sdio.c index f36defa37764..57d965b7f521 100644 --- a/drivers/bluetooth/btmrvl_sdio.c +++ b/drivers/bluetooth/btmrvl_sdio.c @@ -808,6 +808,7 @@ static int btmrvl_sdio_host_to_card(struct btmrvl_private *priv, exit: sdio_release_host(card->func); + kfree(tmpbuf); return ret; } diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c index 34cf04e21795..fd50ead59c79 100644 --- a/drivers/char/agp/amd64-agp.c +++ b/drivers/char/agp/amd64-agp.c @@ -767,16 +767,19 @@ int __init agp_amd64_init(void) static int __init agp_amd64_mod_init(void) { +#ifndef MODULE if (gart_iommu_aperture) return agp_bridges_found ? 0 : -ENODEV; - +#endif return agp_amd64_init(); } static void __exit agp_amd64_cleanup(void) { +#ifndef MODULE if (gart_iommu_aperture) return; +#endif if (aperture_resource) release_resource(aperture_resource); pci_unregister_driver(&agp_amd64_pci_driver); diff --git a/drivers/char/tpm/tpm_infineon.c b/drivers/char/tpm/tpm_infineon.c index ecba4942fc8e..f58440791e65 100644 --- a/drivers/char/tpm/tpm_infineon.c +++ b/drivers/char/tpm/tpm_infineon.c @@ -39,12 +39,12 @@ struct tpm_inf_dev { int iotype; - void __iomem *mem_base; /* MMIO ioremap'd addr */ - unsigned long map_base; /* phys MMIO base */ - unsigned long map_size; /* MMIO region size */ - unsigned int index_off; /* index register offset */ + void __iomem *mem_base; /* MMIO ioremap'd addr */ + unsigned long map_base; /* phys MMIO base */ + unsigned long map_size; /* MMIO region size */ + unsigned int index_off; /* index register offset */ - unsigned int data_regs; /* Data registers */ + unsigned int data_regs; /* Data registers */ unsigned int data_size; unsigned int config_port; /* IO Port config index reg */ @@ -406,14 +406,14 @@ static const struct tpm_vendor_specific tpm_inf = { .miscdev = {.fops = &inf_ops,}, }; -static const struct pnp_device_id tpm_pnp_tbl[] = { +static const struct pnp_device_id tpm_inf_pnp_tbl[] = { /* Infineon TPMs */ {"IFX0101", 0}, {"IFX0102", 0}, {"", 0} }; -MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl); +MODULE_DEVICE_TABLE(pnp, tpm_inf_pnp_tbl); static int __devinit tpm_inf_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id) @@ -430,7 +430,7 @@ static int __devinit tpm_inf_pnp_probe(struct pnp_dev *dev, if (pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) && !(pnp_port_flags(dev, 0) & IORESOURCE_DISABLED)) { - tpm_dev.iotype = TPM_INF_IO_PORT; + tpm_dev.iotype = TPM_INF_IO_PORT; tpm_dev.config_port = pnp_port_start(dev, 0); tpm_dev.config_size = pnp_port_len(dev, 0); @@ -459,9 +459,9 @@ static int __devinit tpm_inf_pnp_probe(struct pnp_dev *dev, goto err_last; } } else if (pnp_mem_valid(dev, 0) && - !(pnp_mem_flags(dev, 0) & IORESOURCE_DISABLED)) { + !(pnp_mem_flags(dev, 0) & IORESOURCE_DISABLED)) { - tpm_dev.iotype = TPM_INF_IO_MEM; + tpm_dev.iotype = TPM_INF_IO_MEM; tpm_dev.map_base = pnp_mem_start(dev, 0); tpm_dev.map_size = pnp_mem_len(dev, 0); @@ -563,11 +563,11 @@ static int __devinit tpm_inf_pnp_probe(struct pnp_dev *dev, "product id 0x%02x%02x" "%s\n", tpm_dev.iotype == TPM_INF_IO_PORT ? - tpm_dev.config_port : - tpm_dev.map_base + tpm_dev.index_off, + tpm_dev.config_port : + tpm_dev.map_base + tpm_dev.index_off, tpm_dev.iotype == TPM_INF_IO_PORT ? - tpm_dev.data_regs : - tpm_dev.map_base + tpm_dev.data_regs, + tpm_dev.data_regs : + tpm_dev.map_base + tpm_dev.data_regs, version[0], version[1], vendorid[0], vendorid[1], productid[0], productid[1], chipname); @@ -607,20 +607,55 @@ static __devexit void tpm_inf_pnp_remove(struct pnp_dev *dev) iounmap(tpm_dev.mem_base); release_mem_region(tpm_dev.map_base, tpm_dev.map_size); } + tpm_dev_vendor_release(chip); tpm_remove_hardware(chip->dev); } } +static int tpm_inf_pnp_suspend(struct pnp_dev *dev, pm_message_t pm_state) +{ + struct tpm_chip *chip = pnp_get_drvdata(dev); + int rc; + if (chip) { + u8 savestate[] = { + 0, 193, /* TPM_TAG_RQU_COMMAND */ + 0, 0, 0, 10, /* blob length (in bytes) */ + 0, 0, 0, 152 /* TPM_ORD_SaveState */ + }; + dev_info(&dev->dev, "saving TPM state\n"); + rc = tpm_inf_send(chip, savestate, sizeof(savestate)); + if (rc < 0) { + dev_err(&dev->dev, "error while saving TPM state\n"); + return rc; + } + } + return 0; +} + +static int tpm_inf_pnp_resume(struct pnp_dev *dev) +{ + /* Re-configure TPM after suspending */ + tpm_config_out(ENABLE_REGISTER_PAIR, TPM_INF_ADDR); + tpm_config_out(IOLIMH, TPM_INF_ADDR); + tpm_config_out((tpm_dev.data_regs >> 8) & 0xff, TPM_INF_DATA); + tpm_config_out(IOLIML, TPM_INF_ADDR); + tpm_config_out((tpm_dev.data_regs & 0xff), TPM_INF_DATA); + /* activate register */ + tpm_config_out(TPM_DAR, TPM_INF_ADDR); + tpm_config_out(0x01, TPM_INF_DATA); + tpm_config_out(DISABLE_REGISTER_PAIR, TPM_INF_ADDR); + /* disable RESET, LP and IRQC */ + tpm_data_out(RESET_LP_IRQC_DISABLE, CMD); + return tpm_pm_resume(&dev->dev); +} + static struct pnp_driver tpm_inf_pnp_driver = { .name = "tpm_inf_pnp", - .driver = { - .owner = THIS_MODULE, - .suspend = tpm_pm_suspend, - .resume = tpm_pm_resume, - }, - .id_table = tpm_pnp_tbl, + .id_table = tpm_inf_pnp_tbl, .probe = tpm_inf_pnp_probe, - .remove = __devexit_p(tpm_inf_pnp_remove), + .suspend = tpm_inf_pnp_suspend, + .resume = tpm_inf_pnp_resume, + .remove = __devexit_p(tpm_inf_pnp_remove) }; static int __init init_inf(void) @@ -638,5 +673,5 @@ module_exit(cleanup_inf); MODULE_AUTHOR("Marcel Selhorst <[email protected]>"); MODULE_DESCRIPTION("Driver for Infineon TPM SLD 9630 TT 1.1 / SLB 9635 TT 1.2"); -MODULE_VERSION("1.9"); +MODULE_VERSION("1.9.2"); MODULE_LICENSE("GPL"); diff --git a/drivers/cpufreq/cpufreq_ondemand.c b/drivers/cpufreq/cpufreq_ondemand.c index 4b34ade2332b..bd444dc93cf2 100644 --- a/drivers/cpufreq/cpufreq_ondemand.c +++ b/drivers/cpufreq/cpufreq_ondemand.c @@ -554,6 +554,9 @@ static void dbs_check_cpu(struct cpu_dbs_info_s *this_dbs_info) (dbs_tuners_ins.up_threshold - dbs_tuners_ins.down_differential); + if (freq_next < policy->min) + freq_next = policy->min; + if (!dbs_tuners_ins.powersave_bias) { __cpufreq_driver_target(policy, freq_next, CPUFREQ_RELATION_L); diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c index b5f2ee0f8e2c..64a937262a40 100644 --- a/drivers/dma/coh901318.c +++ b/drivers/dma/coh901318.c @@ -613,8 +613,6 @@ static void dma_tasklet(unsigned long data) cohd_fin->pending_irqs--; cohc->completed = cohd_fin->desc.cookie; - BUG_ON(cohc->nbr_active_done && cohd_fin == NULL); - if (cohc->nbr_active_done == 0) return; diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 6f51a0a7a8bb..e7a3230fb7d5 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -826,6 +826,7 @@ void dma_async_device_unregister(struct dma_device *device) chan->dev->chan = NULL; mutex_unlock(&dma_list_mutex); device_unregister(&chan->dev->device); + free_percpu(chan->local); } } EXPORT_SYMBOL(dma_async_device_unregister); diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index 8b905161fbf4..948d563941c9 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c @@ -467,7 +467,7 @@ err_srcs: if (iterations > 0) while (!kthread_should_stop()) { - DECLARE_WAIT_QUEUE_HEAD(wait_dmatest_exit); + DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wait_dmatest_exit); interruptible_sleep_on(&wait_dmatest_exit); } diff --git a/drivers/dma/ioat/dma_v2.c b/drivers/dma/ioat/dma_v2.c index 5f7a500e18d0..5cc37afe2bc1 100644 --- a/drivers/dma/ioat/dma_v2.c +++ b/drivers/dma/ioat/dma_v2.c @@ -249,7 +249,7 @@ int ioat2_quiesce(struct ioat_chan_common *chan, unsigned long tmo) if (is_ioat_active(status) || is_ioat_idle(status)) ioat_suspend(chan); while (is_ioat_active(status) || is_ioat_idle(status)) { - if (end && time_after(jiffies, end)) { + if (tmo && time_after(jiffies, end)) { err = -ETIMEDOUT; break; } diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c index 9a5bc1a7389e..e80bae1673fa 100644 --- a/drivers/dma/ipu/ipu_idmac.c +++ b/drivers/dma/ipu/ipu_idmac.c @@ -761,12 +761,10 @@ static void ipu_select_buffer(enum ipu_channel channel, int buffer_n) * @buffer_n: buffer number to update. * 0 or 1 are the only valid values. * @phyaddr: buffer physical address. - * @return: Returns 0 on success or negative error code on failure. This - * function will fail if the buffer is set to ready. */ /* Called under spin_lock(_irqsave)(&ichan->lock) */ -static int ipu_update_channel_buffer(struct idmac_channel *ichan, - int buffer_n, dma_addr_t phyaddr) +static void ipu_update_channel_buffer(struct idmac_channel *ichan, + int buffer_n, dma_addr_t phyaddr) { enum ipu_channel channel = ichan->dma_chan.chan_id; uint32_t reg; @@ -806,8 +804,6 @@ static int ipu_update_channel_buffer(struct idmac_channel *ichan, } spin_unlock_irqrestore(&ipu_data.lock, flags); - - return 0; } /* Called under spin_lock_irqsave(&ichan->lock) */ @@ -816,7 +812,6 @@ static int ipu_submit_buffer(struct idmac_channel *ichan, { unsigned int chan_id = ichan->dma_chan.chan_id; struct device *dev = &ichan->dma_chan.dev->device; - int ret; if (async_tx_test_ack(&desc->txd)) return -EINTR; @@ -827,14 +822,7 @@ static int ipu_submit_buffer(struct idmac_channel *ichan, * could make it conditional on status >= IPU_CHANNEL_ENABLED, but * doing it again shouldn't hurt either. */ - ret = ipu_update_channel_buffer(ichan, buf_idx, - sg_dma_address(sg)); - - if (ret < 0) { - dev_err(dev, "Updating sg %p on channel 0x%x buffer %d failed!\n", - sg, chan_id, buf_idx); - return ret; - } + ipu_update_channel_buffer(ichan, buf_idx, sg_dma_address(sg)); ipu_select_buffer(chan_id, buf_idx); dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n", @@ -1379,10 +1367,11 @@ static irqreturn_t idmac_interrupt(int irq, void *dev_id) if (likely(sgnew) && ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) { - callback = desc->txd.callback; - callback_param = desc->txd.callback_param; + callback = descnew->txd.callback; + callback_param = descnew->txd.callback_param; spin_unlock(&ichan->lock); - callback(callback_param); + if (callback) + callback(callback_param); spin_lock(&ichan->lock); } diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 000dc67b85b7..3391e6739d06 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -2658,10 +2658,11 @@ static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt) * the memory system completely. A command line option allows to force-enable * hardware ECC later in amd64_enable_ecc_error_reporting(). */ -static const char *ecc_warning = - "WARNING: ECC is disabled by BIOS. Module will NOT be loaded.\n" - " Either Enable ECC in the BIOS, or set 'ecc_enable_override'.\n" - " Also, use of the override can cause unknown side effects.\n"; +static const char *ecc_msg = + "ECC disabled in the BIOS or no ECC capability, module will not load.\n" + " Either enable ECC checking or force module loading by setting " + "'ecc_enable_override'.\n" + " (Note that use of the override may cause unknown side effects.)\n"; static int amd64_check_ecc_enabled(struct amd64_pvt *pvt) { @@ -2673,7 +2674,7 @@ static int amd64_check_ecc_enabled(struct amd64_pvt *pvt) ecc_enabled = !!(value & K8_NBCFG_ECC_ENABLE); if (!ecc_enabled) - amd64_printk(KERN_WARNING, "This node reports that Memory ECC " + amd64_printk(KERN_NOTICE, "This node reports that Memory ECC " "is currently disabled, set F3x%x[22] (%s).\n", K8_NBCFG, pci_name(pvt->misc_f3_ctl)); else @@ -2681,13 +2682,13 @@ static int amd64_check_ecc_enabled(struct amd64_pvt *pvt) nb_mce_en = amd64_nb_mce_bank_enabled_on_node(pvt->mc_node_id); if (!nb_mce_en) - amd64_printk(KERN_WARNING, "NB MCE bank disabled, set MSR " + amd64_printk(KERN_NOTICE, "NB MCE bank disabled, set MSR " "0x%08x[4] on node %d to enable.\n", MSR_IA32_MCG_CTL, pvt->mc_node_id); if (!ecc_enabled || !nb_mce_en) { if (!ecc_enable_override) { - amd64_printk(KERN_WARNING, "%s", ecc_warning); + amd64_printk(KERN_NOTICE, "%s", ecc_msg); return -ENODEV; } ecc_enable_override = 0; diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c index cf27402af97b..ecd5928d7110 100644 --- a/drivers/edac/mpc85xx_edac.c +++ b/drivers/edac/mpc85xx_edac.c @@ -804,8 +804,8 @@ static void __devinit mpc85xx_init_csrows(struct mem_ctl_info *mci) end <<= (24 - PAGE_SHIFT); end |= (1 << (24 - PAGE_SHIFT)) - 1; - csrow->first_page = start >> PAGE_SHIFT; - csrow->last_page = end >> PAGE_SHIFT; + csrow->first_page = start; + csrow->last_page = end; csrow->nr_pages = end + 1 - start; csrow->grain = 8; csrow->mtype = mtype; @@ -892,10 +892,6 @@ static int __devinit mpc85xx_mc_err_probe(struct of_device *op, mpc85xx_init_csrows(mci); -#ifdef CONFIG_EDAC_DEBUG - edac_mc_register_mcidev_debug((struct attribute **)debug_attr); -#endif - /* store the original error disable bits */ orig_ddr_err_disable = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); diff --git a/drivers/firewire/net.c b/drivers/firewire/net.c index cbaf420c36c5..2d3dc7ded0a9 100644 --- a/drivers/firewire/net.c +++ b/drivers/firewire/net.c @@ -893,20 +893,31 @@ static void fwnet_receive_broadcast(struct fw_iso_context *context, static struct kmem_cache *fwnet_packet_task_cache; +static void fwnet_free_ptask(struct fwnet_packet_task *ptask) +{ + dev_kfree_skb_any(ptask->skb); + kmem_cache_free(fwnet_packet_task_cache, ptask); +} + static int fwnet_send_packet(struct fwnet_packet_task *ptask); static void fwnet_transmit_packet_done(struct fwnet_packet_task *ptask) { - struct fwnet_device *dev; + struct fwnet_device *dev = ptask->dev; unsigned long flags; - - dev = ptask->dev; + bool free; spin_lock_irqsave(&dev->lock, flags); - list_del(&ptask->pt_link); - spin_unlock_irqrestore(&dev->lock, flags); - ptask->outstanding_pkts--; /* FIXME access inside lock */ + ptask->outstanding_pkts--; + + /* Check whether we or the networking TX soft-IRQ is last user. */ + free = (ptask->outstanding_pkts == 0 && !list_empty(&ptask->pt_link)); + + if (ptask->outstanding_pkts == 0) + list_del(&ptask->pt_link); + + spin_unlock_irqrestore(&dev->lock, flags); if (ptask->outstanding_pkts > 0) { u16 dg_size; @@ -951,10 +962,10 @@ static void fwnet_transmit_packet_done(struct fwnet_packet_task *ptask) ptask->max_payload = skb->len + RFC2374_FRAG_HDR_SIZE; } fwnet_send_packet(ptask); - } else { - dev_kfree_skb_any(ptask->skb); - kmem_cache_free(fwnet_packet_task_cache, ptask); } + + if (free) + fwnet_free_ptask(ptask); } static void fwnet_write_complete(struct fw_card *card, int rcode, @@ -977,6 +988,7 @@ static int fwnet_send_packet(struct fwnet_packet_task *ptask) unsigned tx_len; struct rfc2734_header *bufhdr; unsigned long flags; + bool free; dev = ptask->dev; tx_len = ptask->max_payload; @@ -1022,12 +1034,16 @@ static int fwnet_send_packet(struct fwnet_packet_task *ptask) generation, SCODE_100, 0ULL, ptask->skb->data, tx_len + 8, fwnet_write_complete, ptask); - /* FIXME race? */ spin_lock_irqsave(&dev->lock, flags); - list_add_tail(&ptask->pt_link, &dev->broadcasted_list); + + /* If the AT tasklet already ran, we may be last user. */ + free = (ptask->outstanding_pkts == 0 && list_empty(&ptask->pt_link)); + if (!free) + list_add_tail(&ptask->pt_link, &dev->broadcasted_list); + spin_unlock_irqrestore(&dev->lock, flags); - return 0; + goto out; } fw_send_request(dev->card, &ptask->transaction, @@ -1035,12 +1051,19 @@ static int fwnet_send_packet(struct fwnet_packet_task *ptask) ptask->generation, ptask->speed, ptask->fifo_addr, ptask->skb->data, tx_len, fwnet_write_complete, ptask); - /* FIXME race? */ spin_lock_irqsave(&dev->lock, flags); - list_add_tail(&ptask->pt_link, &dev->sent_list); + + /* If the AT tasklet already ran, we may be last user. */ + free = (ptask->outstanding_pkts == 0 && list_empty(&ptask->pt_link)); + if (!free) + list_add_tail(&ptask->pt_link, &dev->sent_list); + spin_unlock_irqrestore(&dev->lock, flags); dev->netdev->trans_start = jiffies; + out: + if (free) + fwnet_free_ptask(ptask); return 0; } @@ -1298,6 +1321,8 @@ static netdev_tx_t fwnet_tx(struct sk_buff *skb, struct net_device *net) spin_unlock_irqrestore(&dev->lock, flags); ptask->max_payload = max_payload; + INIT_LIST_HEAD(&ptask->pt_link); + fwnet_send_packet(ptask); return NETDEV_TX_OK; diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c index 2345d4103fe6..43ebf337b131 100644 --- a/drivers/firewire/ohci.c +++ b/drivers/firewire/ohci.c @@ -2101,11 +2101,6 @@ static int ohci_queue_iso_transmit(struct fw_iso_context *base, u32 payload_index, payload_end_index, next_page_index; int page, end_page, i, length, offset; - /* - * FIXME: Cycle lost behavior should be configurable: lose - * packet, retransmit or terminate.. - */ - p = packet; payload_index = payload; @@ -2135,6 +2130,14 @@ static int ohci_queue_iso_transmit(struct fw_iso_context *base, if (!p->skip) { d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE); d[0].req_count = cpu_to_le16(8); + /* + * Link the skip address to this descriptor itself. This causes + * a context to skip a cycle whenever lost cycles or FIFO + * overruns occur, without dropping the data. The application + * should then decide whether this is an error condition or not. + * FIXME: Make the context's cycle-lost behaviour configurable? + */ + d[0].branch_address = cpu_to_le32(d_bus | z); header = (__le32 *) &d[1]; header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) | diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index f665b05592f3..ab6c97330412 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -598,6 +598,50 @@ struct drm_display_mode *drm_mode_std(struct drm_device *dev, return mode; } +/* + * EDID is delightfully ambiguous about how interlaced modes are to be + * encoded. Our internal representation is of frame height, but some + * HDTV detailed timings are encoded as field height. + * + * The format list here is from CEA, in frame size. Technically we + * should be checking refresh rate too. Whatever. + */ +static void +drm_mode_do_interlace_quirk(struct drm_display_mode *mode, + struct detailed_pixel_timing *pt) +{ + int i; + static const struct { + int w, h; + } cea_interlaced[] = { + { 1920, 1080 }, + { 720, 480 }, + { 1440, 480 }, + { 2880, 480 }, + { 720, 576 }, + { 1440, 576 }, + { 2880, 576 }, + }; + static const int n_sizes = + sizeof(cea_interlaced)/sizeof(cea_interlaced[0]); + + if (!(pt->misc & DRM_EDID_PT_INTERLACED)) + return; + + for (i = 0; i < n_sizes; i++) { + if ((mode->hdisplay == cea_interlaced[i].w) && + (mode->vdisplay == cea_interlaced[i].h / 2)) { + mode->vdisplay *= 2; + mode->vsync_start *= 2; + mode->vsync_end *= 2; + mode->vtotal *= 2; + mode->vtotal |= 1; + } + } + + mode->flags |= DRM_MODE_FLAG_INTERLACE; +} + /** * drm_mode_detailed - create a new mode from an EDID detailed timing section * @dev: DRM device (needed to create new mode) @@ -680,8 +724,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, drm_mode_set_name(mode); - if (pt->misc & DRM_EDID_PT_INTERLACED) - mode->flags |= DRM_MODE_FLAG_INTERLACE; + drm_mode_do_interlace_quirk(mode, pt); if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c index cdec32977129..2ac074c8f5d2 100644 --- a/drivers/gpu/drm/drm_mm.c +++ b/drivers/gpu/drm/drm_mm.c @@ -405,7 +405,8 @@ struct drm_mm_node *drm_mm_search_free_in_range(const struct drm_mm *mm, wasted += alignment - tmp; } - if (entry->size >= size + wasted) { + if (entry->size >= size + wasted && + (entry->start + wasted + size) <= end) { if (!best_match) return entry; if (entry->size < best_size) { diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index e660ac07f3b2..2307f98349f7 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -735,8 +735,10 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data, if (cmdbuf->num_cliprects) { cliprects = kcalloc(cmdbuf->num_cliprects, sizeof(struct drm_clip_rect), GFP_KERNEL); - if (cliprects == NULL) + if (cliprects == NULL) { + ret = -ENOMEM; goto fail_batch_free; + } ret = copy_from_user(cliprects, cmdbuf->cliprects, cmdbuf->num_cliprects * diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index ecac882e1d54..79beffcf5936 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -174,78 +174,100 @@ const static struct pci_device_id pciidlist[] = { MODULE_DEVICE_TABLE(pci, pciidlist); #endif -static int i915_suspend(struct drm_device *dev, pm_message_t state) +static int i915_drm_freeze(struct drm_device *dev) { - struct drm_i915_private *dev_priv = dev->dev_private; - - if (!dev || !dev_priv) { - DRM_ERROR("dev: %p, dev_priv: %p\n", dev, dev_priv); - DRM_ERROR("DRM not initialized, aborting suspend.\n"); - return -ENODEV; - } - - if (state.event == PM_EVENT_PRETHAW) - return 0; - pci_save_state(dev->pdev); /* If KMS is active, we do the leavevt stuff here */ if (drm_core_check_feature(dev, DRIVER_MODESET)) { - if (i915_gem_idle(dev)) + int error = i915_gem_idle(dev); + if (error) { dev_err(&dev->pdev->dev, - "GEM idle failed, resume may fail\n"); + "GEM idle failed, resume might fail\n"); + return error; + } drm_irq_uninstall(dev); } i915_save_state(dev); + return 0; +} + +static void i915_drm_suspend(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + intel_opregion_free(dev, 1); + /* Modeset on resume, not lid events */ + dev_priv->modeset_on_lid = 0; +} + +static int i915_suspend(struct drm_device *dev, pm_message_t state) +{ + int error; + + if (!dev || !dev->dev_private) { + DRM_ERROR("dev: %p\n", dev); + DRM_ERROR("DRM not initialized, aborting suspend.\n"); + return -ENODEV; + } + + if (state.event == PM_EVENT_PRETHAW) + return 0; + + error = i915_drm_freeze(dev); + if (error) + return error; + + i915_drm_suspend(dev); + if (state.event == PM_EVENT_SUSPEND) { /* Shut down the device */ pci_disable_device(dev->pdev); pci_set_power_state(dev->pdev, PCI_D3hot); } - /* Modeset on resume, not lid events */ - dev_priv->modeset_on_lid = 0; - return 0; } -static int i915_resume(struct drm_device *dev) +static int i915_drm_thaw(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; - int ret = 0; - - if (pci_enable_device(dev->pdev)) - return -1; - pci_set_master(dev->pdev); - - i915_restore_state(dev); - - intel_opregion_init(dev, 1); + int error = 0; /* KMS EnterVT equivalent */ if (drm_core_check_feature(dev, DRIVER_MODESET)) { mutex_lock(&dev->struct_mutex); dev_priv->mm.suspended = 0; - ret = i915_gem_init_ringbuffer(dev); - if (ret != 0) - ret = -1; + error = i915_gem_init_ringbuffer(dev); mutex_unlock(&dev->struct_mutex); drm_irq_install(dev); - } - if (drm_core_check_feature(dev, DRIVER_MODESET)) { + /* Resume the modeset for every activated CRTC */ drm_helper_resume_force_mode(dev); } dev_priv->modeset_on_lid = 0; - return ret; + return error; +} + +static int i915_resume(struct drm_device *dev) +{ + if (pci_enable_device(dev->pdev)) + return -EIO; + + pci_set_master(dev->pdev); + + i915_restore_state(dev); + + intel_opregion_init(dev, 1); + + return i915_drm_thaw(dev); } /** @@ -386,57 +408,69 @@ i915_pci_remove(struct pci_dev *pdev) drm_put_dev(dev); } -static int -i915_pci_suspend(struct pci_dev *pdev, pm_message_t state) +static int i915_pm_suspend(struct device *dev) { - struct drm_device *dev = pci_get_drvdata(pdev); + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + int error; - return i915_suspend(dev, state); -} + if (!drm_dev || !drm_dev->dev_private) { + dev_err(dev, "DRM not initialized, aborting suspend.\n"); + return -ENODEV; + } -static int -i915_pci_resume(struct pci_dev *pdev) -{ - struct drm_device *dev = pci_get_drvdata(pdev); + error = i915_drm_freeze(drm_dev); + if (error) + return error; - return i915_resume(dev); -} + i915_drm_suspend(drm_dev); -static int -i915_pm_suspend(struct device *dev) -{ - return i915_pci_suspend(to_pci_dev(dev), PMSG_SUSPEND); -} + pci_disable_device(pdev); + pci_set_power_state(pdev, PCI_D3hot); -static int -i915_pm_resume(struct device *dev) -{ - return i915_pci_resume(to_pci_dev(dev)); + return 0; } -static int -i915_pm_freeze(struct device *dev) +static int i915_pm_resume(struct device *dev) { - return i915_pci_suspend(to_pci_dev(dev), PMSG_FREEZE); + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + + return i915_resume(drm_dev); } -static int -i915_pm_thaw(struct device *dev) +static int i915_pm_freeze(struct device *dev) { - /* thaw during hibernate, do nothing! */ - return 0; + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + + if (!drm_dev || !drm_dev->dev_private) { + dev_err(dev, "DRM not initialized, aborting suspend.\n"); + return -ENODEV; + } + + return i915_drm_freeze(drm_dev); } -static int -i915_pm_poweroff(struct device *dev) +static int i915_pm_thaw(struct device *dev) { - return i915_pci_suspend(to_pci_dev(dev), PMSG_HIBERNATE); + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + + return i915_drm_thaw(drm_dev); } -static int -i915_pm_restore(struct device *dev) +static int i915_pm_poweroff(struct device *dev) { - return i915_pci_resume(to_pci_dev(dev)); + struct pci_dev *pdev = to_pci_dev(dev); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + int error; + + error = i915_drm_freeze(drm_dev); + if (!error) + i915_drm_suspend(drm_dev); + + return error; } const struct dev_pm_ops i915_pm_ops = { @@ -445,7 +479,7 @@ const struct dev_pm_ops i915_pm_ops = { .freeze = i915_pm_freeze, .thaw = i915_pm_thaw, .poweroff = i915_pm_poweroff, - .restore = i915_pm_restore, + .restore = i915_pm_resume, }; static struct vm_operations_struct i915_gem_vm_ops = { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index aaf934d96f21..b99b6a841d95 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -493,6 +493,15 @@ typedef struct drm_i915_private { struct list_head flushing_list; /** + * List of objects currently pending a GPU write flush. + * + * All elements on this list will belong to either the + * active_list or flushing_list, last_rendering_seqno can + * be used to differentiate between the two elements. + */ + struct list_head gpu_write_list; + + /** * LRU list of objects which are not in the ringbuffer and * are ready to unbind, but are still in the GTT. * @@ -592,6 +601,8 @@ struct drm_i915_gem_object { /** This object's place on the active/flushing/inactive lists */ struct list_head list; + /** This object's place on GPU write list */ + struct list_head gpu_write_list; /** This object's place on the fenced object LRU */ struct list_head fence_list; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index b4c8c0230689..ec8a0d7ffa39 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -1552,6 +1552,8 @@ i915_gem_object_move_to_inactive(struct drm_gem_object *obj) else list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); + BUG_ON(!list_empty(&obj_priv->gpu_write_list)); + obj_priv->last_rendering_seqno = 0; if (obj_priv->active) { obj_priv->active = 0; @@ -1622,7 +1624,8 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv, struct drm_i915_gem_object *obj_priv, *next; list_for_each_entry_safe(obj_priv, next, - &dev_priv->mm.flushing_list, list) { + &dev_priv->mm.gpu_write_list, + gpu_write_list) { struct drm_gem_object *obj = obj_priv->obj; if ((obj->write_domain & flush_domains) == @@ -1630,6 +1633,7 @@ i915_add_request(struct drm_device *dev, struct drm_file *file_priv, uint32_t old_write_domain = obj->write_domain; obj->write_domain = 0; + list_del_init(&obj_priv->gpu_write_list); i915_gem_object_move_to_active(obj, seqno); trace_i915_gem_object_change_domain(obj, @@ -2084,8 +2088,8 @@ static int i915_gem_evict_everything(struct drm_device *dev) { drm_i915_private_t *dev_priv = dev->dev_private; - uint32_t seqno; int ret; + uint32_t seqno; bool lists_empty; spin_lock(&dev_priv->mm.active_list_lock); @@ -2107,6 +2111,8 @@ i915_gem_evict_everything(struct drm_device *dev) if (ret) return ret; + BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); + ret = i915_gem_evict_from_inactive_list(dev); if (ret) return ret; @@ -2701,7 +2707,7 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) old_write_domain = obj->write_domain; i915_gem_flush(dev, 0, obj->write_domain); seqno = i915_add_request(dev, NULL, obj->write_domain); - obj->write_domain = 0; + BUG_ON(obj->write_domain); i915_gem_object_move_to_active(obj, seqno); trace_i915_gem_object_change_domain(obj, @@ -3682,8 +3688,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, if (args->num_cliprects != 0) { cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), GFP_KERNEL); - if (cliprects == NULL) + if (cliprects == NULL) { + ret = -ENOMEM; goto pre_mutex_err; + } ret = copy_from_user(cliprects, (struct drm_clip_rect __user *) @@ -3850,16 +3858,23 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, i915_gem_flush(dev, dev->invalidate_domains, dev->flush_domains); - if (dev->flush_domains) + if (dev->flush_domains & I915_GEM_GPU_DOMAINS) (void)i915_add_request(dev, file_priv, dev->flush_domains); } for (i = 0; i < args->buffer_count; i++) { struct drm_gem_object *obj = object_list[i]; + struct drm_i915_gem_object *obj_priv = obj->driver_private; uint32_t old_write_domain = obj->write_domain; obj->write_domain = obj->pending_write_domain; + if (obj->write_domain) + list_move_tail(&obj_priv->gpu_write_list, + &dev_priv->mm.gpu_write_list); + else + list_del_init(&obj_priv->gpu_write_list); + trace_i915_gem_object_change_domain(obj, obj->read_domains, old_write_domain); @@ -4370,6 +4385,7 @@ int i915_gem_init_object(struct drm_gem_object *obj) obj_priv->obj = obj; obj_priv->fence_reg = I915_FENCE_REG_NONE; INIT_LIST_HEAD(&obj_priv->list); + INIT_LIST_HEAD(&obj_priv->gpu_write_list); INIT_LIST_HEAD(&obj_priv->fence_list); obj_priv->madv = I915_MADV_WILLNEED; @@ -4821,6 +4837,7 @@ i915_gem_load(struct drm_device *dev) spin_lock_init(&dev_priv->mm.active_list_lock); INIT_LIST_HEAD(&dev_priv->mm.active_list); INIT_LIST_HEAD(&dev_priv->mm.flushing_list); + INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); INIT_LIST_HEAD(&dev_priv->mm.inactive_list); INIT_LIST_HEAD(&dev_priv->mm.request_list); INIT_LIST_HEAD(&dev_priv->mm.fence_list); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 50ddf4a95c5e..a17d6bdfe63e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -309,21 +309,21 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev) if (de_iir & DE_GSE) ironlake_opregion_gse_intr(dev); - if (de_iir & DE_PLANEA_FLIP_DONE) + if (de_iir & DE_PLANEA_FLIP_DONE) { intel_prepare_page_flip(dev, 0); + intel_finish_page_flip(dev, 0); + } - if (de_iir & DE_PLANEB_FLIP_DONE) + if (de_iir & DE_PLANEB_FLIP_DONE) { intel_prepare_page_flip(dev, 1); + intel_finish_page_flip(dev, 1); + } - if (de_iir & DE_PIPEA_VBLANK) { + if (de_iir & DE_PIPEA_VBLANK) drm_handle_vblank(dev, 0); - intel_finish_page_flip(dev, 0); - } - if (de_iir & DE_PIPEB_VBLANK) { + if (de_iir & DE_PIPEB_VBLANK) drm_handle_vblank(dev, 1); - intel_finish_page_flip(dev, 1); - } /* check event from PCH */ if ((de_iir & DE_PCH_EVENT) && diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 847006c5218e..ab1bd2d3d3b6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -338,6 +338,7 @@ #define FBC_CTL_PERIODIC (1<<30) #define FBC_CTL_INTERVAL_SHIFT (16) #define FBC_CTL_UNCOMPRESSIBLE (1<<14) +#define FBC_C3_IDLE (1<<13) #define FBC_CTL_STRIDE_SHIFT (5) #define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 12775df1bbfd..b27202d23ebc 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -240,33 +240,86 @@ struct intel_limit { #define IRONLAKE_DOT_MAX 350000 #define IRONLAKE_VCO_MIN 1760000 #define IRONLAKE_VCO_MAX 3510000 -#define IRONLAKE_N_MIN 1 -#define IRONLAKE_N_MAX 6 -#define IRONLAKE_M_MIN 79 -#define IRONLAKE_M_MAX 127 #define IRONLAKE_M1_MIN 12 #define IRONLAKE_M1_MAX 22 #define IRONLAKE_M2_MIN 5 #define IRONLAKE_M2_MAX 9 -#define IRONLAKE_P_SDVO_DAC_MIN 5 -#define IRONLAKE_P_SDVO_DAC_MAX 80 -#define IRONLAKE_P_LVDS_MIN 28 -#define IRONLAKE_P_LVDS_MAX 112 -#define IRONLAKE_P1_MIN 1 -#define IRONLAKE_P1_MAX 8 -#define IRONLAKE_P2_SDVO_DAC_SLOW 10 -#define IRONLAKE_P2_SDVO_DAC_FAST 5 -#define IRONLAKE_P2_LVDS_SLOW 14 /* single channel */ -#define IRONLAKE_P2_LVDS_FAST 7 /* double channel */ #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */ -#define IRONLAKE_P_DISPLAY_PORT_MIN 10 -#define IRONLAKE_P_DISPLAY_PORT_MAX 20 -#define IRONLAKE_P2_DISPLAY_PORT_FAST 10 -#define IRONLAKE_P2_DISPLAY_PORT_SLOW 10 -#define IRONLAKE_P2_DISPLAY_PORT_LIMIT 0 -#define IRONLAKE_P1_DISPLAY_PORT_MIN 1 -#define IRONLAKE_P1_DISPLAY_PORT_MAX 2 +/* We have parameter ranges for different type of outputs. */ + +/* DAC & HDMI Refclk 120Mhz */ +#define IRONLAKE_DAC_N_MIN 1 +#define IRONLAKE_DAC_N_MAX 5 +#define IRONLAKE_DAC_M_MIN 79 +#define IRONLAKE_DAC_M_MAX 127 +#define IRONLAKE_DAC_P_MIN 5 +#define IRONLAKE_DAC_P_MAX 80 +#define IRONLAKE_DAC_P1_MIN 1 +#define IRONLAKE_DAC_P1_MAX 8 +#define IRONLAKE_DAC_P2_SLOW 10 +#define IRONLAKE_DAC_P2_FAST 5 + +/* LVDS single-channel 120Mhz refclk */ +#define IRONLAKE_LVDS_S_N_MIN 1 +#define IRONLAKE_LVDS_S_N_MAX 3 +#define IRONLAKE_LVDS_S_M_MIN 79 +#define IRONLAKE_LVDS_S_M_MAX 118 +#define IRONLAKE_LVDS_S_P_MIN 28 +#define IRONLAKE_LVDS_S_P_MAX 112 +#define IRONLAKE_LVDS_S_P1_MIN 2 +#define IRONLAKE_LVDS_S_P1_MAX 8 +#define IRONLAKE_LVDS_S_P2_SLOW 14 +#define IRONLAKE_LVDS_S_P2_FAST 14 + +/* LVDS dual-channel 120Mhz refclk */ +#define IRONLAKE_LVDS_D_N_MIN 1 +#define IRONLAKE_LVDS_D_N_MAX 3 +#define IRONLAKE_LVDS_D_M_MIN 79 +#define IRONLAKE_LVDS_D_M_MAX 127 +#define IRONLAKE_LVDS_D_P_MIN 14 +#define IRONLAKE_LVDS_D_P_MAX 56 +#define IRONLAKE_LVDS_D_P1_MIN 2 +#define IRONLAKE_LVDS_D_P1_MAX 8 +#define IRONLAKE_LVDS_D_P2_SLOW 7 +#define IRONLAKE_LVDS_D_P2_FAST 7 + +/* LVDS single-channel 100Mhz refclk */ +#define IRONLAKE_LVDS_S_SSC_N_MIN 1 +#define IRONLAKE_LVDS_S_SSC_N_MAX 2 +#define IRONLAKE_LVDS_S_SSC_M_MIN 79 +#define IRONLAKE_LVDS_S_SSC_M_MAX 126 +#define IRONLAKE_LVDS_S_SSC_P_MIN 28 +#define IRONLAKE_LVDS_S_SSC_P_MAX 112 +#define IRONLAKE_LVDS_S_SSC_P1_MIN 2 +#define IRONLAKE_LVDS_S_SSC_P1_MAX 8 +#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14 +#define IRONLAKE_LVDS_S_SSC_P2_FAST 14 + +/* LVDS dual-channel 100Mhz refclk */ +#define IRONLAKE_LVDS_D_SSC_N_MIN 1 +#define IRONLAKE_LVDS_D_SSC_N_MAX 3 +#define IRONLAKE_LVDS_D_SSC_M_MIN 79 +#define IRONLAKE_LVDS_D_SSC_M_MAX 126 +#define IRONLAKE_LVDS_D_SSC_P_MIN 14 +#define IRONLAKE_LVDS_D_SSC_P_MAX 42 +#define IRONLAKE_LVDS_D_SSC_P1_MIN 2 +#define IRONLAKE_LVDS_D_SSC_P1_MAX 6 +#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7 +#define IRONLAKE_LVDS_D_SSC_P2_FAST 7 + +/* DisplayPort */ +#define IRONLAKE_DP_N_MIN 1 +#define IRONLAKE_DP_N_MAX 2 +#define IRONLAKE_DP_M_MIN 81 +#define IRONLAKE_DP_M_MAX 90 +#define IRONLAKE_DP_P_MIN 10 +#define IRONLAKE_DP_P_MAX 20 +#define IRONLAKE_DP_P2_FAST 10 +#define IRONLAKE_DP_P2_SLOW 10 +#define IRONLAKE_DP_P2_LIMIT 0 +#define IRONLAKE_DP_P1_MIN 1 +#define IRONLAKE_DP_P1_MAX 2 static bool intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, @@ -474,33 +527,78 @@ static const intel_limit_t intel_limits_pineview_lvds = { .find_pll = intel_find_best_PLL, }; -static const intel_limit_t intel_limits_ironlake_sdvo = { +static const intel_limit_t intel_limits_ironlake_dac = { .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, - .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX }, - .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX }, + .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX }, + .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX }, .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, - .p = { .min = IRONLAKE_P_SDVO_DAC_MIN, .max = IRONLAKE_P_SDVO_DAC_MAX }, - .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX }, + .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX }, + .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX }, .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, - .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW, - .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST }, + .p2_slow = IRONLAKE_DAC_P2_SLOW, + .p2_fast = IRONLAKE_DAC_P2_FAST }, .find_pll = intel_g4x_find_best_PLL, }; -static const intel_limit_t intel_limits_ironlake_lvds = { +static const intel_limit_t intel_limits_ironlake_single_lvds = { .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, - .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX }, - .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX }, + .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX }, + .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX }, .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, - .p = { .min = IRONLAKE_P_LVDS_MIN, .max = IRONLAKE_P_LVDS_MAX }, - .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX }, + .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX }, + .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX }, .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, - .p2_slow = IRONLAKE_P2_LVDS_SLOW, - .p2_fast = IRONLAKE_P2_LVDS_FAST }, + .p2_slow = IRONLAKE_LVDS_S_P2_SLOW, + .p2_fast = IRONLAKE_LVDS_S_P2_FAST }, + .find_pll = intel_g4x_find_best_PLL, +}; + +static const intel_limit_t intel_limits_ironlake_dual_lvds = { + .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, + .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, + .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX }, + .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX }, + .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, + .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, + .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX }, + .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX }, + .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, + .p2_slow = IRONLAKE_LVDS_D_P2_SLOW, + .p2_fast = IRONLAKE_LVDS_D_P2_FAST }, + .find_pll = intel_g4x_find_best_PLL, +}; + +static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { + .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, + .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, + .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX }, + .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX }, + .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, + .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, + .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX }, + .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX }, + .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, + .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW, + .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST }, + .find_pll = intel_g4x_find_best_PLL, +}; + +static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { + .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX }, + .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX }, + .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX }, + .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX }, + .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, + .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, + .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX }, + .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX }, + .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT, + .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW, + .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST }, .find_pll = intel_g4x_find_best_PLL, }; @@ -509,34 +607,53 @@ static const intel_limit_t intel_limits_ironlake_display_port = { .max = IRONLAKE_DOT_MAX }, .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX}, - .n = { .min = IRONLAKE_N_MIN, - .max = IRONLAKE_N_MAX }, - .m = { .min = IRONLAKE_M_MIN, - .max = IRONLAKE_M_MAX }, + .n = { .min = IRONLAKE_DP_N_MIN, + .max = IRONLAKE_DP_N_MAX }, + .m = { .min = IRONLAKE_DP_M_MIN, + .max = IRONLAKE_DP_M_MAX }, .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX }, .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX }, - .p = { .min = IRONLAKE_P_DISPLAY_PORT_MIN, - .max = IRONLAKE_P_DISPLAY_PORT_MAX }, - .p1 = { .min = IRONLAKE_P1_DISPLAY_PORT_MIN, - .max = IRONLAKE_P1_DISPLAY_PORT_MAX}, - .p2 = { .dot_limit = IRONLAKE_P2_DISPLAY_PORT_LIMIT, - .p2_slow = IRONLAKE_P2_DISPLAY_PORT_SLOW, - .p2_fast = IRONLAKE_P2_DISPLAY_PORT_FAST }, + .p = { .min = IRONLAKE_DP_P_MIN, + .max = IRONLAKE_DP_P_MAX }, + .p1 = { .min = IRONLAKE_DP_P1_MIN, + .max = IRONLAKE_DP_P1_MAX}, + .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT, + .p2_slow = IRONLAKE_DP_P2_SLOW, + .p2_fast = IRONLAKE_DP_P2_FAST }, .find_pll = intel_find_pll_ironlake_dp, }; static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc) { + struct drm_device *dev = crtc->dev; + struct drm_i915_private *dev_priv = dev->dev_private; const intel_limit_t *limit; - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) - limit = &intel_limits_ironlake_lvds; - else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || + int refclk = 120; + + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { + if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100) + refclk = 100; + + if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == + LVDS_CLKB_POWER_UP) { + /* LVDS dual channel */ + if (refclk == 100) + limit = &intel_limits_ironlake_dual_lvds_100m; + else + limit = &intel_limits_ironlake_dual_lvds; + } else { + if (refclk == 100) + limit = &intel_limits_ironlake_single_lvds_100m; + else + limit = &intel_limits_ironlake_single_lvds; + } + } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || HAS_eDP) limit = &intel_limits_ironlake_display_port; else - limit = &intel_limits_ironlake_sdvo; + limit = &intel_limits_ironlake_dac; return limit; } @@ -914,6 +1031,8 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) /* enable it... */ fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; + if (IS_I945GM(dev)) + fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */ fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; if (obj_priv->tiling_mode != I915_TILING_NONE) @@ -3962,7 +4081,8 @@ static void intel_crtc_destroy(struct drm_crtc *crtc) struct intel_unpin_work { struct work_struct work; struct drm_device *dev; - struct drm_gem_object *obj; + struct drm_gem_object *old_fb_obj; + struct drm_gem_object *pending_flip_obj; struct drm_pending_vblank_event *event; int pending; }; @@ -3973,8 +4093,9 @@ static void intel_unpin_work_fn(struct work_struct *__work) container_of(__work, struct intel_unpin_work, work); mutex_lock(&work->dev->struct_mutex); - i915_gem_object_unpin(work->obj); - drm_gem_object_unreference(work->obj); + i915_gem_object_unpin(work->old_fb_obj); + drm_gem_object_unreference(work->pending_flip_obj); + drm_gem_object_unreference(work->old_fb_obj); mutex_unlock(&work->dev->struct_mutex); kfree(work); } @@ -3998,7 +4119,7 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe) work = intel_crtc->unpin_work; if (work == NULL || !work->pending) { if (work && !work->pending) { - obj_priv = work->obj->driver_private; + obj_priv = work->pending_flip_obj->driver_private; DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n", obj_priv, atomic_read(&obj_priv->pending_flip)); @@ -4023,7 +4144,7 @@ void intel_finish_page_flip(struct drm_device *dev, int pipe) spin_unlock_irqrestore(&dev->event_lock, flags); - obj_priv = work->obj->driver_private; + obj_priv = work->pending_flip_obj->driver_private; /* Initial scanout buffer will have a 0 pending flip count */ if ((atomic_read(&obj_priv->pending_flip) == 0) || @@ -4060,7 +4181,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_unpin_work *work; unsigned long flags; - int ret; + int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC; + int ret, pipesrc; RING_LOCALS; work = kzalloc(sizeof *work, GFP_KERNEL); @@ -4072,7 +4194,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, work->event = event; work->dev = crtc->dev; intel_fb = to_intel_framebuffer(crtc->fb); - work->obj = intel_fb->obj; + work->old_fb_obj = intel_fb->obj; INIT_WORK(&work->work, intel_unpin_work_fn); /* We borrow the event spin lock for protecting unpin_work */ @@ -4100,14 +4222,16 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, return ret; } - /* Reference the old fb object for the scheduled work. */ - drm_gem_object_reference(work->obj); + /* Reference the objects for the scheduled work. */ + drm_gem_object_reference(work->old_fb_obj); + drm_gem_object_reference(obj); crtc->fb = fb; i915_gem_object_flush_write_domain(obj); drm_vblank_get(dev, intel_crtc->pipe); obj_priv = obj->driver_private; atomic_inc(&obj_priv->pending_flip); + work->pending_flip_obj = obj; BEGIN_LP_RING(4); OUT_RING(MI_DISPLAY_FLIP | @@ -4115,7 +4239,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, OUT_RING(fb->pitch); if (IS_I965G(dev)) { OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode); - OUT_RING((fb->width << 16) | fb->height); + pipesrc = I915_READ(pipesrc_reg); + OUT_RING(pipesrc & 0x0fff0fff); } else { OUT_RING(obj_priv->gtt_offset); OUT_RING(MI_NOOP); diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 371d753e362b..aaabbcbe5905 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c @@ -148,7 +148,7 @@ static int intelfb_create(struct drm_device *dev, uint32_t fb_width, mutex_lock(&dev->struct_mutex); - ret = i915_gem_object_pin(fbo, PAGE_SIZE); + ret = i915_gem_object_pin(fbo, 64*1024); if (ret) { DRM_ERROR("failed to pin fb: %d\n", ret); goto out_unref; diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index b1d0acbae4e4..c2e8a45780d5 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -636,6 +636,13 @@ static const struct dmi_system_id bad_lid_status[] = { DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"), }, }, + { + .ident = "Clevo M5x0N", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "CLEVO Co."), + DMI_MATCH(DMI_BOARD_NAME, "M5x0N"), + }, + }, { } }; diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c index 1cf488247a16..48227e744753 100644 --- a/drivers/gpu/drm/nouveau/nouveau_acpi.c +++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c @@ -90,21 +90,21 @@ int nouveau_hybrid_setup(struct drm_device *dev) { int result; - if (nouveau_dsm(dev, NOUVEAU_DSM_ACTIVE, NOUVEAU_DSM_ACTIVE_QUERY, + if (nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_STATE, &result)) return -ENODEV; NV_INFO(dev, "_DSM hardware status gave 0x%x\n", result); - if (result & 0x1) { /* Stamina mode - disable the external GPU */ + if (result) { /* Ensure that the external GPU is enabled */ + nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_SPEED, NULL); + nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_SPEED, + NULL); + } else { /* Stamina mode - disable the external GPU */ nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_STAMINA, NULL); nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_STAMINA, NULL); - } else { /* Ensure that the external GPU is enabled */ - nouveau_dsm(dev, NOUVEAU_DSM_LED, NOUVEAU_DSM_LED_SPEED, NULL); - nouveau_dsm(dev, NOUVEAU_DSM_POWER, NOUVEAU_DSM_POWER_SPEED, - NULL); } return 0; diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index d7f8d8b4a4b8..0e9cd1d49130 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -1865,7 +1865,7 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) struct drm_nouveau_private *dev_priv = bios->dev->dev_private; - if (dev_priv->card_type >= NV_50) + if (dev_priv->card_type >= NV_40) return 1; /* @@ -3765,7 +3765,6 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, */ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct init_exec iexec = {true, false}; struct nvbios *bios = &dev_priv->VBIOS; uint8_t *table = &bios->data[bios->display.script_table_ptr]; uint8_t *otable = NULL; @@ -3845,8 +3844,6 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, } } - bios->display.output = dcbent; - if (pxclk == 0) { script = ROM16(otable[6]); if (!script) { @@ -3855,7 +3852,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, } NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); - parse_init_table(bios, script, &iexec); + nouveau_bios_run_init_table(dev, script, dcbent); } else if (pxclk == -1) { script = ROM16(otable[8]); @@ -3865,7 +3862,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, } NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); - parse_init_table(bios, script, &iexec); + nouveau_bios_run_init_table(dev, script, dcbent); } else if (pxclk == -2) { if (table[4] >= 12) @@ -3878,7 +3875,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, } NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); - parse_init_table(bios, script, &iexec); + nouveau_bios_run_init_table(dev, script, dcbent); } else if (pxclk > 0) { script = ROM16(otable[table[4] + i*6 + 2]); @@ -3890,7 +3887,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, } NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); - parse_init_table(bios, script, &iexec); + nouveau_bios_run_init_table(dev, script, dcbent); } else if (pxclk < 0) { script = ROM16(otable[table[4] + i*6 + 4]); @@ -3902,7 +3899,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent, } NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); - parse_init_table(bios, script, &iexec); + nouveau_bios_run_init_table(dev, script, dcbent); } return 0; @@ -5865,9 +5862,11 @@ nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table, struct nvbios *bios = &dev_priv->VBIOS; struct init_exec iexec = { true, false }; + mutex_lock(&bios->lock); bios->display.output = dcbent; parse_init_table(bios, table, &iexec); bios->display.output = NULL; + mutex_unlock(&bios->lock); } static bool NVInitVBIOS(struct drm_device *dev) @@ -5876,6 +5875,7 @@ static bool NVInitVBIOS(struct drm_device *dev) struct nvbios *bios = &dev_priv->VBIOS; memset(bios, 0, sizeof(struct nvbios)); + mutex_init(&bios->lock); bios->dev = dev; if (!NVShadowVBIOS(dev, bios->data)) diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h index 058e98c76d89..fd94bd6dc264 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.h +++ b/drivers/gpu/drm/nouveau/nouveau_bios.h @@ -205,6 +205,8 @@ struct nvbios { struct drm_device *dev; struct nouveau_bios_info pub; + struct mutex lock; + uint8_t data[NV_PROM_SIZE]; unsigned int length; bool execute; diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index db0ed4c13f98..028719fddf76 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -65,8 +65,10 @@ nouveau_bo_fixup_align(struct drm_device *dev, /* * Some of the tile_flags have a periodic structure of N*4096 bytes, - * align to to that as well as the page size. Overallocate memory to - * avoid corruption of other buffer objects. + * align to to that as well as the page size. Align the size to the + * appropriate boundaries. This does imply that sizes are rounded up + * 3-7 pages, so be aware of this and do not waste memory by allocating + * many small buffers. */ if (dev_priv->card_type == NV_50) { uint32_t block_size = nouveau_mem_fb_amount(dev) >> 15; @@ -77,22 +79,20 @@ nouveau_bo_fixup_align(struct drm_device *dev, case 0x2800: case 0x4800: case 0x7a00: - *size = roundup(*size, block_size); if (is_power_of_2(block_size)) { - *size += 3 * block_size; for (i = 1; i < 10; i++) { *align = 12 * i * block_size; if (!(*align % 65536)) break; } } else { - *size += 6 * block_size; for (i = 1; i < 10; i++) { *align = 8 * i * block_size; if (!(*align % 65536)) break; } } + *size = roundup(*size, *align); break; default: break; diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c index 343d718a9667..2281f99da7fc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_channel.c +++ b/drivers/gpu/drm/nouveau/nouveau_channel.c @@ -278,12 +278,11 @@ nouveau_channel_free(struct nouveau_channel *chan) /* Ensure the channel is no longer active on the GPU */ pfifo->reassign(dev, false); - if (pgraph->channel(dev) == chan) { - pgraph->fifo_access(dev, false); + pgraph->fifo_access(dev, false); + if (pgraph->channel(dev) == chan) pgraph->unload_context(dev); - pgraph->fifo_access(dev, true); - } pgraph->destroy_context(chan); + pgraph->fifo_access(dev, true); if (pfifo->channel_id(dev) == chan->id) { pfifo->disable(dev); diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 7e6d673f3a23..d2f63353ea97 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -88,13 +88,14 @@ nouveau_connector_destroy(struct drm_connector *drm_connector) { struct nouveau_connector *nv_connector = nouveau_connector(drm_connector); - struct drm_device *dev = nv_connector->base.dev; - - NV_DEBUG_KMS(dev, "\n"); + struct drm_device *dev; if (!nv_connector) return; + dev = nv_connector->base.dev; + NV_DEBUG_KMS(dev, "\n"); + kfree(nv_connector->edid); drm_sysfs_connector_remove(drm_connector); drm_connector_cleanup(drm_connector); diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c index dd4937224220..f954ad93e81f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dp.c +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c @@ -502,12 +502,12 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, break; } - if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) { - ret = -EREMOTEIO; - goto out; - } - if (cmd & 1) { + if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) { + ret = -EREMOTEIO; + goto out; + } + for (i = 0; i < 4; i++) { data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i)); NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]); diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c index 343ab7f17ccc..da3b93b84502 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.c +++ b/drivers/gpu/drm/nouveau/nouveau_drv.c @@ -56,7 +56,7 @@ int nouveau_vram_pushbuf; module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM"); -int nouveau_vram_notify; +int nouveau_vram_notify = 1; module_param_named(vram_notify, nouveau_vram_notify, int, 0400); MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)"); @@ -75,6 +75,14 @@ MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status"); int nouveau_ignorelid = 0; module_param_named(ignorelid, nouveau_ignorelid, int, 0400); +MODULE_PARM_DESC(noagp, "Disable all acceleration"); +int nouveau_noaccel = 0; +module_param_named(noaccel, nouveau_noaccel, int, 0400); + +MODULE_PARM_DESC(noagp, "Disable fbcon acceleration"); +int nouveau_nofbaccel = 0; +module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400); + MODULE_PARM_DESC(tv_norm, "Default TV norm.\n" "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n" "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n" diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 6b9690418bc7..5445cefdd03e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -678,6 +678,8 @@ extern int nouveau_reg_debug; extern char *nouveau_vbios; extern int nouveau_ctxfw; extern int nouveau_ignorelid; +extern int nouveau_nofbaccel; +extern int nouveau_noaccel; /* nouveau_state.c */ extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 0b05c869e0e7..ea879a2efef3 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -107,6 +107,34 @@ static struct fb_ops nouveau_fbcon_ops = { .fb_setcmap = drm_fb_helper_setcmap, }; +static struct fb_ops nv04_fbcon_ops = { + .owner = THIS_MODULE, + .fb_check_var = drm_fb_helper_check_var, + .fb_set_par = drm_fb_helper_set_par, + .fb_setcolreg = drm_fb_helper_setcolreg, + .fb_fillrect = nv04_fbcon_fillrect, + .fb_copyarea = nv04_fbcon_copyarea, + .fb_imageblit = nv04_fbcon_imageblit, + .fb_sync = nouveau_fbcon_sync, + .fb_pan_display = drm_fb_helper_pan_display, + .fb_blank = drm_fb_helper_blank, + .fb_setcmap = drm_fb_helper_setcmap, +}; + +static struct fb_ops nv50_fbcon_ops = { + .owner = THIS_MODULE, + .fb_check_var = drm_fb_helper_check_var, + .fb_set_par = drm_fb_helper_set_par, + .fb_setcolreg = drm_fb_helper_setcolreg, + .fb_fillrect = nv50_fbcon_fillrect, + .fb_copyarea = nv50_fbcon_copyarea, + .fb_imageblit = nv50_fbcon_imageblit, + .fb_sync = nouveau_fbcon_sync, + .fb_pan_display = drm_fb_helper_pan_display, + .fb_blank = drm_fb_helper_blank, + .fb_setcmap = drm_fb_helper_setcmap, +}; + static void nouveau_fbcon_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, u16 blue, int regno) { @@ -267,8 +295,12 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width, dev_priv->fbdev_info = info; strcpy(info->fix.id, "nouveaufb"); - info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA | - FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT; + if (nouveau_nofbaccel) + info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_DISABLED; + else + info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA | + FBINFO_HWACCEL_FILLRECT | + FBINFO_HWACCEL_IMAGEBLIT; info->fbops = &nouveau_fbcon_ops; info->fix.smem_start = dev->mode_config.fb_base + nvbo->bo.offset - dev_priv->vm_vram_base; @@ -316,13 +348,15 @@ nouveau_fbcon_create(struct drm_device *dev, uint32_t fb_width, par->nouveau_fb = nouveau_fb; par->dev = dev; - if (dev_priv->channel) { + if (dev_priv->channel && !nouveau_nofbaccel) { switch (dev_priv->card_type) { case NV_50: nv50_fbcon_accel_init(info); + info->fbops = &nv50_fbcon_ops; break; default: nv04_fbcon_accel_init(info); + info->fbops = &nv04_fbcon_ops; break; }; } diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h index 462e0b87b4bd..f9c34e1a8c11 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.h @@ -40,7 +40,13 @@ int nouveau_fbcon_remove(struct drm_device *dev, struct drm_framebuffer *fb); void nouveau_fbcon_restore(void); void nouveau_fbcon_zfill(struct drm_device *dev); +void nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region); +void nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect); +void nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image); int nv04_fbcon_accel_init(struct fb_info *info); +void nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect); +void nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region); +void nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image); int nv50_fbcon_accel_init(struct fb_info *info); void nouveau_fbcon_gpu_lockup(struct fb_info *info); diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 6ac804b0c9f9..70cc30803e3b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -925,7 +925,9 @@ nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data, } if (req->flags & NOUVEAU_GEM_CPU_PREP_NOBLOCK) { + spin_lock(&nvbo->bo.lock); ret = ttm_bo_wait(&nvbo->bo, false, false, no_wait); + spin_unlock(&nvbo->bo.lock); } else { ret = ttm_bo_synccpu_write_grab(&nvbo->bo, no_wait); if (ret == 0) diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.c b/drivers/gpu/drm/nouveau/nouveau_grctx.c index 419f4c2b3b89..c7ebec696747 100644 --- a/drivers/gpu/drm/nouveau/nouveau_grctx.c +++ b/drivers/gpu/drm/nouveau/nouveau_grctx.c @@ -97,8 +97,8 @@ nouveau_grctx_prog_load(struct drm_device *dev) } pgraph->ctxvals = kmalloc(fw->size, GFP_KERNEL); - if (!pgraph->ctxprog) { - NV_ERROR(dev, "OOM copying ctxprog\n"); + if (!pgraph->ctxvals) { + NV_ERROR(dev, "OOM copying ctxvals\n"); release_firmware(fw); nouveau_grctx_fini(dev); return -ENOMEM; diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c index 3b9bad66162a..447f9f69d6b1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_irq.c +++ b/drivers/gpu/drm/nouveau/nouveau_irq.c @@ -211,6 +211,20 @@ nouveau_fifo_irq_handler(struct drm_device *dev) get + 4); } + if (status & NV_PFIFO_INTR_SEMAPHORE) { + uint32_t sem; + + status &= ~NV_PFIFO_INTR_SEMAPHORE; + nv_wr32(dev, NV03_PFIFO_INTR_0, + NV_PFIFO_INTR_SEMAPHORE); + + sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE); + nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); + + nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4); + nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1); + } + if (status) { NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n", status, chid); @@ -566,86 +580,99 @@ nouveau_pgraph_irq_handler(struct drm_device *dev) static void nv50_pgraph_irq_handler(struct drm_device *dev) { - uint32_t status, nsource; + uint32_t status; - status = nv_rd32(dev, NV03_PGRAPH_INTR); - nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE); + while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) { + uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE); - if (status & 0x00000001) { - nouveau_pgraph_intr_notify(dev, nsource); - status &= ~0x00000001; - nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001); - } + if (status & 0x00000001) { + nouveau_pgraph_intr_notify(dev, nsource); + status &= ~0x00000001; + nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001); + } - if (status & 0x00000010) { - nouveau_pgraph_intr_error(dev, nsource | - NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD); + if (status & 0x00000010) { + nouveau_pgraph_intr_error(dev, nsource | + NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD); - status &= ~0x00000010; - nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010); - } + status &= ~0x00000010; + nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010); + } - if (status & 0x00001000) { - nv_wr32(dev, 0x400500, 0x00000000); - nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); - nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev, - NV40_PGRAPH_INTR_EN) & ~NV_PGRAPH_INTR_CONTEXT_SWITCH); - nv_wr32(dev, 0x400500, 0x00010001); + if (status & 0x00001000) { + nv_wr32(dev, 0x400500, 0x00000000); + nv_wr32(dev, NV03_PGRAPH_INTR, + NV_PGRAPH_INTR_CONTEXT_SWITCH); + nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev, + NV40_PGRAPH_INTR_EN) & + ~NV_PGRAPH_INTR_CONTEXT_SWITCH); + nv_wr32(dev, 0x400500, 0x00010001); - nv50_graph_context_switch(dev); + nv50_graph_context_switch(dev); - status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; - } + status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; + } - if (status & 0x00100000) { - nouveau_pgraph_intr_error(dev, nsource | - NV03_PGRAPH_NSOURCE_DATA_ERROR); + if (status & 0x00100000) { + nouveau_pgraph_intr_error(dev, nsource | + NV03_PGRAPH_NSOURCE_DATA_ERROR); - status &= ~0x00100000; - nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000); - } + status &= ~0x00100000; + nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000); + } - if (status & 0x00200000) { - int r; - - nouveau_pgraph_intr_error(dev, nsource | - NV03_PGRAPH_NSOURCE_PROTECTION_ERROR); - - NV_ERROR(dev, "magic set 1:\n"); - for (r = 0x408900; r <= 0x408910; r += 4) - NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); - nv_wr32(dev, 0x408900, nv_rd32(dev, 0x408904) | 0xc0000000); - for (r = 0x408e08; r <= 0x408e24; r += 4) - NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); - nv_wr32(dev, 0x408e08, nv_rd32(dev, 0x408e08) | 0xc0000000); - - NV_ERROR(dev, "magic set 2:\n"); - for (r = 0x409900; r <= 0x409910; r += 4) - NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); - nv_wr32(dev, 0x409900, nv_rd32(dev, 0x409904) | 0xc0000000); - for (r = 0x409e08; r <= 0x409e24; r += 4) - NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, nv_rd32(dev, r)); - nv_wr32(dev, 0x409e08, nv_rd32(dev, 0x409e08) | 0xc0000000); - - status &= ~0x00200000; - nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource); - nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000); - } + if (status & 0x00200000) { + int r; + + nouveau_pgraph_intr_error(dev, nsource | + NV03_PGRAPH_NSOURCE_PROTECTION_ERROR); + + NV_ERROR(dev, "magic set 1:\n"); + for (r = 0x408900; r <= 0x408910; r += 4) + NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, + nv_rd32(dev, r)); + nv_wr32(dev, 0x408900, + nv_rd32(dev, 0x408904) | 0xc0000000); + for (r = 0x408e08; r <= 0x408e24; r += 4) + NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, + nv_rd32(dev, r)); + nv_wr32(dev, 0x408e08, + nv_rd32(dev, 0x408e08) | 0xc0000000); + + NV_ERROR(dev, "magic set 2:\n"); + for (r = 0x409900; r <= 0x409910; r += 4) + NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, + nv_rd32(dev, r)); + nv_wr32(dev, 0x409900, + nv_rd32(dev, 0x409904) | 0xc0000000); + for (r = 0x409e08; r <= 0x409e24; r += 4) + NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r, + nv_rd32(dev, r)); + nv_wr32(dev, 0x409e08, + nv_rd32(dev, 0x409e08) | 0xc0000000); + + status &= ~0x00200000; + nv_wr32(dev, NV03_PGRAPH_NSOURCE, nsource); + nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000); + } - if (status) { - NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status); - nv_wr32(dev, NV03_PGRAPH_INTR, status); - } + if (status) { + NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", + status); + nv_wr32(dev, NV03_PGRAPH_INTR, status); + } - { - const int isb = (1 << 16) | (1 << 0); + { + const int isb = (1 << 16) | (1 << 0); - if ((nv_rd32(dev, 0x400500) & isb) != isb) - nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | isb); - nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31)); + if ((nv_rd32(dev, 0x400500) & isb) != isb) + nv_wr32(dev, 0x400500, + nv_rd32(dev, 0x400500) | isb); + } } nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING); + nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31)); } static void diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c index 6c66a34b6345..d99dc087f9b1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_notifier.c +++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c @@ -34,15 +34,20 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; struct nouveau_bo *ntfy = NULL; + uint32_t flags; int ret; - ret = nouveau_gem_new(dev, NULL, PAGE_SIZE, 0, nouveau_vram_notify ? - TTM_PL_FLAG_VRAM : TTM_PL_FLAG_TT, + if (nouveau_vram_notify) + flags = TTM_PL_FLAG_VRAM; + else + flags = TTM_PL_FLAG_TT; + + ret = nouveau_gem_new(dev, NULL, PAGE_SIZE, 0, flags, 0, 0x0000, false, true, &ntfy); if (ret) return ret; - ret = nouveau_bo_pin(ntfy, TTM_PL_FLAG_VRAM); + ret = nouveau_bo_pin(ntfy, flags); if (ret) goto out_err; @@ -128,6 +133,8 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, target = NV_DMA_TARGET_PCI; } else { target = NV_DMA_TARGET_AGP; + if (dev_priv->card_type >= NV_50) + offset += dev_priv->vm_gart_base; } } else { NV_ERROR(dev, "Bad DMA target, mem_type %d!\n", diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c index 6c2cf81716df..e7c100ba63a1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_object.c +++ b/drivers/gpu/drm/nouveau/nouveau_object.c @@ -885,11 +885,12 @@ int nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class, struct nouveau_gpuobj **gpuobj_ret) { - struct drm_nouveau_private *dev_priv = chan->dev->dev_private; + struct drm_nouveau_private *dev_priv; struct nouveau_gpuobj *gpuobj; if (!chan || !gpuobj_ret || *gpuobj_ret != NULL) return -EINVAL; + dev_priv = chan->dev->dev_private; gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); if (!gpuobj) diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h index 251f1b3b38b9..aa9b310e41be 100644 --- a/drivers/gpu/drm/nouveau/nouveau_reg.h +++ b/drivers/gpu/drm/nouveau/nouveau_reg.h @@ -99,6 +99,7 @@ * the card will hang early on in the X init process. */ # define NV_PMC_ENABLE_UNK13 (1<<13) +#define NV40_PMC_GRAPH_UNITS 0x00001540 #define NV40_PMC_BACKLIGHT 0x000015f0 # define NV40_PMC_BACKLIGHT_MASK 0x001f0000 #define NV40_PMC_1700 0x00001700 diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index 4c7f1e403e80..ed1590577b6c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c @@ -54,11 +54,12 @@ static void nouveau_sgdma_clear(struct ttm_backend *be) { struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be; - struct drm_device *dev = nvbe->dev; - - NV_DEBUG(nvbe->dev, "\n"); + struct drm_device *dev; if (nvbe && nvbe->pages) { + dev = nvbe->dev; + NV_DEBUG(dev, "\n"); + if (nvbe->bound) be->func->unbind(be); diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index f2d0187ba152..a4851af5b05e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c @@ -310,6 +310,14 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) static unsigned int nouveau_vga_set_decode(void *priv, bool state) { + struct drm_device *dev = priv; + struct drm_nouveau_private *dev_priv = dev->dev_private; + + if (dev_priv->chipset >= 0x40) + nv_wr32(dev, 0x88054, state); + else + nv_wr32(dev, 0x1854, state); + if (state) return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; @@ -427,15 +435,19 @@ nouveau_card_init(struct drm_device *dev) if (ret) goto out_timer; - /* PGRAPH */ - ret = engine->graph.init(dev); - if (ret) - goto out_fb; + if (nouveau_noaccel) + engine->graph.accel_blocked = true; + else { + /* PGRAPH */ + ret = engine->graph.init(dev); + if (ret) + goto out_fb; - /* PFIFO */ - ret = engine->fifo.init(dev); - if (ret) - goto out_graph; + /* PFIFO */ + ret = engine->fifo.init(dev); + if (ret) + goto out_graph; + } /* this call irq_preinstall, register irq handler and * call irq_postinstall @@ -479,9 +491,11 @@ nouveau_card_init(struct drm_device *dev) out_irq: drm_irq_uninstall(dev); out_fifo: - engine->fifo.takedown(dev); + if (!nouveau_noaccel) + engine->fifo.takedown(dev); out_graph: - engine->graph.takedown(dev); + if (!nouveau_noaccel) + engine->graph.takedown(dev); out_fb: engine->fb.takedown(dev); out_timer: @@ -518,8 +532,10 @@ static void nouveau_card_takedown(struct drm_device *dev) dev_priv->channel = NULL; } - engine->fifo.takedown(dev); - engine->graph.takedown(dev); + if (!nouveau_noaccel) { + engine->fifo.takedown(dev); + engine->graph.takedown(dev); + } engine->fb.takedown(dev); engine->timer.takedown(dev); engine->mc.takedown(dev); @@ -817,6 +833,15 @@ int nouveau_ioctl_getparam(struct drm_device *dev, void *data, case NOUVEAU_GETPARAM_VM_VRAM_BASE: getparam->value = dev_priv->vm_vram_base; break; + case NOUVEAU_GETPARAM_GRAPH_UNITS: + /* NV40 and NV50 versions are quite different, but register + * address is the same. User is supposed to know the card + * family anyway... */ + if (dev_priv->chipset >= 0x40) { + getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS); + break; + } + /* FALLTHRU */ default: NV_ERROR(dev, "unknown parameter %lld\n", getparam->param); return -EINVAL; diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index d910873c1368..fd01caabd5c3 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -27,7 +27,7 @@ #include "nouveau_dma.h" #include "nouveau_fbcon.h" -static void +void nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) { struct nouveau_fbcon_par *par = info->par; @@ -54,7 +54,7 @@ nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) FIRE_RING(chan); } -static void +void nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { struct nouveau_fbcon_par *par = info->par; @@ -88,7 +88,7 @@ nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) FIRE_RING(chan); } -static void +void nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) { struct nouveau_fbcon_par *par = info->par; @@ -307,9 +307,6 @@ nv04_fbcon_accel_init(struct fb_info *info) FIRE_RING(chan); - info->fbops->fb_fillrect = nv04_fbcon_fillrect; - info->fbops->fb_copyarea = nv04_fbcon_copyarea; - info->fbops->fb_imageblit = nv04_fbcon_imageblit; return 0; } diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c index 58b917c3341b..21ac6e49b6ee 100644 --- a/drivers/gpu/drm/nouveau/nv17_tv.c +++ b/drivers/gpu/drm/nouveau/nv17_tv.c @@ -579,6 +579,8 @@ static void nv17_tv_restore(struct drm_encoder *encoder) nouveau_encoder(encoder)->restore.output); nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state); + + nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED; } static int nv17_tv_create_resources(struct drm_encoder *encoder, diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c index 40b7360841f8..d1a651e3400c 100644 --- a/drivers/gpu/drm/nouveau/nv50_crtc.c +++ b/drivers/gpu/drm/nouveau/nv50_crtc.c @@ -298,14 +298,17 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk) static void nv50_crtc_destroy(struct drm_crtc *crtc) { - struct drm_device *dev = crtc->dev; - struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); - - NV_DEBUG_KMS(dev, "\n"); + struct drm_device *dev; + struct nouveau_crtc *nv_crtc; if (!crtc) return; + dev = crtc->dev; + nv_crtc = nouveau_crtc(crtc); + + NV_DEBUG_KMS(dev, "\n"); + drm_crtc_cleanup(&nv_crtc->base); nv50_cursor_fini(nv_crtc); diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c index e4f279ee61cf..0f57cdf7ccb2 100644 --- a/drivers/gpu/drm/nouveau/nv50_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv50_fbcon.c @@ -3,7 +3,7 @@ #include "nouveau_dma.h" #include "nouveau_fbcon.h" -static void +void nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) { struct nouveau_fbcon_par *par = info->par; @@ -46,7 +46,7 @@ nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) FIRE_RING(chan); } -static void +void nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) { struct nouveau_fbcon_par *par = info->par; @@ -81,7 +81,7 @@ nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) FIRE_RING(chan); } -static void +void nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) { struct nouveau_fbcon_par *par = info->par; @@ -262,9 +262,6 @@ nv50_fbcon_accel_init(struct fb_info *info) OUT_RING(chan, info->fix.smem_start - dev_priv->fb_phys + dev_priv->vm_vram_base); - info->fbops->fb_fillrect = nv50_fbcon_fillrect; - info->fbops->fb_copyarea = nv50_fbcon_copyarea; - info->fbops->fb_imageblit = nv50_fbcon_imageblit; return 0; } diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c index 32b244bcb482..204a79ff10f4 100644 --- a/drivers/gpu/drm/nouveau/nv50_fifo.c +++ b/drivers/gpu/drm/nouveau/nv50_fifo.c @@ -317,17 +317,20 @@ void nv50_fifo_destroy_context(struct nouveau_channel *chan) { struct drm_device *dev = chan->dev; + struct nouveau_gpuobj_ref *ramfc = chan->ramfc; NV_DEBUG(dev, "ch%d\n", chan->id); - nouveau_gpuobj_ref_del(dev, &chan->ramfc); - nouveau_gpuobj_ref_del(dev, &chan->cache); - + /* This will ensure the channel is seen as disabled. */ + chan->ramfc = NULL; nv50_fifo_channel_disable(dev, chan->id, false); /* Dummy channel, also used on ch 127 */ if (chan->id == 0) nv50_fifo_channel_disable(dev, 127, false); + + nouveau_gpuobj_ref_del(dev, &ramfc); + nouveau_gpuobj_ref_del(dev, &chan->cache); } int diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c index 20319e59d368..6d504801b514 100644 --- a/drivers/gpu/drm/nouveau/nv50_graph.c +++ b/drivers/gpu/drm/nouveau/nv50_graph.c @@ -165,6 +165,12 @@ nv50_graph_channel(struct drm_device *dev) uint32_t inst; int i; + /* Be sure we're not in the middle of a context switch or bad things + * will happen, such as unloading the wrong pgraph context. + */ + if (!nv_wait(0x400300, 0x00000001, 0x00000000)) + NV_ERROR(dev, "Ctxprog is still running\n"); + inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) return NULL; @@ -275,7 +281,7 @@ nv50_graph_load_context(struct nouveau_channel *chan) int nv50_graph_unload_context(struct drm_device *dev) { - uint32_t inst, fifo = nv_rd32(dev, 0x400500); + uint32_t inst; inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR); if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED)) @@ -283,12 +289,10 @@ nv50_graph_unload_context(struct drm_device *dev) inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE; nouveau_wait_for_idle(dev); - nv_wr32(dev, 0x400500, fifo & ~1); nv_wr32(dev, 0x400784, inst); nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20); nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01); nouveau_wait_for_idle(dev); - nv_wr32(dev, 0x400500, fifo); nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst); return 0; diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c index ecf1936b8224..c2fff543b06f 100644 --- a/drivers/gpu/drm/nouveau/nv50_sor.c +++ b/drivers/gpu/drm/nouveau/nv50_sor.c @@ -101,6 +101,7 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode) struct nouveau_encoder *nvenc = nouveau_encoder(enc); if (nvenc == nv_encoder || + nvenc->disconnect != nv50_sor_disconnect || nvenc->dcb->or != nv_encoder->dcb->or) continue; diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig index 5982321be4d5..1c02d23f6fcc 100644 --- a/drivers/gpu/drm/radeon/Kconfig +++ b/drivers/gpu/drm/radeon/Kconfig @@ -1,10 +1,14 @@ config DRM_RADEON_KMS - bool "Enable modesetting on radeon by default" + bool "Enable modesetting on radeon by default - NEW DRIVER" depends on DRM_RADEON help - Choose this option if you want kernel modesetting enabled by default, - and you have a new enough userspace to support this. Running old - userspaces with this enabled will cause pain. + Choose this option if you want kernel modesetting enabled by default. + + This is a completely new driver. It's only part of the existing drm + for compatibility reasons. It requires an entirely different graphics + stack above it and works very differently from the old drm stack. + i.e. don't enable this unless you know what you are doing it may + cause issues or bugs compared to the previous userspace driver stack. When kernel modesetting is enabled the IOCTL of radeon/drm driver are considered as invalid and an error message is printed diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c index e3b44562d265..7f152f66f196 100644 --- a/drivers/gpu/drm/radeon/atom.c +++ b/drivers/gpu/drm/radeon/atom.c @@ -24,6 +24,7 @@ #include <linux/module.h> #include <linux/sched.h> +#include <asm/unaligned.h> #define ATOM_DEBUG @@ -212,7 +213,9 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, case ATOM_ARG_PS: idx = U8(*ptr); (*ptr)++; - val = le32_to_cpu(ctx->ps[idx]); + /* get_unaligned_le32 avoids unaligned accesses from atombios + * tables, noticed on a DEC Alpha. */ + val = get_unaligned_le32((u32 *)&ctx->ps[idx]); if (print) DEBUG("PS[0x%02X,0x%04X]", idx, val); break; @@ -640,7 +643,7 @@ static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) uint8_t count = U8((*ptr)++); SDEBUG(" count: %d\n", count); if (arg == ATOM_UNIT_MICROSEC) - schedule_timeout_uninterruptible(usecs_to_jiffies(count)); + udelay(count); else schedule_timeout_uninterruptible(msecs_to_jiffies(count)); } diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 71060114d5de..99915a682d59 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -332,11 +332,13 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args; int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); unsigned char *base; + int retry_count = 0; memset(&args, 0, sizeof(args)); base = (unsigned char *)rdev->mode_info.atom_context->scratch; +retry: memcpy(base, req_bytes, num_bytes); args.lpAuxRequest = 0; @@ -347,10 +349,12 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); - if (args.ucReplyStatus) { - DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n", + if (args.ucReplyStatus && !args.ucDataOutLen) { + if (args.ucReplyStatus == 0x20 && retry_count++ < 10) + goto retry; + DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n", req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], - chan->rec.i2c_id, args.ucReplyStatus); + chan->rec.i2c_id, args.ucReplyStatus, retry_count); return false; } diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index a1198d99cdf9..2ffcf5a03551 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -1950,6 +1950,13 @@ int r600_resume(struct radeon_device *rdev) DRM_ERROR("radeon: failled testing IB (%d).\n", r); return r; } + + r = r600_audio_init(rdev); + if (r) { + DRM_ERROR("radeon: audio resume failed\n"); + return r; + } + return r; } @@ -1957,6 +1964,7 @@ int r600_suspend(struct radeon_device *rdev) { int r; + r600_audio_fini(rdev); /* FIXME: we should wait for ring to be empty */ r600_cp_stop(rdev); rdev->cp.ready = false; diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c index b1c1d3433454..0dcb6904c4ff 100644 --- a/drivers/gpu/drm/radeon/r600_audio.c +++ b/drivers/gpu/drm/radeon/r600_audio.c @@ -261,7 +261,6 @@ void r600_audio_fini(struct radeon_device *rdev) if (!r600_audio_chipset_supported(rdev)) return; - WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000); - del_timer(&rdev->audio_timer); + WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000); } diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c index af1c3ca8a4cb..446b765ac72a 100644 --- a/drivers/gpu/drm/radeon/r600_blit_kms.c +++ b/drivers/gpu/drm/radeon/r600_blit_kms.c @@ -543,9 +543,6 @@ int r600_vb_ib_get(struct radeon_device *rdev) void r600_vb_ib_put(struct radeon_device *rdev) { radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); - mutex_lock(&rdev->ib_pool.mutex); - list_add_tail(&rdev->r600_blit.vb_ib->list, &rdev->ib_pool.scheduled_ibs); - mutex_unlock(&rdev->ib_pool.mutex); radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); } diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index f57480ba1355..c0356bb193e5 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -96,6 +96,7 @@ extern int radeon_audio; * symbol; */ #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ +/* RADEON_IB_POOL_SIZE must be a power of 2 */ #define RADEON_IB_POOL_SIZE 16 #define RADEON_DEBUGFS_MAX_NUM_FILES 32 #define RADEONFB_CONN_LIMIT 4 @@ -363,11 +364,12 @@ void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); */ struct radeon_ib { struct list_head list; - unsigned long idx; + unsigned idx; uint64_t gpu_addr; struct radeon_fence *fence; - uint32_t *ptr; + uint32_t *ptr; uint32_t length_dw; + bool free; }; /* @@ -377,10 +379,9 @@ struct radeon_ib { struct radeon_ib_pool { struct mutex mutex; struct radeon_bo *robj; - struct list_head scheduled_ibs; struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; bool ready; - DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); + unsigned head_id; }; struct radeon_cp { diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index fa82ca74324e..2dcda6115874 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -287,6 +287,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev, *connector_type = DRM_MODE_CONNECTOR_DVID; } + /* XFX Pine Group device rv730 reports no VGA DDC lines + * even though they are wired up to record 0x93 + */ + if ((dev->pdev->device == 0x9498) && + (dev->pdev->subsystem_vendor == 0x1682) && + (dev->pdev->subsystem_device == 0x2452)) { + struct radeon_device *rdev = dev->dev_private; + *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93); + } return true; } diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c index 4ddfd4b5bc51..7932dc4d6b90 100644 --- a/drivers/gpu/drm/radeon/radeon_benchmark.c +++ b/drivers/gpu/drm/radeon/radeon_benchmark.c @@ -65,31 +65,42 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize, if (r) { goto out_cleanup; } - start_jiffies = jiffies; - for (i = 0; i < n; i++) { - r = radeon_fence_create(rdev, &fence); - if (r) { - goto out_cleanup; + + /* r100 doesn't have dma engine so skip the test */ + if (rdev->asic->copy_dma) { + + start_jiffies = jiffies; + for (i = 0; i < n; i++) { + r = radeon_fence_create(rdev, &fence); + if (r) { + goto out_cleanup; + } + + r = radeon_copy_dma(rdev, saddr, daddr, + size / RADEON_GPU_PAGE_SIZE, fence); + + if (r) { + goto out_cleanup; + } + r = radeon_fence_wait(fence, false); + if (r) { + goto out_cleanup; + } + radeon_fence_unref(&fence); } - r = radeon_copy_dma(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence); - if (r) { - goto out_cleanup; + end_jiffies = jiffies; + time = end_jiffies - start_jiffies; + time = jiffies_to_msecs(time); + if (time > 0) { + i = ((n * size) >> 10) / time; + printk(KERN_INFO "radeon: dma %u bo moves of %ukb from" + " %d to %d in %lums (%ukb/ms %ukb/s %uM/s)\n", + n, size >> 10, + sdomain, ddomain, time, + i, i * 1000, (i * 1000) / 1024); } - r = radeon_fence_wait(fence, false); - if (r) { - goto out_cleanup; - } - radeon_fence_unref(&fence); - } - end_jiffies = jiffies; - time = end_jiffies - start_jiffies; - time = jiffies_to_msecs(time); - if (time > 0) { - i = ((n * size) >> 10) / time; - printk(KERN_INFO "radeon: dma %u bo moves of %ukb from %d to %d" - " in %lums (%ukb/ms %ukb/s %uM/s)\n", n, size >> 10, - sdomain, ddomain, time, i, i * 1000, (i * 1000) / 1024); } + start_jiffies = jiffies; for (i = 0; i < n; i++) { r = radeon_fence_create(rdev, &fence); diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 2d8e5a70f284..238188540017 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -580,16 +580,18 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect struct radeon_connector *radeon_connector = to_radeon_connector(connector); struct drm_encoder *encoder; struct drm_encoder_helper_funcs *encoder_funcs; - bool dret; + bool dret = false; enum drm_connector_status ret = connector_status_disconnected; encoder = radeon_best_single_encoder(connector); if (!encoder) ret = connector_status_disconnected; - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); - dret = radeon_ddc_probe(radeon_connector); - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); + if (radeon_connector->ddc_bus) { + radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); + dret = radeon_ddc_probe(radeon_connector); + radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); + } if (dret) { if (radeon_connector->edid) { kfree(radeon_connector->edid); @@ -740,11 +742,13 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect struct drm_mode_object *obj; int i; enum drm_connector_status ret = connector_status_disconnected; - bool dret; + bool dret = false; - radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); - dret = radeon_ddc_probe(radeon_connector); - radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); + if (radeon_connector->ddc_bus) { + radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); + dret = radeon_ddc_probe(radeon_connector); + radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); + } if (dret) { if (radeon_connector->edid) { kfree(radeon_connector->edid); diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 1190148cf5e6..e9d085021c1f 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -86,7 +86,7 @@ int radeon_cs_parser_relocs(struct radeon_cs_parser *p) &p->validated); } } - return radeon_bo_list_validate(&p->validated, p->ib->fence); + return radeon_bo_list_validate(&p->validated); } int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) @@ -189,12 +189,10 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) { unsigned i; - if (error && parser->ib) { - radeon_bo_list_unvalidate(&parser->validated, - parser->ib->fence); - } else { - radeon_bo_list_unreserve(&parser->validated); + if (!error && parser->ib) { + radeon_bo_list_fence(&parser->validated, parser->ib->fence); } + radeon_bo_list_unreserve(&parser->validated); for (i = 0; i < parser->nrelocs; i++) { if (parser->relocs[i].gobj) { mutex_lock(&parser->rdev->ddev->struct_mutex); diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 6a92f994cc26..7e17a362b54b 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -278,7 +278,7 @@ static void radeon_print_display_setup(struct drm_device *dev) DRM_INFO(" %s\n", connector_names[connector->connector_type]); if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); - if (radeon_connector->ddc_bus) + if (radeon_connector->ddc_bus) { DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", radeon_connector->ddc_bus->rec.mask_clk_reg, radeon_connector->ddc_bus->rec.mask_data_reg, @@ -288,6 +288,15 @@ static void radeon_print_display_setup(struct drm_device *dev) radeon_connector->ddc_bus->rec.en_data_reg, radeon_connector->ddc_bus->rec.y_clk_reg, radeon_connector->ddc_bus->rec.y_data_reg); + } else { + if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || + connector->connector_type == DRM_MODE_CONNECTOR_DVII || + connector->connector_type == DRM_MODE_CONNECTOR_DVID || + connector->connector_type == DRM_MODE_CONNECTOR_DVIA || + connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || + connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) + DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to [email protected]\n"); + } DRM_INFO(" Encoders:\n"); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { radeon_encoder = to_radeon_encoder(encoder); diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 3ba213d1b06c..d71e346e9ab5 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -248,7 +248,7 @@ int radeonfb_create(struct drm_device *dev, if (ret) goto out_unref; - memset_io(fbptr, 0xff, aligned_size); + memset_io(fbptr, 0x0, aligned_size); strcpy(info->fix.id, "radeondrmfb"); diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c index d72a71bff218..f1da370928eb 100644 --- a/drivers/gpu/drm/radeon/radeon_object.c +++ b/drivers/gpu/drm/radeon/radeon_object.c @@ -306,11 +306,10 @@ void radeon_bo_list_unreserve(struct list_head *head) } } -int radeon_bo_list_validate(struct list_head *head, void *fence) +int radeon_bo_list_validate(struct list_head *head) { struct radeon_bo_list *lobj; struct radeon_bo *bo; - struct radeon_fence *old_fence = NULL; int r; r = radeon_bo_list_reserve(head); @@ -334,32 +333,27 @@ int radeon_bo_list_validate(struct list_head *head, void *fence) } lobj->gpu_offset = radeon_bo_gpu_offset(bo); lobj->tiling_flags = bo->tiling_flags; - if (fence) { - old_fence = (struct radeon_fence *)bo->tbo.sync_obj; - bo->tbo.sync_obj = radeon_fence_ref(fence); - bo->tbo.sync_obj_arg = NULL; - } - if (old_fence) { - radeon_fence_unref(&old_fence); - } } return 0; } -void radeon_bo_list_unvalidate(struct list_head *head, void *fence) +void radeon_bo_list_fence(struct list_head *head, void *fence) { struct radeon_bo_list *lobj; - struct radeon_fence *old_fence; - - if (fence) - list_for_each_entry(lobj, head, list) { - old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj); - if (old_fence == fence) { - lobj->bo->tbo.sync_obj = NULL; - radeon_fence_unref(&old_fence); - } + struct radeon_bo *bo; + struct radeon_fence *old_fence = NULL; + + list_for_each_entry(lobj, head, list) { + bo = lobj->bo; + spin_lock(&bo->tbo.lock); + old_fence = (struct radeon_fence *)bo->tbo.sync_obj; + bo->tbo.sync_obj = radeon_fence_ref(fence); + bo->tbo.sync_obj_arg = NULL; + spin_unlock(&bo->tbo.lock); + if (old_fence) { + radeon_fence_unref(&old_fence); } - radeon_bo_list_unreserve(head); + } } int radeon_bo_fbdev_mmap(struct radeon_bo *bo, diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h index a02f18011ad1..7ab43de1e244 100644 --- a/drivers/gpu/drm/radeon/radeon_object.h +++ b/drivers/gpu/drm/radeon/radeon_object.h @@ -156,8 +156,8 @@ extern void radeon_bo_list_add_object(struct radeon_bo_list *lobj, struct list_head *head); extern int radeon_bo_list_reserve(struct list_head *head); extern void radeon_bo_list_unreserve(struct list_head *head); -extern int radeon_bo_list_validate(struct list_head *head, void *fence); -extern void radeon_bo_list_unvalidate(struct list_head *head, void *fence); +extern int radeon_bo_list_validate(struct list_head *head); +extern void radeon_bo_list_fence(struct list_head *head, void *fence); extern int radeon_bo_fbdev_mmap(struct radeon_bo *bo, struct vm_area_struct *vma); extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo, diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 4d12b2d17b4d..694799f6fac1 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c @@ -41,68 +41,55 @@ int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) { struct radeon_fence *fence; struct radeon_ib *nib; - unsigned long i; - int r = 0; + int r = 0, i, c; *ib = NULL; r = radeon_fence_create(rdev, &fence); if (r) { - DRM_ERROR("failed to create fence for new IB\n"); + dev_err(rdev->dev, "failed to create fence for new IB\n"); return r; } mutex_lock(&rdev->ib_pool.mutex); - i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); - if (i < RADEON_IB_POOL_SIZE) { - set_bit(i, rdev->ib_pool.alloc_bm); - rdev->ib_pool.ibs[i].length_dw = 0; - *ib = &rdev->ib_pool.ibs[i]; - mutex_unlock(&rdev->ib_pool.mutex); - goto out; + for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) { + i &= (RADEON_IB_POOL_SIZE - 1); + if (rdev->ib_pool.ibs[i].free) { + nib = &rdev->ib_pool.ibs[i]; + break; + } } - if (list_empty(&rdev->ib_pool.scheduled_ibs)) { - /* we go do nothings here */ + if (nib == NULL) { + /* This should never happen, it means we allocated all + * IB and haven't scheduled one yet, return EBUSY to + * userspace hoping that on ioctl recall we get better + * luck + */ + dev_err(rdev->dev, "no free indirect buffer !\n"); mutex_unlock(&rdev->ib_pool.mutex); - DRM_ERROR("all IB allocated none scheduled.\n"); - r = -EINVAL; - goto out; + radeon_fence_unref(&fence); + return -EBUSY; } - /* get the first ib on the scheduled list */ - nib = list_entry(rdev->ib_pool.scheduled_ibs.next, - struct radeon_ib, list); - if (nib->fence == NULL) { - /* we go do nothings here */ + rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1); + nib->free = false; + if (nib->fence) { mutex_unlock(&rdev->ib_pool.mutex); - DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx); - r = -EINVAL; - goto out; - } - mutex_unlock(&rdev->ib_pool.mutex); - - r = radeon_fence_wait(nib->fence, false); - if (r) { - DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx, - (unsigned long)nib->gpu_addr, nib->length_dw); - DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n"); - goto out; + r = radeon_fence_wait(nib->fence, false); + if (r) { + dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n", + nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw); + mutex_lock(&rdev->ib_pool.mutex); + nib->free = true; + mutex_unlock(&rdev->ib_pool.mutex); + radeon_fence_unref(&fence); + return r; + } + mutex_lock(&rdev->ib_pool.mutex); } radeon_fence_unref(&nib->fence); - + nib->fence = fence; nib->length_dw = 0; - - /* scheduled list is accessed here */ - mutex_lock(&rdev->ib_pool.mutex); - list_del(&nib->list); - INIT_LIST_HEAD(&nib->list); mutex_unlock(&rdev->ib_pool.mutex); - *ib = nib; -out: - if (r) { - radeon_fence_unref(&fence); - } else { - (*ib)->fence = fence; - } - return r; + return 0; } void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) @@ -114,18 +101,7 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) return; } mutex_lock(&rdev->ib_pool.mutex); - if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) { - /* IB is scheduled & not signaled don't do anythings */ - mutex_unlock(&rdev->ib_pool.mutex); - return; - } - list_del(&tmp->list); - INIT_LIST_HEAD(&tmp->list); - if (tmp->fence) - radeon_fence_unref(&tmp->fence); - - tmp->length_dw = 0; - clear_bit(tmp->idx, rdev->ib_pool.alloc_bm); + tmp->free = true; mutex_unlock(&rdev->ib_pool.mutex); } @@ -135,7 +111,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) if (!ib->length_dw || !rdev->cp.ready) { /* TODO: Nothings in the ib we should report. */ - DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); + DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx); return -EINVAL; } @@ -148,7 +124,8 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) radeon_ring_ib_execute(rdev, ib); radeon_fence_emit(rdev, ib->fence); mutex_lock(&rdev->ib_pool.mutex); - list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); + /* once scheduled IB is considered free and protected by the fence */ + ib->free = true; mutex_unlock(&rdev->ib_pool.mutex); radeon_ring_unlock_commit(rdev); return 0; @@ -164,7 +141,6 @@ int radeon_ib_pool_init(struct radeon_device *rdev) if (rdev->ib_pool.robj) return 0; /* Allocate 1M object buffer */ - INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, true, RADEON_GEM_DOMAIN_GTT, &rdev->ib_pool.robj); @@ -195,9 +171,9 @@ int radeon_ib_pool_init(struct radeon_device *rdev) rdev->ib_pool.ibs[i].ptr = ptr + offset; rdev->ib_pool.ibs[i].idx = i; rdev->ib_pool.ibs[i].length_dw = 0; - INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list); + rdev->ib_pool.ibs[i].free = true; } - bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); + rdev->ib_pool.head_id = 0; rdev->ib_pool.ready = true; DRM_INFO("radeon: ib pool ready.\n"); if (radeon_debugfs_ib_init(rdev)) { @@ -214,7 +190,6 @@ void radeon_ib_pool_fini(struct radeon_device *rdev) return; } mutex_lock(&rdev->ib_pool.mutex); - bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); if (rdev->ib_pool.robj) { r = radeon_bo_reserve(rdev->ib_pool.robj, false); if (likely(r == 0)) { @@ -363,7 +338,7 @@ static int radeon_debugfs_ib_info(struct seq_file *m, void *data) if (ib == NULL) { return 0; } - seq_printf(m, "IB %04lu\n", ib->idx); + seq_printf(m, "IB %04u\n", ib->idx); seq_printf(m, "IB fence %p\n", ib->fence); seq_printf(m, "IB size %05u dwords\n", ib->length_dw); for (i = 0; i < ib->length_dw; i++) { diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 1a3e909b7bba..c7320ce4567d 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1020,6 +1020,12 @@ static int ttm_bo_mem_compat(struct ttm_placement *placement, struct ttm_mem_reg *mem) { int i; + struct drm_mm_node *node = mem->mm_node; + + if (node && placement->lpfn != 0 && + (node->start < placement->fpfn || + node->start + node->size > placement->lpfn)) + return -1; for (i = 0; i < placement->num_placement; i++) { if ((placement->placement[i] & mem->placement & diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c index a6e8f687fa64..0c9c0811f42d 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c @@ -348,22 +348,19 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) */ DRM_INFO("It appears like vesafb is loaded. " - "Ignore above error if any. Entering stealth mode.\n"); + "Ignore above error if any.\n"); ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); if (unlikely(ret != 0)) { DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); goto out_no_device; } - vmw_kms_init(dev_priv); - vmw_overlay_init(dev_priv); - } else { - ret = vmw_request_device(dev_priv); - if (unlikely(ret != 0)) - goto out_no_device; - vmw_kms_init(dev_priv); - vmw_overlay_init(dev_priv); - vmw_fb_init(dev_priv); } + ret = vmw_request_device(dev_priv); + if (unlikely(ret != 0)) + goto out_no_device; + vmw_kms_init(dev_priv); + vmw_overlay_init(dev_priv); + vmw_fb_init(dev_priv); dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; register_pm_notifier(&dev_priv->pm_nb); @@ -406,17 +403,15 @@ static int vmw_driver_unload(struct drm_device *dev) unregister_pm_notifier(&dev_priv->pm_nb); - if (!dev_priv->stealth) { - vmw_fb_close(dev_priv); - vmw_kms_close(dev_priv); - vmw_overlay_close(dev_priv); - vmw_release_device(dev_priv); - pci_release_regions(dev->pdev); - } else { - vmw_kms_close(dev_priv); - vmw_overlay_close(dev_priv); + vmw_fb_close(dev_priv); + vmw_kms_close(dev_priv); + vmw_overlay_close(dev_priv); + vmw_release_device(dev_priv); + if (dev_priv->stealth) pci_release_region(dev->pdev, 2); - } + else + pci_release_regions(dev->pdev); + if (dev_priv->capabilities & SVGA_CAP_IRQMASK) drm_irq_uninstall(dev_priv->dev); if (dev->devname == vmw_devname) @@ -585,11 +580,6 @@ static int vmw_master_set(struct drm_device *dev, int ret = 0; DRM_INFO("Master set.\n"); - if (dev_priv->stealth) { - ret = vmw_request_device(dev_priv); - if (unlikely(ret != 0)) - return ret; - } if (active) { BUG_ON(active != &dev_priv->fbdev_master); @@ -649,18 +639,11 @@ static void vmw_master_drop(struct drm_device *dev, ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); - if (dev_priv->stealth) { - ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); - if (unlikely(ret != 0)) - DRM_ERROR("Unable to clean VRAM on master drop.\n"); - vmw_release_device(dev_priv); - } dev_priv->active_master = &dev_priv->fbdev_master; ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); ttm_vt_unlock(&dev_priv->fbdev_master.lock); - if (!dev_priv->stealth) - vmw_fb_on(dev_priv); + vmw_fb_on(dev_priv); } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h index 135be9688c90..356dc935ec13 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h @@ -39,10 +39,10 @@ #include "ttm/ttm_execbuf_util.h" #include "ttm/ttm_module.h" -#define VMWGFX_DRIVER_DATE "20090724" -#define VMWGFX_DRIVER_MAJOR 0 -#define VMWGFX_DRIVER_MINOR 1 -#define VMWGFX_DRIVER_PATCHLEVEL 2 +#define VMWGFX_DRIVER_DATE "20100209" +#define VMWGFX_DRIVER_MAJOR 1 +#define VMWGFX_DRIVER_MINOR 0 +#define VMWGFX_DRIVER_PATCHLEVEL 0 #define VMWGFX_FILE_PAGE_OFFSET 0x00100000 #define VMWGFX_FIFO_STATIC_SIZE (1024*1024) #define VMWGFX_MAX_RELOCATIONS 2048 @@ -113,6 +113,7 @@ struct vmw_fifo_state { unsigned long static_buffer_size; bool using_bounce_buffer; uint32_t capabilities; + struct mutex fifo_mutex; struct rw_semaphore rwsem; }; @@ -213,7 +214,7 @@ struct vmw_private { * Fencing and IRQs. */ - uint32_t fence_seq; + atomic_t fence_seq; wait_queue_head_t fence_queue; wait_queue_head_t fifo_queue; atomic_t fence_queue_waiters; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c index 4f4f6432be8b..a93367041cdc 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c @@ -559,6 +559,9 @@ int vmw_fb_init(struct vmw_private *vmw_priv) info->pixmap.scan_align = 1; #endif + info->aperture_base = vmw_priv->vram_start; + info->aperture_size = vmw_priv->vram_size; + /* * Dirty & Deferred IO */ diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c index 4157547cc6e4..39d43a01d846 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c @@ -74,6 +74,7 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) fifo->reserved_size = 0; fifo->using_bounce_buffer = false; + mutex_init(&fifo->fifo_mutex); init_rwsem(&fifo->rwsem); /* @@ -117,7 +118,7 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) (unsigned int) min, (unsigned int) fifo->capabilities); - dev_priv->fence_seq = dev_priv->last_read_sequence; + atomic_set(&dev_priv->fence_seq, dev_priv->last_read_sequence); iowrite32(dev_priv->last_read_sequence, fifo_mem + SVGA_FIFO_FENCE); return vmw_fifo_send_fence(dev_priv, &dummy); @@ -283,7 +284,7 @@ void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; int ret; - down_write(&fifo_state->rwsem); + mutex_lock(&fifo_state->fifo_mutex); max = ioread32(fifo_mem + SVGA_FIFO_MAX); min = ioread32(fifo_mem + SVGA_FIFO_MIN); next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); @@ -351,7 +352,7 @@ void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) } out_err: fifo_state->reserved_size = 0; - up_write(&fifo_state->rwsem); + mutex_unlock(&fifo_state->fifo_mutex); return NULL; } @@ -426,6 +427,7 @@ void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) } + down_write(&fifo_state->rwsem); if (fifo_state->using_bounce_buffer || reserveable) { next_cmd += bytes; if (next_cmd >= max) @@ -437,8 +439,9 @@ void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) if (reserveable) iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); mb(); - vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); up_write(&fifo_state->rwsem); + vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); + mutex_unlock(&fifo_state->fifo_mutex); } int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence) @@ -451,9 +454,7 @@ int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence) fm = vmw_fifo_reserve(dev_priv, bytes); if (unlikely(fm == NULL)) { - down_write(&fifo_state->rwsem); - *sequence = dev_priv->fence_seq; - up_write(&fifo_state->rwsem); + *sequence = atomic_read(&dev_priv->fence_seq); ret = -ENOMEM; (void)vmw_fallback_wait(dev_priv, false, true, *sequence, false, 3*HZ); @@ -461,7 +462,7 @@ int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *sequence) } do { - *sequence = dev_priv->fence_seq++; + *sequence = atomic_add_return(1, &dev_priv->fence_seq); } while (*sequence == 0); if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) { diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c index 778851f9f1d6..1c7a316454d8 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c @@ -48,6 +48,12 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data, case DRM_VMW_PARAM_FIFO_OFFSET: param->value = dev_priv->mmio_start; break; + case DRM_VMW_PARAM_HW_CAPS: + param->value = dev_priv->capabilities; + break; + case DRM_VMW_PARAM_FIFO_CAPS: + param->value = dev_priv->fifo.capabilities; + break; default: DRM_ERROR("Illegal vmwgfx get param request: %d\n", param->param); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c index d40086fc8647..4d7cb5393860 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c @@ -85,19 +85,12 @@ bool vmw_fence_signaled(struct vmw_private *dev_priv, return true; /** - * Below is to signal stale fences that have wrapped. - * First, block fence submission. - */ - - down_read(&fifo_state->rwsem); - - /** * Then check if the sequence is higher than what we've actually * emitted. Then the fence is stale and signaled. */ - ret = ((dev_priv->fence_seq - sequence) > VMW_FENCE_WRAP); - up_read(&fifo_state->rwsem); + ret = ((atomic_read(&dev_priv->fence_seq) - sequence) + > VMW_FENCE_WRAP); return ret; } @@ -127,7 +120,7 @@ int vmw_fallback_wait(struct vmw_private *dev_priv, if (fifo_idle) down_read(&fifo_state->rwsem); - signal_seq = dev_priv->fence_seq; + signal_seq = atomic_read(&dev_priv->fence_seq); ret = 0; for (;;) { diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index eeba6d1d06e4..31f9afed0a63 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -769,10 +769,10 @@ int vmw_kms_init(struct vmw_private *dev_priv) drm_mode_config_init(dev); dev->mode_config.funcs = &vmw_kms_funcs; - dev->mode_config.min_width = 640; - dev->mode_config.min_height = 480; - dev->mode_config.max_width = 2048; - dev->mode_config.max_height = 2048; + dev->mode_config.min_width = 1; + dev->mode_config.min_height = 1; + dev->mode_config.max_width = dev_priv->fb_max_width; + dev->mode_config.max_height = dev_priv->fb_max_height; ret = vmw_kms_init_legacy_display_system(dev_priv); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c index c7efbd47ab84..f8fbbc67a406 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c @@ -35,11 +35,6 @@ #define VMW_RES_SURFACE ttm_driver_type1 #define VMW_RES_STREAM ttm_driver_type2 -/* XXX: This isn't a real hardware flag, but just a hack for kernel to - * know about primary surfaces. Find a better way to accomplish this. - */ -#define SVGA3D_SURFACE_HINT_SCANOUT (1 << 9) - struct vmw_user_context { struct ttm_base_object base; struct vmw_resource res; @@ -579,6 +574,7 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data, srf->flags = req->flags; srf->format = req->format; + srf->scanout = req->scanout; memcpy(srf->mip_levels, req->mip_levels, sizeof(srf->mip_levels)); srf->num_sizes = 0; for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i) @@ -604,16 +600,6 @@ int vmw_surface_define_ioctl(struct drm_device *dev, void *data, if (unlikely(ret != 0)) goto out_err1; - if (srf->flags & SVGA3D_SURFACE_HINT_SCANOUT) { - /* we should not send this flag down to hardware since - * its not a official one - */ - srf->flags &= ~SVGA3D_SURFACE_HINT_SCANOUT; - srf->scanout = true; - } else { - srf->scanout = false; - } - if (srf->scanout && srf->num_sizes == 1 && srf->sizes[0].width == 64 && diff --git a/drivers/gpu/vga/vgaarb.c b/drivers/gpu/vga/vgaarb.c index 1ac0c93603c9..24b56dc54597 100644 --- a/drivers/gpu/vga/vgaarb.c +++ b/drivers/gpu/vga/vgaarb.c @@ -961,7 +961,7 @@ static ssize_t vga_arb_write(struct file *file, const char __user * buf, remaining -= 7; pr_devel("client 0x%p called 'target'\n", priv); /* if target is default */ - if (!strncmp(buf, "default", 7)) + if (!strncmp(kbuf, "default", 7)) pdev = pci_dev_get(vga_default_device()); else { if (!vga_pci_str_to_vars(curr_pos, remaining, diff --git a/drivers/i2c/busses/i2c-tiny-usb.c b/drivers/i2c/busses/i2c-tiny-usb.c index b1c050ff311d..e29b6d5ba8ef 100644 --- a/drivers/i2c/busses/i2c-tiny-usb.c +++ b/drivers/i2c/busses/i2c-tiny-usb.c @@ -13,6 +13,7 @@ #include <linux/kernel.h> #include <linux/errno.h> #include <linux/module.h> +#include <linux/types.h> /* include interfaces to usb layer */ #include <linux/usb.h> @@ -31,8 +32,8 @@ #define CMD_I2C_IO_END (1<<1) /* i2c bit delay, default is 10us -> 100kHz */ -static int delay = 10; -module_param(delay, int, 0); +static unsigned short delay = 10; +module_param(delay, ushort, 0); MODULE_PARM_DESC(delay, "bit delay in microseconds, " "e.g. 10 for 100kHz (default is 100kHz)"); @@ -109,7 +110,7 @@ static int usb_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) static u32 usb_func(struct i2c_adapter *adapter) { - u32 func; + __le32 func; /* get functionality from adapter */ if (usb_read(adapter, CMD_GET_FUNC, 0, 0, &func, sizeof(func)) != @@ -118,7 +119,7 @@ static u32 usb_func(struct i2c_adapter *adapter) return 0; } - return func; + return le32_to_cpu(func); } /* This is the actual algorithm we define */ @@ -216,8 +217,7 @@ static int i2c_tiny_usb_probe(struct usb_interface *interface, "i2c-tiny-usb at bus %03d device %03d", dev->usb_dev->bus->busnum, dev->usb_dev->devnum); - if (usb_write(&dev->adapter, CMD_SET_DELAY, - cpu_to_le16(delay), 0, NULL, 0) != 0) { + if (usb_write(&dev->adapter, CMD_SET_DELAY, delay, 0, NULL, 0) != 0) { dev_err(&dev->adapter.dev, "failure setting delay to %dus\n", delay); retval = -EIO; diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c index cc9b5940fa97..875e34e0b235 100644 --- a/drivers/infiniband/core/cma.c +++ b/drivers/infiniband/core/cma.c @@ -2115,9 +2115,7 @@ int rdma_bind_addr(struct rdma_cm_id *id, struct sockaddr *addr) if (ret) goto err1; - if (cma_loopback_addr(addr)) { - ret = cma_bind_loopback(id_priv); - } else if (!cma_zero_addr(addr)) { + if (!cma_any_addr(addr)) { ret = rdma_translate_ip(addr, &id->route.addr.dev_addr); if (ret) goto err1; diff --git a/drivers/input/keyboard/locomokbd.c b/drivers/input/keyboard/locomokbd.c index 9caed30f3bbb..b1ab29861e1c 100644 --- a/drivers/input/keyboard/locomokbd.c +++ b/drivers/input/keyboard/locomokbd.c @@ -192,11 +192,18 @@ static void locomokbd_scankeyboard(struct locomokbd *locomokbd) static irqreturn_t locomokbd_interrupt(int irq, void *dev_id) { struct locomokbd *locomokbd = dev_id; + u16 r; + + r = locomo_readl(locomokbd->base + LOCOMO_KIC); + if ((r & 0x0001) == 0) + return IRQ_HANDLED; + + locomo_writel(r & ~0x0100, locomokbd->base + LOCOMO_KIC); /* Ack */ + /** wait chattering delay **/ udelay(100); locomokbd_scankeyboard(locomokbd); - return IRQ_HANDLED; } @@ -210,6 +217,25 @@ static void locomokbd_timer_callback(unsigned long data) locomokbd_scankeyboard(locomokbd); } +static int locomokbd_open(struct input_dev *dev) +{ + struct locomokbd *locomokbd = input_get_drvdata(dev); + u16 r; + + r = locomo_readl(locomokbd->base + LOCOMO_KIC) | 0x0010; + locomo_writel(r, locomokbd->base + LOCOMO_KIC); + return 0; +} + +static void locomokbd_close(struct input_dev *dev) +{ + struct locomokbd *locomokbd = input_get_drvdata(dev); + u16 r; + + r = locomo_readl(locomokbd->base + LOCOMO_KIC) & ~0x0010; + locomo_writel(r, locomokbd->base + LOCOMO_KIC); +} + static int __devinit locomokbd_probe(struct locomo_dev *dev) { struct locomokbd *locomokbd; @@ -253,6 +279,8 @@ static int __devinit locomokbd_probe(struct locomo_dev *dev) input_dev->id.vendor = 0x0001; input_dev->id.product = 0x0001; input_dev->id.version = 0x0100; + input_dev->open = locomokbd_open; + input_dev->close = locomokbd_close; input_dev->dev.parent = &dev->dev; input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP) | @@ -261,6 +289,8 @@ static int __devinit locomokbd_probe(struct locomo_dev *dev) input_dev->keycodesize = sizeof(locomokbd_keycode[0]); input_dev->keycodemax = ARRAY_SIZE(locomokbd_keycode); + input_set_drvdata(input_dev, locomokbd); + memcpy(locomokbd->keycode, locomokbd_keycode, sizeof(locomokbd->keycode)); for (i = 0; i < LOCOMOKBD_NUMKEYS; i++) set_bit(locomokbd->keycode[i], input_dev->keybit); diff --git a/drivers/input/mouse/psmouse-base.c b/drivers/input/mouse/psmouse-base.c index 9774bdfaa482..d8c0c8d6992c 100644 --- a/drivers/input/mouse/psmouse-base.c +++ b/drivers/input/mouse/psmouse-base.c @@ -1141,7 +1141,14 @@ static void psmouse_cleanup(struct serio *serio) psmouse_deactivate(parent); } - psmouse_deactivate(psmouse); + psmouse_set_state(psmouse, PSMOUSE_INITIALIZING); + + /* + * Disable stream mode so cleanup routine can proceed undisturbed. + */ + if (ps2_command(&psmouse->ps2dev, NULL, PSMOUSE_CMD_DISABLE)) + printk(KERN_WARNING "psmouse.c: Failed to disable mouse on %s\n", + psmouse->ps2dev.serio->phys); if (psmouse->cleanup) psmouse->cleanup(psmouse); diff --git a/drivers/input/serio/i8042.c b/drivers/input/serio/i8042.c index d84a36e545f6..b54aee7cd9e3 100644 --- a/drivers/input/serio/i8042.c +++ b/drivers/input/serio/i8042.c @@ -1161,9 +1161,17 @@ static int i8042_pm_restore(struct device *dev) return 0; } +static int i8042_pm_thaw(struct device *dev) +{ + i8042_interrupt(0, NULL); + + return 0; +} + static const struct dev_pm_ops i8042_pm_ops = { .suspend = i8042_pm_reset, .resume = i8042_pm_restore, + .thaw = i8042_pm_thaw, .poweroff = i8042_pm_reset, .restore = i8042_pm_restore, }; diff --git a/drivers/md/dm-log-userspace-transfer.c b/drivers/md/dm-log-userspace-transfer.c index 54abf9e303b7..f1c8cae70b4b 100644 --- a/drivers/md/dm-log-userspace-transfer.c +++ b/drivers/md/dm-log-userspace-transfer.c @@ -172,11 +172,15 @@ int dm_consult_userspace(const char *uuid, uint64_t luid, int request_type, { int r = 0; size_t dummy = 0; - int overhead_size = - sizeof(struct dm_ulog_request *) + sizeof(struct cn_msg); + int overhead_size = sizeof(struct dm_ulog_request) + sizeof(struct cn_msg); struct dm_ulog_request *tfr = prealloced_ulog_tfr; struct receiving_pkg pkg; + /* + * Given the space needed to hold the 'struct cn_msg' and + * 'struct dm_ulog_request' - do we have enough payload + * space remaining? + */ if (data_size > (DM_ULOG_PREALLOCED_SIZE - overhead_size)) { DMINFO("Size of tfr exceeds preallocated size"); return -EINVAL; @@ -191,7 +195,7 @@ resend: */ mutex_lock(&dm_ulog_lock); - memset(tfr, 0, DM_ULOG_PREALLOCED_SIZE - overhead_size); + memset(tfr, 0, DM_ULOG_PREALLOCED_SIZE - sizeof(struct cn_msg)); memcpy(tfr->uuid, uuid, DM_UUID_LEN); tfr->luid = luid; tfr->seq = dm_ulog_seq++; diff --git a/drivers/md/dm-raid1.c b/drivers/md/dm-raid1.c index ad779bd13aec..6c1046df81f6 100644 --- a/drivers/md/dm-raid1.c +++ b/drivers/md/dm-raid1.c @@ -724,7 +724,7 @@ static void do_writes(struct mirror_set *ms, struct bio_list *writes) /* * Dispatch io. */ - if (unlikely(ms->log_failure)) { + if (unlikely(ms->log_failure) && errors_handled(ms)) { spin_lock_irq(&ms->lock); bio_list_merge(&ms->failures, &sync); spin_unlock_irq(&ms->lock); diff --git a/drivers/md/dm-region-hash.c b/drivers/md/dm-region-hash.c index 5f19ceb6fe91..168bd38f5006 100644 --- a/drivers/md/dm-region-hash.c +++ b/drivers/md/dm-region-hash.c @@ -660,10 +660,9 @@ void dm_rh_recovery_end(struct dm_region *reg, int success) spin_lock_irq(&rh->region_lock); if (success) list_add(®->list, ®->rh->recovered_regions); - else { - reg->state = DM_RH_NOSYNC; + else list_add(®->list, ®->rh->failed_recovered_regions); - } + spin_unlock_irq(&rh->region_lock); rh->wakeup_workers(rh->context); diff --git a/drivers/md/dm-snap-persistent.c b/drivers/md/dm-snap-persistent.c index 7d08879689ac..c097d8a4823d 100644 --- a/drivers/md/dm-snap-persistent.c +++ b/drivers/md/dm-snap-persistent.c @@ -254,7 +254,7 @@ static int chunk_io(struct pstore *ps, void *area, chunk_t chunk, int rw, * Issue the synchronous I/O from a different thread * to avoid generic_make_request recursion. */ - INIT_WORK(&req.work, do_metadata); + INIT_WORK_ON_STACK(&req.work, do_metadata); queue_work(ps->metadata_wq, &req.work); flush_workqueue(ps->metadata_wq); diff --git a/drivers/md/dm-stripe.c b/drivers/md/dm-stripe.c index e0efc1adcaff..bd58703ee8f6 100644 --- a/drivers/md/dm-stripe.c +++ b/drivers/md/dm-stripe.c @@ -110,7 +110,7 @@ static int stripe_ctr(struct dm_target *ti, unsigned int argc, char **argv) } stripes = simple_strtoul(argv[0], &end, 10); - if (*end) { + if (!stripes || *end) { ti->error = "Invalid stripe count"; return -EINVAL; } diff --git a/drivers/md/dm-sysfs.c b/drivers/md/dm-sysfs.c index f53392df7b97..f91b40942e07 100644 --- a/drivers/md/dm-sysfs.c +++ b/drivers/md/dm-sysfs.c @@ -80,20 +80,12 @@ static struct sysfs_ops dm_sysfs_ops = { }; /* - * The sysfs structure is embedded in md struct, nothing to do here - */ -static void dm_sysfs_release(struct kobject *kobj) -{ -} - -/* * dm kobject is embedded in mapped_device structure * no need to define release function here */ static struct kobj_type dm_ktype = { .sysfs_ops = &dm_sysfs_ops, .default_attrs = dm_attrs, - .release = dm_sysfs_release }; /* diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 3167480b532c..aa4e2aa86d49 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -1595,10 +1595,15 @@ static int dm_prep_fn(struct request_queue *q, struct request *rq) return BLKPREP_OK; } -static void map_request(struct dm_target *ti, struct request *clone, - struct mapped_device *md) +/* + * Returns: + * 0 : the request has been processed (not requeued) + * !0 : the request has been requeued + */ +static int map_request(struct dm_target *ti, struct request *clone, + struct mapped_device *md) { - int r; + int r, requeued = 0; struct dm_rq_target_io *tio = clone->end_io_data; /* @@ -1625,6 +1630,7 @@ static void map_request(struct dm_target *ti, struct request *clone, case DM_MAPIO_REQUEUE: /* The target wants to requeue the I/O */ dm_requeue_unmapped_request(clone); + requeued = 1; break; default: if (r > 0) { @@ -1636,6 +1642,8 @@ static void map_request(struct dm_target *ti, struct request *clone, dm_kill_unmapped_request(clone, r); break; } + + return requeued; } /* @@ -1677,12 +1685,17 @@ static void dm_request_fn(struct request_queue *q) atomic_inc(&md->pending[rq_data_dir(clone)]); spin_unlock(q->queue_lock); - map_request(ti, clone, md); + if (map_request(ti, clone, md)) + goto requeued; + spin_lock_irq(q->queue_lock); } goto out; +requeued: + spin_lock_irq(q->queue_lock); + plug_and_out: if (!elv_queue_empty(q)) /* Some requests still remain, retry later */ diff --git a/drivers/md/md.c b/drivers/md/md.c index dd3dfe42d5a9..a20a71e5efd3 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -4075,8 +4075,10 @@ static void mddev_delayed_delete(struct work_struct *ws) { mddev_t *mddev = container_of(ws, mddev_t, del_work); - if (mddev->private == &md_redundancy_group) { + if (mddev->private) { sysfs_remove_group(&mddev->kobj, &md_redundancy_group); + if (mddev->private != (void*)1) + sysfs_remove_group(&mddev->kobj, mddev->private); if (mddev->sysfs_action) sysfs_put(mddev->sysfs_action); mddev->sysfs_action = NULL; @@ -4287,10 +4289,7 @@ static int do_md_run(mddev_t * mddev) sysfs_notify_dirent(rdev->sysfs_state); } - md_probe(mddev->unit, NULL, NULL); disk = mddev->gendisk; - if (!disk) - return -ENOMEM; spin_lock(&pers_lock); pers = find_pers(mddev->level, mddev->clevel); @@ -4530,8 +4529,8 @@ static int do_md_stop(mddev_t * mddev, int mode, int is_open) mddev->queue->unplug_fn = NULL; mddev->queue->backing_dev_info.congested_fn = NULL; module_put(mddev->pers->owner); - if (mddev->pers->sync_request) - mddev->private = &md_redundancy_group; + if (mddev->pers->sync_request && mddev->private == NULL) + mddev->private = (void*)1; mddev->pers = NULL; /* tell userspace to handle 'inactive' */ sysfs_notify_dirent(mddev->sysfs_state); @@ -4578,9 +4577,6 @@ out: } mddev->bitmap_info.offset = 0; - /* make sure all md_delayed_delete calls have finished */ - flush_scheduled_work(); - export_array(mddev); mddev->array_sectors = 0; diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index e84204eb12df..ceb24afdc147 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -5136,9 +5136,8 @@ static int stop(mddev_t *mddev) mddev->thread = NULL; mddev->queue->backing_dev_info.congested_fn = NULL; blk_sync_queue(mddev->queue); /* the unplug fn references 'conf'*/ - sysfs_remove_group(&mddev->kobj, &raid5_attrs_group); free_conf(conf); - mddev->private = NULL; + mddev->private = &raid5_attrs_group; return 0; } @@ -5464,11 +5463,11 @@ static int raid5_start_reshape(mddev_t *mddev) !test_bit(Faulty, &rdev->flags)) { if (raid5_add_disk(mddev, rdev) == 0) { char nm[20]; - if (rdev->raid_disk >= conf->previous_raid_disks) + if (rdev->raid_disk >= conf->previous_raid_disks) { set_bit(In_sync, &rdev->flags); - else + added_devices++; + } else rdev->recovery_offset = 0; - added_devices++; sprintf(nm, "rd%d", rdev->raid_disk); if (sysfs_create_link(&mddev->kobj, &rdev->kobj, nm)) @@ -5480,9 +5479,12 @@ static int raid5_start_reshape(mddev_t *mddev) break; } + /* When a reshape changes the number of devices, ->degraded + * is measured against the large of the pre and post number of + * devices.*/ if (mddev->delta_disks > 0) { spin_lock_irqsave(&conf->device_lock, flags); - mddev->degraded = (conf->raid_disks - conf->previous_raid_disks) + mddev->degraded += (conf->raid_disks - conf->previous_raid_disks) - added_devices; spin_unlock_irqrestore(&conf->device_lock, flags); } diff --git a/drivers/media/dvb/dvb-core/dmxdev.c b/drivers/media/dvb/dvb-core/dmxdev.c index c37790ad92d0..9ddc57909d49 100644 --- a/drivers/media/dvb/dvb-core/dmxdev.c +++ b/drivers/media/dvb/dvb-core/dmxdev.c @@ -761,7 +761,6 @@ static int dvb_demux_open(struct inode *inode, struct file *file) dvb_ringbuffer_init(&dmxdevfilter->buffer, NULL, 8192); dmxdevfilter->type = DMXDEV_TYPE_NONE; dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_ALLOCATED); - INIT_LIST_HEAD(&dmxdevfilter->feed.ts); init_timer(&dmxdevfilter->timer); dvbdev->users++; @@ -887,6 +886,7 @@ static int dvb_dmxdev_pes_filter_set(struct dmxdev *dmxdev, dmxdevfilter->type = DMXDEV_TYPE_PES; memcpy(&dmxdevfilter->params, params, sizeof(struct dmx_pes_filter_params)); + INIT_LIST_HEAD(&dmxdevfilter->feed.ts); dvb_dmxdev_filter_state_set(dmxdevfilter, DMXDEV_STATE_SET); diff --git a/drivers/media/dvb/dvb-core/dvb_demux.c b/drivers/media/dvb/dvb-core/dvb_demux.c index b78cfb7d1897..67f189b7aa1f 100644 --- a/drivers/media/dvb/dvb-core/dvb_demux.c +++ b/drivers/media/dvb/dvb-core/dvb_demux.c @@ -426,16 +426,7 @@ static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf) }; }; - if (dvb_demux_tscheck) { - if (!demux->cnt_storage) - demux->cnt_storage = vmalloc(MAX_PID + 1); - - if (!demux->cnt_storage) { - printk(KERN_WARNING "Couldn't allocate memory for TS/TEI check. Disabling it\n"); - dvb_demux_tscheck = 0; - goto no_dvb_demux_tscheck; - } - + if (demux->cnt_storage) { /* check pkt counter */ if (pid < MAX_PID) { if (buf[1] & 0x80) @@ -454,7 +445,6 @@ static void dvb_dmx_swfilter_packet(struct dvb_demux *demux, const u8 *buf) }; /* end check */ }; -no_dvb_demux_tscheck: list_for_each_entry(feed, &demux->feed_list, list_head) { if ((feed->pid != pid) && (feed->pid != 0x2000)) @@ -1246,6 +1236,7 @@ int dvb_dmx_init(struct dvb_demux *dvbdemux) dvbdemux->feed = vmalloc(dvbdemux->feednum * sizeof(struct dvb_demux_feed)); if (!dvbdemux->feed) { vfree(dvbdemux->filter); + dvbdemux->filter = NULL; return -ENOMEM; } for (i = 0; i < dvbdemux->filternum; i++) { @@ -1257,6 +1248,13 @@ int dvb_dmx_init(struct dvb_demux *dvbdemux) dvbdemux->feed[i].index = i; } + if (dvb_demux_tscheck) { + dvbdemux->cnt_storage = vmalloc(MAX_PID + 1); + + if (!dvbdemux->cnt_storage) + printk(KERN_WARNING "Couldn't allocate memory for TS/TEI check. Disabling it\n"); + } + INIT_LIST_HEAD(&dvbdemux->frontend_list); for (i = 0; i < DMX_TS_PES_OTHER; i++) { diff --git a/drivers/message/fusion/mptscsih.c b/drivers/message/fusion/mptscsih.c index 57752751712b..81279b3d694c 100644 --- a/drivers/message/fusion/mptscsih.c +++ b/drivers/message/fusion/mptscsih.c @@ -1796,7 +1796,7 @@ mptscsih_abort(struct scsi_cmnd * SCpnt) dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "task abort: " "Command not in the active list! (sc=%p)\n", ioc->name, SCpnt)); - retval = 0; + retval = SUCCESS; goto out; } diff --git a/drivers/mmc/card/mmc_test.c b/drivers/mmc/card/mmc_test.c index b9f1e84897cc..e7f8027165e6 100644 --- a/drivers/mmc/card/mmc_test.c +++ b/drivers/mmc/card/mmc_test.c @@ -74,6 +74,9 @@ static void mmc_test_prepare_mrq(struct mmc_test_card *test, } mrq->cmd->arg = dev_addr; + if (!mmc_card_blockaddr(test->card)) + mrq->cmd->arg <<= 9; + mrq->cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; if (blocks == 1) @@ -190,7 +193,7 @@ static int __mmc_test_prepare(struct mmc_test_card *test, int write) } for (i = 0;i < BUFFER_SIZE / 512;i++) { - ret = mmc_test_buffer_transfer(test, test->buffer, i * 512, 512, 1); + ret = mmc_test_buffer_transfer(test, test->buffer, i, 512, 1); if (ret) return ret; } @@ -219,7 +222,7 @@ static int mmc_test_cleanup(struct mmc_test_card *test) memset(test->buffer, 0, 512); for (i = 0;i < BUFFER_SIZE / 512;i++) { - ret = mmc_test_buffer_transfer(test, test->buffer, i * 512, 512, 1); + ret = mmc_test_buffer_transfer(test, test->buffer, i, 512, 1); if (ret) return ret; } @@ -426,7 +429,7 @@ static int mmc_test_transfer(struct mmc_test_card *test, for (i = 0;i < sectors;i++) { ret = mmc_test_buffer_transfer(test, test->buffer + i * 512, - dev_addr + i * 512, 512, 0); + dev_addr + i, 512, 0); if (ret) return ret; } diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 677cd53f18c3..4f99274b24c2 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -444,7 +444,7 @@ config MTD_NAND_FSL_UPM config MTD_NAND_MXC tristate "MXC NAND support" - depends on ARCH_MX2 || ARCH_MX3 + depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 help This enables the driver for the NAND flash controller on the MXC processors. diff --git a/drivers/net/ax88796.c b/drivers/net/ax88796.c index 62d9c9cc5671..1dd4403247ca 100644 --- a/drivers/net/ax88796.c +++ b/drivers/net/ax88796.c @@ -921,7 +921,7 @@ static int ax_probe(struct platform_device *pdev) size = (res->end - res->start) + 1; ax->mem2 = request_mem_region(res->start, size, pdev->name); - if (ax->mem == NULL) { + if (ax->mem2 == NULL) { dev_err(&pdev->dev, "cannot reserve registers\n"); ret = -ENXIO; goto exit_mem1; diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c index fee6eee7ae5b..006cb2efcd22 100644 --- a/drivers/net/benet/be_cmds.c +++ b/drivers/net/benet/be_cmds.c @@ -296,6 +296,7 @@ static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, req_hdr->opcode = opcode; req_hdr->subsystem = subsystem; req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); + req_hdr->version = 0; } static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, diff --git a/drivers/net/cxgb3/sge.c b/drivers/net/cxgb3/sge.c index bdbd14727e4b..318a018ca7c5 100644 --- a/drivers/net/cxgb3/sge.c +++ b/drivers/net/cxgb3/sge.c @@ -2079,6 +2079,7 @@ static void lro_add_page(struct adapter *adap, struct sge_qset *qs, struct sge_fl *fl, int len, int complete) { struct rx_sw_desc *sd = &fl->sdesc[fl->cidx]; + struct port_info *pi = netdev_priv(qs->netdev); struct sk_buff *skb = NULL; struct cpl_rx_pkt *cpl; struct skb_frag_struct *rx_frag; @@ -2116,11 +2117,18 @@ static void lro_add_page(struct adapter *adap, struct sge_qset *qs, if (!nr_frags) { offset = 2 + sizeof(struct cpl_rx_pkt); - qs->lro_va = sd->pg_chunk.va + 2; - } - len -= offset; + cpl = qs->lro_va = sd->pg_chunk.va + 2; - prefetch(qs->lro_va); + if ((pi->rx_offload & T3_RX_CSUM) && + cpl->csum_valid && cpl->csum == htons(0xffff)) { + skb->ip_summed = CHECKSUM_UNNECESSARY; + qs->port_stats[SGE_PSTAT_RX_CSUM_GOOD]++; + } else + skb->ip_summed = CHECKSUM_NONE; + } else + cpl = qs->lro_va; + + len -= offset; rx_frag += nr_frags; rx_frag->page = sd->pg_chunk.page; @@ -2136,12 +2144,8 @@ static void lro_add_page(struct adapter *adap, struct sge_qset *qs, return; skb_record_rx_queue(skb, qs - &adap->sge.qs[0]); - skb->ip_summed = CHECKSUM_UNNECESSARY; - cpl = qs->lro_va; if (unlikely(cpl->vlan_valid)) { - struct net_device *dev = qs->netdev; - struct port_info *pi = netdev_priv(dev); struct vlan_group *grp = pi->vlan_grp; if (likely(grp != NULL)) { diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index 997124d2992a..c881347cb26d 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c @@ -421,6 +421,8 @@ static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; if (tx_queue > IGB_N0_QUEUE) msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; + if (!adapter->msix_entries && msix_vector == 0) + msixbm |= E1000_EIMS_OTHER; array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); q_vector->eims_value = msixbm; break; @@ -877,7 +879,6 @@ static int igb_request_irq(struct igb_adapter *adapter) { struct net_device *netdev = adapter->netdev; struct pci_dev *pdev = adapter->pdev; - struct e1000_hw *hw = &adapter->hw; int err = 0; if (adapter->msix_entries) { @@ -909,20 +910,7 @@ static int igb_request_irq(struct igb_adapter *adapter) igb_setup_all_tx_resources(adapter); igb_setup_all_rx_resources(adapter); } else { - switch (hw->mac.type) { - case e1000_82575: - wr32(E1000_MSIXBM(0), - (E1000_EICR_RX_QUEUE0 | - E1000_EICR_TX_QUEUE0 | - E1000_EIMS_OTHER)); - break; - case e1000_82580: - case e1000_82576: - wr32(E1000_IVAR0, E1000_IVAR_VALID); - break; - default: - break; - } + igb_assign_vector(adapter->q_vector[0], 0); } if (adapter->flags & IGB_FLAG_HAS_MSI) { @@ -1140,6 +1128,8 @@ int igb_up(struct igb_adapter *adapter) } if (adapter->msix_entries) igb_configure_msix(adapter); + else + igb_assign_vector(adapter->q_vector[0], 0); /* Clear any pending interrupts. */ rd32(E1000_ICR); diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c index 3103f4165311..35a06b47587b 100644 --- a/drivers/net/ixgbe/ixgbe_82598.c +++ b/drivers/net/ixgbe/ixgbe_82598.c @@ -357,12 +357,34 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num) u32 fctrl_reg; u32 rmcs_reg; u32 reg; + u32 link_speed = 0; + bool link_up; #ifdef CONFIG_DCB if (hw->fc.requested_mode == ixgbe_fc_pfc) goto out; #endif /* CONFIG_DCB */ + /* + * On 82598 having Rx FC on causes resets while doing 1G + * so if it's on turn it off once we know link_speed. For + * more details see 82598 Specification update. + */ + hw->mac.ops.check_link(hw, &link_speed, &link_up, false); + if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) { + switch (hw->fc.requested_mode) { + case ixgbe_fc_full: + hw->fc.requested_mode = ixgbe_fc_tx_pause; + break; + case ixgbe_fc_rx_pause: + hw->fc.requested_mode = ixgbe_fc_none; + break; + default: + /* no change */ + break; + } + } + /* Negotiate the fc mode to use */ ret_val = ixgbe_fc_autoneg(hw); if (ret_val) diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index b5f64ad67975..951b73cf5ca2 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c @@ -5179,7 +5179,7 @@ dma_error: ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info); } - return count; + return 0; } static void ixgbe_tx_queue(struct ixgbe_adapter *adapter, @@ -5329,8 +5329,11 @@ static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) struct ixgbe_adapter *adapter = netdev_priv(dev); int txq = smp_processor_id(); - if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) + if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { + while (unlikely(txq >= dev->real_num_tx_queues)) + txq -= dev->real_num_tx_queues; return txq; + } #ifdef IXGBE_FCOE if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && @@ -5760,6 +5763,10 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev, if (err) goto err_sw_init; + /* Make it possible the adapter to be woken up via WOL */ + if (adapter->hw.mac.type == ixgbe_mac_82599EB) + IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); + /* * If there is a fan on this device and it has failed log the * failure. diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c index 9f9d6081959b..24279e6e55f5 100644 --- a/drivers/net/netxen/netxen_nic_main.c +++ b/drivers/net/netxen/netxen_nic_main.c @@ -1941,7 +1941,7 @@ static void netxen_tx_timeout_task(struct work_struct *work) netif_wake_queue(adapter->netdev); clear_bit(__NX_RESETTING, &adapter->state); - + return; } else { clear_bit(__NX_RESETTING, &adapter->state); if (!netxen_nic_reset_context(adapter)) { @@ -2240,7 +2240,9 @@ netxen_detach_work(struct work_struct *work) netxen_nic_down(adapter, netdev); + rtnl_lock(); netxen_nic_detach(adapter); + rtnl_unlock(); status = NXRD32(adapter, NETXEN_PEG_HALT_STATUS1); diff --git a/drivers/net/sfc/efx.c b/drivers/net/sfc/efx.c index 103e8b0e2a0d..46997e177ee3 100644 --- a/drivers/net/sfc/efx.c +++ b/drivers/net/sfc/efx.c @@ -2284,6 +2284,7 @@ static int __devinit efx_pci_probe(struct pci_dev *pci_dev, fail2: efx_fini_struct(efx); fail1: + WARN_ON(rc > 0); EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); free_netdev(net_dev); return rc; diff --git a/drivers/net/sfc/qt202x_phy.c b/drivers/net/sfc/qt202x_phy.c index e0d13a451019..67eec7a6e487 100644 --- a/drivers/net/sfc/qt202x_phy.c +++ b/drivers/net/sfc/qt202x_phy.c @@ -320,7 +320,7 @@ static int qt202x_reset_phy(struct efx_nic *efx) falcon_board(efx)->type->init_phy(efx); - return rc; + return 0; fail: EFX_ERR(efx, "PHY reset timed out\n"); diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index d760650c5c04..67249c3c9f50 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c @@ -1025,11 +1025,8 @@ static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot) { struct sky2_tx_le *le = sky2->tx_le + *slot; - struct tx_ring_info *re = sky2->tx_ring + *slot; *slot = RING_NEXT(*slot, sky2->tx_ring_size); - re->flags = 0; - re->skb = NULL; le->ctrl = 0; return le; } @@ -1622,8 +1619,7 @@ static unsigned tx_le_req(const struct sk_buff *skb) return count; } -static void sky2_tx_unmap(struct pci_dev *pdev, - const struct tx_ring_info *re) +static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re) { if (re->flags & TX_MAP_SINGLE) pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), @@ -1633,6 +1629,7 @@ static void sky2_tx_unmap(struct pci_dev *pdev, pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr), pci_unmap_len(re, maplen), PCI_DMA_TODEVICE); + re->flags = 0; } /* @@ -1839,6 +1836,7 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done) dev->stats.tx_packets++; dev->stats.tx_bytes += skb->len; + re->skb = NULL; dev_kfree_skb_any(skb); sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size); diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c index c93f58f5c6f2..317aa34b21cf 100644 --- a/drivers/net/via-velocity.c +++ b/drivers/net/via-velocity.c @@ -1877,13 +1877,12 @@ static void velocity_error(struct velocity_info *vptr, int status) /** * tx_srv - transmit interrupt service * @vptr; Velocity - * @status: * * Scan the queues looking for transmitted packets that * we can complete and clean up. Update any statistics as * necessary/ */ -static int velocity_tx_srv(struct velocity_info *vptr, u32 status) +static int velocity_tx_srv(struct velocity_info *vptr) { struct tx_desc *td; int qnum; @@ -2090,14 +2089,12 @@ static int velocity_receive_frame(struct velocity_info *vptr, int idx) /** * velocity_rx_srv - service RX interrupt * @vptr: velocity - * @status: adapter status (unused) * * Walk the receive ring of the velocity adapter and remove * any received packets from the receive queue. Hand the ring * slots back to the adapter for reuse. */ -static int velocity_rx_srv(struct velocity_info *vptr, int status, - int budget_left) +static int velocity_rx_srv(struct velocity_info *vptr, int budget_left) { struct net_device_stats *stats = &vptr->dev->stats; int rd_curr = vptr->rx.curr; @@ -2151,32 +2148,24 @@ static int velocity_poll(struct napi_struct *napi, int budget) struct velocity_info *vptr = container_of(napi, struct velocity_info, napi); unsigned int rx_done; - u32 isr_status; - - spin_lock(&vptr->lock); - isr_status = mac_read_isr(vptr->mac_regs); - - /* Ack the interrupt */ - mac_write_isr(vptr->mac_regs, isr_status); - if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI))) - velocity_error(vptr, isr_status); + unsigned long flags; + spin_lock_irqsave(&vptr->lock, flags); /* * Do rx and tx twice for performance (taken from the VIA * out-of-tree driver). */ - rx_done = velocity_rx_srv(vptr, isr_status, budget / 2); - velocity_tx_srv(vptr, isr_status); - rx_done += velocity_rx_srv(vptr, isr_status, budget - rx_done); - velocity_tx_srv(vptr, isr_status); - - spin_unlock(&vptr->lock); + rx_done = velocity_rx_srv(vptr, budget / 2); + velocity_tx_srv(vptr); + rx_done += velocity_rx_srv(vptr, budget - rx_done); + velocity_tx_srv(vptr); /* If budget not fully consumed, exit the polling mode */ if (rx_done < budget) { napi_complete(napi); mac_enable_int(vptr->mac_regs); } + spin_unlock_irqrestore(&vptr->lock, flags); return rx_done; } @@ -2206,10 +2195,17 @@ static irqreturn_t velocity_intr(int irq, void *dev_instance) return IRQ_NONE; } + /* Ack the interrupt */ + mac_write_isr(vptr->mac_regs, isr_status); + if (likely(napi_schedule_prep(&vptr->napi))) { mac_disable_int(vptr->mac_regs); __napi_schedule(&vptr->napi); } + + if (isr_status & (~(ISR_PRXI | ISR_PPRXI | ISR_PTXI | ISR_PPTXI))) + velocity_error(vptr, isr_status); + spin_unlock(&vptr->lock); return IRQ_HANDLED; @@ -3100,7 +3096,7 @@ static int velocity_resume(struct pci_dev *pdev) velocity_init_registers(vptr, VELOCITY_INIT_WOL); mac_disable_int(vptr->mac_regs); - velocity_tx_srv(vptr, 0); + velocity_tx_srv(vptr); for (i = 0; i < vptr->tx.numq; i++) { if (vptr->tx.used[i]) @@ -3344,6 +3340,7 @@ static int velocity_set_coalesce(struct net_device *dev, { struct velocity_info *vptr = netdev_priv(dev); int max_us = 0x3f * 64; + unsigned long flags; /* 6 bits of */ if (ecmd->tx_coalesce_usecs > max_us) @@ -3365,6 +3362,7 @@ static int velocity_set_coalesce(struct net_device *dev, ecmd->tx_coalesce_usecs); /* Setup the interrupt suppression and queue timers */ + spin_lock_irqsave(&vptr->lock, flags); mac_disable_int(vptr->mac_regs); setup_adaptive_interrupts(vptr); setup_queue_timers(vptr); @@ -3372,6 +3370,7 @@ static int velocity_set_coalesce(struct net_device *dev, mac_write_int_mask(vptr->int_mask, vptr->mac_regs); mac_clear_isr(vptr->mac_regs); mac_enable_int(vptr->mac_regs); + spin_unlock_irqrestore(&vptr->lock, flags); return 0; } diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c index fa12b9060b0b..29bf33692f71 100644 --- a/drivers/net/wireless/ath/ath9k/xmit.c +++ b/drivers/net/wireless/ath/ath9k/xmit.c @@ -1615,7 +1615,7 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, bf->bf_frmlen -= padsize; } - if (conf_is_ht(&hw->conf) && !is_pae(skb)) + if (conf_is_ht(&hw->conf)) bf->bf_state.bf_type |= BUF_HT; bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); @@ -1701,7 +1701,7 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, goto tx_done; } - if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { + if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && !is_pae(skb)) { /* * Try aggregation if it's a unicast data frame * and the destination is HT capable. diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h index fe3bf9491997..c484cc253892 100644 --- a/drivers/net/wireless/b43/b43.h +++ b/drivers/net/wireless/b43/b43.h @@ -115,6 +115,7 @@ #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */ #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */ #define B43_MMIO_RNG 0x65A +#define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */ #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */ #define B43_MMIO_IFSCTL_USE_EDCF 0x0004 #define B43_MMIO_POWERUP_DELAY 0x6A8 diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c index 4c41cfe44f26..490fb45d1d05 100644 --- a/drivers/net/wireless/b43/main.c +++ b/drivers/net/wireless/b43/main.c @@ -628,10 +628,17 @@ static void b43_upload_card_macaddress(struct b43_wldev *dev) static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) { /* slot_time is in usec. */ - if (dev->phy.type != B43_PHYTYPE_G) + /* This test used to exit for all but a G PHY. */ + if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) return; - b43_write16(dev, 0x684, 510 + slot_time); - b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); + b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time); + /* Shared memory location 0x0010 is the slot time and should be + * set to slot_time; however, this register is initially 0 and changing + * the value adversely affects the transmit rate for BCM4311 + * devices. Until this behavior is unterstood, delete this step + * + * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); + */ } static void b43_short_slot_timing_enable(struct b43_wldev *dev) diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c index 5461f105bd2d..d10bea64fce3 100644 --- a/drivers/net/wireless/iwlwifi/iwl-core.c +++ b/drivers/net/wireless/iwlwifi/iwl-core.c @@ -2744,6 +2744,7 @@ int iwl_mac_config(struct ieee80211_hw *hw, u32 changed) if ((le16_to_cpu(priv->staging_rxon.channel) != ch)) priv->staging_rxon.flags = 0; + iwl_set_rxon_ht(priv, ht_conf); iwl_set_rxon_channel(priv, conf->channel); iwl_set_flags_for_band(priv, conf->channel->band); diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c index 6f36b6e79f5e..2dbce85404aa 100644 --- a/drivers/net/wireless/iwlwifi/iwl-rx.c +++ b/drivers/net/wireless/iwlwifi/iwl-rx.c @@ -928,7 +928,10 @@ static void iwl_pass_packet_to_mac80211(struct iwl_priv *priv, if (ieee80211_is_mgmt(fc) || ieee80211_has_protected(fc) || ieee80211_has_morefrags(fc) || - le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) + le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG || + (ieee80211_is_data_qos(fc) && + *ieee80211_get_qos_ctl(hdr) & + IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)) ret = skb_linearize(skb); else ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ? diff --git a/drivers/net/wireless/iwmc3200wifi/rx.c b/drivers/net/wireless/iwmc3200wifi/rx.c index 6d6ed7485175..f727b4a83196 100644 --- a/drivers/net/wireless/iwmc3200wifi/rx.c +++ b/drivers/net/wireless/iwmc3200wifi/rx.c @@ -794,7 +794,7 @@ static int iwm_mlme_update_bss_table(struct iwm_priv *iwm, u8 *buf, } bss->bss = kzalloc(bss_len, GFP_KERNEL); - if (!bss) { + if (!bss->bss) { kfree(bss); IWM_ERR(iwm, "Couldn't allocate bss\n"); return -ENOMEM; diff --git a/drivers/net/wireless/rtl818x/rtl8187_dev.c b/drivers/net/wireless/rtl818x/rtl8187_dev.c index bc5726dd5fe4..7ba3052b0708 100644 --- a/drivers/net/wireless/rtl818x/rtl8187_dev.c +++ b/drivers/net/wireless/rtl818x/rtl8187_dev.c @@ -65,6 +65,7 @@ static struct usb_device_id rtl8187_table[] __devinitdata = { /* Sitecom */ {USB_DEVICE(0x0df6, 0x000d), .driver_info = DEVICE_RTL8187}, {USB_DEVICE(0x0df6, 0x0028), .driver_info = DEVICE_RTL8187B}, + {USB_DEVICE(0x0df6, 0x0029), .driver_info = DEVICE_RTL8187B}, /* Sphairon Access Systems GmbH */ {USB_DEVICE(0x114B, 0x0150), .driver_info = DEVICE_RTL8187}, /* Dick Smith Electronics */ diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c index 8e952fdab764..cb2fd01eddae 100644 --- a/drivers/pci/hotplug/acpiphp_glue.c +++ b/drivers/pci/hotplug/acpiphp_glue.c @@ -720,12 +720,6 @@ static int acpiphp_bus_add(struct acpiphp_func *func) -ret_val); goto acpiphp_bus_add_out; } - /* - * try to start anyway. We could have failed to add - * simply because this bus had previously been added - * on another add. Don't bother with the return value - * we just keep going. - */ ret_val = acpi_bus_start(device); acpiphp_bus_add_out: diff --git a/drivers/pcmcia/sa1111_generic.c b/drivers/pcmcia/sa1111_generic.c index de6bc333d299..db79ca61cf96 100644 --- a/drivers/pcmcia/sa1111_generic.c +++ b/drivers/pcmcia/sa1111_generic.c @@ -21,11 +21,18 @@ #include "sa1111_generic.h" +#define IDX_IRQ_S0_READY_NINT (0) +#define IDX_IRQ_S0_CD_VALID (1) +#define IDX_IRQ_S0_BVD1_STSCHG (2) +#define IDX_IRQ_S1_READY_NINT (3) +#define IDX_IRQ_S1_CD_VALID (4) +#define IDX_IRQ_S1_BVD1_STSCHG (5) + static struct pcmcia_irqs irqs[] = { - { 0, IRQ_S0_CD_VALID, "SA1111 PCMCIA card detect" }, - { 0, IRQ_S0_BVD1_STSCHG, "SA1111 PCMCIA BVD1" }, - { 1, IRQ_S1_CD_VALID, "SA1111 CF card detect" }, - { 1, IRQ_S1_BVD1_STSCHG, "SA1111 CF BVD1" }, + { 0, NO_IRQ, "SA1111 PCMCIA card detect" }, + { 0, NO_IRQ, "SA1111 PCMCIA BVD1" }, + { 1, NO_IRQ, "SA1111 CF card detect" }, + { 1, NO_IRQ, "SA1111 CF BVD1" }, }; static int sa1111_pcmcia_hw_init(struct soc_pcmcia_socket *skt) @@ -136,7 +143,9 @@ int sa1111_pcmcia_add(struct sa1111_dev *dev, struct pcmcia_low_level *ops, s->soc.ops = ops; s->soc.socket.owner = ops->owner; s->soc.socket.dev.parent = &dev->dev; - s->soc.socket.pci_irq = s->soc.nr ? IRQ_S1_READY_NINT : IRQ_S0_READY_NINT; + s->soc.socket.pci_irq = s->soc.nr ? + dev->irq[IDX_IRQ_S0_READY_NINT] : + dev->irq[IDX_IRQ_S1_READY_NINT]; s->dev = dev; ret = add(&s->soc); @@ -162,6 +171,12 @@ static int pcmcia_probe(struct sa1111_dev *dev) base = dev->mapbase; + /* Initialize PCMCIA IRQs */ + irqs[0].irq = dev->irq[IDX_IRQ_S0_CD_VALID]; + irqs[1].irq = dev->irq[IDX_IRQ_S0_BVD1_STSCHG]; + irqs[2].irq = dev->irq[IDX_IRQ_S1_CD_VALID]; + irqs[3].irq = dev->irq[IDX_IRQ_S1_BVD1_STSCHG]; + /* * Initialise the suspend state. */ diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c index e67e4feb35cb..eb603f1d55ca 100644 --- a/drivers/platform/x86/thinkpad_acpi.c +++ b/drivers/platform/x86/thinkpad_acpi.c @@ -5771,7 +5771,7 @@ static void thermal_exit(void) case TPACPI_THERMAL_ACPI_TMP07: case TPACPI_THERMAL_ACPI_UPDT: sysfs_remove_group(&tpacpi_sensors_pdev->dev.kobj, - &thermal_temp_input16_group); + &thermal_temp_input8_group); break; case TPACPI_THERMAL_NONE: default: diff --git a/drivers/power/wm97xx_battery.c b/drivers/power/wm97xx_battery.c index fa39e759a275..6ea3cb5837c7 100644 --- a/drivers/power/wm97xx_battery.c +++ b/drivers/power/wm97xx_battery.c @@ -175,8 +175,14 @@ static int __devinit wm97xx_bat_probe(struct platform_device *dev) dev_err(&dev->dev, "Do not pass platform_data through " "wm97xx_bat_set_pdata!\n"); return -EINVAL; - } else - pdata = wmdata->batt_pdata; + } + + if (!wmdata) { + dev_err(&dev->dev, "No platform data supplied\n"); + return -EINVAL; + } + + pdata = wmdata->batt_pdata; if (dev->id != -1) return -EINVAL; diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 686ef270ecf7..b60a4c9f8f16 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -661,7 +661,7 @@ static int suspend_prepare(struct regulator_dev *rdev, suspend_state_t state) static void print_constraints(struct regulator_dev *rdev) { struct regulation_constraints *constraints = rdev->constraints; - char buf[80]; + char buf[80] = ""; int count = 0; int ret; diff --git a/drivers/regulator/lp3971.c b/drivers/regulator/lp3971.c index 76d08c282f9c..4f33a0f4a179 100644 --- a/drivers/regulator/lp3971.c +++ b/drivers/regulator/lp3971.c @@ -183,7 +183,7 @@ static int lp3971_ldo_set_voltage(struct regulator_dev *dev, if (vol_map[val] >= min_vol) break; - if (vol_map[val] > max_vol) + if (val > LDO_VOL_MAX_IDX || vol_map[val] > max_vol) return -EINVAL; return lp3971_set_bits(lp3971, LP3971_LDO_VOL_CONTR_REG(ldo), @@ -272,7 +272,7 @@ static int lp3971_dcdc_set_voltage(struct regulator_dev *dev, if (vol_map[val] >= min_vol) break; - if (vol_map[val] > max_vol) + if (val > BUCK_TARGET_VOL_MAX_IDX || vol_map[val] > max_vol) return -EINVAL; ret = lp3971_set_bits(lp3971, LP3971_BUCK_TARGET_VOL1_REG(buck), diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 999fe80c4051..62b654af9237 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -531,7 +531,7 @@ static inline int qdio_inbound_q_done(struct qdio_q *q) qdio_siga_sync_q(q); get_buf_state(q, q->first_to_check, &state, 0); - if (state == SLSB_P_INPUT_PRIMED) + if (state == SLSB_P_INPUT_PRIMED || state == SLSB_P_INPUT_ERROR) /* more work coming */ return 0; @@ -960,6 +960,8 @@ void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm, qdio_handle_activate_check(cdev, intparm, cstat, dstat); break; + case QDIO_IRQ_STATE_STOPPED: + break; default: WARN_ON(1); } diff --git a/drivers/s390/scsi/zfcp_fc.c b/drivers/s390/scsi/zfcp_fc.c index 0f7b493fb105..271399f62f1b 100644 --- a/drivers/s390/scsi/zfcp_fc.c +++ b/drivers/s390/scsi/zfcp_fc.c @@ -671,12 +671,11 @@ static void zfcp_fc_ct_els_job_handler(void *data) { struct fc_bsg_job *job = data; struct zfcp_fsf_ct_els *zfcp_ct_els = job->dd_data; - int status = zfcp_ct_els->status; - int reply_status; + struct fc_bsg_reply *jr = job->reply; - reply_status = status ? FC_CTELS_STATUS_REJECT : FC_CTELS_STATUS_OK; - job->reply->reply_data.ctels_reply.status = reply_status; - job->reply->reply_payload_rcv_len = job->reply_payload.payload_len; + jr->reply_payload_rcv_len = job->reply_payload.payload_len; + jr->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK; + jr->result = zfcp_ct_els->status ? -EIO : 0; job->job_done(job); } diff --git a/drivers/scsi/arm/fas216.c b/drivers/scsi/arm/fas216.c index 477542602284..9e71ac611146 100644 --- a/drivers/scsi/arm/fas216.c +++ b/drivers/scsi/arm/fas216.c @@ -2516,7 +2516,7 @@ int fas216_eh_device_reset(struct scsi_cmnd *SCpnt) if (info->scsi.phase == PHASE_IDLE) fas216_kick(info); - mod_timer(&info->eh_timer, 30 * HZ); + mod_timer(&info->eh_timer, jiffies + 30 * HZ); spin_unlock_irqrestore(&info->host_lock, flags); /* diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h index f61fb8d01330..8bc6f53691e9 100644 --- a/drivers/scsi/qla2xxx/qla_gbl.h +++ b/drivers/scsi/qla2xxx/qla_gbl.h @@ -453,6 +453,5 @@ extern void qla24xx_wrt_req_reg(struct qla_hw_data *, uint16_t, uint16_t); extern void qla25xx_wrt_req_reg(struct qla_hw_data *, uint16_t, uint16_t); extern void qla25xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t); extern void qla24xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t); -extern struct scsi_qla_host * qla25xx_get_host(struct rsp_que *); #endif /* _QLA_GBL_H */ diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index ffd0efdff40e..6fc63b98818c 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c @@ -1917,6 +1917,7 @@ qla24xx_msix_rsp_q(int irq, void *dev_id) struct rsp_que *rsp; struct device_reg_24xx __iomem *reg; struct scsi_qla_host *vha; + unsigned long flags; rsp = (struct rsp_que *) dev_id; if (!rsp) { @@ -1927,15 +1928,15 @@ qla24xx_msix_rsp_q(int irq, void *dev_id) ha = rsp->hw; reg = &ha->iobase->isp24; - spin_lock_irq(&ha->hardware_lock); + spin_lock_irqsave(&ha->hardware_lock, flags); - vha = qla25xx_get_host(rsp); + vha = pci_get_drvdata(ha->pdev); qla24xx_process_response_queue(vha, rsp); if (!ha->flags.disable_msix_handshake) { WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); RD_REG_DWORD_RELAXED(®->hccr); } - spin_unlock_irq(&ha->hardware_lock); + spin_unlock_irqrestore(&ha->hardware_lock, flags); return IRQ_HANDLED; } @@ -1946,6 +1947,7 @@ qla25xx_msix_rsp_q(int irq, void *dev_id) struct qla_hw_data *ha; struct rsp_que *rsp; struct device_reg_24xx __iomem *reg; + unsigned long flags; rsp = (struct rsp_que *) dev_id; if (!rsp) { @@ -1958,10 +1960,10 @@ qla25xx_msix_rsp_q(int irq, void *dev_id) /* Clear the interrupt, if enabled, for this response queue */ if (rsp->options & ~BIT_6) { reg = &ha->iobase->isp24; - spin_lock_irq(&ha->hardware_lock); + spin_lock_irqsave(&ha->hardware_lock, flags); WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); RD_REG_DWORD_RELAXED(®->hccr); - spin_unlock_irq(&ha->hardware_lock); + spin_unlock_irqrestore(&ha->hardware_lock, flags); } queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work); @@ -1979,6 +1981,7 @@ qla24xx_msix_default(int irq, void *dev_id) uint32_t stat; uint32_t hccr; uint16_t mb[4]; + unsigned long flags; rsp = (struct rsp_que *) dev_id; if (!rsp) { @@ -1990,7 +1993,7 @@ qla24xx_msix_default(int irq, void *dev_id) reg = &ha->iobase->isp24; status = 0; - spin_lock_irq(&ha->hardware_lock); + spin_lock_irqsave(&ha->hardware_lock, flags); vha = pci_get_drvdata(ha->pdev); do { stat = RD_REG_DWORD(®->host_status); @@ -2039,7 +2042,7 @@ qla24xx_msix_default(int irq, void *dev_id) } WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); } while (0); - spin_unlock_irq(&ha->hardware_lock); + spin_unlock_irqrestore(&ha->hardware_lock, flags); if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && (status & MBX_INTERRUPT) && ha->flags.mbox_int) { @@ -2277,30 +2280,3 @@ int qla25xx_request_irq(struct rsp_que *rsp) msix->rsp = rsp; return ret; } - -struct scsi_qla_host * -qla25xx_get_host(struct rsp_que *rsp) -{ - srb_t *sp; - struct qla_hw_data *ha = rsp->hw; - struct scsi_qla_host *vha = NULL; - struct sts_entry_24xx *pkt; - struct req_que *req; - uint16_t que; - uint32_t handle; - - pkt = (struct sts_entry_24xx *) rsp->ring_ptr; - que = MSW(pkt->handle); - handle = (uint32_t) LSW(pkt->handle); - req = ha->req_q_map[que]; - if (handle < MAX_OUTSTANDING_COMMANDS) { - sp = req->outstanding_cmds[handle]; - if (sp) - return sp->fcport->vha; - else - goto base_que; - } -base_que: - vha = pci_get_drvdata(ha->pdev); - return vha; -} diff --git a/drivers/scsi/qla2xxx/qla_mid.c b/drivers/scsi/qla2xxx/qla_mid.c index b901aa267e7d..ff17dee28613 100644 --- a/drivers/scsi/qla2xxx/qla_mid.c +++ b/drivers/scsi/qla2xxx/qla_mid.c @@ -636,13 +636,15 @@ failed: static void qla_do_work(struct work_struct *work) { + unsigned long flags; struct rsp_que *rsp = container_of(work, struct rsp_que, q_work); struct scsi_qla_host *vha; + struct qla_hw_data *ha = rsp->hw; - spin_lock_irq(&rsp->hw->hardware_lock); - vha = qla25xx_get_host(rsp); + spin_lock_irqsave(&rsp->hw->hardware_lock, flags); + vha = pci_get_drvdata(ha->pdev); qla24xx_process_response_queue(vha, rsp); - spin_unlock_irq(&rsp->hw->hardware_lock); + spin_unlock_irqrestore(&rsp->hw->hardware_lock, flags); } /* create response queue */ diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index c3e37c8e7e26..e9b15c3746fa 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c @@ -83,6 +83,9 @@ static unsigned int skip_txen_test; /* force skip of txen test at init time */ #define PASS_LIMIT 256 +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + + /* * We default to IRQ0 for the "no irq" hack. Some * machine types want others as well - they're free @@ -1792,7 +1795,7 @@ static unsigned int serial8250_tx_empty(struct uart_port *port) up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; spin_unlock_irqrestore(&up->port.lock, flags); - return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0; + return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; } static unsigned int serial8250_get_mctrl(struct uart_port *port) @@ -1850,8 +1853,6 @@ static void serial8250_break_ctl(struct uart_port *port, int break_state) spin_unlock_irqrestore(&up->port.lock, flags); } -#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) - /* * Wait for transmitter & holding register to empty */ diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 406ad918cbac..df62f4ea4f69 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -459,7 +459,7 @@ config SERIAL_SAMSUNG_UARTS int depends on ARM && PLAT_S3C default 2 if ARCH_S3C2400 - default 4 if ARCH_S5PC1XX || ARCH_S3C64XX || CPU_S3C2443 + default 4 if ARCH_S5P6440 || ARCH_S5PC1XX || ARCH_S5PV210 || ARCH_S3C64XX || CPU_S3C2443 default 3 help Select the number of available UART ports for the Samsung S3C @@ -526,11 +526,11 @@ config SERIAL_S3C24A0 Serial port support for the Samsung S3C24A0 SoC config SERIAL_S3C6400 - tristate "Samsung S3C6400/S3C6410 Serial port support" - depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410) + tristate "Samsung S3C6400/S3C6410/S5P6440 Serial port support" + depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440) default y help - Serial port support for the Samsung S3C6400 and S3C6410 + Serial port support for the Samsung S3C6400, S3C6410 and S5P6440 SoCs config SERIAL_S5PC100 @@ -540,6 +540,13 @@ config SERIAL_S5PC100 help Serial port support for the Samsung S5PC100 SoCs +config SERIAL_S5PV210 + tristate "Samsung S5PV210 Serial port support" + depends on SERIAL_SAMSUNG && CPU_S5PV210 + default y + help + Serial port support for Samsung's S5P Family of SoC's + config SERIAL_MAX3100 tristate "MAX3100 support" depends on SPI diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5548fe7df61d..6aa4723b74ee 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o +obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o obj-$(CONFIG_SERIAL_MUX) += mux.o diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index 60d665a17a88..b801f5ab2b7b 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c @@ -440,7 +440,7 @@ static irqreturn_t imx_rxint(int irq, void *dev_id) temp = readl(sport->port.membase + USR2); if (temp & USR2_BRCD) { - writel(temp | USR2_BRCD, sport->port.membase + USR2); + writel(USR2_BRCD, sport->port.membase + USR2); if (uart_handle_break(&sport->port)) continue; } diff --git a/drivers/serial/s5pv210.c b/drivers/serial/s5pv210.c new file mode 100644 index 000000000000..8dc03837617b --- /dev/null +++ b/drivers/serial/s5pv210.c @@ -0,0 +1,154 @@ +/* linux/drivers/serial/s5pv210.c + * + * Copyright (c) 2010 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * Based on drivers/serial/s3c6400.c + * + * Driver for Samsung S5PV210 SoC UARTs. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <linux/module.h> +#include <linux/ioport.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/init.h> +#include <linux/serial_core.h> +#include <linux/serial.h> + +#include <asm/irq.h> +#include <mach/hardware.h> +#include <plat/regs-serial.h> +#include "samsung.h" + +static int s5pv210_serial_setsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + if (strcmp(clk->name, "pclk") == 0) + ucon &= ~S5PV210_UCON_CLKMASK; + else if (strcmp(clk->name, "uclk1") == 0) + ucon |= S5PV210_UCON_CLKMASK; + else { + printk(KERN_ERR "unknown clock source %s\n", clk->name); + return -EINVAL; + } + + wr_regl(port, S3C2410_UCON, ucon); + return 0; +} + + +static int s5pv210_serial_getsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + u32 ucon = rd_regl(port, S3C2410_UCON); + + clk->divisor = 1; + + switch (ucon & S5PV210_UCON_CLKMASK) { + case S5PV210_UCON_PCLK: + clk->name = "pclk"; + break; + case S5PV210_UCON_UCLK: + clk->name = "uclk1"; + break; + } + + return 0; +} + +static int s5pv210_serial_resetport(struct uart_port *port, + struct s3c2410_uartcfg *cfg) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + ucon &= S5PV210_UCON_CLKMASK; + wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); + wr_regl(port, S3C2410_ULCON, cfg->ulcon); + + /* reset both fifos */ + wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); + wr_regl(port, S3C2410_UFCON, cfg->ufcon); + + return 0; +} + +#define S5PV210_UART_DEFAULT_INFO(fifo_size) \ + .name = "Samsung S5PV210 UART0", \ + .type = PORT_S3C6400, \ + .fifosize = fifo_size, \ + .has_divslot = 1, \ + .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ + .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ + .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ + .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ + .get_clksrc = s5pv210_serial_getsource, \ + .set_clksrc = s5pv210_serial_setsource, \ + .reset_port = s5pv210_serial_resetport + +static struct s3c24xx_uart_info s5p_port_fifo256 = { + S5PV210_UART_DEFAULT_INFO(256), +}; + +static struct s3c24xx_uart_info s5p_port_fifo64 = { + S5PV210_UART_DEFAULT_INFO(64), +}; + +static struct s3c24xx_uart_info s5p_port_fifo16 = { + S5PV210_UART_DEFAULT_INFO(16), +}; + +static struct s3c24xx_uart_info *s5p_uart_inf[] = { + [0] = &s5p_port_fifo256, + [1] = &s5p_port_fifo64, + [2] = &s5p_port_fifo16, + [3] = &s5p_port_fifo16, +}; + +/* device management */ +static int s5p_serial_probe(struct platform_device *pdev) +{ + return s3c24xx_serial_probe(pdev, s5p_uart_inf[pdev->id]); +} + +static struct platform_driver s5p_serial_drv = { + .probe = s5p_serial_probe, + .remove = __devexit_p(s3c24xx_serial_remove), + .driver = { + .name = "s5pv210-uart", + .owner = THIS_MODULE, + }, +}; + +static int __init s5pv210_serial_console_init(void) +{ + return s3c24xx_serial_initconsole(&s5p_serial_drv, s5p_uart_inf); +} + +console_initcall(s5pv210_serial_console_init); + +static int __init s5p_serial_init(void) +{ + return s3c24xx_serial_init(&s5p_serial_drv, *s5p_uart_inf); +} + +static void __exit s5p_serial_exit(void) +{ + platform_driver_unregister(&s5p_serial_drv); +} + +module_init(s5p_serial_init); +module_exit(s5p_serial_exit); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:s5pv210-uart"); +MODULE_DESCRIPTION("Samsung S5PV210 UART Driver support"); +MODULE_AUTHOR("Thomas Abraham <[email protected]>"); diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c index 52e3df113ec0..6982243736d1 100644 --- a/drivers/serial/samsung.c +++ b/drivers/serial/samsung.c @@ -1374,7 +1374,7 @@ s3c24xx_serial_get_options(struct uart_port *port, int *baud, * data. */ -static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) +static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info **info) { struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports; struct platform_device **platdev_ptr; @@ -1385,7 +1385,7 @@ static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info) platdev_ptr = s3c24xx_uart_devs; for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++, ptr++, platdev_ptr++) { - s3c24xx_serial_init_port(ptr, info, *platdev_ptr); + s3c24xx_serial_init_port(ptr, info[i], *platdev_ptr); } return 0; @@ -1451,7 +1451,7 @@ static struct console s3c24xx_serial_console = { }; int s3c24xx_serial_initconsole(struct platform_driver *drv, - struct s3c24xx_uart_info *info) + struct s3c24xx_uart_info **info) { struct platform_device *dev = s3c24xx_uart_devs[0]; diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h index 1fb22343df42..0ac06a07d25f 100644 --- a/drivers/serial/samsung.h +++ b/drivers/serial/samsung.h @@ -75,19 +75,24 @@ extern int s3c24xx_serial_probe(struct platform_device *dev, extern int __devexit s3c24xx_serial_remove(struct platform_device *dev); extern int s3c24xx_serial_initconsole(struct platform_driver *drv, - struct s3c24xx_uart_info *uart); + struct s3c24xx_uart_info **uart); extern int s3c24xx_serial_init(struct platform_driver *drv, struct s3c24xx_uart_info *info); #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE -#define s3c24xx_console_init(__drv, __inf) \ -static int __init s3c_serial_console_init(void) \ -{ \ - return s3c24xx_serial_initconsole(__drv, __inf); \ -} \ - \ +#define s3c24xx_console_init(__drv, __inf) \ +static int __init s3c_serial_console_init(void) \ +{ \ + struct s3c24xx_uart_info *uinfo[CONFIG_SERIAL_SAMSUNG_UARTS]; \ + int i; \ + \ + for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) \ + uinfo[i] = __inf; \ + return s3c24xx_serial_initconsole(__drv, uinfo); \ +} \ + \ console_initcall(s3c_serial_console_init) #else diff --git a/drivers/ssb/main.c b/drivers/ssb/main.c index 5681ebed9c65..03dfd27c4bfb 100644 --- a/drivers/ssb/main.c +++ b/drivers/ssb/main.c @@ -494,8 +494,7 @@ static int ssb_devices_register(struct ssb_bus *bus) #endif break; case SSB_BUSTYPE_SDIO: -#ifdef CONFIG_SSB_SDIO - sdev->irq = bus->host_sdio->dev.irq; +#ifdef CONFIG_SSB_SDIOHOST dev->parent = &bus->host_sdio->dev; #endif break; diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c index 6e8bcdfd23b4..a678186f218f 100644 --- a/drivers/usb/core/devio.c +++ b/drivers/usb/core/devio.c @@ -1312,9 +1312,9 @@ static int processcompl(struct async *as, void __user * __user *arg) void __user *addr = as->userurb; unsigned int i; - if (as->userbuffer) + if (as->userbuffer && urb->actual_length) if (copy_to_user(as->userbuffer, urb->transfer_buffer, - urb->transfer_buffer_length)) + urb->actual_length)) goto err_out; if (put_user(as->status, &userurb->status)) goto err_out; @@ -1334,14 +1334,11 @@ static int processcompl(struct async *as, void __user * __user *arg) } } - free_async(as); - if (put_user(addr, (void __user * __user *)arg)) return -EFAULT; return 0; err_out: - free_async(as); return -EFAULT; } @@ -1371,8 +1368,11 @@ static struct async *reap_as(struct dev_state *ps) static int proc_reapurb(struct dev_state *ps, void __user *arg) { struct async *as = reap_as(ps); - if (as) - return processcompl(as, (void __user * __user *)arg); + if (as) { + int retval = processcompl(as, (void __user * __user *)arg); + free_async(as); + return retval; + } if (signal_pending(current)) return -EINTR; return -EIO; @@ -1380,11 +1380,16 @@ static int proc_reapurb(struct dev_state *ps, void __user *arg) static int proc_reapurbnonblock(struct dev_state *ps, void __user *arg) { + int retval; struct async *as; - if (!(as = async_getcompleted(ps))) - return -EAGAIN; - return processcompl(as, (void __user * __user *)arg); + as = async_getcompleted(ps); + retval = -EAGAIN; + if (as) { + retval = processcompl(as, (void __user * __user *)arg); + free_async(as); + } + return retval; } #ifdef CONFIG_COMPAT @@ -1475,9 +1480,9 @@ static int processcompl_compat(struct async *as, void __user * __user *arg) void __user *addr = as->userurb; unsigned int i; - if (as->userbuffer) + if (as->userbuffer && urb->actual_length) if (copy_to_user(as->userbuffer, urb->transfer_buffer, - urb->transfer_buffer_length)) + urb->actual_length)) return -EFAULT; if (put_user(as->status, &userurb->status)) return -EFAULT; @@ -1497,7 +1502,6 @@ static int processcompl_compat(struct async *as, void __user * __user *arg) } } - free_async(as); if (put_user(ptr_to_compat(addr), (u32 __user *)arg)) return -EFAULT; return 0; @@ -1506,8 +1510,11 @@ static int processcompl_compat(struct async *as, void __user * __user *arg) static int proc_reapurb_compat(struct dev_state *ps, void __user *arg) { struct async *as = reap_as(ps); - if (as) - return processcompl_compat(as, (void __user * __user *)arg); + if (as) { + int retval = processcompl_compat(as, (void __user * __user *)arg); + free_async(as); + return retval; + } if (signal_pending(current)) return -EINTR; return -EIO; @@ -1515,11 +1522,16 @@ static int proc_reapurb_compat(struct dev_state *ps, void __user *arg) static int proc_reapurbnonblock_compat(struct dev_state *ps, void __user *arg) { + int retval; struct async *as; - if (!(as = async_getcompleted(ps))) - return -EAGAIN; - return processcompl_compat(as, (void __user * __user *)arg); + retval = -EAGAIN; + as = async_getcompleted(ps); + if (as) { + retval = processcompl_compat(as, (void __user * __user *)arg); + free_async(as); + } + return retval; } diff --git a/drivers/usb/gadget/f_eem.c b/drivers/usb/gadget/f_eem.c index 0a577d5694fd..d4f0db58a8ad 100644 --- a/drivers/usb/gadget/f_eem.c +++ b/drivers/usb/gadget/f_eem.c @@ -358,7 +358,7 @@ done: * b15: bmType (0 == data) */ len = skb->len; - put_unaligned_le16((len & 0x3FFF) | BIT(14), skb_push(skb, 2)); + put_unaligned_le16(len & 0x3FFF, skb_push(skb, 2)); /* add a zero-length EEM packet, if needed */ if (padlen) @@ -464,7 +464,6 @@ static int eem_unwrap(struct gether *port, } /* validate CRC */ - crc = get_unaligned_le32(skb->data + len - ETH_FCS_LEN); if (header & BIT(14)) { crc = get_unaligned_le32(skb->data + len - ETH_FCS_LEN); diff --git a/drivers/usb/gadget/fsl_mx3_udc.c b/drivers/usb/gadget/fsl_mx3_udc.c index 4bc2bf3d602e..20a802ecaa15 100644 --- a/drivers/usb/gadget/fsl_mx3_udc.c +++ b/drivers/usb/gadget/fsl_mx3_udc.c @@ -17,6 +17,8 @@ #include <linux/fsl_devices.h> #include <linux/platform_device.h> +#include <mach/hardware.h> + static struct clk *mxc_ahb_clk; static struct clk *mxc_usb_clk; @@ -28,14 +30,16 @@ int fsl_udc_clk_init(struct platform_device *pdev) pdata = pdev->dev.platform_data; - mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb"); - if (IS_ERR(mxc_ahb_clk)) - return PTR_ERR(mxc_ahb_clk); + if (!cpu_is_mx35()) { + mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb"); + if (IS_ERR(mxc_ahb_clk)) + return PTR_ERR(mxc_ahb_clk); - ret = clk_enable(mxc_ahb_clk); - if (ret < 0) { - dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n"); - goto eenahb; + ret = clk_enable(mxc_ahb_clk); + if (ret < 0) { + dev_err(&pdev->dev, "clk_enable(\"usb_ahb\") failed\n"); + goto eenahb; + } } /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */ @@ -50,6 +54,7 @@ int fsl_udc_clk_init(struct platform_device *pdev) if (pdata->phy_mode != FSL_USB2_PHY_ULPI && (freq < 59999000 || freq > 60001000)) { dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq); + ret = -EINVAL; goto eclkrate; } @@ -66,9 +71,11 @@ eclkrate: clk_put(mxc_usb_clk); mxc_usb_clk = NULL; egusb: - clk_disable(mxc_ahb_clk); + if (!cpu_is_mx35()) + clk_disable(mxc_ahb_clk); eenahb: - clk_put(mxc_ahb_clk); + if (!cpu_is_mx35()) + clk_put(mxc_ahb_clk); return ret; } @@ -90,6 +97,8 @@ void fsl_udc_clk_release(void) clk_disable(mxc_usb_clk); clk_put(mxc_usb_clk); } - clk_disable(mxc_ahb_clk); - clk_put(mxc_ahb_clk); + if (!cpu_is_mx35()) { + clk_disable(mxc_ahb_clk); + clk_put(mxc_ahb_clk); + } } diff --git a/drivers/usb/gadget/multi.c b/drivers/usb/gadget/multi.c index 429560100b10..76496f5d272c 100644 --- a/drivers/usb/gadget/multi.c +++ b/drivers/usb/gadget/multi.c @@ -29,7 +29,7 @@ #if defined USB_ETH_RNDIS # undef USB_ETH_RNDIS #endif -#ifdef CONFIG_USB_ETH_RNDIS +#ifdef CONFIG_USB_G_MULTI_RNDIS # define USB_ETH_RNDIS y #endif diff --git a/drivers/usb/gadget/pxa25x_udc.c b/drivers/usb/gadget/pxa25x_udc.c index e6fedbd5a654..be5fb34d9602 100644 --- a/drivers/usb/gadget/pxa25x_udc.c +++ b/drivers/usb/gadget/pxa25x_udc.c @@ -65,6 +65,10 @@ #include <mach/pxa25x-udc.h> #endif +#ifdef CONFIG_ARCH_LUBBOCK +#include <mach/lubbock.h> +#endif + #include <asm/mach/udc_pxa2xx.h> diff --git a/drivers/usb/gadget/r8a66597-udc.c b/drivers/usb/gadget/r8a66597-udc.c index e220fb8091a3..8b45145b9136 100644 --- a/drivers/usb/gadget/r8a66597-udc.c +++ b/drivers/usb/gadget/r8a66597-udc.c @@ -26,6 +26,7 @@ #include <linux/io.h> #include <linux/platform_device.h> #include <linux/clk.h> +#include <linux/err.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c index 4b5dbd0127f5..5fc80a104150 100644 --- a/drivers/usb/gadget/s3c-hsotg.c +++ b/drivers/usb/gadget/s3c-hsotg.c @@ -2582,6 +2582,7 @@ err: hsotg->gadget.dev.driver = NULL; return ret; } +EXPORT_SYMBOL(usb_gadget_register_driver); int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) { diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c index c75d9270c752..19372673bf09 100644 --- a/drivers/usb/host/ehci-hub.c +++ b/drivers/usb/host/ehci-hub.c @@ -196,7 +196,9 @@ static int ehci_bus_suspend (struct usb_hcd *hcd) if (hostpc_reg) { u32 t3; + spin_unlock_irq(&ehci->lock); msleep(5);/* 5ms for HCD enter low pwr mode */ + spin_lock_irq(&ehci->lock); t3 = ehci_readl(ehci, hostpc_reg); ehci_writel(ehci, t3 | HOSTPC_PHCD, hostpc_reg); t3 = ehci_readl(ehci, hostpc_reg); @@ -904,17 +906,18 @@ static int ehci_hub_control ( if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) != 0) goto error; - ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); + /* After above check the port must be connected. * Set appropriate bit thus could put phy into low power * mode if we have hostpc feature */ + temp &= ~PORT_WKCONN_E; + temp |= PORT_WKDISC_E | PORT_WKOC_E; + ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); if (hostpc_reg) { - temp &= ~PORT_WKCONN_E; - temp |= (PORT_WKDISC_E | PORT_WKOC_E); - ehci_writel(ehci, temp | PORT_SUSPEND, - status_reg); + spin_unlock_irqrestore(&ehci->lock, flags); msleep(5);/* 5ms for HCD enter low pwr mode */ + spin_lock_irqsave(&ehci->lock, flags); temp1 = ehci_readl(ehci, hostpc_reg); ehci_writel(ehci, temp1 | HOSTPC_PHCD, hostpc_reg); diff --git a/drivers/usb/host/fhci-tds.c b/drivers/usb/host/fhci-tds.c index d224ab467a40..e1232890c78b 100644 --- a/drivers/usb/host/fhci-tds.c +++ b/drivers/usb/host/fhci-tds.c @@ -105,7 +105,7 @@ void fhci_ep0_free(struct fhci_usb *usb) if (ep->td_base) cpm_muram_free(cpm_muram_offset(ep->td_base)); - if (ep->conf_frame_Q) { + if (kfifo_initialized(&ep->conf_frame_Q)) { size = cq_howmany(&ep->conf_frame_Q); for (; size; size--) { struct packet *pkt = cq_get(&ep->conf_frame_Q); @@ -115,7 +115,7 @@ void fhci_ep0_free(struct fhci_usb *usb) cq_delete(&ep->conf_frame_Q); } - if (ep->empty_frame_Q) { + if (kfifo_initialized(&ep->empty_frame_Q)) { size = cq_howmany(&ep->empty_frame_Q); for (; size; size--) { struct packet *pkt = cq_get(&ep->empty_frame_Q); @@ -125,7 +125,7 @@ void fhci_ep0_free(struct fhci_usb *usb) cq_delete(&ep->empty_frame_Q); } - if (ep->dummy_packets_Q) { + if (kfifo_initialized(&ep->dummy_packets_Q)) { size = cq_howmany(&ep->dummy_packets_Q); for (; size; size--) { u8 *buff = cq_get(&ep->dummy_packets_Q); diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index 0ceec123ddfd..bee558aed427 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -35,7 +35,9 @@ #include <linux/usb.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/mm.h> #include <linux/irq.h> +#include <asm/cacheflush.h> #include "../core/hcd.h" #include "r8a66597.h" @@ -820,6 +822,26 @@ static void enable_r8a66597_pipe(struct r8a66597 *r8a66597, struct urb *urb, enable_r8a66597_pipe_dma(r8a66597, dev, pipe, urb); } +static void r8a66597_urb_done(struct r8a66597 *r8a66597, struct urb *urb, + int status) +__releases(r8a66597->lock) +__acquires(r8a66597->lock) +{ + if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { + void *ptr; + + for (ptr = urb->transfer_buffer; + ptr < urb->transfer_buffer + urb->transfer_buffer_length; + ptr += PAGE_SIZE) + flush_dcache_page(virt_to_page(ptr)); + } + + usb_hcd_unlink_urb_from_ep(r8a66597_to_hcd(r8a66597), urb); + spin_unlock(&r8a66597->lock); + usb_hcd_giveback_urb(r8a66597_to_hcd(r8a66597), urb, status); + spin_lock(&r8a66597->lock); +} + /* this function must be called with interrupt disabled */ static void force_dequeue(struct r8a66597 *r8a66597, u16 pipenum, u16 address) { @@ -838,15 +860,9 @@ static void force_dequeue(struct r8a66597 *r8a66597, u16 pipenum, u16 address) list_del(&td->queue); kfree(td); - if (urb) { - usb_hcd_unlink_urb_from_ep(r8a66597_to_hcd(r8a66597), - urb); + if (urb) + r8a66597_urb_done(r8a66597, urb, -ENODEV); - spin_unlock(&r8a66597->lock); - usb_hcd_giveback_urb(r8a66597_to_hcd(r8a66597), urb, - -ENODEV); - spin_lock(&r8a66597->lock); - } break; } } @@ -1006,6 +1022,8 @@ static void start_root_hub_sampling(struct r8a66597 *r8a66597, int port, /* this function must be called with interrupt disabled */ static void r8a66597_check_syssts(struct r8a66597 *r8a66597, int port, u16 syssts) +__releases(r8a66597->lock) +__acquires(r8a66597->lock) { if (syssts == SE0) { r8a66597_write(r8a66597, ~ATTCH, get_intsts_reg(port)); @@ -1023,7 +1041,9 @@ static void r8a66597_check_syssts(struct r8a66597 *r8a66597, int port, usb_hcd_resume_root_hub(r8a66597_to_hcd(r8a66597)); } + spin_unlock(&r8a66597->lock); usb_hcd_poll_rh_status(r8a66597_to_hcd(r8a66597)); + spin_lock(&r8a66597->lock); } /* this function must be called with interrupt disabled */ @@ -1283,10 +1303,7 @@ __releases(r8a66597->lock) __acquires(r8a66597->lock) if (usb_pipeisoc(urb->pipe)) urb->start_frame = r8a66597_get_frame(hcd); - usb_hcd_unlink_urb_from_ep(r8a66597_to_hcd(r8a66597), urb); - spin_unlock(&r8a66597->lock); - usb_hcd_giveback_urb(hcd, urb, status); - spin_lock(&r8a66597->lock); + r8a66597_urb_done(r8a66597, urb, status); } if (restart) { diff --git a/drivers/usb/misc/sisusbvga/sisusb.c b/drivers/usb/misc/sisusbvga/sisusb.c index 0025847743f3..8b37a4b9839e 100644 --- a/drivers/usb/misc/sisusbvga/sisusb.c +++ b/drivers/usb/misc/sisusbvga/sisusb.c @@ -3245,6 +3245,7 @@ static struct usb_device_id sisusb_table [] = { { USB_DEVICE(0x0711, 0x0902) }, { USB_DEVICE(0x0711, 0x0903) }, { USB_DEVICE(0x0711, 0x0918) }, + { USB_DEVICE(0x0711, 0x0920) }, { USB_DEVICE(0x182d, 0x021c) }, { USB_DEVICE(0x182d, 0x0269) }, { } diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig index de56b3d743d7..3d2d3e549bd1 100644 --- a/drivers/usb/otg/Kconfig +++ b/drivers/usb/otg/Kconfig @@ -44,6 +44,7 @@ config ISP1301_OMAP config USB_ULPI bool "Generic ULPI Transceiver Driver" depends on ARM + select USB_OTG_UTILS help Enable this to support ULPI connected USB OTG transceivers which are likely found on embedded boards. diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c index 216f187582ab..7638828e7317 100644 --- a/drivers/usb/serial/ftdi_sio.c +++ b/drivers/usb/serial/ftdi_sio.c @@ -50,7 +50,7 @@ * Version Information */ #define DRIVER_VERSION "v1.5.0" -#define DRIVER_AUTHOR "Greg Kroah-Hartman <[email protected]>, Bill Ryder <[email protected]>, Kuba Ober <[email protected]>" +#define DRIVER_AUTHOR "Greg Kroah-Hartman <[email protected]>, Bill Ryder <[email protected]>, Kuba Ober <[email protected]>, Andreas Mohr" #define DRIVER_DESC "USB FTDI Serial Converters Driver" static int debug; @@ -145,10 +145,15 @@ static struct ftdi_sio_quirk ftdi_HE_TIRA1_quirk = { +/* + * Device ID not listed? Test via module params product/vendor or + * /sys/bus/usb/ftdi_sio/new_id, then send patch/report! + */ static struct usb_device_id id_table_combined [] = { { USB_DEVICE(FTDI_VID, FTDI_AMC232_PID) }, { USB_DEVICE(FTDI_VID, FTDI_CANUSB_PID) }, { USB_DEVICE(FTDI_VID, FTDI_CANDAPTER_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_NXTCAM_PID) }, { USB_DEVICE(FTDI_VID, FTDI_SCS_DEVICE_0_PID) }, { USB_DEVICE(FTDI_VID, FTDI_SCS_DEVICE_1_PID) }, { USB_DEVICE(FTDI_VID, FTDI_SCS_DEVICE_2_PID) }, @@ -552,9 +557,16 @@ static struct usb_device_id id_table_combined [] = { { USB_DEVICE(FTDI_VID, FTDI_IBS_PEDO_PID) }, { USB_DEVICE(FTDI_VID, FTDI_IBS_PROD_PID) }, /* - * Due to many user requests for multiple ELV devices we enable - * them by default. + * ELV devices: */ + { USB_DEVICE(FTDI_VID, FTDI_ELV_USR_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_MSM1_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_KL100_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_WS550_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_EC3000_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_WS888_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_TWS550_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_FEM_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_CLI7000_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_PPS7330_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_TFM100_PID) }, @@ -571,11 +583,17 @@ static struct usb_device_id id_table_combined [] = { { USB_DEVICE(FTDI_VID, FTDI_ELV_PCK100_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_RFP500_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_FS20SIG_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_UTP8_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_WS300PC_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_WS444PC_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_FHZ1300PC_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_EM1010PC_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_WS500_PID) }, { USB_DEVICE(FTDI_VID, FTDI_ELV_HS485_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_UMS100_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_TFD128_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_FM3RX_PID) }, + { USB_DEVICE(FTDI_VID, FTDI_ELV_WS777_PID) }, { USB_DEVICE(FTDI_VID, LINX_SDMUSBQSS_PID) }, { USB_DEVICE(FTDI_VID, LINX_MASTERDEVEL2_PID) }, { USB_DEVICE(FTDI_VID, LINX_FUTURE_0_PID) }, @@ -697,6 +715,7 @@ static struct usb_device_id id_table_combined [] = { { USB_DEVICE(RATOC_VENDOR_ID, RATOC_PRODUCT_ID_USB60F) }, { USB_DEVICE(FTDI_VID, FTDI_REU_TINY_PID) }, { USB_DEVICE(PAPOUCH_VID, PAPOUCH_QUIDO4x4_PID) }, + { USB_DEVICE(PAPOUCH_VID, PAPOUCH_AD4USB_PID) }, { USB_DEVICE(FTDI_VID, FTDI_DOMINTELL_DGQG_PID) }, { USB_DEVICE(FTDI_VID, FTDI_DOMINTELL_DUSB_PID) }, { USB_DEVICE(ALTI2_VID, ALTI2_N3_PID) }, diff --git a/drivers/usb/serial/ftdi_sio_ids.h b/drivers/usb/serial/ftdi_sio_ids.h index da92b4952ffb..c8951aeed983 100644 --- a/drivers/usb/serial/ftdi_sio_ids.h +++ b/drivers/usb/serial/ftdi_sio_ids.h @@ -38,6 +38,8 @@ /* www.candapter.com Ewert Energy Systems CANdapter device */ #define FTDI_CANDAPTER_PID 0x9F80 /* Product Id */ +#define FTDI_NXTCAM_PID 0xABB8 /* NXTCam for Mindstorms NXT */ + /* OOCDlink by Joern Kaipf <[email protected]> * (http://www.joernonline.de/dw/doku.php?id=start&idx=projects:oocdlink) */ #define FTDI_OOCDLINK_PID 0xbaf8 /* Amontec JTAGkey */ @@ -161,22 +163,37 @@ /* * ELV USB devices submitted by Christian Abt of ELV (www.elv.de). * All of these devices use FTDI's vendor ID (0x0403). + * Further IDs taken from ELV Windows .inf file. * * The previously included PID for the UO 100 module was incorrect. * In fact, that PID was for ELV's UR 100 USB-RS232 converter (0xFB58). * * Armin Laeuger originally sent the PID for the UM 100 module. */ +#define FTDI_ELV_USR_PID 0xE000 /* ELV Universal-Sound-Recorder */ +#define FTDI_ELV_MSM1_PID 0xE001 /* ELV Mini-Sound-Modul */ +#define FTDI_ELV_KL100_PID 0xE002 /* ELV Kfz-Leistungsmesser KL 100 */ +#define FTDI_ELV_WS550_PID 0xE004 /* WS 550 */ +#define FTDI_ELV_EC3000_PID 0xE006 /* ENERGY CONTROL 3000 USB */ +#define FTDI_ELV_WS888_PID 0xE008 /* WS 888 */ +#define FTDI_ELV_TWS550_PID 0xE009 /* Technoline WS 550 */ +#define FTDI_ELV_FEM_PID 0xE00A /* Funk Energie Monitor */ #define FTDI_ELV_FHZ1300PC_PID 0xE0E8 /* FHZ 1300 PC */ #define FTDI_ELV_WS500_PID 0xE0E9 /* PC-Wetterstation (WS 500) */ #define FTDI_ELV_HS485_PID 0xE0EA /* USB to RS-485 adapter */ +#define FTDI_ELV_UMS100_PID 0xE0EB /* ELV USB Master-Slave Schaltsteckdose UMS 100 */ +#define FTDI_ELV_TFD128_PID 0xE0EC /* ELV Temperatur-Feuchte-Datenlogger TFD 128 */ +#define FTDI_ELV_FM3RX_PID 0xE0ED /* ELV Messwertuebertragung FM3 RX */ +#define FTDI_ELV_WS777_PID 0xE0EE /* Conrad WS 777 */ #define FTDI_ELV_EM1010PC_PID 0xE0EF /* Engery monitor EM 1010 PC */ #define FTDI_ELV_CSI8_PID 0xE0F0 /* Computer-Schalt-Interface (CSI 8) */ #define FTDI_ELV_EM1000DL_PID 0xE0F1 /* PC-Datenlogger fuer Energiemonitor (EM 1000 DL) */ #define FTDI_ELV_PCK100_PID 0xE0F2 /* PC-Kabeltester (PCK 100) */ #define FTDI_ELV_RFP500_PID 0xE0F3 /* HF-Leistungsmesser (RFP 500) */ #define FTDI_ELV_FS20SIG_PID 0xE0F4 /* Signalgeber (FS 20 SIG) */ +#define FTDI_ELV_UTP8_PID 0xE0F5 /* ELV UTP 8 */ #define FTDI_ELV_WS300PC_PID 0xE0F6 /* PC-Wetterstation (WS 300 PC) */ +#define FTDI_ELV_WS444PC_PID 0xE0F7 /* Conrad WS 444 PC */ #define FTDI_PHI_FISCO_PID 0xE40B /* PHI Fisco USB to Serial cable */ #define FTDI_ELV_UAD8_PID 0xF068 /* USB-AD-Wandler (UAD 8) */ #define FTDI_ELV_UDA7_PID 0xF069 /* USB-DA-Wandler (UDA 7) */ @@ -968,6 +985,7 @@ #define PAPOUCH_VID 0x5050 /* Vendor ID */ #define PAPOUCH_TMU_PID 0x0400 /* TMU USB Thermometer */ #define PAPOUCH_QUIDO4x4_PID 0x0900 /* Quido 4/4 Module */ +#define PAPOUCH_AD4USB_PID 0x8003 /* AD4USB Measurement Module */ /* * Marvell SheevaPlug diff --git a/drivers/usb/serial/sierra.c b/drivers/usb/serial/sierra.c index ac1b6449fb6a..3eb6143bb646 100644 --- a/drivers/usb/serial/sierra.c +++ b/drivers/usb/serial/sierra.c @@ -298,6 +298,7 @@ static struct usb_device_id id_table [] = { { USB_DEVICE(0x1199, 0x68A3), /* Sierra Wireless Direct IP modems */ .driver_info = (kernel_ulong_t)&direct_ip_interface_blacklist }, + { USB_DEVICE(0x413C, 0x08133) }, /* Dell Computer Corp. Wireless 5720 VZW Mobile Broadband (EVDO Rev-A) Minicard GPS Port */ { } }; diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h index c932f9053188..49575fba3756 100644 --- a/drivers/usb/storage/unusual_devs.h +++ b/drivers/usb/storage/unusual_devs.h @@ -941,7 +941,7 @@ UNUSUAL_DEV( 0x07ab, 0xfccd, 0x0000, 0x9999, UNUSUAL_DEV( 0x07af, 0x0004, 0x0100, 0x0133, "Microtech", "USB-SCSI-DB25", - US_SC_SCSI, US_PR_BULK, usb_stor_euscsi_init, + US_SC_DEVICE, US_PR_DEVICE, usb_stor_euscsi_init, US_FL_SCM_MULT_TARG ), UNUSUAL_DEV( 0x07af, 0x0005, 0x0100, 0x0100, diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 5a5c303a6373..83d40ed2f2d6 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -400,9 +400,12 @@ config FB_SA1100 If you plan to use the LCD display with your SA-1100 system, say Y here. +config HAVE_FB_IMX + bool + config FB_IMX tristate "Motorola i.MX LCD support" - depends on FB && (ARCH_MX1 || ARCH_MX2) + depends on FB && (HAVE_FB_IMX || ARCH_MX1 || ARCH_MX2) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT diff --git a/fs/9p/v9fs.c b/fs/9p/v9fs.c index cf62b05e296a..7d6c2139891d 100644 --- a/fs/9p/v9fs.c +++ b/fs/9p/v9fs.c @@ -84,7 +84,7 @@ static const match_table_t tokens = { static int v9fs_parse_options(struct v9fs_session_info *v9ses, char *opts) { - char *options; + char *options, *tmp_options; substring_t args[MAX_OPT_ARGS]; char *p; int option = 0; @@ -102,9 +102,12 @@ static int v9fs_parse_options(struct v9fs_session_info *v9ses, char *opts) if (!opts) return 0; - options = kstrdup(opts, GFP_KERNEL); - if (!options) + tmp_options = kstrdup(opts, GFP_KERNEL); + if (!tmp_options) { + ret = -ENOMEM; goto fail_option_alloc; + } + options = tmp_options; while ((p = strsep(&options, ",")) != NULL) { int token; @@ -159,8 +162,12 @@ static int v9fs_parse_options(struct v9fs_session_info *v9ses, char *opts) break; case Opt_cache: s = match_strdup(&args[0]); - if (!s) - goto fail_option_alloc; + if (!s) { + ret = -ENOMEM; + P9_DPRINTK(P9_DEBUG_ERROR, + "problem allocating copy of cache arg\n"); + goto free_and_return; + } if (strcmp(s, "loose") == 0) v9ses->cache = CACHE_LOOSE; @@ -173,8 +180,12 @@ static int v9fs_parse_options(struct v9fs_session_info *v9ses, char *opts) case Opt_access: s = match_strdup(&args[0]); - if (!s) - goto fail_option_alloc; + if (!s) { + ret = -ENOMEM; + P9_DPRINTK(P9_DEBUG_ERROR, + "problem allocating copy of access arg\n"); + goto free_and_return; + } v9ses->flags &= ~V9FS_ACCESS_MASK; if (strcmp(s, "user") == 0) @@ -194,13 +205,11 @@ static int v9fs_parse_options(struct v9fs_session_info *v9ses, char *opts) continue; } } - kfree(options); - return ret; +free_and_return: + kfree(tmp_options); fail_option_alloc: - P9_DPRINTK(P9_DEBUG_ERROR, - "failed to allocate copy of option argument\n"); - return -ENOMEM; + return ret; } /** diff --git a/fs/9p/v9fs_vfs.h b/fs/9p/v9fs_vfs.h index 3a7560e35865..ed835836e0dc 100644 --- a/fs/9p/v9fs_vfs.h +++ b/fs/9p/v9fs_vfs.h @@ -60,3 +60,4 @@ void v9fs_dentry_release(struct dentry *); int v9fs_uflags2omode(int uflags, int extended); ssize_t v9fs_file_readn(struct file *, char *, char __user *, u32, u64); +void v9fs_blank_wstat(struct p9_wstat *wstat); diff --git a/fs/9p/vfs_file.c b/fs/9p/vfs_file.c index 3902bf43a088..74a0461a9ac0 100644 --- a/fs/9p/vfs_file.c +++ b/fs/9p/vfs_file.c @@ -257,6 +257,23 @@ v9fs_file_write(struct file *filp, const char __user * data, return total; } +static int v9fs_file_fsync(struct file *filp, struct dentry *dentry, + int datasync) +{ + struct p9_fid *fid; + struct p9_wstat wstat; + int retval; + + P9_DPRINTK(P9_DEBUG_VFS, "filp %p dentry %p datasync %x\n", filp, + dentry, datasync); + + fid = filp->private_data; + v9fs_blank_wstat(&wstat); + + retval = p9_client_wstat(fid, &wstat); + return retval; +} + static const struct file_operations v9fs_cached_file_operations = { .llseek = generic_file_llseek, .read = do_sync_read, @@ -266,6 +283,7 @@ static const struct file_operations v9fs_cached_file_operations = { .release = v9fs_dir_release, .lock = v9fs_file_lock, .mmap = generic_file_readonly_mmap, + .fsync = v9fs_file_fsync, }; const struct file_operations v9fs_file_operations = { @@ -276,4 +294,5 @@ const struct file_operations v9fs_file_operations = { .release = v9fs_dir_release, .lock = v9fs_file_lock, .mmap = generic_file_readonly_mmap, + .fsync = v9fs_file_fsync, }; diff --git a/fs/9p/vfs_inode.c b/fs/9p/vfs_inode.c index 9d03d1ebca6f..a407fa3388c0 100644 --- a/fs/9p/vfs_inode.c +++ b/fs/9p/vfs_inode.c @@ -176,7 +176,7 @@ int v9fs_uflags2omode(int uflags, int extended) * */ -static void +void v9fs_blank_wstat(struct p9_wstat *wstat) { wstat->type = ~0; diff --git a/fs/btrfs/file.c b/fs/btrfs/file.c index 9d0809629967..6ed434ac037f 100644 --- a/fs/btrfs/file.c +++ b/fs/btrfs/file.c @@ -720,13 +720,15 @@ again: inode->i_ino, orig_offset); BUG_ON(ret); } - fi = btrfs_item_ptr(leaf, path->slots[0], - struct btrfs_file_extent_item); if (del_nr == 0) { + fi = btrfs_item_ptr(leaf, path->slots[0], + struct btrfs_file_extent_item); btrfs_set_file_extent_type(leaf, fi, BTRFS_FILE_EXTENT_REG); btrfs_mark_buffer_dirty(leaf); } else { + fi = btrfs_item_ptr(leaf, del_slot - 1, + struct btrfs_file_extent_item); btrfs_set_file_extent_type(leaf, fi, BTRFS_FILE_EXTENT_REG); btrfs_set_file_extent_num_bytes(leaf, fi, diff --git a/fs/cifs/CHANGES b/fs/cifs/CHANGES index 7b2600b380d7..49503d2edc7e 100644 --- a/fs/cifs/CHANGES +++ b/fs/cifs/CHANGES @@ -1,3 +1,7 @@ +Version 1.62 +------------ +Add sockopt=TCP_NODELAY mount option. + Version 1.61 ------------ Fix append problem to Samba servers (files opened with O_APPEND could diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h index ac2b24c192f8..78c1b86d55f6 100644 --- a/fs/cifs/cifsfs.h +++ b/fs/cifs/cifsfs.h @@ -113,5 +113,5 @@ extern long cifs_ioctl(struct file *filep, unsigned int cmd, unsigned long arg); extern const struct export_operations cifs_export_ops; #endif /* EXPERIMENTAL */ -#define CIFS_VERSION "1.61" +#define CIFS_VERSION "1.62" #endif /* _CIFSFS_H */ diff --git a/fs/cifs/cifsglob.h b/fs/cifs/cifsglob.h index 4b35f7ec0583..ed751bb657db 100644 --- a/fs/cifs/cifsglob.h +++ b/fs/cifs/cifsglob.h @@ -149,6 +149,7 @@ struct TCP_Server_Info { bool svlocal:1; /* local server or remote */ bool noblocksnd; /* use blocking sendmsg */ bool noautotune; /* do not autotune send buf sizes */ + bool tcp_nodelay; atomic_t inFlight; /* number of requests on the wire to server */ #ifdef CONFIG_CIFS_STATS2 atomic_t inSend; /* requests trying to send */ diff --git a/fs/cifs/connect.c b/fs/cifs/connect.c index 3bbcaa716b3c..2e9e09ca0e30 100644 --- a/fs/cifs/connect.c +++ b/fs/cifs/connect.c @@ -98,7 +98,7 @@ struct smb_vol { bool nostrictsync:1; /* do not force expensive SMBflush on every sync */ unsigned int rsize; unsigned int wsize; - unsigned int sockopt; + bool sockopt_tcp_nodelay:1; unsigned short int port; char *prepath; }; @@ -1142,9 +1142,11 @@ cifs_parse_mount_options(char *options, const char *devname, simple_strtoul(value, &value, 0); } } else if (strnicmp(data, "sockopt", 5) == 0) { - if (value && *value) { - vol->sockopt = - simple_strtoul(value, &value, 0); + if (!value || !*value) { + cERROR(1, ("no socket option specified")); + continue; + } else if (strnicmp(value, "TCP_NODELAY", 11) == 0) { + vol->sockopt_tcp_nodelay = 1; } } else if (strnicmp(data, "netbiosname", 4) == 0) { if (!value || !*value || (*value == ' ')) { @@ -1514,6 +1516,7 @@ cifs_get_tcp_session(struct smb_vol *volume_info) tcp_ses->noblocksnd = volume_info->noblocksnd; tcp_ses->noautotune = volume_info->noautotune; + tcp_ses->tcp_nodelay = volume_info->sockopt_tcp_nodelay; atomic_set(&tcp_ses->inFlight, 0); init_waitqueue_head(&tcp_ses->response_q); init_waitqueue_head(&tcp_ses->request_q); @@ -1764,6 +1767,7 @@ static int ipv4_connect(struct TCP_Server_Info *server) { int rc = 0; + int val; bool connected = false; __be16 orig_port = 0; struct socket *socket = server->ssocket; @@ -1845,6 +1849,14 @@ ipv4_connect(struct TCP_Server_Info *server) socket->sk->sk_rcvbuf = 140 * 1024; } + if (server->tcp_nodelay) { + val = 1; + rc = kernel_setsockopt(socket, SOL_TCP, TCP_NODELAY, + (char *)&val, sizeof(val)); + if (rc) + cFYI(1, ("set TCP_NODELAY socket option error %d", rc)); + } + cFYI(1, ("sndbuf %d rcvbuf %d rcvtimeo 0x%lx", socket->sk->sk_sndbuf, socket->sk->sk_rcvbuf, socket->sk->sk_rcvtimeo)); @@ -1916,6 +1928,7 @@ static int ipv6_connect(struct TCP_Server_Info *server) { int rc = 0; + int val; bool connected = false; __be16 orig_port = 0; struct socket *socket = server->ssocket; @@ -1987,6 +2000,15 @@ ipv6_connect(struct TCP_Server_Info *server) */ socket->sk->sk_rcvtimeo = 7 * HZ; socket->sk->sk_sndtimeo = 5 * HZ; + + if (server->tcp_nodelay) { + val = 1; + rc = kernel_setsockopt(socket, SOL_TCP, TCP_NODELAY, + (char *)&val, sizeof(val)); + if (rc) + cFYI(1, ("set TCP_NODELAY socket option error %d", rc)); + } + server->ssocket = socket; return rc; diff --git a/fs/cifs/inode.c b/fs/cifs/inode.c index cf18ee765590..e3fda978f481 100644 --- a/fs/cifs/inode.c +++ b/fs/cifs/inode.c @@ -1762,8 +1762,18 @@ cifs_setattr_unix(struct dentry *direntry, struct iattr *attrs) CIFS_MOUNT_MAP_SPECIAL_CHR); } - if (!rc) + if (!rc) { rc = inode_setattr(inode, attrs); + + /* force revalidate when any of these times are set since some + of the fs types (eg ext3, fat) do not have fine enough + time granularity to match protocol, and we do not have a + a way (yet) to query the server fs's time granularity (and + whether it rounds times down). + */ + if (!rc && (attrs->ia_valid & (ATTR_MTIME | ATTR_CTIME))) + cifsInode->time = 0; + } out: kfree(args); kfree(full_path); diff --git a/fs/cifs/readdir.c b/fs/cifs/readdir.c index f84062f9a985..c343b14ba2d3 100644 --- a/fs/cifs/readdir.c +++ b/fs/cifs/readdir.c @@ -77,6 +77,11 @@ cifs_readdir_lookup(struct dentry *parent, struct qstr *name, cFYI(1, ("For %s", name->name)); + if (parent->d_op && parent->d_op->d_hash) + parent->d_op->d_hash(parent, name); + else + name->hash = full_name_hash(name->name, name->len); + dentry = d_lookup(parent, name); if (dentry) { /* FIXME: check for inode number changes? */ @@ -666,12 +671,11 @@ static int cifs_get_name_from_search_buf(struct qstr *pqst, min(len, max_len), nlt, cifs_sb->mnt_cifs_flags & CIFS_MOUNT_MAP_SPECIAL_CHR); + pqst->len -= nls_nullsize(nlt); } else { pqst->name = filename; pqst->len = len; } - pqst->hash = full_name_hash(pqst->name, pqst->len); -/* cFYI(1, ("filldir on %s",pqst->name)); */ return rc; } diff --git a/fs/cifs/sess.c b/fs/cifs/sess.c index 7085a6275c4c..aaa9c1c5a5bd 100644 --- a/fs/cifs/sess.c +++ b/fs/cifs/sess.c @@ -223,9 +223,9 @@ static void unicode_ssetup_strings(char **pbcc_area, struct cifsSesInfo *ses, /* null user mount */ *bcc_ptr = 0; *(bcc_ptr+1) = 0; - } else { /* 300 should be long enough for any conceivable user name */ + } else { bytes_ret = cifs_strtoUCS((__le16 *) bcc_ptr, ses->userName, - 300, nls_cp); + MAX_USERNAME_SIZE, nls_cp); } bcc_ptr += 2 * bytes_ret; bcc_ptr += 2; /* account for null termination */ @@ -246,11 +246,10 @@ static void ascii_ssetup_strings(char **pbcc_area, struct cifsSesInfo *ses, /* copy user */ if (ses->userName == NULL) { /* BB what about null user mounts - check that we do this BB */ - } else { /* 300 should be long enough for any conceivable user name */ - strncpy(bcc_ptr, ses->userName, 300); + } else { + strncpy(bcc_ptr, ses->userName, MAX_USERNAME_SIZE); } - /* BB improve check for overflow */ - bcc_ptr += strnlen(ses->userName, 300); + bcc_ptr += strnlen(ses->userName, MAX_USERNAME_SIZE); *bcc_ptr = 0; bcc_ptr++; /* account for null termination */ diff --git a/fs/compat_ioctl.c b/fs/compat_ioctl.c index c5c45de1a2ee..0ca9ec4a79c3 100644 --- a/fs/compat_ioctl.c +++ b/fs/compat_ioctl.c @@ -301,6 +301,12 @@ static int sg_ioctl_trans(unsigned int fd, unsigned int cmd, u32 data; void __user *dxferp; int err; + int interface_id; + + if (get_user(interface_id, &sgio32->interface_id)) + return -EFAULT; + if (interface_id != 'S') + return sys_ioctl(fd, cmd, (unsigned long)sgio32); if (get_user(iovec_count, &sgio32->iovec_count)) return -EFAULT; @@ -936,6 +942,7 @@ COMPATIBLE_IOCTL(TCSETSF) COMPATIBLE_IOCTL(TIOCLINUX) COMPATIBLE_IOCTL(TIOCSBRK) COMPATIBLE_IOCTL(TIOCCBRK) +COMPATIBLE_IOCTL(TIOCGSID) COMPATIBLE_IOCTL(TIOCGICOUNT) /* Little t */ COMPATIBLE_IOCTL(TIOCGETD) @@ -1038,6 +1045,8 @@ COMPATIBLE_IOCTL(FIOQSIZE) #ifdef CONFIG_BLOCK /* loop */ IGNORE_IOCTL(LOOP_CLR_FD) +/* md calls this on random blockdevs */ +IGNORE_IOCTL(RAID_VERSION) /* SG stuff */ COMPATIBLE_IOCTL(SG_SET_TIMEOUT) COMPATIBLE_IOCTL(SG_GET_TIMEOUT) diff --git a/fs/exec.c b/fs/exec.c index 0790a107ff7e..e95c692ef0e4 100644 --- a/fs/exec.c +++ b/fs/exec.c @@ -571,6 +571,9 @@ int setup_arg_pages(struct linux_binprm *bprm, struct vm_area_struct *prev = NULL; unsigned long vm_flags; unsigned long stack_base; + unsigned long stack_size; + unsigned long stack_expand; + unsigned long rlim_stack; #ifdef CONFIG_STACK_GROWSUP /* Limit stack size to 1GB */ @@ -627,10 +630,24 @@ int setup_arg_pages(struct linux_binprm *bprm, goto out_unlock; } + stack_expand = EXTRA_STACK_VM_PAGES * PAGE_SIZE; + stack_size = vma->vm_end - vma->vm_start; + /* + * Align this down to a page boundary as expand_stack + * will align it up. + */ + rlim_stack = rlimit(RLIMIT_STACK) & PAGE_MASK; + rlim_stack = min(rlim_stack, stack_size); #ifdef CONFIG_STACK_GROWSUP - stack_base = vma->vm_end + EXTRA_STACK_VM_PAGES * PAGE_SIZE; + if (stack_size + stack_expand > rlim_stack) + stack_base = vma->vm_start + rlim_stack; + else + stack_base = vma->vm_end + stack_expand; #else - stack_base = vma->vm_start - EXTRA_STACK_VM_PAGES * PAGE_SIZE; + if (stack_size + stack_expand > rlim_stack) + stack_base = vma->vm_end - rlim_stack; + else + stack_base = vma->vm_start - stack_expand; #endif ret = expand_stack(vma, stack_base); if (ret) diff --git a/fs/gfs2/bmap.c b/fs/gfs2/bmap.c index 6d47379e794b..583e823307ae 100644 --- a/fs/gfs2/bmap.c +++ b/fs/gfs2/bmap.c @@ -541,7 +541,7 @@ static int gfs2_bmap_alloc(struct inode *inode, const sector_t lblock, *ptr++ = cpu_to_be64(bn++); break; } - } while (state != ALLOC_DATA); + } while ((state != ALLOC_DATA) || !dblock); ip->i_height = height; gfs2_add_inode_blocks(&ip->i_inode, alloced); diff --git a/fs/gfs2/ops_fstype.c b/fs/gfs2/ops_fstype.c index 8a102f731003..a86ed6381566 100644 --- a/fs/gfs2/ops_fstype.c +++ b/fs/gfs2/ops_fstype.c @@ -725,7 +725,7 @@ static int init_journal(struct gfs2_sbd *sdp, int undo) goto fail; } - error = -EINVAL; + error = -EUSERS; if (!gfs2_jindex_size(sdp)) { fs_err(sdp, "no journals!\n"); goto fail_jindex; diff --git a/fs/nfs/direct.c b/fs/nfs/direct.c index e1d415e97849..0d289823e856 100644 --- a/fs/nfs/direct.c +++ b/fs/nfs/direct.c @@ -342,6 +342,7 @@ static ssize_t nfs_direct_read_schedule_segment(struct nfs_direct_req *dreq, data->res.fattr = &data->fattr; data->res.eof = 0; data->res.count = bytes; + nfs_fattr_init(&data->fattr); msg.rpc_argp = &data->args; msg.rpc_resp = &data->res; @@ -575,6 +576,7 @@ static void nfs_direct_commit_schedule(struct nfs_direct_req *dreq) data->res.count = 0; data->res.fattr = &data->fattr; data->res.verf = &data->verf; + nfs_fattr_init(&data->fattr); NFS_PROTO(data->inode)->commit_setup(data, &msg); @@ -766,6 +768,7 @@ static ssize_t nfs_direct_write_schedule_segment(struct nfs_direct_req *dreq, data->res.fattr = &data->fattr; data->res.count = bytes; data->res.verf = &data->verf; + nfs_fattr_init(&data->fattr); task_setup_data.task = &data->task; task_setup_data.callback_data = data; diff --git a/fs/nfs/fscache.c b/fs/nfs/fscache.c index fa588006588d..237874f1af23 100644 --- a/fs/nfs/fscache.c +++ b/fs/nfs/fscache.c @@ -354,12 +354,11 @@ void nfs_fscache_reset_inode_cookie(struct inode *inode) */ int nfs_fscache_release_page(struct page *page, gfp_t gfp) { - struct nfs_inode *nfsi = NFS_I(page->mapping->host); - struct fscache_cookie *cookie = nfsi->fscache; - - BUG_ON(!cookie); - if (PageFsCache(page)) { + struct nfs_inode *nfsi = NFS_I(page->mapping->host); + struct fscache_cookie *cookie = nfsi->fscache; + + BUG_ON(!cookie); dfprintk(FSCACHE, "NFS: fscache releasepage (0x%p/0x%p/0x%p)\n", cookie, page, nfsi); diff --git a/fs/nfs/mount_clnt.c b/fs/nfs/mount_clnt.c index 0adefc40cc89..59047f8d7d72 100644 --- a/fs/nfs/mount_clnt.c +++ b/fs/nfs/mount_clnt.c @@ -120,7 +120,7 @@ static struct { { .status = MNT3ERR_INVAL, .errno = -EINVAL, }, { .status = MNT3ERR_NAMETOOLONG, .errno = -ENAMETOOLONG, }, { .status = MNT3ERR_NOTSUPP, .errno = -ENOTSUPP, }, - { .status = MNT3ERR_SERVERFAULT, .errno = -ESERVERFAULT, }, + { .status = MNT3ERR_SERVERFAULT, .errno = -EREMOTEIO, }, }; struct mountres { diff --git a/fs/nfs/nfs2xdr.c b/fs/nfs/nfs2xdr.c index 5e078b222b4e..7bc2da8efd4a 100644 --- a/fs/nfs/nfs2xdr.c +++ b/fs/nfs/nfs2xdr.c @@ -699,7 +699,7 @@ static struct { { NFSERR_BAD_COOKIE, -EBADCOOKIE }, { NFSERR_NOTSUPP, -ENOTSUPP }, { NFSERR_TOOSMALL, -ETOOSMALL }, - { NFSERR_SERVERFAULT, -ESERVERFAULT }, + { NFSERR_SERVERFAULT, -EREMOTEIO }, { NFSERR_BADTYPE, -EBADTYPE }, { NFSERR_JUKEBOX, -EJUKEBOX }, { -1, -EIO } diff --git a/fs/nfs/nfs4xdr.c b/fs/nfs/nfs4xdr.c index e437fd6a819f..5cd5184b56db 100644 --- a/fs/nfs/nfs4xdr.c +++ b/fs/nfs/nfs4xdr.c @@ -4631,7 +4631,7 @@ static int decode_sequence(struct xdr_stream *xdr, * If the server returns different values for sessionID, slotID or * sequence number, the server is looney tunes. */ - status = -ESERVERFAULT; + status = -EREMOTEIO; if (memcmp(id.data, res->sr_session->sess_id.data, NFS4_MAX_SESSIONID_LEN)) { @@ -5774,7 +5774,7 @@ static struct { { NFS4ERR_BAD_COOKIE, -EBADCOOKIE }, { NFS4ERR_NOTSUPP, -ENOTSUPP }, { NFS4ERR_TOOSMALL, -ETOOSMALL }, - { NFS4ERR_SERVERFAULT, -ESERVERFAULT }, + { NFS4ERR_SERVERFAULT, -EREMOTEIO }, { NFS4ERR_BADTYPE, -EBADTYPE }, { NFS4ERR_LOCKED, -EAGAIN }, { NFS4ERR_SYMLINK, -ELOOP }, @@ -5801,7 +5801,7 @@ nfs4_stat_to_errno(int stat) } if (stat <= 10000 || stat > 10100) { /* The server is looney tunes. */ - return -ESERVERFAULT; + return -EREMOTEIO; } /* If we cannot translate the error, the recovery routines should * handle it. diff --git a/fs/nfs/write.c b/fs/nfs/write.c index 7b54b8bb101f..d63d964a0392 100644 --- a/fs/nfs/write.c +++ b/fs/nfs/write.c @@ -1598,8 +1598,7 @@ int nfs_migrate_page(struct address_space *mapping, struct page *newpage, struct nfs_page *req; int ret; - if (PageFsCache(page)) - nfs_fscache_release_page(page, GFP_KERNEL); + nfs_fscache_release_page(page, GFP_KERNEL); req = nfs_find_and_lock_request(page); ret = PTR_ERR(req); diff --git a/fs/nfsd/export.c b/fs/nfsd/export.c index c487810a2366..a0c4016413f1 100644 --- a/fs/nfsd/export.c +++ b/fs/nfsd/export.c @@ -1316,19 +1316,11 @@ rqst_exp_parent(struct svc_rqst *rqstp, struct path *path) static struct svc_export *find_fsidzero_export(struct svc_rqst *rqstp) { - struct svc_export *exp; u32 fsidv[2]; mk_fsid(FSID_NUM, fsidv, 0, 0, 0, NULL); - exp = rqst_exp_find(rqstp, FSID_NUM, fsidv); - /* - * We shouldn't have accepting an nfsv4 request at all if we - * don't have a pseudoexport!: - */ - if (IS_ERR(exp) && PTR_ERR(exp) == -ENOENT) - exp = ERR_PTR(-ESERVERFAULT); - return exp; + return rqst_exp_find(rqstp, FSID_NUM, fsidv); } /* diff --git a/fs/ocfs2/aops.c b/fs/ocfs2/aops.c index 3dae4a13f6e4..7e9df11260f4 100644 --- a/fs/ocfs2/aops.c +++ b/fs/ocfs2/aops.c @@ -599,7 +599,7 @@ bail: return ret; } -/* +/* * ocfs2_dio_end_io is called by the dio core when a dio is finished. We're * particularly interested in the aio/dio case. Like the core uses * i_alloc_sem, we use the rw_lock DLM lock to protect io on one node from @@ -670,7 +670,7 @@ static ssize_t ocfs2_direct_IO(int rw, ret = blockdev_direct_IO_no_locking(rw, iocb, inode, inode->i_sb->s_bdev, iov, offset, - nr_segs, + nr_segs, ocfs2_direct_IO_get_blocks, ocfs2_dio_end_io); diff --git a/fs/ocfs2/buffer_head_io.c b/fs/ocfs2/buffer_head_io.c index d43d34a1dd31..21c808f752d8 100644 --- a/fs/ocfs2/buffer_head_io.c +++ b/fs/ocfs2/buffer_head_io.c @@ -368,7 +368,7 @@ int ocfs2_read_blocks(struct ocfs2_caching_info *ci, u64 block, int nr, } ocfs2_metadata_cache_io_unlock(ci); - mlog(ML_BH_IO, "block=(%llu), nr=(%d), cached=%s, flags=0x%x\n", + mlog(ML_BH_IO, "block=(%llu), nr=(%d), cached=%s, flags=0x%x\n", (unsigned long long)block, nr, ((flags & OCFS2_BH_IGNORE_CACHE) || ignore_cache) ? "no" : "yes", flags); diff --git a/fs/ocfs2/cluster/heartbeat.c b/fs/ocfs2/cluster/heartbeat.c index eda5b8bcddd5..5c9890006708 100644 --- a/fs/ocfs2/cluster/heartbeat.c +++ b/fs/ocfs2/cluster/heartbeat.c @@ -78,7 +78,7 @@ static struct o2hb_callback *hbcall_from_type(enum o2hb_callback_type type); unsigned int o2hb_dead_threshold = O2HB_DEFAULT_DEAD_THRESHOLD; -/* Only sets a new threshold if there are no active regions. +/* Only sets a new threshold if there are no active regions. * * No locking or otherwise interesting code is required for reading * o2hb_dead_threshold as it can't change once regions are active and @@ -170,7 +170,7 @@ static void o2hb_write_timeout(struct work_struct *work) mlog(ML_ERROR, "Heartbeat write timeout to device %s after %u " "milliseconds\n", reg->hr_dev_name, - jiffies_to_msecs(jiffies - reg->hr_last_timeout_start)); + jiffies_to_msecs(jiffies - reg->hr_last_timeout_start)); o2quo_disk_timeout(); } @@ -624,7 +624,7 @@ static int o2hb_check_slot(struct o2hb_region *reg, "seq %llu last %llu changed %u equal %u\n", slot->ds_node_num, (long long)slot->ds_last_generation, le32_to_cpu(hb_block->hb_cksum), - (unsigned long long)le64_to_cpu(hb_block->hb_seq), + (unsigned long long)le64_to_cpu(hb_block->hb_seq), (unsigned long long)slot->ds_last_time, slot->ds_changed_samples, slot->ds_equal_samples); diff --git a/fs/ocfs2/cluster/tcp.c b/fs/ocfs2/cluster/tcp.c index 334f231a422c..d8d0c65ac03c 100644 --- a/fs/ocfs2/cluster/tcp.c +++ b/fs/ocfs2/cluster/tcp.c @@ -485,7 +485,7 @@ static void o2net_set_nn_state(struct o2net_node *nn, } if (was_valid && !valid) { - printk(KERN_INFO "o2net: no longer connected to " + printk(KERN_NOTICE "o2net: no longer connected to " SC_NODEF_FMT "\n", SC_NODEF_ARGS(old_sc)); o2net_complete_nodes_nsw(nn); } @@ -493,7 +493,7 @@ static void o2net_set_nn_state(struct o2net_node *nn, if (!was_valid && valid) { o2quo_conn_up(o2net_num_from_nn(nn)); cancel_delayed_work(&nn->nn_connect_expired); - printk(KERN_INFO "o2net: %s " SC_NODEF_FMT "\n", + printk(KERN_NOTICE "o2net: %s " SC_NODEF_FMT "\n", o2nm_this_node() > sc->sc_node->nd_num ? "connected to" : "accepted connection from", SC_NODEF_ARGS(sc)); @@ -930,7 +930,7 @@ static void o2net_sendpage(struct o2net_sock_container *sc, cond_resched(); continue; } - mlog(ML_ERROR, "sendpage of size %zu to " SC_NODEF_FMT + mlog(ML_ERROR, "sendpage of size %zu to " SC_NODEF_FMT " failed with %zd\n", size, SC_NODEF_ARGS(sc), ret); o2net_ensure_shutdown(nn, sc, 0); break; @@ -1476,14 +1476,14 @@ static void o2net_idle_timer(unsigned long data) do_gettimeofday(&now); - printk(KERN_INFO "o2net: connection to " SC_NODEF_FMT " has been idle for %u.%u " + printk(KERN_NOTICE "o2net: connection to " SC_NODEF_FMT " has been idle for %u.%u " "seconds, shutting it down.\n", SC_NODEF_ARGS(sc), o2net_idle_timeout() / 1000, o2net_idle_timeout() % 1000); mlog(ML_NOTICE, "here are some times that might help debug the " "situation: (tmr %ld.%ld now %ld.%ld dr %ld.%ld adv " "%ld.%ld:%ld.%ld func (%08x:%u) %ld.%ld:%ld.%ld)\n", - sc->sc_tv_timer.tv_sec, (long) sc->sc_tv_timer.tv_usec, + sc->sc_tv_timer.tv_sec, (long) sc->sc_tv_timer.tv_usec, now.tv_sec, (long) now.tv_usec, sc->sc_tv_data_ready.tv_sec, (long) sc->sc_tv_data_ready.tv_usec, sc->sc_tv_advance_start.tv_sec, diff --git a/fs/ocfs2/cluster/tcp_internal.h b/fs/ocfs2/cluster/tcp_internal.h index 8d58cfe410b1..96fa7ebc530c 100644 --- a/fs/ocfs2/cluster/tcp_internal.h +++ b/fs/ocfs2/cluster/tcp_internal.h @@ -32,10 +32,10 @@ * on their number */ #define O2NET_QUORUM_DELAY_MS ((o2hb_dead_threshold + 2) * O2HB_REGION_TIMEOUT_MS) -/* +/* * This version number represents quite a lot, unfortunately. It not * only represents the raw network message protocol on the wire but also - * locking semantics of the file system using the protocol. It should + * locking semantics of the file system using the protocol. It should * be somewhere else, I'm sure, but right now it isn't. * * With version 11, we separate out the filesystem locking portion. The diff --git a/fs/ocfs2/dlm/dlmapi.h b/fs/ocfs2/dlm/dlmapi.h index b5786a787fab..3cfa114aa391 100644 --- a/fs/ocfs2/dlm/dlmapi.h +++ b/fs/ocfs2/dlm/dlmapi.h @@ -95,7 +95,7 @@ const char *dlm_errname(enum dlm_status err); mlog(ML_ERROR, "dlm status = %s\n", dlm_errname((st))); \ } while (0) -#define DLM_LKSB_UNUSED1 0x01 +#define DLM_LKSB_UNUSED1 0x01 #define DLM_LKSB_PUT_LVB 0x02 #define DLM_LKSB_GET_LVB 0x04 #define DLM_LKSB_UNUSED2 0x08 diff --git a/fs/ocfs2/dlm/dlmast.c b/fs/ocfs2/dlm/dlmast.c index 01cf8cc3d286..dccc439fa087 100644 --- a/fs/ocfs2/dlm/dlmast.c +++ b/fs/ocfs2/dlm/dlmast.c @@ -123,7 +123,7 @@ static void __dlm_queue_ast(struct dlm_ctxt *dlm, struct dlm_lock *lock) dlm_lock_put(lock); /* free up the reserved bast that we are cancelling. * guaranteed that this will not be the last reserved - * ast because *both* an ast and a bast were reserved + * ast because *both* an ast and a bast were reserved * to get to this point. the res->spinlock will not be * taken here */ dlm_lockres_release_ast(dlm, res); diff --git a/fs/ocfs2/dlm/dlmconvert.c b/fs/ocfs2/dlm/dlmconvert.c index ca96bce50e18..f283bce776b4 100644 --- a/fs/ocfs2/dlm/dlmconvert.c +++ b/fs/ocfs2/dlm/dlmconvert.c @@ -396,7 +396,7 @@ static enum dlm_status dlm_send_remote_convert_request(struct dlm_ctxt *dlm, /* instead of logging the same network error over * and over, sleep here and wait for the heartbeat * to notice the node is dead. times out after 5s. */ - dlm_wait_for_node_death(dlm, res->owner, + dlm_wait_for_node_death(dlm, res->owner, DLM_NODE_DEATH_WAIT_MAX); ret = DLM_RECOVERING; mlog(0, "node %u died so returning DLM_RECOVERING " diff --git a/fs/ocfs2/dlm/dlmdebug.c b/fs/ocfs2/dlm/dlmdebug.c index 42b0bad7a612..0cd24cf54396 100644 --- a/fs/ocfs2/dlm/dlmdebug.c +++ b/fs/ocfs2/dlm/dlmdebug.c @@ -102,7 +102,7 @@ void __dlm_print_one_lock_resource(struct dlm_lock_resource *res) assert_spin_locked(&res->spinlock); stringify_lockname(res->lockname.name, res->lockname.len, - buf, sizeof(buf) - 1); + buf, sizeof(buf)); printk("lockres: %s, owner=%u, state=%u\n", buf, res->owner, res->state); printk(" last used: %lu, refcnt: %u, on purge list: %s\n", diff --git a/fs/ocfs2/dlm/dlmdomain.c b/fs/ocfs2/dlm/dlmdomain.c index 0334000676d3..988c9055fd4e 100644 --- a/fs/ocfs2/dlm/dlmdomain.c +++ b/fs/ocfs2/dlm/dlmdomain.c @@ -816,7 +816,7 @@ static int dlm_query_join_handler(struct o2net_msg *msg, u32 len, void *data, } /* Once the dlm ctxt is marked as leaving then we don't want - * to be put in someone's domain map. + * to be put in someone's domain map. * Also, explicitly disallow joining at certain troublesome * times (ie. during recovery). */ if (dlm && dlm->dlm_state != DLM_CTXT_LEAVING) { diff --git a/fs/ocfs2/dlm/dlmlock.c b/fs/ocfs2/dlm/dlmlock.c index 437698e9465f..733337772671 100644 --- a/fs/ocfs2/dlm/dlmlock.c +++ b/fs/ocfs2/dlm/dlmlock.c @@ -269,7 +269,7 @@ static enum dlm_status dlmlock_remote(struct dlm_ctxt *dlm, } dlm_revert_pending_lock(res, lock); dlm_lock_put(lock); - } else if (dlm_is_recovery_lock(res->lockname.name, + } else if (dlm_is_recovery_lock(res->lockname.name, res->lockname.len)) { /* special case for the $RECOVERY lock. * there will never be an AST delivered to put diff --git a/fs/ocfs2/dlm/dlmmaster.c b/fs/ocfs2/dlm/dlmmaster.c index 03ccf9a7b1f4..a659606dcb95 100644 --- a/fs/ocfs2/dlm/dlmmaster.c +++ b/fs/ocfs2/dlm/dlmmaster.c @@ -366,7 +366,7 @@ void dlm_hb_event_notify_attached(struct dlm_ctxt *dlm, int idx, int node_up) struct dlm_master_list_entry *mle; assert_spin_locked(&dlm->spinlock); - + list_for_each_entry(mle, &dlm->mle_hb_events, hb_events) { if (node_up) dlm_mle_node_up(dlm, mle, NULL, idx); @@ -833,7 +833,7 @@ lookup: __dlm_insert_mle(dlm, mle); /* still holding the dlm spinlock, check the recovery map - * to see if there are any nodes that still need to be + * to see if there are any nodes that still need to be * considered. these will not appear in the mle nodemap * but they might own this lockres. wait on them. */ bit = find_next_bit(dlm->recovery_map, O2NM_MAX_NODES, 0); @@ -883,7 +883,7 @@ redo_request: msleep(500); } continue; - } + } dlm_kick_recovery_thread(dlm); msleep(1000); @@ -939,8 +939,8 @@ wait: res->lockname.name, blocked); if (++tries > 20) { mlog(ML_ERROR, "%s:%.*s: spinning on " - "dlm_wait_for_lock_mastery, blocked=%d\n", - dlm->name, res->lockname.len, + "dlm_wait_for_lock_mastery, blocked=%d\n", + dlm->name, res->lockname.len, res->lockname.name, blocked); dlm_print_one_lock_resource(res); dlm_print_one_mle(mle); @@ -1029,7 +1029,7 @@ recheck: ret = dlm_restart_lock_mastery(dlm, res, mle, *blocked); b = (mle->type == DLM_MLE_BLOCK); if ((*blocked && !b) || (!*blocked && b)) { - mlog(0, "%s:%.*s: status change: old=%d new=%d\n", + mlog(0, "%s:%.*s: status change: old=%d new=%d\n", dlm->name, res->lockname.len, res->lockname.name, *blocked, b); *blocked = b; @@ -1602,7 +1602,7 @@ send_response: } mlog(0, "%u is the owner of %.*s, cleaning everyone else\n", dlm->node_num, res->lockname.len, res->lockname.name); - ret = dlm_dispatch_assert_master(dlm, res, 0, request->node_idx, + ret = dlm_dispatch_assert_master(dlm, res, 0, request->node_idx, DLM_ASSERT_MASTER_MLE_CLEANUP); if (ret < 0) { mlog(ML_ERROR, "failed to dispatch assert master work\n"); @@ -1701,7 +1701,7 @@ again: if (r & DLM_ASSERT_RESPONSE_REASSERT) { mlog(0, "%.*s: node %u create mles on other " - "nodes and requests a re-assert\n", + "nodes and requests a re-assert\n", namelen, lockname, to); reassert = 1; } @@ -1812,7 +1812,7 @@ int dlm_assert_master_handler(struct o2net_msg *msg, u32 len, void *data, spin_unlock(&dlm->master_lock); spin_unlock(&dlm->spinlock); goto done; - } + } } } spin_unlock(&dlm->master_lock); @@ -1883,7 +1883,7 @@ ok: int extra_ref = 0; int nn = -1; int rr, err = 0; - + spin_lock(&mle->spinlock); if (mle->type == DLM_MLE_BLOCK || mle->type == DLM_MLE_MIGRATION) extra_ref = 1; @@ -1891,7 +1891,7 @@ ok: /* MASTER mle: if any bits set in the response map * then the calling node needs to re-assert to clear * up nodes that this node contacted */ - while ((nn = find_next_bit (mle->response_map, O2NM_MAX_NODES, + while ((nn = find_next_bit (mle->response_map, O2NM_MAX_NODES, nn+1)) < O2NM_MAX_NODES) { if (nn != dlm->node_num && nn != assert->node_idx) master_request = 1; @@ -2002,7 +2002,7 @@ kill: __dlm_print_one_lock_resource(res); spin_unlock(&res->spinlock); spin_unlock(&dlm->spinlock); - *ret_data = (void *)res; + *ret_data = (void *)res; dlm_put(dlm); return -EINVAL; } @@ -2040,10 +2040,10 @@ int dlm_dispatch_assert_master(struct dlm_ctxt *dlm, item->u.am.request_from = request_from; item->u.am.flags = flags; - if (ignore_higher) - mlog(0, "IGNORE HIGHER: %.*s\n", res->lockname.len, + if (ignore_higher) + mlog(0, "IGNORE HIGHER: %.*s\n", res->lockname.len, res->lockname.name); - + spin_lock(&dlm->work_lock); list_add_tail(&item->list, &dlm->work_list); spin_unlock(&dlm->work_lock); @@ -2133,7 +2133,7 @@ put: * think that $RECOVERY is currently mastered by a dead node. If so, * we wait a short time to allow that node to get notified by its own * heartbeat stack, then check again. All $RECOVERY lock resources - * mastered by dead nodes are purged when the hearbeat callback is + * mastered by dead nodes are purged when the hearbeat callback is * fired, so we can know for sure that it is safe to continue once * the node returns a live node or no node. */ static int dlm_pre_master_reco_lockres(struct dlm_ctxt *dlm, @@ -2174,7 +2174,7 @@ static int dlm_pre_master_reco_lockres(struct dlm_ctxt *dlm, ret = -EAGAIN; } spin_unlock(&dlm->spinlock); - mlog(0, "%s: reco lock master is %u\n", dlm->name, + mlog(0, "%s: reco lock master is %u\n", dlm->name, master); break; } @@ -2602,7 +2602,7 @@ fail: mlog(0, "%s:%.*s: timed out during migration\n", dlm->name, res->lockname.len, res->lockname.name); - /* avoid hang during shutdown when migrating lockres + /* avoid hang during shutdown when migrating lockres * to a node which also goes down */ if (dlm_is_node_dead(dlm, target)) { mlog(0, "%s:%.*s: expected migration " @@ -2738,7 +2738,7 @@ static int dlm_migration_can_proceed(struct dlm_ctxt *dlm, can_proceed = !!(res->state & DLM_LOCK_RES_MIGRATING); spin_unlock(&res->spinlock); - /* target has died, so make the caller break out of the + /* target has died, so make the caller break out of the * wait_event, but caller must recheck the domain_map */ spin_lock(&dlm->spinlock); if (!test_bit(mig_target, dlm->domain_map)) diff --git a/fs/ocfs2/dlm/dlmrecovery.c b/fs/ocfs2/dlm/dlmrecovery.c index 2f9e4e19a4f2..344bcf90cbf4 100644 --- a/fs/ocfs2/dlm/dlmrecovery.c +++ b/fs/ocfs2/dlm/dlmrecovery.c @@ -1050,7 +1050,7 @@ static void dlm_move_reco_locks_to_list(struct dlm_ctxt *dlm, if (lock->ml.node == dead_node) { mlog(0, "AHA! there was " "a $RECOVERY lock for dead " - "node %u (%s)!\n", + "node %u (%s)!\n", dead_node, dlm->name); list_del_init(&lock->list); dlm_lock_put(lock); @@ -1164,6 +1164,39 @@ static void dlm_init_migratable_lockres(struct dlm_migratable_lockres *mres, mres->master = master; } +static void dlm_prepare_lvb_for_migration(struct dlm_lock *lock, + struct dlm_migratable_lockres *mres, + int queue) +{ + if (!lock->lksb) + return; + + /* Ignore lvb in all locks in the blocked list */ + if (queue == DLM_BLOCKED_LIST) + return; + + /* Only consider lvbs in locks with granted EX or PR lock levels */ + if (lock->ml.type != LKM_EXMODE && lock->ml.type != LKM_PRMODE) + return; + + if (dlm_lvb_is_empty(mres->lvb)) { + memcpy(mres->lvb, lock->lksb->lvb, DLM_LVB_LEN); + return; + } + + /* Ensure the lvb copied for migration matches in other valid locks */ + if (!memcmp(mres->lvb, lock->lksb->lvb, DLM_LVB_LEN)) + return; + + mlog(ML_ERROR, "Mismatched lvb in lock cookie=%u:%llu, name=%.*s, " + "node=%u\n", + dlm_get_lock_cookie_node(be64_to_cpu(lock->ml.cookie)), + dlm_get_lock_cookie_seq(be64_to_cpu(lock->ml.cookie)), + lock->lockres->lockname.len, lock->lockres->lockname.name, + lock->ml.node); + dlm_print_one_lock_resource(lock->lockres); + BUG(); +} /* returns 1 if this lock fills the network structure, * 0 otherwise */ @@ -1181,20 +1214,7 @@ static int dlm_add_lock_to_array(struct dlm_lock *lock, ml->list = queue; if (lock->lksb) { ml->flags = lock->lksb->flags; - /* send our current lvb */ - if (ml->type == LKM_EXMODE || - ml->type == LKM_PRMODE) { - /* if it is already set, this had better be a PR - * and it has to match */ - if (!dlm_lvb_is_empty(mres->lvb) && - (ml->type == LKM_EXMODE || - memcmp(mres->lvb, lock->lksb->lvb, DLM_LVB_LEN))) { - mlog(ML_ERROR, "mismatched lvbs!\n"); - dlm_print_one_lock_resource(lock->lockres); - BUG(); - } - memcpy(mres->lvb, lock->lksb->lvb, DLM_LVB_LEN); - } + dlm_prepare_lvb_for_migration(lock, mres, queue); } ml->node = lock->ml.node; mres->num_locks++; @@ -1730,6 +1750,7 @@ static int dlm_process_recovery_data(struct dlm_ctxt *dlm, struct dlm_lock *lock = NULL; u8 from = O2NM_MAX_NODES; unsigned int added = 0; + __be64 c; mlog(0, "running %d locks for this lockres\n", mres->num_locks); for (i=0; i<mres->num_locks; i++) { @@ -1777,19 +1798,48 @@ static int dlm_process_recovery_data(struct dlm_ctxt *dlm, /* lock is always created locally first, and * destroyed locally last. it must be on the list */ if (!lock) { - __be64 c = ml->cookie; - mlog(ML_ERROR, "could not find local lock " - "with cookie %u:%llu!\n", + c = ml->cookie; + mlog(ML_ERROR, "Could not find local lock " + "with cookie %u:%llu, node %u, " + "list %u, flags 0x%x, type %d, " + "conv %d, highest blocked %d\n", dlm_get_lock_cookie_node(be64_to_cpu(c)), - dlm_get_lock_cookie_seq(be64_to_cpu(c))); + dlm_get_lock_cookie_seq(be64_to_cpu(c)), + ml->node, ml->list, ml->flags, ml->type, + ml->convert_type, ml->highest_blocked); + __dlm_print_one_lock_resource(res); + BUG(); + } + + if (lock->ml.node != ml->node) { + c = lock->ml.cookie; + mlog(ML_ERROR, "Mismatched node# in lock " + "cookie %u:%llu, name %.*s, node %u\n", + dlm_get_lock_cookie_node(be64_to_cpu(c)), + dlm_get_lock_cookie_seq(be64_to_cpu(c)), + res->lockname.len, res->lockname.name, + lock->ml.node); + c = ml->cookie; + mlog(ML_ERROR, "Migrate lock cookie %u:%llu, " + "node %u, list %u, flags 0x%x, type %d, " + "conv %d, highest blocked %d\n", + dlm_get_lock_cookie_node(be64_to_cpu(c)), + dlm_get_lock_cookie_seq(be64_to_cpu(c)), + ml->node, ml->list, ml->flags, ml->type, + ml->convert_type, ml->highest_blocked); __dlm_print_one_lock_resource(res); BUG(); } - BUG_ON(lock->ml.node != ml->node); if (tmpq != queue) { - mlog(0, "lock was on %u instead of %u for %.*s\n", - j, ml->list, res->lockname.len, res->lockname.name); + c = ml->cookie; + mlog(0, "Lock cookie %u:%llu was on list %u " + "instead of list %u for %.*s\n", + dlm_get_lock_cookie_node(be64_to_cpu(c)), + dlm_get_lock_cookie_seq(be64_to_cpu(c)), + j, ml->list, res->lockname.len, + res->lockname.name); + __dlm_print_one_lock_resource(res); spin_unlock(&res->spinlock); continue; } @@ -1839,7 +1889,7 @@ static int dlm_process_recovery_data(struct dlm_ctxt *dlm, * the lvb. */ memcpy(res->lvb, mres->lvb, DLM_LVB_LEN); } else { - /* otherwise, the node is sending its + /* otherwise, the node is sending its * most recent valid lvb info */ BUG_ON(ml->type != LKM_EXMODE && ml->type != LKM_PRMODE); @@ -1886,7 +1936,7 @@ skip_lvb: spin_lock(&res->spinlock); list_for_each_entry(lock, queue, list) { if (lock->ml.cookie == ml->cookie) { - __be64 c = lock->ml.cookie; + c = lock->ml.cookie; mlog(ML_ERROR, "%s:%.*s: %u:%llu: lock already " "exists on this lockres!\n", dlm->name, res->lockname.len, res->lockname.name, @@ -2114,7 +2164,7 @@ static void dlm_revalidate_lvb(struct dlm_ctxt *dlm, assert_spin_locked(&res->spinlock); if (res->owner == dlm->node_num) - /* if this node owned the lockres, and if the dead node + /* if this node owned the lockres, and if the dead node * had an EX when he died, blank out the lvb */ search_node = dead_node; else { @@ -2152,7 +2202,7 @@ static void dlm_free_dead_locks(struct dlm_ctxt *dlm, /* this node is the lockres master: * 1) remove any stale locks for the dead node - * 2) if the dead node had an EX when he died, blank out the lvb + * 2) if the dead node had an EX when he died, blank out the lvb */ assert_spin_locked(&dlm->spinlock); assert_spin_locked(&res->spinlock); @@ -2193,7 +2243,12 @@ static void dlm_free_dead_locks(struct dlm_ctxt *dlm, mlog(0, "%s:%.*s: freed %u locks for dead node %u, " "dropping ref from lockres\n", dlm->name, res->lockname.len, res->lockname.name, freed, dead_node); - BUG_ON(!test_bit(dead_node, res->refmap)); + if(!test_bit(dead_node, res->refmap)) { + mlog(ML_ERROR, "%s:%.*s: freed %u locks for dead node %u, " + "but ref was not set\n", dlm->name, + res->lockname.len, res->lockname.name, freed, dead_node); + __dlm_print_one_lock_resource(res); + } dlm_lockres_clear_refmap_bit(dead_node, res); } else if (test_bit(dead_node, res->refmap)) { mlog(0, "%s:%.*s: dead node %u had a ref, but had " @@ -2260,7 +2315,7 @@ static void dlm_do_local_recovery_cleanup(struct dlm_ctxt *dlm, u8 dead_node) } spin_unlock(&res->spinlock); continue; - } + } spin_lock(&res->spinlock); /* zero the lvb if necessary */ dlm_revalidate_lvb(dlm, res, dead_node); @@ -2411,7 +2466,7 @@ static void dlm_reco_unlock_ast(void *astdata, enum dlm_status st) * this function on each node racing to become the recovery * master will not stop attempting this until either: * a) this node gets the EX (and becomes the recovery master), - * or b) dlm->reco.new_master gets set to some nodenum + * or b) dlm->reco.new_master gets set to some nodenum * != O2NM_INVALID_NODE_NUM (another node will do the reco). * so each time a recovery master is needed, the entire cluster * will sync at this point. if the new master dies, that will @@ -2424,7 +2479,7 @@ static int dlm_pick_recovery_master(struct dlm_ctxt *dlm) mlog(0, "starting recovery of %s at %lu, dead=%u, this=%u\n", dlm->name, jiffies, dlm->reco.dead_node, dlm->node_num); -again: +again: memset(&lksb, 0, sizeof(lksb)); ret = dlmlock(dlm, LKM_EXMODE, &lksb, LKM_NOQUEUE|LKM_RECOVERY, @@ -2437,8 +2492,8 @@ again: if (ret == DLM_NORMAL) { mlog(0, "dlm=%s dlmlock says I got it (this=%u)\n", dlm->name, dlm->node_num); - - /* got the EX lock. check to see if another node + + /* got the EX lock. check to see if another node * just became the reco master */ if (dlm_reco_master_ready(dlm)) { mlog(0, "%s: got reco EX lock, but %u will " @@ -2451,12 +2506,12 @@ again: /* see if recovery was already finished elsewhere */ spin_lock(&dlm->spinlock); if (dlm->reco.dead_node == O2NM_INVALID_NODE_NUM) { - status = -EINVAL; + status = -EINVAL; mlog(0, "%s: got reco EX lock, but " "node got recovered already\n", dlm->name); if (dlm->reco.new_master != O2NM_INVALID_NODE_NUM) { mlog(ML_ERROR, "%s: new master is %u " - "but no dead node!\n", + "but no dead node!\n", dlm->name, dlm->reco.new_master); BUG(); } @@ -2468,7 +2523,7 @@ again: * set the master and send the messages to begin recovery */ if (!status) { mlog(0, "%s: dead=%u, this=%u, sending " - "begin_reco now\n", dlm->name, + "begin_reco now\n", dlm->name, dlm->reco.dead_node, dlm->node_num); status = dlm_send_begin_reco_message(dlm, dlm->reco.dead_node); @@ -2501,7 +2556,7 @@ again: mlog(0, "dlm=%s dlmlock says another node got it (this=%u)\n", dlm->name, dlm->node_num); /* another node is master. wait on - * reco.new_master != O2NM_INVALID_NODE_NUM + * reco.new_master != O2NM_INVALID_NODE_NUM * for at most one second */ wait_event_timeout(dlm->dlm_reco_thread_wq, dlm_reco_master_ready(dlm), @@ -2589,7 +2644,13 @@ retry: "begin reco msg (%d)\n", dlm->name, nodenum, ret); ret = 0; } - if (ret == -EAGAIN) { + + /* + * Prior to commit aad1b15310b9bcd59fa81ab8f2b1513b59553ea8, + * dlm_begin_reco_handler() returned EAGAIN and not -EAGAIN. + * We are handling both for compatibility reasons. + */ + if (ret == -EAGAIN || ret == EAGAIN) { mlog(0, "%s: trying to start recovery of node " "%u, but node %u is waiting for last recovery " "to complete, backoff for a bit\n", dlm->name, @@ -2599,7 +2660,7 @@ retry: } if (ret < 0) { struct dlm_lock_resource *res; - /* this is now a serious problem, possibly ENOMEM + /* this is now a serious problem, possibly ENOMEM * in the network stack. must retry */ mlog_errno(ret); mlog(ML_ERROR, "begin reco of dlm %s to node %u " @@ -2612,7 +2673,7 @@ retry: } else { mlog(ML_ERROR, "recovery lock not found\n"); } - /* sleep for a bit in hopes that we can avoid + /* sleep for a bit in hopes that we can avoid * another ENOMEM */ msleep(100); goto retry; @@ -2664,7 +2725,7 @@ int dlm_begin_reco_handler(struct o2net_msg *msg, u32 len, void *data, } if (dlm->reco.dead_node != O2NM_INVALID_NODE_NUM) { mlog(ML_NOTICE, "%s: dead_node previously set to %u, " - "node %u changing it to %u\n", dlm->name, + "node %u changing it to %u\n", dlm->name, dlm->reco.dead_node, br->node_idx, br->dead_node); } dlm_set_reco_master(dlm, br->node_idx); @@ -2730,8 +2791,8 @@ stage2: if (ret < 0) { mlog_errno(ret); if (dlm_is_host_down(ret)) { - /* this has no effect on this recovery - * session, so set the status to zero to + /* this has no effect on this recovery + * session, so set the status to zero to * finish out the last recovery */ mlog(ML_ERROR, "node %u went down after this " "node finished recovery.\n", nodenum); @@ -2768,7 +2829,7 @@ int dlm_finalize_reco_handler(struct o2net_msg *msg, u32 len, void *data, mlog(0, "%s: node %u finalizing recovery stage%d of " "node %u (%u:%u)\n", dlm->name, fr->node_idx, stage, fr->dead_node, dlm->reco.dead_node, dlm->reco.new_master); - + spin_lock(&dlm->spinlock); if (dlm->reco.new_master != fr->node_idx) { diff --git a/fs/ocfs2/dlm/dlmunlock.c b/fs/ocfs2/dlm/dlmunlock.c index 00f53b2aea76..49e29ecd0201 100644 --- a/fs/ocfs2/dlm/dlmunlock.c +++ b/fs/ocfs2/dlm/dlmunlock.c @@ -190,8 +190,8 @@ static enum dlm_status dlmunlock_common(struct dlm_ctxt *dlm, actions &= ~(DLM_UNLOCK_REMOVE_LOCK| DLM_UNLOCK_REGRANT_LOCK| DLM_UNLOCK_CLEAR_CONVERT_TYPE); - } else if (status == DLM_RECOVERING || - status == DLM_MIGRATING || + } else if (status == DLM_RECOVERING || + status == DLM_MIGRATING || status == DLM_FORWARD) { /* must clear the actions because this unlock * is about to be retried. cannot free or do @@ -661,14 +661,14 @@ retry: if (call_ast) { mlog(0, "calling unlockast(%p, %d)\n", data, status); if (is_master) { - /* it is possible that there is one last bast + /* it is possible that there is one last bast * pending. make sure it is flushed, then * call the unlockast. * not an issue if this is a mastered remotely, * since this lock has been removed from the * lockres queues and cannot be found. */ dlm_kick_thread(dlm, NULL); - wait_event(dlm->ast_wq, + wait_event(dlm->ast_wq, dlm_lock_basts_flushed(dlm, lock)); } (*unlockast)(data, status); diff --git a/fs/ocfs2/dlmglue.c b/fs/ocfs2/dlmglue.c index c5e4a49e3a12..e044019cb3b1 100644 --- a/fs/ocfs2/dlmglue.c +++ b/fs/ocfs2/dlmglue.c @@ -875,6 +875,14 @@ static inline void ocfs2_generic_handle_convert_action(struct ocfs2_lock_res *lo lockres_or_flags(lockres, OCFS2_LOCK_NEEDS_REFRESH); lockres->l_level = lockres->l_requested; + + /* + * We set the OCFS2_LOCK_UPCONVERT_FINISHING flag before clearing + * the OCFS2_LOCK_BUSY flag to prevent the dc thread from + * downconverting the lock before the upconvert has fully completed. + */ + lockres_or_flags(lockres, OCFS2_LOCK_UPCONVERT_FINISHING); + lockres_clear_flags(lockres, OCFS2_LOCK_BUSY); mlog_exit_void(); @@ -907,8 +915,6 @@ static int ocfs2_generic_handle_bast(struct ocfs2_lock_res *lockres, assert_spin_locked(&lockres->l_lock); - lockres_or_flags(lockres, OCFS2_LOCK_BLOCKED); - if (level > lockres->l_blocking) { /* only schedule a downconvert if we haven't already scheduled * one that goes low enough to satisfy the level we're @@ -921,6 +927,9 @@ static int ocfs2_generic_handle_bast(struct ocfs2_lock_res *lockres, lockres->l_blocking = level; } + if (needs_downconvert) + lockres_or_flags(lockres, OCFS2_LOCK_BLOCKED); + mlog_exit(needs_downconvert); return needs_downconvert; } @@ -1133,6 +1142,7 @@ static inline void ocfs2_recover_from_dlm_error(struct ocfs2_lock_res *lockres, mlog_entry_void(); spin_lock_irqsave(&lockres->l_lock, flags); lockres_clear_flags(lockres, OCFS2_LOCK_BUSY); + lockres_clear_flags(lockres, OCFS2_LOCK_UPCONVERT_FINISHING); if (convert) lockres->l_action = OCFS2_AST_INVALID; else @@ -1323,13 +1333,13 @@ static int __ocfs2_cluster_lock(struct ocfs2_super *osb, again: wait = 0; + spin_lock_irqsave(&lockres->l_lock, flags); + if (catch_signals && signal_pending(current)) { ret = -ERESTARTSYS; - goto out; + goto unlock; } - spin_lock_irqsave(&lockres->l_lock, flags); - mlog_bug_on_msg(lockres->l_flags & OCFS2_LOCK_FREEING, "Cluster lock called on freeing lockres %s! flags " "0x%lx\n", lockres->l_name, lockres->l_flags); @@ -1346,6 +1356,25 @@ again: goto unlock; } + if (lockres->l_flags & OCFS2_LOCK_UPCONVERT_FINISHING) { + /* + * We've upconverted. If the lock now has a level we can + * work with, we take it. If, however, the lock is not at the + * required level, we go thru the full cycle. One way this could + * happen is if a process requesting an upconvert to PR is + * closely followed by another requesting upconvert to an EX. + * If the process requesting EX lands here, we want it to + * continue attempting to upconvert and let the process + * requesting PR take the lock. + * If multiple processes request upconvert to PR, the first one + * here will take the lock. The others will have to go thru the + * OCFS2_LOCK_BLOCKED check to ensure that there is no pending + * downconvert request. + */ + if (level <= lockres->l_level) + goto update_holders; + } + if (lockres->l_flags & OCFS2_LOCK_BLOCKED && !ocfs2_may_continue_on_blocked_lock(lockres, level)) { /* is the lock is currently blocked on behalf of @@ -1416,11 +1445,14 @@ again: goto again; } +update_holders: /* Ok, if we get here then we're good to go. */ ocfs2_inc_holders(lockres, level); ret = 0; unlock: + lockres_clear_flags(lockres, OCFS2_LOCK_UPCONVERT_FINISHING); + spin_unlock_irqrestore(&lockres->l_lock, flags); out: /* @@ -3155,7 +3187,7 @@ out: /* Mark the lockres as being dropped. It will no longer be * queued if blocking, but we still may have to wait on it * being dequeued from the downconvert thread before we can consider - * it safe to drop. + * it safe to drop. * * You can *not* attempt to call cluster_lock on this lockres anymore. */ void ocfs2_mark_lockres_freeing(struct ocfs2_lock_res *lockres) @@ -3352,6 +3384,7 @@ static int ocfs2_unblock_lock(struct ocfs2_super *osb, unsigned long flags; int blocking; int new_level; + int level; int ret = 0; int set_lvb = 0; unsigned int gen; @@ -3360,9 +3393,17 @@ static int ocfs2_unblock_lock(struct ocfs2_super *osb, spin_lock_irqsave(&lockres->l_lock, flags); - BUG_ON(!(lockres->l_flags & OCFS2_LOCK_BLOCKED)); - recheck: + /* + * Is it still blocking? If not, we have no more work to do. + */ + if (!(lockres->l_flags & OCFS2_LOCK_BLOCKED)) { + BUG_ON(lockres->l_blocking != DLM_LOCK_NL); + spin_unlock_irqrestore(&lockres->l_lock, flags); + ret = 0; + goto leave; + } + if (lockres->l_flags & OCFS2_LOCK_BUSY) { /* XXX * This is a *big* race. The OCFS2_LOCK_PENDING flag @@ -3401,6 +3442,31 @@ recheck: goto leave; } + /* + * This prevents livelocks. OCFS2_LOCK_UPCONVERT_FINISHING flag is + * set when the ast is received for an upconvert just before the + * OCFS2_LOCK_BUSY flag is cleared. Now if the fs received a bast + * on the heels of the ast, we want to delay the downconvert just + * enough to allow the up requestor to do its task. Because this + * lock is in the blocked queue, the lock will be downconverted + * as soon as the requestor is done with the lock. + */ + if (lockres->l_flags & OCFS2_LOCK_UPCONVERT_FINISHING) + goto leave_requeue; + + /* + * How can we block and yet be at NL? We were trying to upconvert + * from NL and got canceled. The code comes back here, and now + * we notice and clear BLOCKING. + */ + if (lockres->l_level == DLM_LOCK_NL) { + BUG_ON(lockres->l_ex_holders || lockres->l_ro_holders); + lockres->l_blocking = DLM_LOCK_NL; + lockres_clear_flags(lockres, OCFS2_LOCK_BLOCKED); + spin_unlock_irqrestore(&lockres->l_lock, flags); + goto leave; + } + /* if we're blocking an exclusive and we have *any* holders, * then requeue. */ if ((lockres->l_blocking == DLM_LOCK_EX) @@ -3438,6 +3504,7 @@ recheck: * may sleep, so we save off a copy of what we're blocking as * it may change while we're not holding the spin lock. */ blocking = lockres->l_blocking; + level = lockres->l_level; spin_unlock_irqrestore(&lockres->l_lock, flags); ctl->unblock_action = lockres->l_ops->downconvert_worker(lockres, blocking); @@ -3446,7 +3513,7 @@ recheck: goto leave; spin_lock_irqsave(&lockres->l_lock, flags); - if (blocking != lockres->l_blocking) { + if ((blocking != lockres->l_blocking) || (level != lockres->l_level)) { /* If this changed underneath us, then we can't drop * it just yet. */ goto recheck; diff --git a/fs/ocfs2/export.c b/fs/ocfs2/export.c index 15713cbb865c..19ad145d2af3 100644 --- a/fs/ocfs2/export.c +++ b/fs/ocfs2/export.c @@ -239,7 +239,7 @@ static int ocfs2_encode_fh(struct dentry *dentry, u32 *fh_in, int *max_len, mlog(0, "Encoding parent: blkno: %llu, generation: %u\n", (unsigned long long)blkno, generation); } - + *max_len = len; bail: diff --git a/fs/ocfs2/extent_map.c b/fs/ocfs2/extent_map.c index d35a27f4523e..5328529e7fd2 100644 --- a/fs/ocfs2/extent_map.c +++ b/fs/ocfs2/extent_map.c @@ -192,7 +192,7 @@ static int ocfs2_try_to_merge_extent_map(struct ocfs2_extent_map_item *emi, emi->ei_clusters += ins->ei_clusters; return 1; } else if ((ins->ei_phys + ins->ei_clusters) == emi->ei_phys && - (ins->ei_cpos + ins->ei_clusters) == emi->ei_phys && + (ins->ei_cpos + ins->ei_clusters) == emi->ei_cpos && ins->ei_flags == emi->ei_flags) { emi->ei_phys = ins->ei_phys; emi->ei_cpos = ins->ei_cpos; diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c index 06ccf6a86d35..558ce0312421 100644 --- a/fs/ocfs2/file.c +++ b/fs/ocfs2/file.c @@ -749,7 +749,7 @@ static int ocfs2_write_zero_page(struct inode *inode, int ret; offset = (size & (PAGE_CACHE_SIZE-1)); /* Within page */ - /* ugh. in prepare/commit_write, if from==to==start of block, we + /* ugh. in prepare/commit_write, if from==to==start of block, we ** skip the prepare. make sure we never send an offset for the start ** of a block */ @@ -1779,7 +1779,7 @@ static int ocfs2_prepare_inode_for_write(struct dentry *dentry, struct inode *inode = dentry->d_inode; loff_t saved_pos, end; - /* + /* * We start with a read level meta lock and only jump to an ex * if we need to make modifications here. */ @@ -2013,8 +2013,8 @@ out_dio: /* buffered aio wouldn't have proper lock coverage today */ BUG_ON(ret == -EIOCBQUEUED && !(file->f_flags & O_DIRECT)); - if ((file->f_flags & O_DSYNC && !direct_io) || IS_SYNC(inode) || - (file->f_flags & O_DIRECT && has_refcount)) { + if (((file->f_flags & O_DSYNC) && !direct_io) || IS_SYNC(inode) || + ((file->f_flags & O_DIRECT) && has_refcount)) { ret = filemap_fdatawrite_range(file->f_mapping, pos, pos + count - 1); if (ret < 0) @@ -2033,7 +2033,7 @@ out_dio: pos + count - 1); } - /* + /* * deep in g_f_a_w_n()->ocfs2_direct_IO we pass in a ocfs2_dio_end_io * function pointer which is called when o_direct io completes so that * it can unlock our rw lock. (it's the clustered equivalent of @@ -2198,7 +2198,7 @@ static ssize_t ocfs2_file_aio_read(struct kiocb *iocb, goto bail; } - /* + /* * buffered reads protect themselves in ->readpage(). O_DIRECT reads * need locks to protect pending reads from racing with truncate. */ @@ -2220,10 +2220,10 @@ static ssize_t ocfs2_file_aio_read(struct kiocb *iocb, * We're fine letting folks race truncates and extending * writes with read across the cluster, just like they can * locally. Hence no rw_lock during read. - * + * * Take and drop the meta data lock to update inode fields * like i_size. This allows the checks down below - * generic_file_aio_read() a chance of actually working. + * generic_file_aio_read() a chance of actually working. */ ret = ocfs2_inode_lock_atime(inode, filp->f_vfsmnt, &lock_level); if (ret < 0) { @@ -2248,7 +2248,7 @@ static ssize_t ocfs2_file_aio_read(struct kiocb *iocb, bail: if (have_alloc_sem) up_read(&inode->i_alloc_sem); - if (rw_level != -1) + if (rw_level != -1) ocfs2_rw_unlock(inode, rw_level); mlog_exit(ret); diff --git a/fs/ocfs2/inode.c b/fs/ocfs2/inode.c index 0297fb8982b8..88459bdd1ff3 100644 --- a/fs/ocfs2/inode.c +++ b/fs/ocfs2/inode.c @@ -475,7 +475,7 @@ static int ocfs2_read_locked_inode(struct inode *inode, if (args->fi_flags & OCFS2_FI_FLAG_ORPHAN_RECOVERY) { status = ocfs2_try_open_lock(inode, 0); if (status) { - make_bad_inode(inode); + make_bad_inode(inode); return status; } } @@ -684,7 +684,7 @@ bail: return status; } -/* +/* * Serialize with orphan dir recovery. If the process doing * recovery on this orphan dir does an iget() with the dir * i_mutex held, we'll deadlock here. Instead we detect this diff --git a/fs/ocfs2/ioctl.c b/fs/ocfs2/ioctl.c index 31fbb0619510..7d9d9c132cef 100644 --- a/fs/ocfs2/ioctl.c +++ b/fs/ocfs2/ioctl.c @@ -7,6 +7,7 @@ #include <linux/fs.h> #include <linux/mount.h> +#include <linux/compat.h> #define MLOG_MASK_PREFIX ML_INODE #include <cluster/masklog.h> @@ -181,6 +182,10 @@ long ocfs2_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) #ifdef CONFIG_COMPAT long ocfs2_compat_ioctl(struct file *file, unsigned cmd, unsigned long arg) { + bool preserve; + struct reflink_arguments args; + struct inode *inode = file->f_path.dentry->d_inode; + switch (cmd) { case OCFS2_IOC32_GETFLAGS: cmd = OCFS2_IOC_GETFLAGS; @@ -195,8 +200,15 @@ long ocfs2_compat_ioctl(struct file *file, unsigned cmd, unsigned long arg) case OCFS2_IOC_GROUP_EXTEND: case OCFS2_IOC_GROUP_ADD: case OCFS2_IOC_GROUP_ADD64: - case OCFS2_IOC_REFLINK: break; + case OCFS2_IOC_REFLINK: + if (copy_from_user(&args, (struct reflink_arguments *)arg, + sizeof(args))) + return -EFAULT; + preserve = (args.preserve != 0); + + return ocfs2_reflink_ioctl(inode, compat_ptr(args.old_path), + compat_ptr(args.new_path), preserve); default: return -ENOIOCTLCMD; } diff --git a/fs/ocfs2/journal.c b/fs/ocfs2/journal.c index bf34c491ae96..9336c60e3a36 100644 --- a/fs/ocfs2/journal.c +++ b/fs/ocfs2/journal.c @@ -2034,7 +2034,7 @@ static int ocfs2_queue_orphans(struct ocfs2_super *osb, status = -ENOENT; mlog_errno(status); return status; - } + } mutex_lock(&orphan_dir_inode->i_mutex); status = ocfs2_inode_lock(orphan_dir_inode, NULL, 0); diff --git a/fs/ocfs2/ocfs2.h b/fs/ocfs2/ocfs2.h index 9362eea7424b..740f448041e2 100644 --- a/fs/ocfs2/ocfs2.h +++ b/fs/ocfs2/ocfs2.h @@ -136,6 +136,10 @@ enum ocfs2_unlock_action { #define OCFS2_LOCK_PENDING (0x00000400) /* This lockres is pending a call to dlm_lock. Only exists with BUSY set. */ +#define OCFS2_LOCK_UPCONVERT_FINISHING (0x00000800) /* blocks the dc thread + * from downconverting + * before the upconvert + * has completed */ struct ocfs2_lock_res_ops; diff --git a/fs/ocfs2/ocfs2_fs.h b/fs/ocfs2/ocfs2_fs.h index 1a1a679e51b5..7638a38c32bc 100644 --- a/fs/ocfs2/ocfs2_fs.h +++ b/fs/ocfs2/ocfs2_fs.h @@ -1417,9 +1417,16 @@ static inline int ocfs2_fast_symlink_chars(int blocksize) return blocksize - offsetof(struct ocfs2_dinode, id2.i_symlink); } -static inline int ocfs2_max_inline_data(int blocksize) +static inline int ocfs2_max_inline_data_with_xattr(int blocksize, + struct ocfs2_dinode *di) { - return blocksize - offsetof(struct ocfs2_dinode, id2.i_data.id_data); + if (di && (di->i_dyn_features & OCFS2_INLINE_XATTR_FL)) + return blocksize - + offsetof(struct ocfs2_dinode, id2.i_data.id_data) - + di->i_xattr_inline_size; + else + return blocksize - + offsetof(struct ocfs2_dinode, id2.i_data.id_data); } static inline int ocfs2_extent_recs_per_inode(int blocksize) diff --git a/fs/ocfs2/refcounttree.c b/fs/ocfs2/refcounttree.c index 74db2be75dd6..8ae65c9c020c 100644 --- a/fs/ocfs2/refcounttree.c +++ b/fs/ocfs2/refcounttree.c @@ -2945,7 +2945,7 @@ static int ocfs2_duplicate_clusters_by_page(handle_t *handle, while (offset < end) { page_index = offset >> PAGE_CACHE_SHIFT; - map_end = (page_index + 1) << PAGE_CACHE_SHIFT; + map_end = ((loff_t)page_index + 1) << PAGE_CACHE_SHIFT; if (map_end > end) map_end = end; @@ -2957,8 +2957,12 @@ static int ocfs2_duplicate_clusters_by_page(handle_t *handle, page = grab_cache_page(mapping, page_index); - /* This page can't be dirtied before we CoW it out. */ - BUG_ON(PageDirty(page)); + /* + * In case PAGE_CACHE_SIZE <= CLUSTER_SIZE, This page + * can't be dirtied before we CoW it out. + */ + if (PAGE_CACHE_SIZE <= OCFS2_SB(sb)->s_clustersize) + BUG_ON(PageDirty(page)); if (!PageUptodate(page)) { ret = block_read_full_page(page, ocfs2_get_block); @@ -3170,7 +3174,7 @@ static int ocfs2_cow_sync_writeback(struct super_block *sb, while (offset < end) { page_index = offset >> PAGE_CACHE_SHIFT; - map_end = (page_index + 1) << PAGE_CACHE_SHIFT; + map_end = ((loff_t)page_index + 1) << PAGE_CACHE_SHIFT; if (map_end > end) map_end = end; diff --git a/fs/ocfs2/stack_o2cb.c b/fs/ocfs2/stack_o2cb.c index e49c41050264..3038c92af493 100644 --- a/fs/ocfs2/stack_o2cb.c +++ b/fs/ocfs2/stack_o2cb.c @@ -277,7 +277,7 @@ static int o2cb_cluster_connect(struct ocfs2_cluster_connection *conn) u32 dlm_key; struct dlm_ctxt *dlm; struct o2dlm_private *priv; - struct dlm_protocol_version dlm_version; + struct dlm_protocol_version fs_version; BUG_ON(conn == NULL); BUG_ON(o2cb_stack.sp_proto == NULL); @@ -304,18 +304,18 @@ static int o2cb_cluster_connect(struct ocfs2_cluster_connection *conn) /* used by the dlm code to make message headers unique, each * node in this domain must agree on this. */ dlm_key = crc32_le(0, conn->cc_name, conn->cc_namelen); - dlm_version.pv_major = conn->cc_version.pv_major; - dlm_version.pv_minor = conn->cc_version.pv_minor; + fs_version.pv_major = conn->cc_version.pv_major; + fs_version.pv_minor = conn->cc_version.pv_minor; - dlm = dlm_register_domain(conn->cc_name, dlm_key, &dlm_version); + dlm = dlm_register_domain(conn->cc_name, dlm_key, &fs_version); if (IS_ERR(dlm)) { rc = PTR_ERR(dlm); mlog_errno(rc); goto out_free; } - conn->cc_version.pv_major = dlm_version.pv_major; - conn->cc_version.pv_minor = dlm_version.pv_minor; + conn->cc_version.pv_major = fs_version.pv_major; + conn->cc_version.pv_minor = fs_version.pv_minor; conn->cc_lockspace = dlm; dlm_register_eviction_cb(dlm, &priv->op_eviction_cb); diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index 26069917a9f5..755cd49a5ef3 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -1062,7 +1062,7 @@ static int ocfs2_fill_super(struct super_block *sb, void *data, int silent) "file system, but write access is " "unavailable.\n"); else - mlog_errno(status); + mlog_errno(status); goto read_super_error; } diff --git a/fs/ocfs2/symlink.c b/fs/ocfs2/symlink.c index 49b133ccbf11..32499d213fc4 100644 --- a/fs/ocfs2/symlink.c +++ b/fs/ocfs2/symlink.c @@ -137,20 +137,20 @@ static void *ocfs2_fast_follow_link(struct dentry *dentry, } memcpy(link, target, len); - nd_set_link(nd, link); bail: + nd_set_link(nd, status ? ERR_PTR(status) : link); brelse(bh); mlog_exit(status); - return status ? ERR_PTR(status) : link; + return NULL; } static void ocfs2_fast_put_link(struct dentry *dentry, struct nameidata *nd, void *cookie) { - char *link = cookie; - - kfree(link); + char *link = nd_get_link(nd); + if (!IS_ERR(link)) + kfree(link); } const struct inode_operations ocfs2_symlink_inode_operations = { diff --git a/fs/ocfs2/uptodate.c b/fs/ocfs2/uptodate.c index c61369342a27..a0a120e82b97 100644 --- a/fs/ocfs2/uptodate.c +++ b/fs/ocfs2/uptodate.c @@ -267,8 +267,8 @@ static int ocfs2_buffer_cached(struct ocfs2_caching_info *ci, } /* Warning: even if it returns true, this does *not* guarantee that - * the block is stored in our inode metadata cache. - * + * the block is stored in our inode metadata cache. + * * This can be called under lock_buffer() */ int ocfs2_buffer_uptodate(struct ocfs2_caching_info *ci, diff --git a/fs/reiserfs/inode.c b/fs/reiserfs/inode.c index 9087b10209e6..2df0f5c7c60b 100644 --- a/fs/reiserfs/inode.c +++ b/fs/reiserfs/inode.c @@ -1497,9 +1497,11 @@ struct inode *reiserfs_iget(struct super_block *s, const struct cpu_key *key) args.objectid = key->on_disk_key.k_objectid; args.dirid = key->on_disk_key.k_dir_id; + reiserfs_write_unlock(s); inode = iget5_locked(s, key->on_disk_key.k_objectid, reiserfs_find_actor, reiserfs_init_locked_inode, (void *)(&args)); + reiserfs_write_lock(s); if (!inode) return ERR_PTR(-ENOMEM); diff --git a/fs/sysfs/inode.c b/fs/sysfs/inode.c index 220b758523ae..6a06a1d1ea7b 100644 --- a/fs/sysfs/inode.c +++ b/fs/sysfs/inode.c @@ -81,24 +81,23 @@ int sysfs_sd_setattr(struct sysfs_dirent *sd, struct iattr * iattr) if (!sd_attrs) return -ENOMEM; sd->s_iattr = sd_attrs; - } else { - /* attributes were changed at least once in past */ - iattrs = &sd_attrs->ia_iattr; - - if (ia_valid & ATTR_UID) - iattrs->ia_uid = iattr->ia_uid; - if (ia_valid & ATTR_GID) - iattrs->ia_gid = iattr->ia_gid; - if (ia_valid & ATTR_ATIME) - iattrs->ia_atime = iattr->ia_atime; - if (ia_valid & ATTR_MTIME) - iattrs->ia_mtime = iattr->ia_mtime; - if (ia_valid & ATTR_CTIME) - iattrs->ia_ctime = iattr->ia_ctime; - if (ia_valid & ATTR_MODE) { - umode_t mode = iattr->ia_mode; - iattrs->ia_mode = sd->s_mode = mode; - } + } + /* attributes were changed at least once in past */ + iattrs = &sd_attrs->ia_iattr; + + if (ia_valid & ATTR_UID) + iattrs->ia_uid = iattr->ia_uid; + if (ia_valid & ATTR_GID) + iattrs->ia_gid = iattr->ia_gid; + if (ia_valid & ATTR_ATIME) + iattrs->ia_atime = iattr->ia_atime; + if (ia_valid & ATTR_MTIME) + iattrs->ia_mtime = iattr->ia_mtime; + if (ia_valid & ATTR_CTIME) + iattrs->ia_ctime = iattr->ia_ctime; + if (ia_valid & ATTR_MODE) { + umode_t mode = iattr->ia_mode; + iattrs->ia_mode = sd->s_mode = mode; } return 0; } diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h index 1e67c441ea82..f745948b61e4 100644 --- a/include/drm/nouveau_drm.h +++ b/include/drm/nouveau_drm.h @@ -77,6 +77,7 @@ struct drm_nouveau_gpuobj_free { #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10 #define NOUVEAU_GETPARAM_CHIPSET_ID 11 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 +#define NOUVEAU_GETPARAM_GRAPH_UNITS 13 struct drm_nouveau_getparam { uint64_t param; uint64_t value; diff --git a/include/drm/vmwgfx_drm.h b/include/drm/vmwgfx_drm.h index 2be7e1249b6f..c7645f480d12 100644 --- a/include/drm/vmwgfx_drm.h +++ b/include/drm/vmwgfx_drm.h @@ -68,7 +68,8 @@ #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 #define DRM_VMW_PARAM_3D 2 #define DRM_VMW_PARAM_FIFO_OFFSET 3 - +#define DRM_VMW_PARAM_HW_CAPS 4 +#define DRM_VMW_PARAM_FIFO_CAPS 5 /** * struct drm_vmw_getparam_arg @@ -181,6 +182,8 @@ struct drm_vmw_context_arg { * The size of the array should equal the total number of mipmap levels. * @shareable: Boolean whether other clients (as identified by file descriptors) * may reference this surface. + * @scanout: Boolean whether the surface is intended to be used as a + * scanout. * * Input data to the DRM_VMW_CREATE_SURFACE Ioctl. * Output data from the DRM_VMW_REF_SURFACE Ioctl. @@ -192,7 +195,7 @@ struct drm_vmw_surface_create_req { uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; uint64_t size_addr; int32_t shareable; - uint32_t pad64; + int32_t scanout; }; /** @@ -295,17 +298,28 @@ union drm_vmw_surface_reference_arg { * * @commands: User-space address of a command buffer cast to an uint64_t. * @command-size: Size in bytes of the command buffer. + * @throttle-us: Sleep until software is less than @throttle_us + * microseconds ahead of hardware. The driver may round this value + * to the nearest kernel tick. * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an * uint64_t. + * @version: Allows expanding the execbuf ioctl parameters without breaking + * backwards compatibility, since user-space will always tell the kernel + * which version it uses. + * @flags: Execbuf flags. None currently. * * Argument to the DRM_VMW_EXECBUF Ioctl. */ +#define DRM_VMW_EXECBUF_VERSION 0 + struct drm_vmw_execbuf_arg { uint64_t commands; uint32_t command_size; - uint32_t pad64; + uint32_t throttle_us; uint64_t fence_rep; + uint32_t version; + uint32_t flags; }; /** diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h index ab94335b4bb9..6816be6c3f77 100644 --- a/include/linux/amba/bus.h +++ b/include/linux/amba/bus.h @@ -1,5 +1,9 @@ /* - * linux/include/asm-arm/hardware/amba.h + * linux/include/amba/bus.h + * + * This device type deals with ARM PrimeCells and anything else that + * presents a proper CID (0xB105F00D) at the end of the I/O register + * region or that is derived from a PrimeCell. * * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved. * diff --git a/include/linux/hw_breakpoint.h b/include/linux/hw_breakpoint.h index 070ba0621738..5977b724f7c6 100644 --- a/include/linux/hw_breakpoint.h +++ b/include/linux/hw_breakpoint.h @@ -44,7 +44,7 @@ static inline int hw_breakpoint_type(struct perf_event *bp) return bp->attr.bp_type; } -static inline int hw_breakpoint_len(struct perf_event *bp) +static inline unsigned long hw_breakpoint_len(struct perf_event *bp) { return bp->attr.bp_len; } diff --git a/include/linux/input.h b/include/linux/input.h index 735ceaf1bc2d..663208afb64c 100644 --- a/include/linux/input.h +++ b/include/linux/input.h @@ -376,6 +376,7 @@ struct input_absinfo { #define KEY_DISPLAY_OFF 245 /* display device to off state */ #define KEY_WIMAX 246 +#define KEY_RFKILL 247 /* Key that controls all radios */ /* Range 248 - 255 is reserved for special needs of AT keyboard driver */ diff --git a/include/linux/kfifo.h b/include/linux/kfifo.h index 6f6c5f300af6..bc0fc795bd35 100644 --- a/include/linux/kfifo.h +++ b/include/linux/kfifo.h @@ -124,7 +124,7 @@ extern __must_check unsigned int kfifo_out_peek(struct kfifo *fifo, */ static inline bool kfifo_initialized(struct kfifo *fifo) { - return fifo->buffer != 0; + return fifo->buffer != NULL; } /** diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 8fa71874113f..a177698d95e2 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -211,11 +211,9 @@ struct perf_event_attr { __u32 wakeup_watermark; /* bytes before wakeup */ }; - __u32 __reserved_2; - - __u64 bp_addr; __u32 bp_type; - __u32 bp_len; + __u64 bp_addr; + __u64 bp_len; }; /* diff --git a/include/net/netns/conntrack.h b/include/net/netns/conntrack.h index ba1ba0c5efd1..63d449807d9b 100644 --- a/include/net/netns/conntrack.h +++ b/include/net/netns/conntrack.h @@ -11,6 +11,8 @@ struct nf_conntrack_ecache; struct netns_ct { atomic_t count; unsigned int expect_count; + unsigned int htable_size; + struct kmem_cache *nf_conntrack_cachep; struct hlist_nulls_head *hash; struct hlist_head *expect_hash; struct hlist_nulls_head unconfirmed; @@ -28,5 +30,6 @@ struct netns_ct { #endif int hash_vmalloc; int expect_vmalloc; + char *slabname; }; #endif diff --git a/include/net/netns/ipv4.h b/include/net/netns/ipv4.h index 2eb3814d6258..9a4b8b714079 100644 --- a/include/net/netns/ipv4.h +++ b/include/net/netns/ipv4.h @@ -40,6 +40,7 @@ struct netns_ipv4 { struct xt_table *iptable_security; struct xt_table *nat_table; struct hlist_head *nat_bysource; + unsigned int nat_htable_size; int nat_vmalloced; #endif diff --git a/kernel/hw_breakpoint.c b/kernel/hw_breakpoint.c index 8a5c7d55ac9f..967e66143e11 100644 --- a/kernel/hw_breakpoint.c +++ b/kernel/hw_breakpoint.c @@ -360,8 +360,8 @@ EXPORT_SYMBOL_GPL(register_user_hw_breakpoint); int modify_user_hw_breakpoint(struct perf_event *bp, struct perf_event_attr *attr) { u64 old_addr = bp->attr.bp_addr; + u64 old_len = bp->attr.bp_len; int old_type = bp->attr.bp_type; - int old_len = bp->attr.bp_len; int err = 0; perf_event_disable(bp); diff --git a/kernel/kfifo.c b/kernel/kfifo.c index 498cabba225e..35edbe22e9a9 100644 --- a/kernel/kfifo.c +++ b/kernel/kfifo.c @@ -80,7 +80,7 @@ int kfifo_alloc(struct kfifo *fifo, unsigned int size, gfp_t gfp_mask) buffer = kmalloc(size, gfp_mask); if (!buffer) { - _kfifo_init(fifo, 0, 0); + _kfifo_init(fifo, NULL, 0); return -ENOMEM; } @@ -97,6 +97,7 @@ EXPORT_SYMBOL(kfifo_alloc); void kfifo_free(struct kfifo *fifo) { kfree(fifo->buffer); + _kfifo_init(fifo, NULL, 0); } EXPORT_SYMBOL(kfifo_free); diff --git a/kernel/perf_event.c b/kernel/perf_event.c index d27746bd3a06..2b19297742cb 100644 --- a/kernel/perf_event.c +++ b/kernel/perf_event.c @@ -4580,7 +4580,7 @@ static int perf_copy_attr(struct perf_event_attr __user *uattr, if (attr->type >= PERF_TYPE_MAX) return -EINVAL; - if (attr->__reserved_1 || attr->__reserved_2) + if (attr->__reserved_1) return -EINVAL; if (attr->sample_type & ~(PERF_SAMPLE_MAX-1)) diff --git a/kernel/softirq.c b/kernel/softirq.c index a09502e2ef75..7c1a67ef0274 100644 --- a/kernel/softirq.c +++ b/kernel/softirq.c @@ -500,22 +500,17 @@ EXPORT_SYMBOL(tasklet_kill); */ /* - * The trampoline is called when the hrtimer expires. If this is - * called from the hrtimer interrupt then we schedule the tasklet as - * the timer callback function expects to run in softirq context. If - * it's called in softirq context anyway (i.e. high resolution timers - * disabled) then the hrtimer callback is called right away. + * The trampoline is called when the hrtimer expires. It schedules a tasklet + * to run __tasklet_hrtimer_trampoline() which in turn will call the intended + * hrtimer callback, but from softirq context. */ static enum hrtimer_restart __hrtimer_tasklet_trampoline(struct hrtimer *timer) { struct tasklet_hrtimer *ttimer = container_of(timer, struct tasklet_hrtimer, timer); - if (hrtimer_is_hres_active(timer)) { - tasklet_hi_schedule(&ttimer->tasklet); - return HRTIMER_NORESTART; - } - return ttimer->function(timer); + tasklet_hi_schedule(&ttimer->tasklet); + return HRTIMER_NORESTART; } /* diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index 7faaa32fbf4f..e2ab064c6d41 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -880,6 +880,7 @@ void getboottime(struct timespec *ts) set_normalized_timespec(ts, -boottime.tv_sec, -boottime.tv_nsec); } +EXPORT_SYMBOL_GPL(getboottime); /** * monotonic_to_bootbased - Convert the monotonic time to boot based. @@ -889,6 +890,7 @@ void monotonic_to_bootbased(struct timespec *ts) { *ts = timespec_add_safe(*ts, total_sleep_time); } +EXPORT_SYMBOL_GPL(monotonic_to_bootbased); unsigned long get_seconds(void) { diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c index 6ea90c0e2c96..50b1b8239806 100644 --- a/kernel/trace/trace_kprobe.c +++ b/kernel/trace/trace_kprobe.c @@ -689,7 +689,7 @@ static int create_trace_probe(int argc, char **argv) return -EINVAL; } /* an address specified */ - ret = strict_strtoul(&argv[0][2], 0, (unsigned long *)&addr); + ret = strict_strtoul(&argv[1][0], 0, (unsigned long *)&addr); if (ret) { pr_info("Failed to parse address.\n"); return ret; diff --git a/kernel/trace/trace_stack.c b/kernel/trace/trace_stack.c index 678a5120ee30..f4bc9b27de5f 100644 --- a/kernel/trace/trace_stack.c +++ b/kernel/trace/trace_stack.c @@ -157,6 +157,7 @@ stack_max_size_write(struct file *filp, const char __user *ubuf, unsigned long val, flags; char buf[64]; int ret; + int cpu; if (count >= sizeof(buf)) return -EINVAL; @@ -171,9 +172,20 @@ stack_max_size_write(struct file *filp, const char __user *ubuf, return ret; local_irq_save(flags); + + /* + * In case we trace inside arch_spin_lock() or after (NMI), + * we will cause circular lock, so we also need to increase + * the percpu trace_active here. + */ + cpu = smp_processor_id(); + per_cpu(trace_active, cpu)++; + arch_spin_lock(&max_stack_lock); *ptr = val; arch_spin_unlock(&max_stack_lock); + + per_cpu(trace_active, cpu)--; local_irq_restore(flags); return count; @@ -206,7 +218,13 @@ t_next(struct seq_file *m, void *v, loff_t *pos) static void *t_start(struct seq_file *m, loff_t *pos) { + int cpu; + local_irq_disable(); + + cpu = smp_processor_id(); + per_cpu(trace_active, cpu)++; + arch_spin_lock(&max_stack_lock); if (*pos == 0) @@ -217,7 +235,13 @@ static void *t_start(struct seq_file *m, loff_t *pos) static void t_stop(struct seq_file *m, void *p) { + int cpu; + arch_spin_unlock(&max_stack_lock); + + cpu = smp_processor_id(); + per_cpu(trace_active, cpu)--; + local_irq_enable(); } diff --git a/net/9p/client.c b/net/9p/client.c index 8af95b2dddd6..09d4f1e2e4a8 100644 --- a/net/9p/client.c +++ b/net/9p/client.c @@ -69,7 +69,7 @@ p9_client_rpc(struct p9_client *c, int8_t type, const char *fmt, ...); static int parse_opts(char *opts, struct p9_client *clnt) { - char *options; + char *options, *tmp_options; char *p; substring_t args[MAX_OPT_ARGS]; int option; @@ -81,12 +81,13 @@ static int parse_opts(char *opts, struct p9_client *clnt) if (!opts) return 0; - options = kstrdup(opts, GFP_KERNEL); - if (!options) { + tmp_options = kstrdup(opts, GFP_KERNEL); + if (!tmp_options) { P9_DPRINTK(P9_DEBUG_ERROR, "failed to allocate copy of option string\n"); return -ENOMEM; } + options = tmp_options; while ((p = strsep(&options, ",")) != NULL) { int token; @@ -108,6 +109,13 @@ static int parse_opts(char *opts, struct p9_client *clnt) break; case Opt_trans: clnt->trans_mod = v9fs_get_trans_by_name(&args[0]); + if(clnt->trans_mod == NULL) { + P9_DPRINTK(P9_DEBUG_ERROR, + "Could not find request transport: %s\n", + (char *) &args[0]); + ret = -EINVAL; + goto free_and_return; + } break; case Opt_legacy: clnt->dotu = 0; @@ -117,7 +125,8 @@ static int parse_opts(char *opts, struct p9_client *clnt) } } - kfree(options); +free_and_return: + kfree(tmp_options); return ret; } @@ -667,18 +676,12 @@ struct p9_client *p9_client_create(const char *dev_name, char *options) clnt->trans = NULL; spin_lock_init(&clnt->lock); INIT_LIST_HEAD(&clnt->fidlist); - clnt->fidpool = p9_idpool_create(); - if (IS_ERR(clnt->fidpool)) { - err = PTR_ERR(clnt->fidpool); - clnt->fidpool = NULL; - goto error; - } p9_tag_init(clnt); err = parse_opts(options, clnt); if (err < 0) - goto error; + goto free_client; if (!clnt->trans_mod) clnt->trans_mod = v9fs_get_default_trans(); @@ -687,7 +690,14 @@ struct p9_client *p9_client_create(const char *dev_name, char *options) err = -EPROTONOSUPPORT; P9_DPRINTK(P9_DEBUG_ERROR, "No transport defined or default transport\n"); - goto error; + goto free_client; + } + + clnt->fidpool = p9_idpool_create(); + if (IS_ERR(clnt->fidpool)) { + err = PTR_ERR(clnt->fidpool); + clnt->fidpool = NULL; + goto put_trans; } P9_DPRINTK(P9_DEBUG_MUX, "clnt %p trans %p msize %d dotu %d\n", @@ -695,19 +705,25 @@ struct p9_client *p9_client_create(const char *dev_name, char *options) err = clnt->trans_mod->create(clnt, dev_name, options); if (err) - goto error; + goto destroy_fidpool; if ((clnt->msize+P9_IOHDRSZ) > clnt->trans_mod->maxsize) clnt->msize = clnt->trans_mod->maxsize-P9_IOHDRSZ; err = p9_client_version(clnt); if (err) - goto error; + goto close_trans; return clnt; -error: - p9_client_destroy(clnt); +close_trans: + clnt->trans_mod->close(clnt); +destroy_fidpool: + p9_idpool_destroy(clnt->fidpool); +put_trans: + v9fs_put_trans(clnt->trans_mod); +free_client: + kfree(clnt); return ERR_PTR(err); } EXPORT_SYMBOL(p9_client_create); @@ -1214,10 +1230,11 @@ static int p9_client_statsize(struct p9_wstat *wst, int optional) { int ret; + /* NOTE: size shouldn't include its own length */ /* size[2] type[2] dev[4] qid[13] */ /* mode[4] atime[4] mtime[4] length[8]*/ /* name[s] uid[s] gid[s] muid[s] */ - ret = 2+2+4+13+4+4+4+8+2+2+2+2; + ret = 2+4+13+4+4+4+8+2+2+2+2; if (wst->name) ret += strlen(wst->name); @@ -1258,7 +1275,7 @@ int p9_client_wstat(struct p9_fid *fid, struct p9_wstat *wst) wst->name, wst->uid, wst->gid, wst->muid, wst->extension, wst->n_uid, wst->n_gid, wst->n_muid); - req = p9_client_rpc(clnt, P9_TWSTAT, "dwS", fid->fid, wst->size, wst); + req = p9_client_rpc(clnt, P9_TWSTAT, "dwS", fid->fid, wst->size+2, wst); if (IS_ERR(req)) { err = PTR_ERR(req); goto error; diff --git a/net/9p/trans_fd.c b/net/9p/trans_fd.c index be1cb909d8c0..31d0b05582a9 100644 --- a/net/9p/trans_fd.c +++ b/net/9p/trans_fd.c @@ -714,7 +714,7 @@ static int parse_opts(char *params, struct p9_fd_opts *opts) char *p; substring_t args[MAX_OPT_ARGS]; int option; - char *options; + char *options, *tmp_options; int ret; opts->port = P9_PORT; @@ -724,12 +724,13 @@ static int parse_opts(char *params, struct p9_fd_opts *opts) if (!params) return 0; - options = kstrdup(params, GFP_KERNEL); - if (!options) { + tmp_options = kstrdup(params, GFP_KERNEL); + if (!tmp_options) { P9_DPRINTK(P9_DEBUG_ERROR, "failed to allocate copy of option string\n"); return -ENOMEM; } + options = tmp_options; while ((p = strsep(&options, ",")) != NULL) { int token; @@ -760,7 +761,8 @@ static int parse_opts(char *params, struct p9_fd_opts *opts) continue; } } - kfree(options); + + kfree(tmp_options); return 0; } diff --git a/net/9p/trans_rdma.c b/net/9p/trans_rdma.c index 65cb29db03f8..2c95a89c0f46 100644 --- a/net/9p/trans_rdma.c +++ b/net/9p/trans_rdma.c @@ -166,7 +166,7 @@ static int parse_opts(char *params, struct p9_rdma_opts *opts) char *p; substring_t args[MAX_OPT_ARGS]; int option; - char *options; + char *options, *tmp_options; int ret; opts->port = P9_PORT; @@ -177,12 +177,13 @@ static int parse_opts(char *params, struct p9_rdma_opts *opts) if (!params) return 0; - options = kstrdup(params, GFP_KERNEL); - if (!options) { + tmp_options = kstrdup(params, GFP_KERNEL); + if (!tmp_options) { P9_DPRINTK(P9_DEBUG_ERROR, "failed to allocate copy of option string\n"); return -ENOMEM; } + options = tmp_options; while ((p = strsep(&options, ",")) != NULL) { int token; @@ -216,7 +217,7 @@ static int parse_opts(char *params, struct p9_rdma_opts *opts) } /* RQ must be at least as large as the SQ */ opts->rq_depth = max(opts->rq_depth, opts->sq_depth); - kfree(options); + kfree(tmp_options); return 0; } diff --git a/net/9p/trans_virtio.c b/net/9p/trans_virtio.c index ea1e3daabefe..cb50f4ae5eef 100644 --- a/net/9p/trans_virtio.c +++ b/net/9p/trans_virtio.c @@ -102,7 +102,8 @@ static void p9_virtio_close(struct p9_client *client) struct virtio_chan *chan = client->trans; mutex_lock(&virtio_9p_lock); - chan->inuse = false; + if (chan) + chan->inuse = false; mutex_unlock(&virtio_9p_lock); } @@ -311,6 +312,7 @@ p9_virtio_create(struct p9_client *client, const char *devname, char *args) } client->trans = (void *)chan; + client->status = Connected; chan->client = client; return 0; diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c index b7c4224f4e7d..b10e3cdb08f8 100644 --- a/net/bluetooth/hci_conn.c +++ b/net/bluetooth/hci_conn.c @@ -377,6 +377,9 @@ struct hci_conn *hci_connect(struct hci_dev *hdev, int type, bdaddr_t *dst, __u8 if (acl->state == BT_CONNECTED && (sco->state == BT_OPEN || sco->state == BT_CLOSED)) { + acl->power_save = 1; + hci_conn_enter_active_mode(acl); + if (lmp_esco_capable(hdev)) hci_setup_sync(sco, acl->handle); else diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c index 28517bad796c..592da5c909c1 100644 --- a/net/bluetooth/hci_event.c +++ b/net/bluetooth/hci_event.c @@ -1699,6 +1699,7 @@ static inline void hci_sync_conn_complete_evt(struct hci_dev *hdev, struct sk_bu break; case 0x1c: /* SCO interval rejected */ + case 0x1a: /* Unsupported Remote Feature */ case 0x1f: /* Unspecified error */ if (conn->out && conn->attempt < 2) { conn->pkt_type = (hdev->esco_type & SCO_ESCO_MASK) | diff --git a/net/bluetooth/hidp/core.c b/net/bluetooth/hidp/core.c index 6cf526d06e21..fc6ec1e72652 100644 --- a/net/bluetooth/hidp/core.c +++ b/net/bluetooth/hidp/core.c @@ -703,29 +703,9 @@ static void hidp_close(struct hid_device *hid) static int hidp_parse(struct hid_device *hid) { struct hidp_session *session = hid->driver_data; - struct hidp_connadd_req *req = session->req; - unsigned char *buf; - int ret; - - buf = kmalloc(req->rd_size, GFP_KERNEL); - if (!buf) - return -ENOMEM; - - if (copy_from_user(buf, req->rd_data, req->rd_size)) { - kfree(buf); - return -EFAULT; - } - - ret = hid_parse_report(session->hid, buf, req->rd_size); - - kfree(buf); - - if (ret) - return ret; - - session->req = NULL; - return 0; + return hid_parse_report(session->hid, session->rd_data, + session->rd_size); } static int hidp_start(struct hid_device *hid) @@ -770,12 +750,24 @@ static int hidp_setup_hid(struct hidp_session *session, bdaddr_t src, dst; int err; + session->rd_data = kzalloc(req->rd_size, GFP_KERNEL); + if (!session->rd_data) + return -ENOMEM; + + if (copy_from_user(session->rd_data, req->rd_data, req->rd_size)) { + err = -EFAULT; + goto fault; + } + session->rd_size = req->rd_size; + hid = hid_allocate_device(); - if (IS_ERR(hid)) - return PTR_ERR(hid); + if (IS_ERR(hid)) { + err = PTR_ERR(hid); + goto fault; + } session->hid = hid; - session->req = req; + hid->driver_data = session; baswap(&src, &bt_sk(session->ctrl_sock->sk)->src); @@ -806,6 +798,10 @@ failed: hid_destroy_device(hid); session->hid = NULL; +fault: + kfree(session->rd_data); + session->rd_data = NULL; + return err; } @@ -900,6 +896,9 @@ unlink: session->hid = NULL; } + kfree(session->rd_data); + session->rd_data = NULL; + purge: skb_queue_purge(&session->ctrl_transmit); skb_queue_purge(&session->intr_transmit); diff --git a/net/bluetooth/hidp/hidp.h b/net/bluetooth/hidp/hidp.h index faf3d74c3586..a4e215d50c10 100644 --- a/net/bluetooth/hidp/hidp.h +++ b/net/bluetooth/hidp/hidp.h @@ -154,7 +154,9 @@ struct hidp_session { struct sk_buff_head ctrl_transmit; struct sk_buff_head intr_transmit; - struct hidp_connadd_req *req; + /* Report descriptor */ + __u8 *rd_data; + uint rd_size; }; static inline void hidp_schedule(struct hidp_session *session) diff --git a/net/bluetooth/rfcomm/core.c b/net/bluetooth/rfcomm/core.c index fc5ee3296e22..89f4a59eb82b 100644 --- a/net/bluetooth/rfcomm/core.c +++ b/net/bluetooth/rfcomm/core.c @@ -252,7 +252,6 @@ static void rfcomm_session_timeout(unsigned long arg) BT_DBG("session %p state %ld", s, s->state); set_bit(RFCOMM_TIMED_OUT, &s->flags); - rfcomm_session_put(s); rfcomm_schedule(RFCOMM_SCHED_TIMEO); } @@ -1151,7 +1150,11 @@ static int rfcomm_recv_ua(struct rfcomm_session *s, u8 dlci) break; case BT_DISCONN: - rfcomm_session_put(s); + /* When socket is closed and we are not RFCOMM + * initiator rfcomm_process_rx already calls + * rfcomm_session_put() */ + if (s->sock->sk->sk_state != BT_CLOSED) + rfcomm_session_put(s); break; } } @@ -1920,6 +1923,7 @@ static inline void rfcomm_process_sessions(void) if (test_and_clear_bit(RFCOMM_TIMED_OUT, &s->flags)) { s->state = BT_DISCONN; rfcomm_send_disc(s, 0); + rfcomm_session_put(s); continue; } diff --git a/net/core/dst.c b/net/core/dst.c index 57bc4d5b8d08..cb1b3488b739 100644 --- a/net/core/dst.c +++ b/net/core/dst.c @@ -17,6 +17,7 @@ #include <linux/string.h> #include <linux/types.h> #include <net/net_namespace.h> +#include <linux/sched.h> #include <net/dst.h> @@ -79,6 +80,7 @@ loop: while ((dst = next) != NULL) { next = dst->next; prefetch(&next->next); + cond_resched(); if (likely(atomic_read(&dst->__refcnt))) { last->next = dst; last = dst; diff --git a/net/core/ethtool.c b/net/core/ethtool.c index d8aee584e8d1..236a9988ea91 100644 --- a/net/core/ethtool.c +++ b/net/core/ethtool.c @@ -927,6 +927,7 @@ int dev_ethtool(struct net *net, struct ifreq *ifr) case ETHTOOL_GPERMADDR: case ETHTOOL_GUFO: case ETHTOOL_GGSO: + case ETHTOOL_GGRO: case ETHTOOL_GFLAGS: case ETHTOOL_GPFLAGS: case ETHTOOL_GRXFH: diff --git a/net/core/pktgen.c b/net/core/pktgen.c index de0c2c726420..2e692afdc55d 100644 --- a/net/core/pktgen.c +++ b/net/core/pktgen.c @@ -3524,6 +3524,7 @@ static int pktgen_thread_worker(void *arg) wait_event_interruptible_timeout(t->queue, t->control != 0, HZ/10); + try_to_freeze(); continue; } diff --git a/net/dccp/ccid.c b/net/dccp/ccid.c index 57dfb9c8c4f2..ff16e9df1969 100644 --- a/net/dccp/ccid.c +++ b/net/dccp/ccid.c @@ -83,7 +83,7 @@ static struct kmem_cache *ccid_kmem_cache_create(int obj_size, char *slab_name_f va_list args; va_start(args, fmt); - vsnprintf(slab_name_fmt, sizeof(slab_name_fmt), fmt, args); + vsnprintf(slab_name_fmt, CCID_SLAB_NAME_LENGTH, fmt, args); va_end(args); slab = kmem_cache_create(slab_name_fmt, sizeof(struct ccid) + obj_size, 0, diff --git a/net/dccp/ccid.h b/net/dccp/ccid.h index 269958bf7fe9..6df6f8ac9636 100644 --- a/net/dccp/ccid.h +++ b/net/dccp/ccid.h @@ -19,7 +19,9 @@ #include <linux/list.h> #include <linux/module.h> -#define CCID_MAX 255 +/* maximum value for a CCID (RFC 4340, 19.5) */ +#define CCID_MAX 255 +#define CCID_SLAB_NAME_LENGTH 32 struct tcp_info; @@ -49,8 +51,8 @@ struct ccid_operations { const char *ccid_name; struct kmem_cache *ccid_hc_rx_slab, *ccid_hc_tx_slab; - char ccid_hc_rx_slab_name[32]; - char ccid_hc_tx_slab_name[32]; + char ccid_hc_rx_slab_name[CCID_SLAB_NAME_LENGTH]; + char ccid_hc_tx_slab_name[CCID_SLAB_NAME_LENGTH]; __u32 ccid_hc_rx_obj_size, ccid_hc_tx_obj_size; /* Interface Routines */ diff --git a/net/dccp/probe.c b/net/dccp/probe.c index bace1d8cbcfd..f5b3464f1242 100644 --- a/net/dccp/probe.c +++ b/net/dccp/probe.c @@ -161,8 +161,8 @@ static __init int dccpprobe_init(void) if (!proc_net_fops_create(&init_net, procname, S_IRUSR, &dccpprobe_fops)) goto err0; - ret = try_then_request_module((register_jprobe(&dccp_send_probe) == 0), - "dccp"); + try_then_request_module((ret = register_jprobe(&dccp_send_probe)) == 0, + "dccp"); if (ret) goto err1; diff --git a/net/ipv4/igmp.c b/net/ipv4/igmp.c index 76c08402c933..a42f658e756a 100644 --- a/net/ipv4/igmp.c +++ b/net/ipv4/igmp.c @@ -946,7 +946,6 @@ int igmp_rcv(struct sk_buff *skb) break; case IGMP_HOST_MEMBERSHIP_REPORT: case IGMPV2_HOST_MEMBERSHIP_REPORT: - case IGMPV3_HOST_MEMBERSHIP_REPORT: /* Is it our report looped back? */ if (skb_rtable(skb)->fl.iif == 0) break; @@ -960,6 +959,7 @@ int igmp_rcv(struct sk_buff *skb) in_dev_put(in_dev); return pim_rcv_v1(skb); #endif + case IGMPV3_HOST_MEMBERSHIP_REPORT: case IGMP_DVMRP: case IGMP_TRACE: case IGMP_HOST_LEAVE_MESSAGE: diff --git a/net/ipv4/ipcomp.c b/net/ipv4/ipcomp.c index 38fbf04150ae..544ce0876f12 100644 --- a/net/ipv4/ipcomp.c +++ b/net/ipv4/ipcomp.c @@ -124,16 +124,12 @@ static int ipcomp4_init_state(struct xfrm_state *x) if (x->props.mode == XFRM_MODE_TUNNEL) { err = ipcomp_tunnel_attach(x); if (err) - goto error_tunnel; + goto out; } err = 0; out: return err; - -error_tunnel: - ipcomp_destroy(x); - goto out; } static const struct xfrm_type ipcomp_type = { diff --git a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c index 06632762ba5f..90203e1b9187 100644 --- a/net/ipv4/netfilter/arp_tables.c +++ b/net/ipv4/netfilter/arp_tables.c @@ -925,10 +925,10 @@ static int get_info(struct net *net, void __user *user, int *len, int compat) if (t && !IS_ERR(t)) { struct arpt_getinfo info; const struct xt_table_info *private = t->private; - #ifdef CONFIG_COMPAT + struct xt_table_info tmp; + if (compat) { - struct xt_table_info tmp; ret = compat_table_info(private, &tmp); xt_compat_flush_offsets(NFPROTO_ARP); private = &tmp; diff --git a/net/ipv4/netfilter/ip_tables.c b/net/ipv4/netfilter/ip_tables.c index 572330a552ef..3ce53cf13d5a 100644 --- a/net/ipv4/netfilter/ip_tables.c +++ b/net/ipv4/netfilter/ip_tables.c @@ -1132,10 +1132,10 @@ static int get_info(struct net *net, void __user *user, int *len, int compat) if (t && !IS_ERR(t)) { struct ipt_getinfo info; const struct xt_table_info *private = t->private; - #ifdef CONFIG_COMPAT + struct xt_table_info tmp; + if (compat) { - struct xt_table_info tmp; ret = compat_table_info(private, &tmp); xt_compat_flush_offsets(AF_INET); private = &tmp; diff --git a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c index d171b123a656..d1ea38a7c490 100644 --- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c +++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4.c @@ -210,7 +210,7 @@ static ctl_table ip_ct_sysctl_table[] = { }, { .procname = "ip_conntrack_buckets", - .data = &nf_conntrack_htable_size, + .data = &init_net.ct.htable_size, .maxlen = sizeof(unsigned int), .mode = 0444, .proc_handler = proc_dointvec, diff --git a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4_compat.c b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4_compat.c index 8668a3defda6..2fb7b76da94f 100644 --- a/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4_compat.c +++ b/net/ipv4/netfilter/nf_conntrack_l3proto_ipv4_compat.c @@ -32,7 +32,7 @@ static struct hlist_nulls_node *ct_get_first(struct seq_file *seq) struct hlist_nulls_node *n; for (st->bucket = 0; - st->bucket < nf_conntrack_htable_size; + st->bucket < net->ct.htable_size; st->bucket++) { n = rcu_dereference(net->ct.hash[st->bucket].first); if (!is_a_nulls(n)) @@ -50,7 +50,7 @@ static struct hlist_nulls_node *ct_get_next(struct seq_file *seq, head = rcu_dereference(head->next); while (is_a_nulls(head)) { if (likely(get_nulls_value(head) == st->bucket)) { - if (++st->bucket >= nf_conntrack_htable_size) + if (++st->bucket >= net->ct.htable_size) return NULL; } head = rcu_dereference(net->ct.hash[st->bucket].first); diff --git a/net/ipv4/netfilter/nf_nat_core.c b/net/ipv4/netfilter/nf_nat_core.c index fe1a64479dd0..26066a2327ad 100644 --- a/net/ipv4/netfilter/nf_nat_core.c +++ b/net/ipv4/netfilter/nf_nat_core.c @@ -35,9 +35,6 @@ static DEFINE_SPINLOCK(nf_nat_lock); static struct nf_conntrack_l3proto *l3proto __read_mostly; -/* Calculated at init based on memory size */ -static unsigned int nf_nat_htable_size __read_mostly; - #define MAX_IP_NAT_PROTO 256 static const struct nf_nat_protocol *nf_nat_protos[MAX_IP_NAT_PROTO] __read_mostly; @@ -72,7 +69,7 @@ EXPORT_SYMBOL_GPL(nf_nat_proto_put); /* We keep an extra hash for each conntrack, for fast searching. */ static inline unsigned int -hash_by_src(const struct nf_conntrack_tuple *tuple) +hash_by_src(const struct net *net, const struct nf_conntrack_tuple *tuple) { unsigned int hash; @@ -80,7 +77,7 @@ hash_by_src(const struct nf_conntrack_tuple *tuple) hash = jhash_3words((__force u32)tuple->src.u3.ip, (__force u32)tuple->src.u.all, tuple->dst.protonum, 0); - return ((u64)hash * nf_nat_htable_size) >> 32; + return ((u64)hash * net->ipv4.nat_htable_size) >> 32; } /* Is this tuple already taken? (not by us) */ @@ -147,7 +144,7 @@ find_appropriate_src(struct net *net, struct nf_conntrack_tuple *result, const struct nf_nat_range *range) { - unsigned int h = hash_by_src(tuple); + unsigned int h = hash_by_src(net, tuple); const struct nf_conn_nat *nat; const struct nf_conn *ct; const struct hlist_node *n; @@ -330,7 +327,7 @@ nf_nat_setup_info(struct nf_conn *ct, if (have_to_hash) { unsigned int srchash; - srchash = hash_by_src(&ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); + srchash = hash_by_src(net, &ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); spin_lock_bh(&nf_nat_lock); /* nf_conntrack_alter_reply might re-allocate exntension aera */ nat = nfct_nat(ct); @@ -679,8 +676,10 @@ nfnetlink_parse_nat_setup(struct nf_conn *ct, static int __net_init nf_nat_net_init(struct net *net) { - net->ipv4.nat_bysource = nf_ct_alloc_hashtable(&nf_nat_htable_size, - &net->ipv4.nat_vmalloced, 0); + /* Leave them the same for the moment. */ + net->ipv4.nat_htable_size = net->ct.htable_size; + net->ipv4.nat_bysource = nf_ct_alloc_hashtable(&net->ipv4.nat_htable_size, + &net->ipv4.nat_vmalloced, 0); if (!net->ipv4.nat_bysource) return -ENOMEM; return 0; @@ -703,7 +702,7 @@ static void __net_exit nf_nat_net_exit(struct net *net) nf_ct_iterate_cleanup(net, &clean_nat, NULL); synchronize_rcu(); nf_ct_free_hashtable(net->ipv4.nat_bysource, net->ipv4.nat_vmalloced, - nf_nat_htable_size); + net->ipv4.nat_htable_size); } static struct pernet_operations nf_nat_net_ops = { @@ -724,9 +723,6 @@ static int __init nf_nat_init(void) return ret; } - /* Leave them the same for the moment. */ - nf_nat_htable_size = nf_conntrack_htable_size; - ret = register_pernet_subsys(&nf_nat_net_ops); if (ret < 0) goto cleanup_extend; diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index 28e029632493..3fddc69ccccc 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -5783,11 +5783,9 @@ int tcp_rcv_state_process(struct sock *sk, struct sk_buff *skb, /* tcp_ack considers this ACK as duplicate * and does not calculate rtt. - * Fix it at least with timestamps. + * Force it here. */ - if (tp->rx_opt.saw_tstamp && - tp->rx_opt.rcv_tsecr && !tp->srtt) - tcp_ack_saw_tstamp(sk, 0); + tcp_ack_update_rtt(sk, 0, 0); if (tp->rx_opt.tstamp_ok) tp->advmss -= TCPOLEN_TSTAMP_ALIGNED; diff --git a/net/ipv6/ipcomp6.c b/net/ipv6/ipcomp6.c index 2f2a5ca2c878..002e6eef9120 100644 --- a/net/ipv6/ipcomp6.c +++ b/net/ipv6/ipcomp6.c @@ -154,16 +154,12 @@ static int ipcomp6_init_state(struct xfrm_state *x) if (x->props.mode == XFRM_MODE_TUNNEL) { err = ipcomp6_tunnel_attach(x); if (err) - goto error_tunnel; + goto out; } err = 0; out: return err; -error_tunnel: - ipcomp_destroy(x); - - goto out; } static const struct xfrm_type ipcomp6_type = diff --git a/net/ipv6/netfilter/ip6_tables.c b/net/ipv6/netfilter/ip6_tables.c index 480d7f8c9802..8a7e0f52e177 100644 --- a/net/ipv6/netfilter/ip6_tables.c +++ b/net/ipv6/netfilter/ip6_tables.c @@ -1164,10 +1164,10 @@ static int get_info(struct net *net, void __user *user, int *len, int compat) if (t && !IS_ERR(t)) { struct ip6t_getinfo info; const struct xt_table_info *private = t->private; - #ifdef CONFIG_COMPAT + struct xt_table_info tmp; + if (compat) { - struct xt_table_info tmp; ret = compat_table_info(private, &tmp); xt_compat_flush_offsets(AF_INET6); private = &tmp; diff --git a/net/irda/irnet/irnet_ppp.c b/net/irda/irnet/irnet_ppp.c index 156020d138b5..6b3602de359a 100644 --- a/net/irda/irnet/irnet_ppp.c +++ b/net/irda/irnet/irnet_ppp.c @@ -698,15 +698,18 @@ dev_irnet_ioctl( /* Query PPP channel and unit number */ case PPPIOCGCHAN: + lock_kernel(); if(ap->ppp_open && !put_user(ppp_channel_index(&ap->chan), (int __user *)argp)) err = 0; + unlock_kernel(); break; case PPPIOCGUNIT: lock_kernel(); if(ap->ppp_open && !put_user(ppp_unit_number(&ap->chan), (int __user *)argp)) - err = 0; + err = 0; + unlock_kernel(); break; /* All these ioctls can be passed both directly and from ppp_generic, diff --git a/net/key/af_key.c b/net/key/af_key.c index 76fa6fef6473..539f43bc97db 100644 --- a/net/key/af_key.c +++ b/net/key/af_key.c @@ -3794,9 +3794,9 @@ static struct pernet_operations pfkey_net_ops = { static void __exit ipsec_pfkey_exit(void) { - unregister_pernet_subsys(&pfkey_net_ops); xfrm_unregister_km(&pfkeyv2_mgr); sock_unregister(PF_KEY); + unregister_pernet_subsys(&pfkey_net_ops); proto_unregister(&key_proto); } @@ -3807,21 +3807,22 @@ static int __init ipsec_pfkey_init(void) if (err != 0) goto out; - err = sock_register(&pfkey_family_ops); + err = register_pernet_subsys(&pfkey_net_ops); if (err != 0) goto out_unregister_key_proto; + err = sock_register(&pfkey_family_ops); + if (err != 0) + goto out_unregister_pernet; err = xfrm_register_km(&pfkeyv2_mgr); if (err != 0) goto out_sock_unregister; - err = register_pernet_subsys(&pfkey_net_ops); - if (err != 0) - goto out_xfrm_unregister_km; out: return err; -out_xfrm_unregister_km: - xfrm_unregister_km(&pfkeyv2_mgr); + out_sock_unregister: sock_unregister(PF_KEY); +out_unregister_pernet: + unregister_pernet_subsys(&pfkey_net_ops); out_unregister_key_proto: proto_unregister(&key_proto); goto out; diff --git a/net/mac80211/ibss.c b/net/mac80211/ibss.c index 1f2db647bb5c..22f0c2aa7a89 100644 --- a/net/mac80211/ibss.c +++ b/net/mac80211/ibss.c @@ -647,7 +647,7 @@ static void ieee80211_rx_mgmt_probe_req(struct ieee80211_sub_if_data *sdata, } if (pos[1] != 0 && (pos[1] != ifibss->ssid_len || - !memcmp(pos + 2, ifibss->ssid, ifibss->ssid_len))) { + memcmp(pos + 2, ifibss->ssid, ifibss->ssid_len))) { /* Ignore ProbeReq for foreign SSID */ return; } diff --git a/net/mac80211/rate.c b/net/mac80211/rate.c index b9007f80cb92..12a2bff7dcdb 100644 --- a/net/mac80211/rate.c +++ b/net/mac80211/rate.c @@ -245,6 +245,9 @@ void rate_control_get_rate(struct ieee80211_sub_if_data *sdata, info->control.rates[i].count = 1; } + if (sdata->local->hw.flags & IEEE80211_HW_HAS_RATE_CONTROL) + return; + if (sta && sdata->force_unicast_rateidx > -1) { info->control.rates[0].idx = sdata->force_unicast_rateidx; } else { diff --git a/net/mac80211/scan.c b/net/mac80211/scan.c index f934c9620b73..bc17cf7d68db 100644 --- a/net/mac80211/scan.c +++ b/net/mac80211/scan.c @@ -439,6 +439,16 @@ static int __ieee80211_start_scan(struct ieee80211_sub_if_data *sdata, if (local->scan_req) return -EBUSY; + if (req != local->int_scan_req && + sdata->vif.type == NL80211_IFTYPE_STATION && + !list_empty(&ifmgd->work_list)) { + /* actually wait for the work it's doing to finish/time out */ + set_bit(IEEE80211_STA_REQ_SCAN, &ifmgd->request); + local->scan_req = req; + local->scan_sdata = sdata; + return 0; + } + if (local->ops->hw_scan) { u8 *ies; @@ -463,14 +473,6 @@ static int __ieee80211_start_scan(struct ieee80211_sub_if_data *sdata, local->scan_req = req; local->scan_sdata = sdata; - if (req != local->int_scan_req && - sdata->vif.type == NL80211_IFTYPE_STATION && - !list_empty(&ifmgd->work_list)) { - /* actually wait for the work it's doing to finish/time out */ - set_bit(IEEE80211_STA_REQ_SCAN, &ifmgd->request); - return 0; - } - if (local->ops->hw_scan) __set_bit(SCAN_HW_SCANNING, &local->scanning); else diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c index 0e98c3282d42..4d79e3c1616c 100644 --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c @@ -30,6 +30,7 @@ #include <linux/netdevice.h> #include <linux/socket.h> #include <linux/mm.h> +#include <linux/nsproxy.h> #include <linux/rculist_nulls.h> #include <net/netfilter/nf_conntrack.h> @@ -63,8 +64,6 @@ EXPORT_SYMBOL_GPL(nf_conntrack_max); struct nf_conn nf_conntrack_untracked __read_mostly; EXPORT_SYMBOL_GPL(nf_conntrack_untracked); -static struct kmem_cache *nf_conntrack_cachep __read_mostly; - static int nf_conntrack_hash_rnd_initted; static unsigned int nf_conntrack_hash_rnd; @@ -86,9 +85,10 @@ static u_int32_t __hash_conntrack(const struct nf_conntrack_tuple *tuple, return ((u64)h * size) >> 32; } -static inline u_int32_t hash_conntrack(const struct nf_conntrack_tuple *tuple) +static inline u_int32_t hash_conntrack(const struct net *net, + const struct nf_conntrack_tuple *tuple) { - return __hash_conntrack(tuple, nf_conntrack_htable_size, + return __hash_conntrack(tuple, net->ct.htable_size, nf_conntrack_hash_rnd); } @@ -296,7 +296,7 @@ __nf_conntrack_find(struct net *net, const struct nf_conntrack_tuple *tuple) { struct nf_conntrack_tuple_hash *h; struct hlist_nulls_node *n; - unsigned int hash = hash_conntrack(tuple); + unsigned int hash = hash_conntrack(net, tuple); /* Disable BHs the entire time since we normally need to disable them * at least once for the stats anyway. @@ -366,10 +366,11 @@ static void __nf_conntrack_hash_insert(struct nf_conn *ct, void nf_conntrack_hash_insert(struct nf_conn *ct) { + struct net *net = nf_ct_net(ct); unsigned int hash, repl_hash; - hash = hash_conntrack(&ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); - repl_hash = hash_conntrack(&ct->tuplehash[IP_CT_DIR_REPLY].tuple); + hash = hash_conntrack(net, &ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); + repl_hash = hash_conntrack(net, &ct->tuplehash[IP_CT_DIR_REPLY].tuple); __nf_conntrack_hash_insert(ct, hash, repl_hash); } @@ -397,8 +398,8 @@ __nf_conntrack_confirm(struct sk_buff *skb) if (CTINFO2DIR(ctinfo) != IP_CT_DIR_ORIGINAL) return NF_ACCEPT; - hash = hash_conntrack(&ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); - repl_hash = hash_conntrack(&ct->tuplehash[IP_CT_DIR_REPLY].tuple); + hash = hash_conntrack(net, &ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple); + repl_hash = hash_conntrack(net, &ct->tuplehash[IP_CT_DIR_REPLY].tuple); /* We're not in hash table, and we refuse to set up related connections for unconfirmed conns. But packet copies and @@ -468,7 +469,7 @@ nf_conntrack_tuple_taken(const struct nf_conntrack_tuple *tuple, struct net *net = nf_ct_net(ignored_conntrack); struct nf_conntrack_tuple_hash *h; struct hlist_nulls_node *n; - unsigned int hash = hash_conntrack(tuple); + unsigned int hash = hash_conntrack(net, tuple); /* Disable BHs the entire time since we need to disable them at * least once for the stats anyway. @@ -503,7 +504,7 @@ static noinline int early_drop(struct net *net, unsigned int hash) int dropped = 0; rcu_read_lock(); - for (i = 0; i < nf_conntrack_htable_size; i++) { + for (i = 0; i < net->ct.htable_size; i++) { hlist_nulls_for_each_entry_rcu(h, n, &net->ct.hash[hash], hnnode) { tmp = nf_ct_tuplehash_to_ctrack(h); @@ -523,7 +524,7 @@ static noinline int early_drop(struct net *net, unsigned int hash) if (cnt >= NF_CT_EVICTION_RANGE) break; - hash = (hash + 1) % nf_conntrack_htable_size; + hash = (hash + 1) % net->ct.htable_size; } rcu_read_unlock(); @@ -557,7 +558,7 @@ struct nf_conn *nf_conntrack_alloc(struct net *net, if (nf_conntrack_max && unlikely(atomic_read(&net->ct.count) > nf_conntrack_max)) { - unsigned int hash = hash_conntrack(orig); + unsigned int hash = hash_conntrack(net, orig); if (!early_drop(net, hash)) { atomic_dec(&net->ct.count); if (net_ratelimit()) @@ -572,7 +573,7 @@ struct nf_conn *nf_conntrack_alloc(struct net *net, * Do not use kmem_cache_zalloc(), as this cache uses * SLAB_DESTROY_BY_RCU. */ - ct = kmem_cache_alloc(nf_conntrack_cachep, gfp); + ct = kmem_cache_alloc(net->ct.nf_conntrack_cachep, gfp); if (ct == NULL) { pr_debug("nf_conntrack_alloc: Can't alloc conntrack.\n"); atomic_dec(&net->ct.count); @@ -611,7 +612,7 @@ void nf_conntrack_free(struct nf_conn *ct) nf_ct_ext_destroy(ct); atomic_dec(&net->ct.count); nf_ct_ext_free(ct); - kmem_cache_free(nf_conntrack_cachep, ct); + kmem_cache_free(net->ct.nf_conntrack_cachep, ct); } EXPORT_SYMBOL_GPL(nf_conntrack_free); @@ -1014,7 +1015,7 @@ get_next_corpse(struct net *net, int (*iter)(struct nf_conn *i, void *data), struct hlist_nulls_node *n; spin_lock_bh(&nf_conntrack_lock); - for (; *bucket < nf_conntrack_htable_size; (*bucket)++) { + for (; *bucket < net->ct.htable_size; (*bucket)++) { hlist_nulls_for_each_entry(h, n, &net->ct.hash[*bucket], hnnode) { ct = nf_ct_tuplehash_to_ctrack(h); if (iter(ct, data)) @@ -1113,9 +1114,12 @@ static void nf_ct_release_dying_list(struct net *net) static void nf_conntrack_cleanup_init_net(void) { + /* wait until all references to nf_conntrack_untracked are dropped */ + while (atomic_read(&nf_conntrack_untracked.ct_general.use) > 1) + schedule(); + nf_conntrack_helper_fini(); nf_conntrack_proto_fini(); - kmem_cache_destroy(nf_conntrack_cachep); } static void nf_conntrack_cleanup_net(struct net *net) @@ -1127,15 +1131,14 @@ static void nf_conntrack_cleanup_net(struct net *net) schedule(); goto i_see_dead_people; } - /* wait until all references to nf_conntrack_untracked are dropped */ - while (atomic_read(&nf_conntrack_untracked.ct_general.use) > 1) - schedule(); nf_ct_free_hashtable(net->ct.hash, net->ct.hash_vmalloc, - nf_conntrack_htable_size); + net->ct.htable_size); nf_conntrack_ecache_fini(net); nf_conntrack_acct_fini(net); nf_conntrack_expect_fini(net); + kmem_cache_destroy(net->ct.nf_conntrack_cachep); + kfree(net->ct.slabname); free_percpu(net->ct.stat); } @@ -1190,10 +1193,12 @@ int nf_conntrack_set_hashsize(const char *val, struct kernel_param *kp) { int i, bucket, vmalloced, old_vmalloced; unsigned int hashsize, old_size; - int rnd; struct hlist_nulls_head *hash, *old_hash; struct nf_conntrack_tuple_hash *h; + if (current->nsproxy->net_ns != &init_net) + return -EOPNOTSUPP; + /* On boot, we can set this without any fancy locking. */ if (!nf_conntrack_htable_size) return param_set_uint(val, kp); @@ -1206,33 +1211,29 @@ int nf_conntrack_set_hashsize(const char *val, struct kernel_param *kp) if (!hash) return -ENOMEM; - /* We have to rehahs for the new table anyway, so we also can - * use a newrandom seed */ - get_random_bytes(&rnd, sizeof(rnd)); - /* Lookups in the old hash might happen in parallel, which means we * might get false negatives during connection lookup. New connections * created because of a false negative won't make it into the hash * though since that required taking the lock. */ spin_lock_bh(&nf_conntrack_lock); - for (i = 0; i < nf_conntrack_htable_size; i++) { + for (i = 0; i < init_net.ct.htable_size; i++) { while (!hlist_nulls_empty(&init_net.ct.hash[i])) { h = hlist_nulls_entry(init_net.ct.hash[i].first, struct nf_conntrack_tuple_hash, hnnode); hlist_nulls_del_rcu(&h->hnnode); - bucket = __hash_conntrack(&h->tuple, hashsize, rnd); + bucket = __hash_conntrack(&h->tuple, hashsize, + nf_conntrack_hash_rnd); hlist_nulls_add_head_rcu(&h->hnnode, &hash[bucket]); } } - old_size = nf_conntrack_htable_size; + old_size = init_net.ct.htable_size; old_vmalloced = init_net.ct.hash_vmalloc; old_hash = init_net.ct.hash; - nf_conntrack_htable_size = hashsize; + init_net.ct.htable_size = nf_conntrack_htable_size = hashsize; init_net.ct.hash_vmalloc = vmalloced; init_net.ct.hash = hash; - nf_conntrack_hash_rnd = rnd; spin_unlock_bh(&nf_conntrack_lock); nf_ct_free_hashtable(old_hash, old_vmalloced, old_size); @@ -1271,15 +1272,6 @@ static int nf_conntrack_init_init_net(void) NF_CONNTRACK_VERSION, nf_conntrack_htable_size, nf_conntrack_max); - nf_conntrack_cachep = kmem_cache_create("nf_conntrack", - sizeof(struct nf_conn), - 0, SLAB_DESTROY_BY_RCU, NULL); - if (!nf_conntrack_cachep) { - printk(KERN_ERR "Unable to create nf_conn slab cache\n"); - ret = -ENOMEM; - goto err_cache; - } - ret = nf_conntrack_proto_init(); if (ret < 0) goto err_proto; @@ -1288,13 +1280,19 @@ static int nf_conntrack_init_init_net(void) if (ret < 0) goto err_helper; + /* Set up fake conntrack: to never be deleted, not in any hashes */ +#ifdef CONFIG_NET_NS + nf_conntrack_untracked.ct_net = &init_net; +#endif + atomic_set(&nf_conntrack_untracked.ct_general.use, 1); + /* - and look it like as a confirmed connection */ + set_bit(IPS_CONFIRMED_BIT, &nf_conntrack_untracked.status); + return 0; err_helper: nf_conntrack_proto_fini(); err_proto: - kmem_cache_destroy(nf_conntrack_cachep); -err_cache: return ret; } @@ -1316,7 +1314,24 @@ static int nf_conntrack_init_net(struct net *net) ret = -ENOMEM; goto err_stat; } - net->ct.hash = nf_ct_alloc_hashtable(&nf_conntrack_htable_size, + + net->ct.slabname = kasprintf(GFP_KERNEL, "nf_conntrack_%p", net); + if (!net->ct.slabname) { + ret = -ENOMEM; + goto err_slabname; + } + + net->ct.nf_conntrack_cachep = kmem_cache_create(net->ct.slabname, + sizeof(struct nf_conn), 0, + SLAB_DESTROY_BY_RCU, NULL); + if (!net->ct.nf_conntrack_cachep) { + printk(KERN_ERR "Unable to create nf_conn slab cache\n"); + ret = -ENOMEM; + goto err_cache; + } + + net->ct.htable_size = nf_conntrack_htable_size; + net->ct.hash = nf_ct_alloc_hashtable(&net->ct.htable_size, &net->ct.hash_vmalloc, 1); if (!net->ct.hash) { ret = -ENOMEM; @@ -1333,15 +1348,6 @@ static int nf_conntrack_init_net(struct net *net) if (ret < 0) goto err_ecache; - /* Set up fake conntrack: - - to never be deleted, not in any hashes */ -#ifdef CONFIG_NET_NS - nf_conntrack_untracked.ct_net = &init_net; -#endif - atomic_set(&nf_conntrack_untracked.ct_general.use, 1); - /* - and look it like as a confirmed connection */ - set_bit(IPS_CONFIRMED_BIT, &nf_conntrack_untracked.status); - return 0; err_ecache: @@ -1350,8 +1356,12 @@ err_acct: nf_conntrack_expect_fini(net); err_expect: nf_ct_free_hashtable(net->ct.hash, net->ct.hash_vmalloc, - nf_conntrack_htable_size); + net->ct.htable_size); err_hash: + kmem_cache_destroy(net->ct.nf_conntrack_cachep); +err_cache: + kfree(net->ct.slabname); +err_slabname: free_percpu(net->ct.stat); err_stat: return ret; diff --git a/net/netfilter/nf_conntrack_expect.c b/net/netfilter/nf_conntrack_expect.c index fdf5d2a1d9b4..2f25ff610982 100644 --- a/net/netfilter/nf_conntrack_expect.c +++ b/net/netfilter/nf_conntrack_expect.c @@ -569,7 +569,7 @@ static void exp_proc_remove(struct net *net) #endif /* CONFIG_PROC_FS */ } -module_param_named(expect_hashsize, nf_ct_expect_hsize, uint, 0600); +module_param_named(expect_hashsize, nf_ct_expect_hsize, uint, 0400); int nf_conntrack_expect_init(struct net *net) { @@ -577,7 +577,7 @@ int nf_conntrack_expect_init(struct net *net) if (net_eq(net, &init_net)) { if (!nf_ct_expect_hsize) { - nf_ct_expect_hsize = nf_conntrack_htable_size / 256; + nf_ct_expect_hsize = net->ct.htable_size / 256; if (!nf_ct_expect_hsize) nf_ct_expect_hsize = 1; } diff --git a/net/netfilter/nf_conntrack_helper.c b/net/netfilter/nf_conntrack_helper.c index 65c2a7bc3afc..4b1a56bd074c 100644 --- a/net/netfilter/nf_conntrack_helper.c +++ b/net/netfilter/nf_conntrack_helper.c @@ -192,7 +192,7 @@ static void __nf_conntrack_helper_unregister(struct nf_conntrack_helper *me, /* Get rid of expecteds, set helpers to NULL. */ hlist_nulls_for_each_entry(h, nn, &net->ct.unconfirmed, hnnode) unhelp(h, me); - for (i = 0; i < nf_conntrack_htable_size; i++) { + for (i = 0; i < net->ct.htable_size; i++) { hlist_nulls_for_each_entry(h, nn, &net->ct.hash[i], hnnode) unhelp(h, me); } diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index 42f21c01a93e..0ffe689dfe97 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c @@ -594,7 +594,7 @@ ctnetlink_dump_table(struct sk_buff *skb, struct netlink_callback *cb) rcu_read_lock(); last = (struct nf_conn *)cb->args[1]; - for (; cb->args[0] < nf_conntrack_htable_size; cb->args[0]++) { + for (; cb->args[0] < init_net.ct.htable_size; cb->args[0]++) { restart: hlist_nulls_for_each_entry_rcu(h, n, &init_net.ct.hash[cb->args[0]], hnnode) { diff --git a/net/netfilter/nf_conntrack_standalone.c b/net/netfilter/nf_conntrack_standalone.c index 028aba667ef7..e310f1561bb2 100644 --- a/net/netfilter/nf_conntrack_standalone.c +++ b/net/netfilter/nf_conntrack_standalone.c @@ -51,7 +51,7 @@ static struct hlist_nulls_node *ct_get_first(struct seq_file *seq) struct hlist_nulls_node *n; for (st->bucket = 0; - st->bucket < nf_conntrack_htable_size; + st->bucket < net->ct.htable_size; st->bucket++) { n = rcu_dereference(net->ct.hash[st->bucket].first); if (!is_a_nulls(n)) @@ -69,7 +69,7 @@ static struct hlist_nulls_node *ct_get_next(struct seq_file *seq, head = rcu_dereference(head->next); while (is_a_nulls(head)) { if (likely(get_nulls_value(head) == st->bucket)) { - if (++st->bucket >= nf_conntrack_htable_size) + if (++st->bucket >= net->ct.htable_size) return NULL; } head = rcu_dereference(net->ct.hash[st->bucket].first); @@ -355,7 +355,7 @@ static ctl_table nf_ct_sysctl_table[] = { }, { .procname = "nf_conntrack_buckets", - .data = &nf_conntrack_htable_size, + .data = &init_net.ct.htable_size, .maxlen = sizeof(unsigned int), .mode = 0444, .proc_handler = proc_dointvec, @@ -421,6 +421,7 @@ static int nf_conntrack_standalone_init_sysctl(struct net *net) goto out_kmemdup; table[1].data = &net->ct.count; + table[2].data = &net->ct.htable_size; table[3].data = &net->ct.sysctl_checksum; table[4].data = &net->ct.sysctl_log_invalid; diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index a4957bf2ca60..4c5972ba8c78 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -455,9 +455,14 @@ static int netlink_create(struct net *net, struct socket *sock, int protocol, if (nl_table[protocol].registered && try_module_get(nl_table[protocol].module)) module = nl_table[protocol].module; + else + err = -EPROTONOSUPPORT; cb_mutex = nl_table[protocol].cb_mutex; netlink_unlock_table(); + if (err < 0) + goto out; + err = __netlink_create(net, sock, cb_mutex, protocol); if (err < 0) goto out_module; diff --git a/net/sched/Kconfig b/net/sched/Kconfig index 929218a47620..21f9c7678aa3 100644 --- a/net/sched/Kconfig +++ b/net/sched/Kconfig @@ -433,7 +433,7 @@ config NET_ACT_POLICE module. To compile this code as a module, choose M here: the - module will be called police. + module will be called act_police. config NET_ACT_GACT tristate "Generic actions" @@ -443,7 +443,7 @@ config NET_ACT_GACT accepting packets. To compile this code as a module, choose M here: the - module will be called gact. + module will be called act_gact. config GACT_PROB bool "Probability support" @@ -459,7 +459,7 @@ config NET_ACT_MIRRED other devices. To compile this code as a module, choose M here: the - module will be called mirred. + module will be called act_mirred. config NET_ACT_IPT tristate "IPtables targets" @@ -469,7 +469,7 @@ config NET_ACT_IPT classification. To compile this code as a module, choose M here: the - module will be called ipt. + module will be called act_ipt. config NET_ACT_NAT tristate "Stateless NAT" @@ -479,7 +479,7 @@ config NET_ACT_NAT netfilter for NAT unless you know what you are doing. To compile this code as a module, choose M here: the - module will be called nat. + module will be called act_nat. config NET_ACT_PEDIT tristate "Packet Editing" @@ -488,7 +488,7 @@ config NET_ACT_PEDIT Say Y here if you want to mangle the content of packets. To compile this code as a module, choose M here: the - module will be called pedit. + module will be called act_pedit. config NET_ACT_SIMP tristate "Simple Example (Debug)" @@ -502,7 +502,7 @@ config NET_ACT_SIMP If unsure, say N. To compile this code as a module, choose M here: the - module will be called simple. + module will be called act_simple. config NET_ACT_SKBEDIT tristate "SKB Editing" @@ -513,7 +513,7 @@ config NET_ACT_SKBEDIT If unsure, say N. To compile this code as a module, choose M here: the - module will be called skbedit. + module will be called act_skbedit. config NET_CLS_IND bool "Incoming device classification" diff --git a/net/xfrm/xfrm_state.c b/net/xfrm/xfrm_state.c index b36cc344474b..f445ea1c5f52 100644 --- a/net/xfrm/xfrm_state.c +++ b/net/xfrm/xfrm_state.c @@ -1102,7 +1102,7 @@ static struct xfrm_state *xfrm_state_clone(struct xfrm_state *orig, int *errp) int err = -ENOMEM; struct xfrm_state *x = xfrm_state_alloc(net); if (!x) - goto error; + goto out; memcpy(&x->id, &orig->id, sizeof(x->id)); memcpy(&x->sel, &orig->sel, sizeof(x->sel)); @@ -1160,16 +1160,10 @@ static struct xfrm_state *xfrm_state_clone(struct xfrm_state *orig, int *errp) return x; error: + xfrm_state_put(x); +out: if (errp) *errp = err; - if (x) { - kfree(x->aalg); - kfree(x->ealg); - kfree(x->calg); - kfree(x->encap); - kfree(x->coaddr); - } - kfree(x); return NULL; } diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c index 6fdca97186e7..88eec3847df2 100644 --- a/sound/arm/pxa2xx-ac97-lib.c +++ b/sound/arm/pxa2xx-ac97-lib.c @@ -22,7 +22,6 @@ #include <asm/irq.h> #include <mach/regs-ac97.h> -#include <mach/pxa2xx-gpio.h> #include <mach/audio.h> static DEFINE_MUTEX(car_mutex); @@ -32,6 +31,8 @@ static struct clk *ac97_clk; static struct clk *ac97conf_clk; static int reset_gpio; +extern void pxa27x_assert_ac97reset(int reset_gpio, int on); + /* * Beware PXA27x bugs: * @@ -42,45 +43,6 @@ static int reset_gpio; * 1 jiffy timeout if interrupt never comes). */ -enum { - RESETGPIO_FORCE_HIGH, - RESETGPIO_FORCE_LOW, - RESETGPIO_NORMAL_ALTFUNC -}; - -/** - * set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA - * @mode: chosen action - * - * As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line - * must be done to insure proper work of AC97 reset line. This function - * computes the correct gpio_mode for further use by reset functions, and - * applied the change through pxa_gpio_mode. - */ -static void set_resetgpio_mode(int resetgpio_action) -{ - int mode = 0; - - if (reset_gpio) - switch (resetgpio_action) { - case RESETGPIO_NORMAL_ALTFUNC: - if (reset_gpio == 113) - mode = 113 | GPIO_ALT_FN_2_OUT; - if (reset_gpio == 95) - mode = 95 | GPIO_ALT_FN_1_OUT; - break; - case RESETGPIO_FORCE_LOW: - mode = reset_gpio | GPIO_OUT | GPIO_DFLT_LOW; - break; - case RESETGPIO_FORCE_HIGH: - mode = reset_gpio | GPIO_OUT | GPIO_DFLT_HIGH; - break; - }; - - if (mode) - pxa_gpio_mode(mode); -} - unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { unsigned short val = -1; @@ -174,12 +136,11 @@ static inline void pxa_ac97_warm_pxa27x(void) { gsr_bits = 0; - /* warm reset broken on Bulverde, - so manually keep AC97 reset high */ - set_resetgpio_mode(RESETGPIO_FORCE_HIGH); + /* warm reset broken on Bulverde, so manually keep AC97 reset high */ + pxa27x_assert_ac97reset(reset_gpio, 1); udelay(10); GCR |= GCR_WARM_RST; - set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC); + pxa27x_assert_ac97reset(reset_gpio, 0); udelay(500); } @@ -345,16 +306,6 @@ EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend); int pxa2xx_ac97_hw_resume(void) { - if (cpu_is_pxa25x() || cpu_is_pxa27x()) { - pxa_gpio_mode(GPIO31_SYNC_AC97_MD); - pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); - pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); - pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); - } - if (cpu_is_pxa27x()) { - /* Use GPIO 113 or 95 as AC97 Reset on Bulverde */ - set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC); - } clk_enable(ac97_clk); return 0; } @@ -386,16 +337,9 @@ int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev) reset_gpio = 113; } - if (cpu_is_pxa25x() || cpu_is_pxa27x()) { - pxa_gpio_mode(GPIO31_SYNC_AC97_MD); - pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); - pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); - pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); - } - if (cpu_is_pxa27x()) { /* Use GPIO 113 as AC97 Reset on Bulverde */ - set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC); + pxa27x_assert_ac97reset(reset_gpio, 0); ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK"); if (IS_ERR(ac97conf_clk)) { ret = PTR_ERR(ac97conf_clk); diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index b8faa6dc5abe..ff6da6f386d1 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -1893,6 +1893,9 @@ static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) if (!bdl_pos_adj[chip->dev_index]) return 1; /* no delayed ack */ + if (WARN_ONCE(!azx_dev->period_bytes, + "hda-intel: zero azx_dev->period_bytes")) + return 0; /* this shouldn't happen! */ if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2) return 0; /* NG - it's below the period boundary */ return 1; /* OK, it's fine */ @@ -2347,7 +2350,7 @@ static void __devinit check_probe_mask(struct azx *chip, int dev) */ static struct snd_pci_quirk msi_black_list[] __devinitdata = { SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ - SND_PCI_QUIRK(0x1043, 0x829c, "ASUS", 0), /* nvidia */ + SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ {} }; diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c index 3bd7712f029b..cf00df9c40f4 100644 --- a/sound/soc/pxa/pxa-ssp.c +++ b/sound/soc/pxa/pxa-ssp.c @@ -42,11 +42,14 @@ * SSP audio private data */ struct ssp_priv { - struct ssp_dev dev; + struct ssp_device *ssp; unsigned int sysclk; int dai_fmt; #ifdef CONFIG_PM - struct ssp_state state; + uint32_t cr0; + uint32_t cr1; + uint32_t to; + uint32_t psp; #endif }; @@ -61,6 +64,22 @@ static void dump_registers(struct ssp_device *ssp) ssp_read_reg(ssp, SSACD)); } +static void ssp_enable(struct ssp_device *ssp) +{ + uint32_t sscr0; + + sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE; + __raw_writel(sscr0, ssp->mmio_base + SSCR0); +} + +static void ssp_disable(struct ssp_device *ssp) +{ + uint32_t sscr0; + + sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE; + __raw_writel(sscr0, ssp->mmio_base + SSCR0); +} + struct pxa2xx_pcm_dma_data { struct pxa2xx_pcm_dma_params params; char name[20]; @@ -94,13 +113,12 @@ static int pxa_ssp_startup(struct snd_pcm_substream *substream, struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; struct ssp_priv *priv = cpu_dai->private_data; + struct ssp_device *ssp = priv->ssp; int ret = 0; if (!cpu_dai->active) { - priv->dev.port = cpu_dai->id + 1; - priv->dev.irq = NO_IRQ; - clk_enable(priv->dev.ssp->clk); - ssp_disable(&priv->dev); + clk_enable(ssp->clk); + ssp_disable(ssp); } if (cpu_dai->dma_data) { @@ -116,10 +134,11 @@ static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; struct ssp_priv *priv = cpu_dai->private_data; + struct ssp_device *ssp = priv->ssp; if (!cpu_dai->active) { - ssp_disable(&priv->dev); - clk_disable(priv->dev.ssp->clk); + ssp_disable(ssp); + clk_disable(ssp->clk); } if (cpu_dai->dma_data) { @@ -133,26 +152,39 @@ static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai) { struct ssp_priv *priv = cpu_dai->private_data; + struct ssp_device *ssp = priv->ssp; if (!cpu_dai->active) return 0; - ssp_save_state(&priv->dev, &priv->state); - clk_disable(priv->dev.ssp->clk); + priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0); + priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1); + priv->to = __raw_readl(ssp->mmio_base + SSTO); + priv->psp = __raw_readl(ssp->mmio_base + SSPSP); + + ssp_disable(ssp); + clk_disable(ssp->clk); return 0; } static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai) { struct ssp_priv *priv = cpu_dai->private_data; + struct ssp_device *ssp = priv->ssp; + uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE; if (!cpu_dai->active) return 0; - clk_enable(priv->dev.ssp->clk); - ssp_restore_state(&priv->dev, &priv->state); - ssp_enable(&priv->dev); + clk_enable(ssp->clk); + + __raw_writel(sssr, ssp->mmio_base + SSSR); + __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); + __raw_writel(priv->cr1, ssp->mmio_base + SSCR1); + __raw_writel(priv->to, ssp->mmio_base + SSTO); + __raw_writel(priv->psp, ssp->mmio_base + SSPSP); + __raw_writel(priv->cr0 | SSCR0_SSE, ssp->mmio_base + SSCR0); return 0; } @@ -201,7 +233,7 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, unsigned int freq, int dir) { struct ssp_priv *priv = cpu_dai->private_data; - struct ssp_device *ssp = priv->dev.ssp; + struct ssp_device *ssp = priv->ssp; int val; u32 sscr0 = ssp_read_reg(ssp, SSCR0) & @@ -242,11 +274,11 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, /* The SSP clock must be disabled when changing SSP clock mode * on PXA2xx. On PXA3xx it must be enabled when doing so. */ if (!cpu_is_pxa3xx()) - clk_disable(priv->dev.ssp->clk); + clk_disable(ssp->clk); val = ssp_read_reg(ssp, SSCR0) | sscr0; ssp_write_reg(ssp, SSCR0, val); if (!cpu_is_pxa3xx()) - clk_enable(priv->dev.ssp->clk); + clk_enable(ssp->clk); return 0; } @@ -258,7 +290,7 @@ static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, int div_id, int div) { struct ssp_priv *priv = cpu_dai->private_data; - struct ssp_device *ssp = priv->dev.ssp; + struct ssp_device *ssp = priv->ssp; int val; switch (div_id) { @@ -309,7 +341,7 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, int source, unsigned int freq_in, unsigned int freq_out) { struct ssp_priv *priv = cpu_dai->private_data; - struct ssp_device *ssp = priv->dev.ssp; + struct ssp_device *ssp = priv->ssp; u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70; #if defined(CONFIG_PXA3xx) @@ -378,7 +410,7 @@ static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) { struct ssp_priv *priv = cpu_dai->private_data; - struct ssp_device *ssp = priv->dev.ssp; + struct ssp_device *ssp = priv->ssp; u32 sscr0; sscr0 = ssp_read_reg(ssp, SSCR0); @@ -413,7 +445,7 @@ static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, int tristate) { struct ssp_priv *priv = cpu_dai->private_data; - struct ssp_device *ssp = priv->dev.ssp; + struct ssp_device *ssp = priv->ssp; u32 sscr1; sscr1 = ssp_read_reg(ssp, SSCR1); @@ -435,7 +467,7 @@ static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) { struct ssp_priv *priv = cpu_dai->private_data; - struct ssp_device *ssp = priv->dev.ssp; + struct ssp_device *ssp = priv->ssp; u32 sscr0; u32 sscr1; u32 sspsp; @@ -530,7 +562,7 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; struct ssp_priv *priv = cpu_dai->private_data; - struct ssp_device *ssp = priv->dev.ssp; + struct ssp_device *ssp = priv->ssp; int chn = params_channels(params); u32 sscr0; u32 sspsp; @@ -640,12 +672,12 @@ static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; int ret = 0; struct ssp_priv *priv = cpu_dai->private_data; - struct ssp_device *ssp = priv->dev.ssp; + struct ssp_device *ssp = priv->ssp; int val; switch (cmd) { case SNDRV_PCM_TRIGGER_RESUME: - ssp_enable(&priv->dev); + ssp_enable(ssp); break; case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: val = ssp_read_reg(ssp, SSCR1); @@ -664,7 +696,7 @@ static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, else val |= SSCR1_RSRE; ssp_write_reg(ssp, SSCR1, val); - ssp_enable(&priv->dev); + ssp_enable(ssp); break; case SNDRV_PCM_TRIGGER_STOP: val = ssp_read_reg(ssp, SSCR1); @@ -675,7 +707,7 @@ static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, ssp_write_reg(ssp, SSCR1, val); break; case SNDRV_PCM_TRIGGER_SUSPEND: - ssp_disable(&priv->dev); + ssp_disable(ssp); break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: val = ssp_read_reg(ssp, SSCR1); @@ -705,8 +737,8 @@ static int pxa_ssp_probe(struct platform_device *pdev, if (!priv) return -ENOMEM; - priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio"); - if (priv->dev.ssp == NULL) { + priv->ssp = ssp_request(dai->id + 1, "SoC audio"); + if (priv->ssp == NULL) { ret = -ENODEV; goto err_priv; } @@ -725,7 +757,7 @@ static void pxa_ssp_remove(struct platform_device *pdev, struct snd_soc_dai *dai) { struct ssp_priv *priv = dai->private_data; - ssp_free(priv->dev.ssp); + ssp_free(priv->ssp); } #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ diff --git a/tools/perf/builtin-top.c b/tools/perf/builtin-top.c index ddc584b64871..4b91d8cf00ec 100644 --- a/tools/perf/builtin-top.c +++ b/tools/perf/builtin-top.c @@ -705,7 +705,7 @@ static void print_mapped_keys(void) fprintf(stdout, "\t[w] toggle display weighted/count[E]r. \t(%d)\n", display_weighted ? 1 : 0); fprintf(stdout, - "\t[K] hide kernel_symbols symbols. \t(%s)\n", + "\t[K] hide kernel_symbols symbols. \t(%s)\n", hide_kernel_symbols ? "yes" : "no"); fprintf(stdout, "\t[U] hide user symbols. \t(%s)\n", diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c index bb0fd6da2d56..8a9e6baa3099 100644 --- a/tools/perf/util/event.c +++ b/tools/perf/util/event.c @@ -295,10 +295,10 @@ void thread__find_addr_location(struct thread *self, al->thread = self; al->addr = addr; - if (cpumode & PERF_RECORD_MISC_KERNEL) { + if (cpumode == PERF_RECORD_MISC_KERNEL) { al->level = 'k'; mg = &session->kmaps; - } else if (cpumode & PERF_RECORD_MISC_USER) + } else if (cpumode == PERF_RECORD_MISC_USER) al->level = '.'; else { al->level = 'H'; |