diff options
| -rw-r--r-- | arch/arm/boot/dts/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/emev2-kzm9d.dts | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/emev2.dtsi | 48 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a73a4.dtsi | 9 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7740-armadillo800eva.dts | 13 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7740.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7779.dtsi | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7790-lager.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7790.dtsi | 52 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7791-koelsch.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 32 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7793-gose.dts | 63 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7793.dtsi | 367 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7794-silk.dts | 102 | ||||
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 19 | ||||
| -rw-r--r-- | arch/arm/boot/dts/sh73a0.dtsi | 3 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a7790-clock.h | 3 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a7791-clock.h | 2 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a7793-clock.h | 164 |
19 files changed, 886 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 246473a244f6..c6e0befabada 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -516,7 +516,9 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r8a7790-lager.dtb \ r8a7791-henninger.dtb \ r8a7791-koelsch.dtb \ + r8a7793-gose.dtb \ r8a7794-alt.dtb \ + r8a7794-silk.dtb \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 1dee0aa4f40c..955c24ee4a8c 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -95,6 +95,14 @@ }; }; +&iic0 { + status = "okay"; +}; + +&iic1 { + status = "okay"; +}; + &pfc { uart1_pins: serial@e1030000 { renesas,groups = "uart1_ctrl", "uart1_data"; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index bb45694d91bc..edad0c4eea35 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -21,6 +21,8 @@ gpio2 = &gpio2; gpio3 = &gpio3; gpio4 = &gpio4; + i2c0 = &iic0; + i2c1 = &iic1; }; cpus { @@ -66,6 +68,30 @@ clock-frequency = <32768>; #clock-cells = <0>; }; + iic0_sclkdiv: iic0_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x624 0>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + iic0_sclk: iic0_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x48c 1>; + clocks = <&iic0_sclkdiv>; + #clock-cells = <0>; + }; + iic1_sclkdiv: iic1_sclkdiv { + compatible = "renesas,emev2-smu-clkdiv"; + reg = <0x624 16>; + clocks = <&pll3_fo>; + #clock-cells = <0>; + }; + iic1_sclk: iic1_sclk { + compatible = "renesas,emev2-smu-gclk"; + reg = <0x490 1>; + clocks = <&iic1_sclkdiv>; + #clock-cells = <0>; + }; pll3_fo: pll3_fo { compatible = "fixed-factor-clock"; clocks = <&c32ki>; @@ -234,4 +260,26 @@ interrupt-controller; #interrupt-cells = <2>; }; + + iic0: i2c@e0070000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-emev2"; + reg = <0xe0070000 0x28>; + interrupts = <0 32 IRQ_TYPE_EDGE_RISING>; + clocks = <&iic0_sclk>; + clock-names = "sclk"; + status = "disabled"; + }; + + iic1: i2c@e10a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-emev2"; + reg = <0xe10a0000 0x28>; + interrupts = <0 33 IRQ_TYPE_EDGE_RISING>; + clocks = <&iic1_sclk>; + clock-names = "sclk"; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 7ee22a41c6c9..cb4f7b2798fe 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -207,6 +207,13 @@ reg = <0 0xe6050000 0 0x9000>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = + <&pfc 0 0 31>, <&pfc 32 32 9>, + <&pfc 64 64 22>, <&pfc 96 96 31>, + <&pfc 128 128 7>, <&pfc 160 160 19>, + <&pfc 192 192 31>, <&pfc 224 224 27>, + <&pfc 256 256 28>, <&pfc 288 288 21>, + <&pfc 320 320 10>; interrupts-extended = <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, @@ -434,7 +441,7 @@ }; gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index 2e31d8c01cbf..105d9c95de4a 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -224,6 +224,9 @@ }; &pfc { + pinctrl-0 = <&lcd0_pins>; + pinctrl-names = "default"; + ether_pins: ether { renesas,groups = "gether_mii", "gether_int"; renesas,function = "gether"; @@ -259,6 +262,16 @@ "fsia_data_in_1", "fsia_data_out_0"; renesas,function = "fsia"; }; + + lcd0_pins: lcd0 { + renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; + renesas,function = "lcd0"; + + /* DBGMD/LCDC0/FSIA MUX */ + gpio-hog; + gpios = <176 0>; + output-high; + }; }; &tpu { diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index d84714468cce..e14cb1438216 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -291,6 +291,7 @@ <0xe605800c 0x20>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 212>; interrupts-extended = <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 5c8071e87ae9..a2b5430d3257 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -148,7 +148,7 @@ interrupt-controller; }; - irqpin0: interrupt-controller@fe780010 { + irqpin0: interrupt-controller@fe78001c { compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; #interrupt-cells = <2>; status = "disabled"; @@ -157,7 +157,8 @@ <0xfe780010 4>, <0xfe780024 4>, <0xfe780044 4>, - <0xfe780064 4>; + <0xfe780064 4>, + <0xfe780000 4>; interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH 0 28 IRQ_TYPE_LEVEL_HIGH 0 29 IRQ_TYPE_LEVEL_HIGH diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 2eb8a995ae9f..37dec5269491 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -174,7 +174,7 @@ 1800000 0>; }; - sound { + rsnd_ak4643: sound { compatible = "simple-audio-card"; simple-audio-card,format = "left_j"; @@ -548,7 +548,7 @@ compatible = "adi,adv7511w"; reg = <0x39>; interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; adi,input-depth = <8>; adi,input-colorspace = "rgb"; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 51ab8865ea37..5b2952d5c700 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -113,7 +113,7 @@ }; gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; @@ -671,6 +671,16 @@ status = "disabled"; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7790"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata0: sata@ee300000 { compatible = "renesas,sata-r8a7790"; reg = <0 0xee300000 0 0x2000>; @@ -862,6 +872,13 @@ status = "disabled"; }; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7790"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_JPU>; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -1249,16 +1266,18 @@ compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; + <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>; #clock-cells = <1>; clock-indices = < R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 - R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER + R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 + R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 >; clock-output-names = - "mlb", "vin3", "vin2", "vin1", "vin0", "ether", - "sata1", "sata0"; + "mlb", "vin3", "vin2", "vin1", "vin0", + "etheravb", "ether", "sata1", "sata0"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -1291,6 +1310,7 @@ <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, + <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; #clock-cells = <1>; @@ -1300,6 +1320,7 @@ R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 R8A7790_CLK_SCU_ALL R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 + R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 >; @@ -1309,6 +1330,7 @@ "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", "scu-all", "scu-dvc1", "scu-dvc0", + "scu-ctu1-mix1", "scu-ctu0-mix0", "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; }; @@ -1524,6 +1546,8 @@ <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, + <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; clock-names = "ssi-all", @@ -1531,6 +1555,8 @@ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", "src.9", "src.8", "src.7", "src.6", "src.5", "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; @@ -1547,6 +1573,22 @@ }; }; + rcar_sound,mix { + mix0: mix@0 { }; + mix1: mix@1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; + ctu02: ctu@2 { }; + ctu03: ctu@3 { }; + ctu10: ctu@4 { }; + ctu11: ctu@5 { }; + ctu12: ctu@6 { }; + ctu13: ctu@7 { }; + }; + rcar_sound,src { src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index cffe33ff4d16..dc158845afdc 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -242,7 +242,7 @@ 1800000 0>; }; - sound { + rsnd_ak4643: sound { compatible = "simple-audio-card"; simple-audio-card,format = "left_j"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index dc1cd3f16606..1cb6c2d07933 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -70,7 +70,7 @@ }; gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; @@ -898,6 +898,13 @@ status = "disabled"; }; + jpu: jpeg-codec@fe980000 { + compatible = "renesas,jpu-r8a7791"; + reg = <0 0xfe980000 0 0x10300>; + interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_JPU>; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -1311,6 +1318,7 @@ <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, + <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; #clock-cells = <1>; @@ -1320,6 +1328,7 @@ R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 R8A7791_CLK_SCU_ALL R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 + R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 >; @@ -1329,6 +1338,7 @@ "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", "scu-all", "scu-dvc1", "scu-dvc0", + "scu-ctu1-mix1", "scu-ctu0-mix0", "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; }; @@ -1582,6 +1592,8 @@ <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, + <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; clock-names = "ssi-all", @@ -1589,6 +1601,8 @@ "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", "src.9", "src.8", "src.7", "src.6", "src.5", "src.4", "src.3", "src.2", "src.1", "src.0", + "ctu.0", "ctu.1", + "mix.0", "mix.1", "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; @@ -1605,6 +1619,22 @@ }; }; + rcar_sound,mix { + mix0: mix@0 { }; + mix1: mix@1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; + ctu02: ctu@2 { }; + ctu03: ctu@3 { }; + ctu10: ctu@4 { }; + ctu11: ctu@5 { }; + ctu12: ctu@6 { }; + ctu13: ctu@7 { }; + }; + rcar_sound,src { src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts new file mode 100644 index 000000000000..96443ec5f6ab --- /dev/null +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -0,0 +1,63 @@ +/* + * Device Tree Source for the Gose board + * + * Copyright (C) 2014-2015 Renesas Electronics Corporation + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7793.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Gose"; + compatible = "renesas,gose", "renesas,r8a7793"; + + aliases { + serial0 = &scif0; + serial1 = &scif1; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif0; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +ðer { + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + +&cmt0 { + status = "okay"; +}; + +&scif0 { + status = "okay"; +}; + +&scif1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi new file mode 100644 index 000000000000..3355c487d108 --- /dev/null +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -0,0 +1,367 @@ +/* + * Device Tree Source for the r8a7793 SoC + * + * Copyright (C) 2014-2015 Renesas Electronics Corporation + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/clock/r8a7793-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "renesas,r8a7793"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + clock-frequency = <1500000000>; + voltage-tolerance = <1>; /* 1% */ + clocks = <&cpg_clocks R8A7793_CLK_Z>; + clock-latency = <300000>; /* 300 us */ + + /* kHz - uV - OPPs unknown yet */ + operating-points = <1500000 1000000>, + <1312500 1000000>, + <1125000 1000000>, + < 937500 1000000>, + < 750000 1000000>, + < 375000 1000000>; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7793_CLK_CMT0>; + clock-names = "fck"; + + renesas,channels-mask = <0x60>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, + <0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 124 IRQ_TYPE_LEVEL_HIGH>, + <0 125 IRQ_TYPE_LEVEL_HIGH>, + <0 126 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_CMT1>; + clock-names = "fck"; + + renesas,channels-mask = <0xff>; + + status = "disabled"; + }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7793", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7793_CLK_IRQC>; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7793", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7793_CLK_SCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7793", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7793_CLK_SCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + ether: ethernet@ee700000 { + compatible = "renesas,ether-r8a7793"; + reg = <0 0xee700000 0 0x400>; + interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp8_clks R8A7793_CLK_ETHER>; + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7793-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z", + "rcan", "adsp"; + }; + + /* Variable factor clocks */ + sd2_clk: sd2_clk@e6150078 { + compatible = "renesas,r8a7793-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + sd3_clk: sd3_clk@e615026c { + compatible = "renesas,r8a7793-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe615026c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd3"; + }; + mmc0_clk: mmc0_clk@e6150240 { + compatible = "renesas,r8a7793-div6-clock", + "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <5>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7793_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + /* Gate clocks */ + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7793-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, + <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, + <&zs_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 + R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 + R8A7793_CLK_3DG R8A7793_CLK_2DDMAC + R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 + R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 + R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 + R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 + R8A7793_CLK_VSP1_S + >; + clock-output-names = + "vcp0", "vpc0", "ssp_dev", "tmu1", + "pvrsrvkm", "tddmac", "fdp1", "fdp0", + "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "vsp1-du0", "vsps"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7793-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, + <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, + <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, + <&rclk_clk>, <&hp_clk>, <&hp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 + R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 + R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 + R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 + R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 + R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 + >; + clock-output-names = + "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", + "i2c7", "pciec", "i2c8", "ssusb", "cmt1", + "usbdmac0", "usbdmac1"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; + clocks = <&cp_clk>; + #clock-cells = <1>; + clock-indices = <R8A7793_CLK_IRQC>; + clock-output-names = "irqc"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7793-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, + <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, + <&zx_clk>, <&zx_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7793_CLK_EHCI R8A7793_CLK_HSUSB + R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 + R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 + R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 + R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 + R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 + R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 + >; + clock-output-names = + "ehci", "hsusb", "hscif2", "scif5", "scif4", + "hscif1", "hscif0", "scif3", "scif2", + "scif1", "scif0", "du1", "du0", "lvds0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7793-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, + <&p_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 + R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 + R8A7793_CLK_ETHER R8A7793_CLK_SATA1 + R8A7793_CLK_SATA0 + >; + clock-output-names = + "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", + "sata1", "sata0"; + }; + }; + +}; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts new file mode 100644 index 000000000000..d4dd5a30ccdf --- /dev/null +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -0,0 +1,102 @@ +/* + * Device Tree Source for the SILK board + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2014-2015 Renesas Solutions Corp. + * Copyright (C) 2014-2015 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7794.dtsi" + +/ { + model = "SILK"; + compatible = "renesas,silk", "renesas,r8a7794"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + d3_3v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + scif2_pins: serial2 { + renesas,groups = "scif2_data"; + renesas,function = "scif2"; + }; + + ether_pins: ether { + renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; + renesas,function = "eth"; + }; + + phy1_pins: phy1 { + renesas,groups = "intc_irq8"; + renesas,function = "intc"; + }; + + mmcif0_pins: mmcif0 { + renesas,groups = "mmc_data8", "mmc_ctrl"; + renesas,function = "mmc"; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy1>; + renesas,ether-link-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&irqc0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&d3_3v>; + vqmmc-supply = <&d3_3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index b73819423311..43acf185ecc4 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -39,7 +39,7 @@ }; gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a7-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; @@ -108,6 +108,12 @@ clocks = <&mstp4_clks R8A7794_CLK_IRQC>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7794"; + reg = <0 0xe6060000 0 0x11c>; + #gpio-range-cells = <3>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,rcar-dmac"; reg = <0 0xe6700000 0 0x20000>; @@ -377,6 +383,17 @@ status = "disabled"; }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; + reg-io-width = <4>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee100000 0 0x200>; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 11e17c5f26e2..ff7c8f298f30 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -392,6 +392,9 @@ <0xe605801c 0x1c>; gpio-controller; #gpio-cells = <2>; + gpio-ranges = + <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, + <&pfc 288 288 22>; interrupts-extended = <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index ff7ca3584e16..7b1ad8922eec 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -108,6 +108,7 @@ #define R8A7790_CLK_VIN2 9 #define R8A7790_CLK_VIN1 10 #define R8A7790_CLK_VIN0 11 +#define R8A7790_CLK_ETHERAVB 12 #define R8A7790_CLK_ETHER 13 #define R8A7790_CLK_SATA1 14 #define R8A7790_CLK_SATA0 15 @@ -143,6 +144,8 @@ #define R8A7790_CLK_SCU_ALL 17 #define R8A7790_CLK_SCU_DVC1 18 #define R8A7790_CLK_SCU_DVC0 19 +#define R8A7790_CLK_SCU_CTU1_MIX1 20 +#define R8A7790_CLK_SCU_CTU0_MIX0 21 #define R8A7790_CLK_SCU_SRC9 22 #define R8A7790_CLK_SCU_SRC8 23 #define R8A7790_CLK_SCU_SRC7 24 diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index 402268384b99..dd09b73c4aaf 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -141,6 +141,8 @@ #define R8A7791_CLK_SCU_ALL 17 #define R8A7791_CLK_SCU_DVC1 18 #define R8A7791_CLK_SCU_DVC0 19 +#define R8A7791_CLK_SCU_CTU1_MIX1 20 +#define R8A7791_CLK_SCU_CTU0_MIX0 21 #define R8A7791_CLK_SCU_SRC9 22 #define R8A7791_CLK_SCU_SRC8 23 #define R8A7791_CLK_SCU_SRC7 24 diff --git a/include/dt-bindings/clock/r8a7793-clock.h b/include/dt-bindings/clock/r8a7793-clock.h new file mode 100644 index 000000000000..1579e07f96a3 --- /dev/null +++ b/include/dt-bindings/clock/r8a7793-clock.h @@ -0,0 +1,164 @@ +/* + * r8a7793 clock definition + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__ +#define __DT_BINDINGS_CLOCK_R8A7793_H__ + +/* CPG */ +#define R8A7793_CLK_MAIN 0 +#define R8A7793_CLK_PLL0 1 +#define R8A7793_CLK_PLL1 2 +#define R8A7793_CLK_PLL3 3 +#define R8A7793_CLK_LB 4 +#define R8A7793_CLK_QSPI 5 +#define R8A7793_CLK_SDH 6 +#define R8A7793_CLK_SD0 7 +#define R8A7793_CLK_Z 8 +#define R8A7793_CLK_RCAN 9 +#define R8A7793_CLK_ADSP 10 + +/* MSTP0 */ +#define R8A7793_CLK_MSIOF0 0 + +/* MSTP1 */ +#define R8A7793_CLK_VCP0 1 +#define R8A7793_CLK_VPC0 3 +#define R8A7793_CLK_SSP1 9 +#define R8A7793_CLK_TMU1 11 +#define R8A7793_CLK_3DG 12 +#define R8A7793_CLK_2DDMAC 15 +#define R8A7793_CLK_FDP1_1 18 +#define R8A7793_CLK_FDP1_0 19 +#define R8A7793_CLK_TMU3 21 +#define R8A7793_CLK_TMU2 22 +#define R8A7793_CLK_CMT0 24 +#define R8A7793_CLK_TMU0 25 +#define R8A7793_CLK_VSP1_DU1 27 +#define R8A7793_CLK_VSP1_DU0 28 +#define R8A7793_CLK_VSP1_S 31 + +/* MSTP2 */ +#define R8A7793_CLK_SCIFA2 2 +#define R8A7793_CLK_SCIFA1 3 +#define R8A7793_CLK_SCIFA0 4 +#define R8A7793_CLK_MSIOF2 5 +#define R8A7793_CLK_SCIFB0 6 +#define R8A7793_CLK_SCIFB1 7 +#define R8A7793_CLK_MSIOF1 8 +#define R8A7793_CLK_SCIFB2 16 +#define R8A7793_CLK_SYS_DMAC1 18 +#define R8A7793_CLK_SYS_DMAC0 19 + +/* MSTP3 */ +#define R8A7793_CLK_TPU0 4 +#define R8A7793_CLK_SDHI2 11 +#define R8A7793_CLK_SDHI1 12 +#define R8A7793_CLK_SDHI0 14 +#define R8A7793_CLK_MMCIF0 15 +#define R8A7793_CLK_IIC0 18 +#define R8A7793_CLK_PCIEC 19 +#define R8A7793_CLK_IIC1 23 +#define R8A7793_CLK_SSUSB 28 +#define R8A7793_CLK_CMT1 29 +#define R8A7793_CLK_USBDMAC0 30 +#define R8A7793_CLK_USBDMAC1 31 + +/* MSTP4 */ +#define R8A7793_CLK_IRQC 7 + +/* MSTP5 */ +#define R8A7793_CLK_AUDIO_DMAC1 1 +#define R8A7793_CLK_AUDIO_DMAC0 2 +#define R8A7793_CLK_ADSP_MOD 6 +#define R8A7793_CLK_THERMAL 22 +#define R8A7793_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7793_CLK_EHCI 3 +#define R8A7793_CLK_HSUSB 4 +#define R8A7793_CLK_HSCIF2 13 +#define R8A7793_CLK_SCIF5 14 +#define R8A7793_CLK_SCIF4 15 +#define R8A7793_CLK_HSCIF1 16 +#define R8A7793_CLK_HSCIF0 17 +#define R8A7793_CLK_SCIF3 18 +#define R8A7793_CLK_SCIF2 19 +#define R8A7793_CLK_SCIF1 20 +#define R8A7793_CLK_SCIF0 21 +#define R8A7793_CLK_DU1 23 +#define R8A7793_CLK_DU0 24 +#define R8A7793_CLK_LVDS0 26 + +/* MSTP8 */ +#define R8A7793_CLK_IPMMU_SGX 0 +#define R8A7793_CLK_VIN2 9 +#define R8A7793_CLK_VIN1 10 +#define R8A7793_CLK_VIN0 11 +#define R8A7793_CLK_ETHER 13 +#define R8A7793_CLK_SATA1 14 +#define R8A7793_CLK_SATA0 15 + +/* MSTP9 */ +#define R8A7793_CLK_GPIO7 4 +#define R8A7793_CLK_GPIO6 5 +#define R8A7793_CLK_GPIO5 7 +#define R8A7793_CLK_GPIO4 8 +#define R8A7793_CLK_GPIO3 9 +#define R8A7793_CLK_GPIO2 10 +#define R8A7793_CLK_GPIO1 11 +#define R8A7793_CLK_GPIO0 12 +#define R8A7793_CLK_RCAN1 15 +#define R8A7793_CLK_RCAN0 16 +#define R8A7793_CLK_QSPI_MOD 17 +#define R8A7793_CLK_I2C5 25 +#define R8A7793_CLK_IICDVFS 26 +#define R8A7793_CLK_I2C4 27 +#define R8A7793_CLK_I2C3 28 +#define R8A7793_CLK_I2C2 29 +#define R8A7793_CLK_I2C1 30 +#define R8A7793_CLK_I2C0 31 + +/* MSTP10 */ +#define R8A7793_CLK_SSI_ALL 5 +#define R8A7793_CLK_SSI9 6 +#define R8A7793_CLK_SSI8 7 +#define R8A7793_CLK_SSI7 8 +#define R8A7793_CLK_SSI6 9 +#define R8A7793_CLK_SSI5 10 +#define R8A7793_CLK_SSI4 11 +#define R8A7793_CLK_SSI3 12 +#define R8A7793_CLK_SSI2 13 +#define R8A7793_CLK_SSI1 14 +#define R8A7793_CLK_SSI0 15 +#define R8A7793_CLK_SCU_ALL 17 +#define R8A7793_CLK_SCU_DVC1 18 +#define R8A7793_CLK_SCU_DVC0 19 +#define R8A7793_CLK_SCU_SRC9 22 +#define R8A7793_CLK_SCU_SRC8 23 +#define R8A7793_CLK_SCU_SRC7 24 +#define R8A7793_CLK_SCU_SRC6 25 +#define R8A7793_CLK_SCU_SRC5 26 +#define R8A7793_CLK_SCU_SRC4 27 +#define R8A7793_CLK_SCU_SRC3 28 +#define R8A7793_CLK_SCU_SRC2 29 +#define R8A7793_CLK_SCU_SRC1 30 +#define R8A7793_CLK_SCU_SRC0 31 + +/* MSTP11 */ +#define R8A7793_CLK_SCIFA3 6 +#define R8A7793_CLK_SCIFA4 7 +#define R8A7793_CLK_SCIFA5 8 + +#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */ |