diff options
30 files changed, 9123 insertions, 69 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file mode 100644 index 000000000000..e4b9f3da2cf0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml @@ -0,0 +1,216 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM845 Pin Controller and GPIO + +maintainers: + - Tomer Maimon <[email protected]> + +description: + The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through + the multiplexing block, Each pin supports GPIO functionality (GPIOx) + and multiple functions that directly connect the pin to different + hardware blocks. + +properties: + compatible: + const: nuvoton,npcm845-pinctrl + + ranges: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + nuvoton,sysgcr: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to access GCR registers. + +patternProperties: + '^gpio@': + type: object + + description: + Eight GPIO banks that each contain 32 GPIOs. + + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-ranges: + maxItems: 1 + + required: + - gpio-controller + - '#gpio-cells' + - reg + - interrupts + - gpio-ranges + + '-mux$': + $ref: pinmux-node.yaml# + + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, + smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b, + smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21, + smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3, + spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2, + spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2, + bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen, + r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3, + fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10, + fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2, + pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2, + ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, + smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, + sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, + mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk, + scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1, + spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den, + smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix, + spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4, + hgpio5, hgpio6, hgpio7 ] + + function: + description: + The function that a group of pins is muxed to + enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, + smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4den, smb4b, + smb4c, smb15, smb16, smb17, smb18, smb19, smb20, smb21, + smb22, smb23, smb23b, smb4d, smb14, smb5, smb4, smb3, + spi0cs1, spi0cs2, spi0cs3, spi1cs0, spi1cs1, spi1cs2, + spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, uart1, jtag2, + bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, r1oen, + r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, fanin3, + fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10, + fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2, + pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2, + ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, + smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, + sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, + mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, lpcclk, + scipme, smi, smb6, smb7, spi1, faninx, r1, spi3, spi3cs1, + spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, smb0den, + smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, spix, + spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4, + hgpio5, hgpio6, hgpio7 ] + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + + '^pin': + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + items: + pattern: '^GPIO([0-9]|[0-9][0-9]|1[0-9][0-9]|2[0-4][0-9]|25[0-6])' + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-low: true + + output-high: true + + drive-push-pull: true + + drive-open-drain: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 4 + + slew-rate: + description: | + 0: Low rate + 1: High rate + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + drive-strength: + enum: [ 0, 1, 2, 4, 8, 12 ] + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - ranges + - '#address-cells' + - '#size-cells' + - nuvoton,sysgcr + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@f0010000 { + compatible = "nuvoton,npcm845-pinctrl"; + ranges = <0x0 0x0 0xf0010000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + nuvoton,sysgcr = <&gcr>; + + gpio0: gpio@0 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0xb0>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + fanin0_pin: fanin0-mux { + groups = "fanin0"; + function = "fanin0"; + }; + + pin34_slew: pin34-slew { + pins = "GPIO34/I3C4_SDA"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml new file mode 100644 index 000000000000..fc6c65fea73b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1315e-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1315E Pin Controller + +maintainers: + - TY Chang <[email protected]> + +description: + The Realtek DHC RTD1315E is a high-definition media processor SoC. The + RTD1315E pin controller is used to control pin function, pull up/down + resistor, drive strength, schmitt trigger and power source. + +properties: + compatible: + const: realtek,rtd1315e-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + items: + enum: [ gpio_0, gpio_1, emmc_rst_n, emmc_dd_sb, emmc_clk, emmc_cmd, + gpio_6, gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, + gpio_13, gpio_14, gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, + gpio_20, emmc_data_0, emmc_data_1, emmc_data_2, usb_cc2, gpio_25, + gpio_26, gpio_27, gpio_28, gpio_29, gpio_30, gpio_31, gpio_32, + gpio_33, gpio_34, gpio_35, hif_data, hif_en, hif_rdy, hif_clk, + gpio_dummy_40, gpio_dummy_41, gpio_dummy_42, gpio_dummy_43, + gpio_dummy_44, gpio_dummy_45, gpio_46, gpio_47, gpio_48, gpio_49, + gpio_50, usb_cc1, emmc_data_3, emmc_data_4, ir_rx, ur0_rx, ur0_tx, + gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, gpio_62, gpio_dummy_63, + gpio_dummy_64, gpio_dummy_65, gpio_66, gpio_67, gpio_68, gpio_69, + gpio_70, gpio_71, gpio_72, gpio_dummy_73, emmc_data_5, emmc_data_6, + emmc_data_7, gpio_dummy_77, gpio_78, gpio_79, gpio_80, gpio_81, + ur2_loc, gspi_loc, hi_width, sf_en, arm_trace_dbg_en, + ejtag_aucpu_loc, ejtag_acpu_loc, ejtag_vcpu_loc, ejtag_scpu_loc, + dmic_loc, vtc_dmic_loc, vtc_tdm_loc, vtc_i2si_loc, tdm_ai_loc, + ai_loc, spdif_loc, hif_en_loc, scan_switch, wd_rset, boot_sel, + reset_n, testmode ] + + function: + enum: [ gpio, nf, emmc, ao, gspi_loc0, gspi_loc1, uart0, uart1, + uart2_loc0, uart2_loc1, i2c0, i2c1, i2c4, i2c5, pcie1, + etn_led, etn_phy, spi, pwm0_loc0, pwm0_loc1, pwm1_loc0, + pwm1_loc1, pwm2_loc0, pwm2_loc1, pwm3_loc0, pwm3_loc1, + spdif_optical_loc0, spdif_optical_loc1, usb_cc1, usb_cc2, + sd, dmic_loc0, dmic_loc1, ai_loc0, ai_loc1, tdm_ai_loc0, + tdm_ai_loc1, hi_loc0, hi_m, vtc_i2so, vtc_i2si_loc0, + vtc_i2si_loc1, vtc_dmic_loc0, vtc_dmic_loc1, vtc_tdm_loc0, + vtc_tdm_loc1, dc_fan, pll_test_loc0, pll_test_loc1, + ir_rx, uart2_disable, gspi_disable, hi_width_disable, + hi_width_1bit, sf_disable, sf_enable, scpu_ejtag_loc0, + scpu_ejtag_loc1, scpu_ejtag_loc2, scpu_ejtag_loc3, + acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2, + vcpu_ejtag_loc0, vcpu_ejtag_loc1, vcpu_ejtag_loc2, + aucpu_ejtag_loc0, aucpu_ejtag_loc1, aucpu_ejtag_loc2, + gpu_ejtag, iso_tristate, dbg_out0, dbg_out1, standby_dbg, + spdif, arm_trace_debug_disable, arm_trace_debug_enable, + aucpu_ejtag_disable, acpu_ejtag_disable, vcpu_ejtag_disable, + scpu_ejtag_disable, vtc_dmic_loc_disable, vtc_tdm_disable, + vtc_i2si_disable, tdm_ai_disable, ai_disable, spdif_disable, + hif_disable, hif_enable, test_loop, pmic_pwrup ] + + drive-strength: + enum: [4, 8] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-push-pull: true + + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + realtek,drive-strength-p: + description: | + Some of pins can be driven using the P-MOS and N-MOS transistor to + achieve finer adjustments. The block-diagram representation is as + follows: + VDD + | + ||--+ + +-----o|| P-MOS-FET + | ||--+ + IN --+ +----- out + | ||--+ + +------|| N-MOS-FET + ||--+ + | + GND + The driving strength of the P-MOS/N-MOS transistors impacts the + waveform's rise/fall times. Greater driving strength results in + shorter rise/fall times. Each P-MOS and N-MOS transistor offers + 8 configurable levels (0 to 7), with higher values indicating + greater driving strength, contributing to achieving the desired + speed. + + The realtek,drive-strength-p is used to control the driving strength + of the P-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,drive-strength-n: + description: | + Similar to the realtek,drive-strength-p, the realtek,drive-strength-n + is used to control the driving strength of the N-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,duty-cycle: + description: | + An integer describing the level to adjust output duty cycle, controlling + the proportion of positive and negative waveforms in nanoseconds. + Valid arguments are described as below: + 0: 0ns + 2: + 0.25ns + 3: + 0.5ns + 4: -0.25ns + 5: -0.5ns + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 2, 3, 4, 5 ] + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4e000 { + compatible = "realtek,rtd1315e-pinctrl"; + reg = <0x4e000 0x130>; + + emmc-hs200-pins { + pins = "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + function = "emmc"; + realtek,drive-strength-p = <0x2>; + realtek,drive-strength-n = <0x2>; + }; + + i2c-0-pins { + pins = "gpio_12", + "gpio_13"; + function = "i2c0"; + drive-strength = <4>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml new file mode 100644 index 000000000000..f07361d60acd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1319d-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1319D Pin Controller + +maintainers: + - TY Chang <[email protected]> + +description: + The Realtek DHC RTD1319D is a high-definition media processor SoC. The + RTD1319D pin controller is used to control pin function, pull up/down + resistor, drive strength, schmitt trigger and power source. + +properties: + compatible: + const: realtek,rtd1319d-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + items: + enum: [ gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, gpio_7, + gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, gpio_14, + gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20, gpio_21, + gpio_22, gpio_23, usb_cc2, gpio_25, gpio_26, gpio_27, gpio_28, + gpio_29, gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, + hif_data, hif_en, hif_rdy, hif_clk, gpio_40, gpio_41, gpio_42, + gpio_43, gpio_44, gpio_45, gpio_46, gpio_47, gpio_48, gpio_49, + gpio_50, usb_cc1, gpio_52, gpio_53, ir_rx, ur0_rx, ur0_tx, + gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, gpio_62, gpio_63, + gpio_64, emmc_rst_n, emmc_dd_sb, emmc_clk, emmc_cmd, emmc_data_0, + emmc_data_1, emmc_data_2, emmc_data_3, emmc_data_4, emmc_data_5, + emmc_data_6, emmc_data_7, dummy, gpio_78, gpio_79, gpio_80, + gpio_81, ur2_loc, gspi_loc, hi_width, sf_en, arm_trace_dbg_en, + ejtag_aucpu_loc, ejtag_acpu_loc, ejtag_vcpu_loc, ejtag_scpu_loc, + dmic_loc, ejtag_secpu_loc, vtc_dmic_loc, vtc_tdm_loc, vtc_i2si_loc, + tdm_ai_loc, ai_loc, spdif_loc, hif_en_loc, sc0_loc, sc1_loc, + scan_switch, wd_rset, boot_sel, reset_n, testmode ] + + function: + enum: [ gpio, nf, emmc, tp0, tp1, sc0, sc0_data0, sc0_data1, sc0_data2, + sc1, sc1_data0, sc1_data1, sc1_data2, ao, gspi_loc0, gspi_loc1, + uart0, uart1, uart2_loc0, uart2_loc1, i2c0, i2c1, i2c3, i2c4, + i2c5, pcie1, sdio, etn_led, etn_phy, spi, pwm0_loc0, pwm0_loc1, + pwm1_loc0, pwm1_loc1, pwm2_loc0, pwm2_loc1, pwm3_loc0, pwm3_loc1, + qam_agc_if0, qam_agc_if1, spdif_optical_loc0, spdif_optical_loc1, + usb_cc1, usb_cc2, vfd, sd, dmic_loc0, dmic_loc1, ai_loc0, ai_loc1, + tdm_ai_loc0, tdm_ai_loc1, hi_loc0, hi_m, vtc_i2so, vtc_i2si_loc0, + vtc_i2si_loc1, vtc_dmic_loc0, vtc_dmic_loc1, vtc_tdm_loc0, + vtc_tdm_loc1, dc_fan, pll_test_loc0, pll_test_loc1, ir_rx, + uart2_disable, gspi_disable, hi_width_disable, hi_width_1bit, + sf_disable, sf_enable, scpu_ejtag_loc0, scpu_ejtag_loc1, + scpu_ejtag_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2, + vcpu_ejtag_loc0, vcpu_ejtag_loc1, vcpu_ejtag_loc2, secpu_ejtag_loc0, + secpu_ejtag_loc1, secpu_ejtag_loc2, aucpu_ejtag_loc0, aucpu_ejtag_loc1, + aucpu_ejtag_loc2, iso_tristate, dbg_out0, dbg_out1, standby_dbg, + spdif, arm_trace_debug_disable, arm_trace_debug_enable, + aucpu_ejtag_disable, acpu_ejtag_disable, vcpu_ejtag_disable, + scpu_ejtag_disable, secpu_ejtag_disable, vtc_dmic_loc_disable, + vtc_tdm_disable, vtc_i2si_disable, tdm_ai_disable, ai_disable, + spdif_disable, hif_disable, hif_enable, test_loop, pmic_pwrup ] + + drive-strength: + enum: [4, 8] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-push-pull: true + + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + realtek,drive-strength-p: + description: | + Some of pins can be driven using the P-MOS and N-MOS transistor to + achieve finer adjustments. The block-diagram representation is as + follows: + VDD + | + ||--+ + +-----o|| P-MOS-FET + | ||--+ + IN --+ +----- out + | ||--+ + +------|| N-MOS-FET + ||--+ + | + GND + The driving strength of the P-MOS/N-MOS transistors impacts the + waveform's rise/fall times. Greater driving strength results in + shorter rise/fall times. Each P-MOS and N-MOS transistor offers + 8 configurable levels (0 to 7), with higher values indicating + greater driving strength, contributing to achieving the desired + speed. + + The realtek,drive-strength-p is used to control the driving strength + of the P-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,drive-strength-n: + description: | + Similar to the realtek,drive-strength-p, the realtek,drive-strength-n + is used to control the driving strength of the N-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,duty-cycle: + description: | + An integer describing the level to adjust output duty cycle, controlling + the proportion of positive and negative waveforms in nanoseconds. + Valid arguments are described as below: + 0: 0ns + 2: + 0.25ns + 3: + 0.5ns + 4: -0.25ns + 5: -0.5ns + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 2, 3, 4, 5 ] + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4e000 { + compatible = "realtek,rtd1319d-pinctrl"; + reg = <0x4e000 0x130>; + + emmc-hs200-pins { + pins = "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + function = "emmc"; + realtek,drive-strength-p = <0x2>; + realtek,drive-strength-n = <0x2>; + }; + + i2c-0-pins { + pins = "gpio_12", + "gpio_13"; + function = "i2c0"; + drive-strength = <4>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml new file mode 100644 index 000000000000..671e4ec84624 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1619b-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1619B Pin Controller + +maintainers: + - TY Chang <[email protected]> + +description: + The Realtek DHC RTD1619B is a high-definition media processor SoC. The + RTD1619B pin controller is used to control pin function, pull up/down + resistor, drive strength, schmitt trigger and power source. + +properties: + compatible: + const: realtek,rtd1619b-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + items: + enum: [ gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, gpio_7, + gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, gpio_14, + gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20, gpio_21, + gpio_22, gpio_23, usb_cc2, gpio_25, gpio_26, gpio_27, gpio_28, + gpio_29, gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, + hif_data, hif_en, hif_rdy, hif_clk, gpio_40, gpio_41, gpio_42, + gpio_43, gpio_44, gpio_45, gpio_46, gpio_47, gpio_48, gpio_49, + gpio_50, usb_cc1, gpio_52, gpio_53, ir_rx, ur0_rx, ur0_tx, + gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, gpio_62, gpio_63, + gpio_64, gpio_65, gpio_66, gpio_67, gpio_68, gpio_69, gpio_70, + gpio_71, gpio_72, gpio_73, gpio_74, gpio_75, gpio_76, emmc_cmd, + spi_ce_n, spi_sck, spi_so, spi_si, emmc_rst_n, emmc_dd_sb, + emmc_clk, emmc_data_0, emmc_data_1, emmc_data_2, emmc_data_3, + emmc_data_4, emmc_data_5, emmc_data_6, emmc_data_7, ur2_loc, + gspi_loc, sdio_loc, hi_loc, hi_width, sf_en, arm_trace_dbg_en, + pwm_01_open_drain_en_loc0, pwm_23_open_drain_en_loc0, + pwm_01_open_drain_en_loc1, pwm_23_open_drain_en_loc1, + ejtag_acpu_loc, ejtag_vcpu_loc, ejtag_scpu_loc, dmic_loc, + iso_gspi_loc, ejtag_ve3_loc, ejtag_aucpu0_loc, ejtag_aucpu1_loc ] + + function: + enum: [ gpio, nf, nf_spi, spi, pmic, spdif, spdif_coaxial, spdif_optical_loc0, + spdif_optical_loc1, emmc_spi, emmc, sc1, uart0, uart1, uart2_loc0, uart2_loc1, + gspi_loc1, iso_gspi_loc1, i2c0, i2c1, i2c3, i2c4, i2c5, pwm0, pwm1, pwm2, + pwm3, etn_led, etn_phy, etn_clk, sc0, vfd, gspi_loc0, iso_gspi_loc0, pcie1, + pcie2, sd, sdio_loc0, sdio_loc1, hi, hi_m, dc_fan, pll_test_loc0, pll_test_loc1, + usb_cc1, usb_cc2, ir_rx, tdm_ai_loc0, tdm_ai_loc1, dmic_loc0, dmic_loc1, + ai_loc0, ai_loc1, tp0, tp1, ao, uart2_disable, gspi_disable, sdio_disable, + hi_loc_disable, hi_loc0, hi_width_disable, hi_width_1bit, vtc_i2si_loc0, + vtc_tdm_loc0, vtc_dmic_loc0, vtc_i2si_loc1, vtc_tdm_loc1, vtc_dmic_loc1, + vtc_i2so, ve3_ejtag_loc0, aucpu0_ejtag_loc0, aucpu1_ejtag_loc0, ve3_ejtag_loc1, + aucpu0_ejtag_loc1, aucpu1_ejtag_loc1, ve3_ejtag_loc2, aucpu0_ejtag_loc2, + aucpu1_ejtag_loc2, scpu_ejtag_loc0, acpu_ejtag_loc0, vcpu_ejtag_loc0, + scpu_ejtag_loc1, acpu_ejtag_loc1, vcpu_ejtag_loc1, scpu_ejtag_loc2, + acpu_ejtag_loc2, vcpu_ejtag_loc2, ve3_ejtag_disable, aucpu0_ejtag_disable, + aucpu1_ejtag_disable, acpu_ejtag_disable, vcpu_ejtag_disable, + scpu_ejtag_disable, iso_gspi_disable, sf_disable, sf_enable, + arm_trace_debug_disable, arm_trace_debug_enable, pwm_normal, pwm_open_drain, + standby_dbg, test_loop_dis ] + + drive-strength: + enum: [4, 8] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-push-pull: true + + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + realtek,drive-strength-p: + description: | + Some of pins can be driven using the P-MOS and N-MOS transistor to + achieve finer adjustments. The block-diagram representation is as + follows: + VDD + | + ||--+ + +-----o|| P-MOS-FET + | ||--+ + IN --+ +----- out + | ||--+ + +------|| N-MOS-FET + ||--+ + | + GND + The driving strength of the P-MOS/N-MOS transistors impacts the + waveform's rise/fall times. Greater driving strength results in + shorter rise/fall times. Each P-MOS and N-MOS transistor offers + 8 configurable levels (0 to 7), with higher values indicating + greater driving strength, contributing to achieving the desired + speed. + + The realtek,drive-strength-p is used to control the driving strength + of the P-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,drive-strength-n: + description: | + Similar to the realtek,drive-strength-p, the realtek,drive-strength-n + is used to control the driving strength of the N-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,duty-cycle: + description: | + An integer describing the level to adjust output duty cycle, controlling + the proportion of positive and negative waveforms in nanoseconds. + Valid arguments are described as below: + 0: 0ns + 2: + 0.25ns + 3: + 0.5ns + 4: -0.25ns + 5: -0.5ns + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 2, 3, 4, 5 ] + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4e000 { + compatible = "realtek,rtd1619b-pinctrl"; + reg = <0x4e000 0x130>; + + emmc-hs200-pins { + pins = "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + function = "emmc"; + realtek,drive-strength-p = <0x2>; + realtek,drive-strength-n = <0x2>; + }; + + i2c-0-pins { + pins = "gpio_12", + "gpio_13"; + function = "i2c0"; + drive-strength = <4>; + }; + }; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 7dfb7190580e..1de4e1edede0 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -520,6 +520,7 @@ source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/nxp/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" +source "drivers/pinctrl/realtek/Kconfig" source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/samsung/Kconfig" source "drivers/pinctrl/spear/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index dd6cda270294..37575deb7a69 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -66,6 +66,7 @@ obj-y += nuvoton/ obj-y += nxp/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-y += qcom/ +obj-$(CONFIG_ARCH_REALTEK) += realtek/ obj-$(CONFIG_PINCTRL_RENESAS) += renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 80838dc54b3a..d376fa7114d1 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1592,9 +1592,10 @@ SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC, SIG_DESC_SET(SCUC20, 16)); SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC); SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC); -SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC, + SIG_DESC_SET(SCUC20, 16)); PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP), - SIG_EXPR_LIST_PTR(A4, USB2AHDP)); + SIG_EXPR_LIST_PTR(A4, USB2AHDP), SIG_EXPR_LIST_PTR(A4, USB2AHPDP)); #define B4 253 SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC); @@ -1602,7 +1603,7 @@ SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC); SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC); SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC); PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN), - SIG_EXPR_LIST_PTR(B4, USB2AHDN)); + SIG_EXPR_LIST_PTR(B4, USB2AHDN), SIG_EXPR_LIST_PTR(B4, USB2AHPDN)); GROUP_DECL(USBA, A4, B4); diff --git a/drivers/pinctrl/berlin/berlin.c b/drivers/pinctrl/berlin/berlin.c index 1e427ea4d31b..9550cc8095c2 100644 --- a/drivers/pinctrl/berlin/berlin.c +++ b/drivers/pinctrl/berlin/berlin.c @@ -96,10 +96,10 @@ static int berlin_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrl_dev, } static const struct pinctrl_ops berlin_pinctrl_ops = { - .get_groups_count = &berlin_pinctrl_get_group_count, - .get_group_name = &berlin_pinctrl_get_group_name, - .dt_node_to_map = &berlin_pinctrl_dt_node_to_map, - .dt_free_map = &pinctrl_utils_free_map, + .get_groups_count = berlin_pinctrl_get_group_count, + .get_group_name = berlin_pinctrl_get_group_name, + .dt_node_to_map = berlin_pinctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, }; static int berlin_pinmux_get_functions_count(struct pinctrl_dev *pctrl_dev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7981.c b/drivers/pinctrl/mediatek/pinctrl-mt7981.c index 0fd2c0c451f9..7e59a4407859 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c @@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; +static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; +static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; + /* GBE_LED0 */ static int mt7981_gbe_led0_pins[] = { 8, }; static int mt7981_gbe_led0_funcs[] = { 3, }; @@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; +static int mt7981_uart1_2_pins[] = { 9, 10, }; +static int mt7981_uart1_2_funcs[] = { 2, 2, }; + /* UART2 */ static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; @@ -805,6 +811,8 @@ static const struct group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), /* @GPIO(4,7) WM_JTAG(3) */ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), + /* @GPIO(4,5) WM_JTAG(4) */ + PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), /* @GPIO(8) GBE_LED0(3) */ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), /* @GPIO(4,6) PTA_EXT(4) */ @@ -861,6 +869,8 @@ static const struct group_desc mt7981_groups[] = { PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), /* @GPIO(26,29): UART1(2) */ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), + /* @GPIO(9,10): UART1(2) */ + PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), /* @GPIO(22,25): UART1(3) */ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), /* @GPIO(22,24) PTA_EXT(4) */ @@ -922,9 +932,9 @@ static const struct group_desc mt7981_groups[] = { */ static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", "wa_aice3", "wm_aice1_2", }; -static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", - "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", - "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; +static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", + "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0", + "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig index 8fe61b348181..2abbfcec1fae 100644 --- a/drivers/pinctrl/nuvoton/Kconfig +++ b/drivers/pinctrl/nuvoton/Kconfig @@ -2,8 +2,7 @@ config PINCTRL_WPCM450 tristate "Pinctrl and GPIO driver for Nuvoton WPCM450" - depends on ARCH_WPCM450 || COMPILE_TEST - depends on OF + depends on (ARCH_WPCM450 || COMPILE_TEST) && OF select PINMUX select PINCONF select GENERIC_PINCONF @@ -32,3 +31,17 @@ config PINCTRL_NPCM7XX help Say Y here to enable pin controller and GPIO support for Nuvoton NPCM750/730/715/705 SoCs. + +config PINCTRL_NPCM8XX + tristate "Pinctrl and GPIO driver for Nuvoton NPCM8XX" + depends on (ARCH_NPCM || COMPILE_TEST) && OF + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIO_GENERIC + select GPIOLIB_IRQCHIP + help + Say Y or M here to enable pin controller and GPIO support for + the Nuvoton NPCM8XX SoC. This is strongly recommended when + building a kernel that will run on this chip. diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile index 9e66f5dc74bf..08031eab0af6 100644 --- a/drivers/pinctrl/nuvoton/Makefile +++ b/drivers/pinctrl/nuvoton/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_PINCTRL_WPCM450) += pinctrl-wpcm450.o obj-$(CONFIG_PINCTRL_NPCM7XX) += pinctrl-npcm7xx.o +obj-$(CONFIG_PINCTRL_NPCM8XX) += pinctrl-npcm8xx.o diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 843ffcd96877..8bdd0124e2eb 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -1588,19 +1588,6 @@ static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev, return 0; } -static int npcm7xx_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - u32 *num_maps) -{ - struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); - - dev_dbg(npcm->dev, "dt_node_to_map: %s\n", np_config->name); - return pinconf_generic_dt_node_to_map(pctldev, np_config, - map, num_maps, - PIN_MAP_TYPE_INVALID); -} - static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, u32 num_maps) { @@ -1612,7 +1599,7 @@ static const struct pinctrl_ops npcm7xx_pinctrl_ops = { .get_group_name = npcm7xx_get_group_name, .get_group_pins = npcm7xx_get_group_pins, .pin_dbg_show = npcm7xx_pin_dbg_show, - .dt_node_to_map = npcm7xx_dt_node_to_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, .dt_free_map = npcm7xx_dt_free_map, }; diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c new file mode 100644 index 000000000000..da21f6a45888 --- /dev/null +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -0,0 +1,2491 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020 Nuvoton Technology corporation. + +#include <linux/bits.h> +#include <linux/device.h> +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/debugfs.h> +#include <linux/seq_file.h> +#include <linux/mod_devicetable.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/consumer.h> +#include <linux/platform_device.h> +#include <linux/property.h> +#include <linux/regmap.h> + +/* GCR registers */ +#define NPCM8XX_GCR_SRCNT 0x068 +#define NPCM8XX_GCR_FLOCKR1 0x074 +#define NPCM8XX_GCR_DSCNT 0x078 +#define NPCM8XX_GCR_I2CSEGSEL 0x0e0 +#define NPCM8XX_GCR_MFSEL1 0x260 +#define NPCM8XX_GCR_MFSEL2 0x264 +#define NPCM8XX_GCR_MFSEL3 0x268 +#define NPCM8XX_GCR_MFSEL4 0x26c +#define NPCM8XX_GCR_MFSEL5 0x270 +#define NPCM8XX_GCR_MFSEL6 0x274 +#define NPCM8XX_GCR_MFSEL7 0x278 + +#define SRCNT_ESPI BIT(3) + +/* GPIO registers */ +#define NPCM8XX_GP_N_TLOCK1 0x00 +#define NPCM8XX_GP_N_DIN 0x04 +#define NPCM8XX_GP_N_POL 0x08 +#define NPCM8XX_GP_N_DOUT 0x0c +#define NPCM8XX_GP_N_OE 0x10 +#define NPCM8XX_GP_N_OTYP 0x14 +#define NPCM8XX_GP_N_MP 0x18 +#define NPCM8XX_GP_N_PU 0x1c +#define NPCM8XX_GP_N_PD 0x20 +#define NPCM8XX_GP_N_DBNC 0x24 +#define NPCM8XX_GP_N_EVTYP 0x28 +#define NPCM8XX_GP_N_EVBE 0x2c +#define NPCM8XX_GP_N_OBL0 0x30 +#define NPCM8XX_GP_N_OBL1 0x34 +#define NPCM8XX_GP_N_OBL2 0x38 +#define NPCM8XX_GP_N_OBL3 0x3c +#define NPCM8XX_GP_N_EVEN 0x40 +#define NPCM8XX_GP_N_EVENS 0x44 +#define NPCM8XX_GP_N_EVENC 0x48 +#define NPCM8XX_GP_N_EVST 0x4c +#define NPCM8XX_GP_N_SPLCK 0x50 +#define NPCM8XX_GP_N_MPLCK 0x54 +#define NPCM8XX_GP_N_IEM 0x58 +#define NPCM8XX_GP_N_OSRC 0x5c +#define NPCM8XX_GP_N_ODSC 0x60 +#define NPCM8XX_GP_N_DOS 0x68 +#define NPCM8XX_GP_N_DOC 0x6c +#define NPCM8XX_GP_N_OES 0x70 +#define NPCM8XX_GP_N_OEC 0x74 +#define NPCM8XX_GP_N_DBNCS0 0x80 +#define NPCM8XX_GP_N_DBNCS1 0x84 +#define NPCM8XX_GP_N_DBNCP0 0x88 +#define NPCM8XX_GP_N_DBNCP1 0x8c +#define NPCM8XX_GP_N_DBNCP2 0x90 +#define NPCM8XX_GP_N_DBNCP3 0x94 +#define NPCM8XX_GP_N_TLOCK2 0xac + +#define NPCM8XX_GPIO_PER_BANK 32 +#define NPCM8XX_GPIO_BANK_NUM 8 +#define NPCM8XX_GCR_NONE 0 + +#define NPCM8XX_DEBOUNCE_MAX 4 +#define NPCM8XX_DEBOUNCE_NSEC 40 +#define NPCM8XX_DEBOUNCE_VAL_MASK GENMASK(23, 4) +#define NPCM8XX_DEBOUNCE_MAX_VAL 0xFFFFF7 + +/* Structure for register banks */ +struct debounce_time { + bool set_val[NPCM8XX_DEBOUNCE_MAX]; + u32 nanosec_val[NPCM8XX_DEBOUNCE_MAX]; +}; + +struct npcm8xx_gpio { + struct gpio_chip gc; + void __iomem *base; + struct debounce_time debounce; + int irqbase; + int irq; + struct irq_chip irq_chip; + u32 pinctrl_id; + int (*direction_input)(struct gpio_chip *chip, unsigned int offset); + int (*direction_output)(struct gpio_chip *chip, unsigned int offset, + int value); + int (*request)(struct gpio_chip *chip, unsigned int offset); + void (*free)(struct gpio_chip *chip, unsigned int offset); +}; + +struct npcm8xx_pinctrl { + struct pinctrl_dev *pctldev; + struct device *dev; + struct npcm8xx_gpio gpio_bank[NPCM8XX_GPIO_BANK_NUM]; + struct irq_domain *domain; + struct regmap *gcr_regmap; + void __iomem *regs; + u32 bank_num; +}; + +/* GPIO handling in the pinctrl driver */ +static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg, + unsigned int pinmask) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + iowrite32(ioread32(reg) | pinmask, reg); + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); +} + +static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg, + unsigned int pinmask) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + iowrite32(ioread32(reg) & ~pinmask, reg); + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); +} + +static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) +{ + struct npcm8xx_gpio *bank = gpiochip_get_data(chip); + + seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n", + ioread32(bank->base + NPCM8XX_GP_N_DIN), + ioread32(bank->base + NPCM8XX_GP_N_DOUT), + ioread32(bank->base + NPCM8XX_GP_N_IEM), + ioread32(bank->base + NPCM8XX_GP_N_OE)); + seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n", + ioread32(bank->base + NPCM8XX_GP_N_PU), + ioread32(bank->base + NPCM8XX_GP_N_PD), + ioread32(bank->base + NPCM8XX_GP_N_DBNC), + ioread32(bank->base + NPCM8XX_GP_N_POL)); + seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n", + ioread32(bank->base + NPCM8XX_GP_N_EVTYP), + ioread32(bank->base + NPCM8XX_GP_N_EVBE), + ioread32(bank->base + NPCM8XX_GP_N_EVEN), + ioread32(bank->base + NPCM8XX_GP_N_EVST)); + seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n", + ioread32(bank->base + NPCM8XX_GP_N_OTYP), + ioread32(bank->base + NPCM8XX_GP_N_OSRC), + ioread32(bank->base + NPCM8XX_GP_N_ODSC)); + seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n", + ioread32(bank->base + NPCM8XX_GP_N_OBL0), + ioread32(bank->base + NPCM8XX_GP_N_OBL1), + ioread32(bank->base + NPCM8XX_GP_N_OBL2), + ioread32(bank->base + NPCM8XX_GP_N_OBL3)); + seq_printf(s, "SLCK:%.8x MLCK:%.8x\n", + ioread32(bank->base + NPCM8XX_GP_N_SPLCK), + ioread32(bank->base + NPCM8XX_GP_N_MPLCK)); +} + +static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct npcm8xx_gpio *bank = gpiochip_get_data(chip); + int ret; + + ret = pinctrl_gpio_direction_input(offset + chip->base); + if (ret) + return ret; + + return bank->direction_input(chip, offset); +} + +static int npcmgpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct npcm8xx_gpio *bank = gpiochip_get_data(chip); + int ret; + + ret = pinctrl_gpio_direction_output(offset + chip->base); + if (ret) + return ret; + + return bank->direction_output(chip, offset, value); +} + +static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct npcm8xx_gpio *bank = gpiochip_get_data(chip); + int ret; + + ret = pinctrl_gpio_request(offset + chip->base); + if (ret) + return ret; + + return bank->request(chip, offset); +} + +static void npcmgpio_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + pinctrl_gpio_free(offset + chip->base); +} + +static void npcmgpio_irq_handler(struct irq_desc *desc) +{ + unsigned long sts, en, bit; + struct npcm8xx_gpio *bank; + struct irq_chip *chip; + struct gpio_chip *gc; + + gc = irq_desc_get_handler_data(desc); + bank = gpiochip_get_data(gc); + chip = irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + sts = ioread32(bank->base + NPCM8XX_GP_N_EVST); + en = ioread32(bank->base + NPCM8XX_GP_N_EVEN); + sts &= en; + for_each_set_bit(bit, &sts, NPCM8XX_GPIO_PER_BANK) + generic_handle_domain_irq(gc->irq.domain, bit); + chained_irq_exit(chip, desc); +} + +static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type) +{ + struct npcm8xx_gpio *bank = + gpiochip_get_data(irq_data_get_irq_chip_data(d)); + unsigned int gpio = BIT(irqd_to_hwirq(d)); + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); + break; + case IRQ_TYPE_EDGE_FALLING: + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); + npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); + break; + case IRQ_TYPE_EDGE_BOTH: + npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVBE, gpio); + break; + case IRQ_TYPE_LEVEL_LOW: + npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); + break; + case IRQ_TYPE_LEVEL_HIGH: + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_POL, gpio); + break; + default: + return -EINVAL; + } + + if (type & IRQ_TYPE_LEVEL_MASK) { + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); + irq_set_handler_locked(d, handle_level_irq); + } else if (type & IRQ_TYPE_EDGE_BOTH) { + npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_EVTYP, gpio); + irq_set_handler_locked(d, handle_edge_irq); + } + + return 0; +} + +static void npcmgpio_irq_ack(struct irq_data *d) +{ + struct npcm8xx_gpio *bank = + gpiochip_get_data(irq_data_get_irq_chip_data(d)); + unsigned int gpio = irqd_to_hwirq(d); + + iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVST); +} + +static void npcmgpio_irq_mask(struct irq_data *d) +{ + struct npcm8xx_gpio *bank = + gpiochip_get_data(irq_data_get_irq_chip_data(d)); + unsigned int gpio = irqd_to_hwirq(d); + + iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENC); +} + +static void npcmgpio_irq_unmask(struct irq_data *d) +{ + struct npcm8xx_gpio *bank = + gpiochip_get_data(irq_data_get_irq_chip_data(d)); + unsigned int gpio = irqd_to_hwirq(d); + + iowrite32(BIT(gpio), bank->base + NPCM8XX_GP_N_EVENS); +} + +static unsigned int npcmgpio_irq_startup(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + unsigned int gpio = irqd_to_hwirq(d); + + /* active-high, input, clear interrupt, enable interrupt */ + npcmgpio_direction_input(gc, gpio); + npcmgpio_irq_ack(d); + npcmgpio_irq_unmask(d); + + return 0; +} + +static struct irq_chip npcmgpio_irqchip = { + .name = "NPCM8XX-GPIO-IRQ", + .irq_ack = npcmgpio_irq_ack, + .irq_unmask = npcmgpio_irq_unmask, + .irq_mask = npcmgpio_irq_mask, + .irq_set_type = npcmgpio_set_irq_type, + .irq_startup = npcmgpio_irq_startup, + .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static const int gpi36_pins[] = { 58 }; +static const int gpi35_pins[] = { 58 }; + +static const int tp_jtag3_pins[] = { 44, 62, 45, 46 }; +static const int tp_uart_pins[] = { 50, 51 }; + +static const int tp_smb2_pins[] = { 24, 25 }; +static const int tp_smb1_pins[] = { 142, 143 }; + +static const int tp_gpio7_pins[] = { 96 }; +static const int tp_gpio6_pins[] = { 97 }; +static const int tp_gpio5_pins[] = { 98 }; +static const int tp_gpio4_pins[] = { 99 }; +static const int tp_gpio3_pins[] = { 100 }; +static const int tp_gpio2_pins[] = { 16 }; +static const int tp_gpio1_pins[] = { 9 }; +static const int tp_gpio0_pins[] = { 8 }; + +static const int tp_gpio2b_pins[] = { 101 }; +static const int tp_gpio1b_pins[] = { 92 }; +static const int tp_gpio0b_pins[] = { 91 }; + +static const int vgadig_pins[] = { 102, 103, 104, 105 }; + +static const int nbu1crts_pins[] = { 44, 62 }; + +static const int fm2_pins[] = { 224, 225, 226, 227, 228, 229, 230 }; +static const int fm1_pins[] = { 175, 176, 177, 203, 191, 192, 233 }; +static const int fm0_pins[] = { 194, 195, 196, 202, 199, 198, 197 }; + +static const int gpio1836_pins[] = { 183, 184, 185, 186 }; +static const int gpio1889_pins[] = { 188, 189 }; +static const int gpo187_pins[] = { 187 }; + +static const int cp1urxd_pins[] = { 41 }; +static const int r3rxer_pins[] = { 212 }; + +static const int cp1gpio2c_pins[] = { 101 }; +static const int cp1gpio3c_pins[] = { 100 }; + +static const int cp1gpio0b_pins[] = { 127 }; +static const int cp1gpio1b_pins[] = { 126 }; +static const int cp1gpio2b_pins[] = { 125 }; +static const int cp1gpio3b_pins[] = { 124 }; +static const int cp1gpio4b_pins[] = { 99 }; +static const int cp1gpio5b_pins[] = { 98 }; +static const int cp1gpio6b_pins[] = { 97 }; +static const int cp1gpio7b_pins[] = { 96 }; + +static const int cp1gpio0_pins[] = { }; +static const int cp1gpio1_pins[] = { }; +static const int cp1gpio2_pins[] = { }; +static const int cp1gpio3_pins[] = { }; +static const int cp1gpio4_pins[] = { }; +static const int cp1gpio5_pins[] = { 17 }; +static const int cp1gpio6_pins[] = { 91 }; +static const int cp1gpio7_pins[] = { 92 }; + +static const int cp1utxd_pins[] = { 42 }; + +static const int spi1cs3_pins[] = { 192 }; +static const int spi1cs2_pins[] = { 191 }; +static const int spi1cs1_pins[] = { 233 }; +static const int spi1cs0_pins[] = { 203 }; + +static const int spi1d23_pins[] = { 191, 192 }; + +static const int j2j3_pins[] = { 44, 62, 45, 46 }; + +static const int r3oen_pins[] = { 213 }; +static const int r2oen_pins[] = { 90 }; +static const int r1oen_pins[] = { 56 }; +static const int bu4b_pins[] = { 98, 99 }; +static const int bu4_pins[] = { 54, 55 }; +static const int bu5b_pins[] = { 100, 101 }; +static const int bu5_pins[] = { 52, 53 }; +static const int bu6_pins[] = { 50, 51 }; +static const int rmii3_pins[] = { 110, 111, 209, 211, 210, 214, 215 }; + +static const int jm1_pins[] = { 136, 137, 138, 139, 140 }; +static const int jm2_pins[] = { 251 }; + +static const int tpgpio5b_pins[] = { 58 }; +static const int tpgpio4b_pins[] = { 57 }; + +static const int clkrun_pins[] = { 162 }; + +static const int i3c5_pins[] = { 106, 107 }; +static const int i3c4_pins[] = { 33, 34 }; +static const int i3c3_pins[] = { 246, 247 }; +static const int i3c2_pins[] = { 244, 245 }; +static const int i3c1_pins[] = { 242, 243 }; +static const int i3c0_pins[] = { 240, 241 }; + +static const int hsi1a_pins[] = { 43, 63 }; +static const int hsi2a_pins[] = { 48, 49 }; +static const int hsi1b_pins[] = { 44, 62 }; +static const int hsi2b_pins[] = { 50, 51 }; +static const int hsi1c_pins[] = { 45, 46, 47, 61 }; +static const int hsi2c_pins[] = { 45, 46, 47, 61 }; + +static const int smb0_pins[] = { 115, 114 }; +static const int smb0b_pins[] = { 195, 194 }; +static const int smb0c_pins[] = { 202, 196 }; +static const int smb0d_pins[] = { 198, 199 }; +static const int smb0den_pins[] = { 197 }; +static const int smb1_pins[] = { 117, 116 }; +static const int smb1b_pins[] = { 126, 127 }; +static const int smb1c_pins[] = { 124, 125 }; +static const int smb1d_pins[] = { 4, 5 }; +static const int smb2_pins[] = { 119, 118 }; +static const int smb2b_pins[] = { 122, 123 }; +static const int smb2c_pins[] = { 120, 121 }; +static const int smb2d_pins[] = { 6, 7 }; +static const int smb3_pins[] = { 30, 31 }; +static const int smb3b_pins[] = { 39, 40 }; +static const int smb3c_pins[] = { 37, 38 }; +static const int smb3d_pins[] = { 59, 60 }; +static const int smb4_pins[] = { 28, 29 }; +static const int smb4b_pins[] = { 18, 19 }; +static const int smb4c_pins[] = { 20, 21 }; +static const int smb4d_pins[] = { 22, 23 }; +static const int smb4den_pins[] = { 17 }; +static const int smb5_pins[] = { 26, 27 }; +static const int smb5b_pins[] = { 13, 12 }; +static const int smb5c_pins[] = { 15, 14 }; +static const int smb5d_pins[] = { 94, 93 }; +static const int ga20kbc_pins[] = { 94, 93 }; + +static const int smb6_pins[] = { 172, 171 }; +static const int smb6b_pins[] = { 2, 3 }; +static const int smb6c_pins[] = { 0, 1 }; +static const int smb6d_pins[] = { 10, 11 }; +static const int smb7_pins[] = { 174, 173 }; +static const int smb7b_pins[] = { 16, 141 }; +static const int smb7c_pins[] = { 24, 25 }; +static const int smb7d_pins[] = { 142, 143 }; +static const int smb8_pins[] = { 129, 128 }; +static const int smb9_pins[] = { 131, 130 }; +static const int smb10_pins[] = { 133, 132 }; +static const int smb11_pins[] = { 135, 134 }; +static const int smb12_pins[] = { 221, 220 }; +static const int smb13_pins[] = { 223, 222 }; +static const int smb14_pins[] = { 22, 23 }; +static const int smb14b_pins[] = { 32, 187 }; +static const int smb15_pins[] = { 20, 21 }; +static const int smb15b_pins[] = { 192, 191 }; + +static const int smb16_pins[] = { 10, 11 }; +static const int smb16b_pins[] = { 218, 219 }; +static const int smb17_pins[] = { 3, 2 }; +static const int smb18_pins[] = { 0, 1 }; +static const int smb19_pins[] = { 60, 59 }; +static const int smb20_pins[] = { 234, 235 }; +static const int smb21_pins[] = { 169, 170 }; +static const int smb22_pins[] = { 40, 39 }; +static const int smb23_pins[] = { 38, 37 }; +static const int smb23b_pins[] = { 134, 135 }; + +static const int fanin0_pins[] = { 64 }; +static const int fanin1_pins[] = { 65 }; +static const int fanin2_pins[] = { 66 }; +static const int fanin3_pins[] = { 67 }; +static const int fanin4_pins[] = { 68 }; +static const int fanin5_pins[] = { 69 }; +static const int fanin6_pins[] = { 70 }; +static const int fanin7_pins[] = { 71 }; +static const int fanin8_pins[] = { 72 }; +static const int fanin9_pins[] = { 73 }; +static const int fanin10_pins[] = { 74 }; +static const int fanin11_pins[] = { 75 }; +static const int fanin12_pins[] = { 76 }; +static const int fanin13_pins[] = { 77 }; +static const int fanin14_pins[] = { 78 }; +static const int fanin15_pins[] = { 79 }; +static const int faninx_pins[] = { 175, 176, 177, 203 }; + +static const int pwm0_pins[] = { 80 }; +static const int pwm1_pins[] = { 81 }; +static const int pwm2_pins[] = { 82 }; +static const int pwm3_pins[] = { 83 }; +static const int pwm4_pins[] = { 144 }; +static const int pwm5_pins[] = { 145 }; +static const int pwm6_pins[] = { 146 }; +static const int pwm7_pins[] = { 147 }; +static const int pwm8_pins[] = { 220 }; +static const int pwm9_pins[] = { 221 }; +static const int pwm10_pins[] = { 234 }; +static const int pwm11_pins[] = { 235 }; + +static const int uart1_pins[] = { 43, 45, 46, 47, 61, 62, 63 }; +static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; + +static const int sg1mdio_pins[] = { 108, 109 }; + +static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, + 213, 214, 215 }; +static const int rg2mdio_pins[] = { 216, 217 }; + +static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, + 213, 214, 215, 216, 217 }; + +static const int iox1_pins[] = { 0, 1, 2, 3 }; +static const int iox2_pins[] = { 4, 5, 6, 7 }; +static const int ioxh_pins[] = { 10, 11, 24, 25 }; + +static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 }; +static const int mmcwp_pins[] = { 153 }; +static const int mmccd_pins[] = { 155 }; +static const int mmcrst_pins[] = { 155 }; +static const int mmc8_pins[] = { 148, 149, 150, 151 }; + +static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 }; +static const int r1err_pins[] = { 56 }; +static const int r1md_pins[] = { 57, 58 }; +static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 }; +static const int r2err_pins[] = { 90 }; +static const int r2md_pins[] = { 91, 92 }; +static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 }; +static const int sd1pwr_pins[] = { 143 }; + +static const int wdog1_pins[] = { 218 }; +static const int wdog2_pins[] = { 219 }; + +static const int bmcuart0a_pins[] = { 41, 42 }; +static const int bmcuart0b_pins[] = { 48, 49 }; +static const int bmcuart1_pins[] = { 43, 44, 62, 63 }; + +static const int scipme_pins[] = { 169 }; +static const int smi_pins[] = { 170 }; +static const int serirq_pins[] = { 168 }; + +static const int clkout_pins[] = { 160 }; +static const int clkreq_pins[] = { 231 }; + +static const int jtag2_pins[] = { 43, 44, 45, 46, 47 }; +static const int gspi_pins[] = { 12, 13, 14, 15 }; + +static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 }; +static const int spixcs1_pins[] = { 228 }; + +static const int spi1_pins[] = { 175, 176, 177 }; +static const int pspi_pins[] = { 17, 18, 19 }; + +static const int spi0cs1_pins[] = { 32 }; + +static const int spi3_pins[] = { 183, 184, 185, 186 }; +static const int spi3cs1_pins[] = { 187 }; +static const int spi3quad_pins[] = { 188, 189 }; +static const int spi3cs2_pins[] = { 188 }; +static const int spi3cs3_pins[] = { 189 }; + +static const int ddc_pins[] = { 204, 205, 206, 207 }; + +static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 }; +static const int lpcclk_pins[] = { 168 }; +static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 }; + +static const int lkgpo0_pins[] = { 16 }; +static const int lkgpo1_pins[] = { 8 }; +static const int lkgpo2_pins[] = { 9 }; + +static const int nprd_smi_pins[] = { 190 }; + +static const int hgpio0_pins[] = { 20 }; +static const int hgpio1_pins[] = { 21 }; +static const int hgpio2_pins[] = { 22 }; +static const int hgpio3_pins[] = { 23 }; +static const int hgpio4_pins[] = { 24 }; +static const int hgpio5_pins[] = { 25 }; +static const int hgpio6_pins[] = { 59 }; +static const int hgpio7_pins[] = { 60 }; + +/* + * pin: name, number + * group: name, npins, pins + * function: name, ngroups, groups + */ +struct npcm8xx_pingroup { + const char *name; + const unsigned int *pins; + int npins; +}; + +#define NPCM8XX_GRPS \ + NPCM8XX_GRP(gpi36), \ + NPCM8XX_GRP(gpi35), \ + NPCM8XX_GRP(tp_jtag3), \ + NPCM8XX_GRP(tp_uart), \ + NPCM8XX_GRP(tp_smb2), \ + NPCM8XX_GRP(tp_smb1), \ + NPCM8XX_GRP(tp_gpio7), \ + NPCM8XX_GRP(tp_gpio6), \ + NPCM8XX_GRP(tp_gpio5), \ + NPCM8XX_GRP(tp_gpio4), \ + NPCM8XX_GRP(tp_gpio3), \ + NPCM8XX_GRP(tp_gpio2), \ + NPCM8XX_GRP(tp_gpio1), \ + NPCM8XX_GRP(tp_gpio0), \ + NPCM8XX_GRP(tp_gpio2b), \ + NPCM8XX_GRP(tp_gpio1b), \ + NPCM8XX_GRP(tp_gpio0b), \ + NPCM8XX_GRP(vgadig), \ + NPCM8XX_GRP(nbu1crts), \ + NPCM8XX_GRP(fm2), \ + NPCM8XX_GRP(fm1), \ + NPCM8XX_GRP(fm0), \ + NPCM8XX_GRP(gpio1836), \ + NPCM8XX_GRP(gpio1889), \ + NPCM8XX_GRP(gpo187), \ + NPCM8XX_GRP(cp1urxd), \ + NPCM8XX_GRP(r3rxer), \ + NPCM8XX_GRP(cp1gpio2c), \ + NPCM8XX_GRP(cp1gpio3c), \ + NPCM8XX_GRP(cp1gpio0b), \ + NPCM8XX_GRP(cp1gpio1b), \ + NPCM8XX_GRP(cp1gpio2b), \ + NPCM8XX_GRP(cp1gpio3b), \ + NPCM8XX_GRP(cp1gpio4b), \ + NPCM8XX_GRP(cp1gpio5b), \ + NPCM8XX_GRP(cp1gpio6b), \ + NPCM8XX_GRP(cp1gpio7b), \ + NPCM8XX_GRP(cp1gpio0), \ + NPCM8XX_GRP(cp1gpio1), \ + NPCM8XX_GRP(cp1gpio2), \ + NPCM8XX_GRP(cp1gpio3), \ + NPCM8XX_GRP(cp1gpio4), \ + NPCM8XX_GRP(cp1gpio5), \ + NPCM8XX_GRP(cp1gpio6), \ + NPCM8XX_GRP(cp1gpio7), \ + NPCM8XX_GRP(cp1utxd), \ + NPCM8XX_GRP(spi1cs3), \ + NPCM8XX_GRP(spi1cs2), \ + NPCM8XX_GRP(spi1cs1), \ + NPCM8XX_GRP(spi1cs0), \ + NPCM8XX_GRP(spi1d23), \ + NPCM8XX_GRP(j2j3), \ + NPCM8XX_GRP(r3oen), \ + NPCM8XX_GRP(r2oen), \ + NPCM8XX_GRP(r1oen), \ + NPCM8XX_GRP(bu4b), \ + NPCM8XX_GRP(bu4), \ + NPCM8XX_GRP(bu5b), \ + NPCM8XX_GRP(bu5), \ + NPCM8XX_GRP(bu6), \ + NPCM8XX_GRP(rmii3), \ + NPCM8XX_GRP(jm1), \ + NPCM8XX_GRP(jm2), \ + NPCM8XX_GRP(tpgpio5b), \ + NPCM8XX_GRP(tpgpio4b), \ + NPCM8XX_GRP(clkrun), \ + NPCM8XX_GRP(i3c5), \ + NPCM8XX_GRP(i3c4), \ + NPCM8XX_GRP(i3c3), \ + NPCM8XX_GRP(i3c2), \ + NPCM8XX_GRP(i3c1), \ + NPCM8XX_GRP(i3c0), \ + NPCM8XX_GRP(hsi1a), \ + NPCM8XX_GRP(hsi2a), \ + NPCM8XX_GRP(hsi1b), \ + NPCM8XX_GRP(hsi2b), \ + NPCM8XX_GRP(hsi1c), \ + NPCM8XX_GRP(hsi2c), \ + NPCM8XX_GRP(smb0), \ + NPCM8XX_GRP(smb0b), \ + NPCM8XX_GRP(smb0c), \ + NPCM8XX_GRP(smb0d), \ + NPCM8XX_GRP(smb0den), \ + NPCM8XX_GRP(smb1), \ + NPCM8XX_GRP(smb1b), \ + NPCM8XX_GRP(smb1c), \ + NPCM8XX_GRP(smb1d), \ + NPCM8XX_GRP(smb2), \ + NPCM8XX_GRP(smb2b), \ + NPCM8XX_GRP(smb2c), \ + NPCM8XX_GRP(smb2d), \ + NPCM8XX_GRP(smb3), \ + NPCM8XX_GRP(smb3b), \ + NPCM8XX_GRP(smb3c), \ + NPCM8XX_GRP(smb3d), \ + NPCM8XX_GRP(smb4), \ + NPCM8XX_GRP(smb4b), \ + NPCM8XX_GRP(smb4c), \ + NPCM8XX_GRP(smb4d), \ + NPCM8XX_GRP(smb4den), \ + NPCM8XX_GRP(smb5), \ + NPCM8XX_GRP(smb5b), \ + NPCM8XX_GRP(smb5c), \ + NPCM8XX_GRP(smb5d), \ + NPCM8XX_GRP(ga20kbc), \ + NPCM8XX_GRP(smb6), \ + NPCM8XX_GRP(smb6b), \ + NPCM8XX_GRP(smb6c), \ + NPCM8XX_GRP(smb6d), \ + NPCM8XX_GRP(smb7), \ + NPCM8XX_GRP(smb7b), \ + NPCM8XX_GRP(smb7c), \ + NPCM8XX_GRP(smb7d), \ + NPCM8XX_GRP(smb8), \ + NPCM8XX_GRP(smb9), \ + NPCM8XX_GRP(smb10), \ + NPCM8XX_GRP(smb11), \ + NPCM8XX_GRP(smb12), \ + NPCM8XX_GRP(smb13), \ + NPCM8XX_GRP(smb14), \ + NPCM8XX_GRP(smb14b), \ + NPCM8XX_GRP(smb15), \ + NPCM8XX_GRP(smb15b), \ + NPCM8XX_GRP(smb16), \ + NPCM8XX_GRP(smb16b), \ + NPCM8XX_GRP(smb17), \ + NPCM8XX_GRP(smb18), \ + NPCM8XX_GRP(smb19), \ + NPCM8XX_GRP(smb20), \ + NPCM8XX_GRP(smb21), \ + NPCM8XX_GRP(smb22), \ + NPCM8XX_GRP(smb23), \ + NPCM8XX_GRP(smb23b), \ + NPCM8XX_GRP(fanin0), \ + NPCM8XX_GRP(fanin1), \ + NPCM8XX_GRP(fanin2), \ + NPCM8XX_GRP(fanin3), \ + NPCM8XX_GRP(fanin4), \ + NPCM8XX_GRP(fanin5), \ + NPCM8XX_GRP(fanin6), \ + NPCM8XX_GRP(fanin7), \ + NPCM8XX_GRP(fanin8), \ + NPCM8XX_GRP(fanin9), \ + NPCM8XX_GRP(fanin10), \ + NPCM8XX_GRP(fanin11), \ + NPCM8XX_GRP(fanin12), \ + NPCM8XX_GRP(fanin13), \ + NPCM8XX_GRP(fanin14), \ + NPCM8XX_GRP(fanin15), \ + NPCM8XX_GRP(faninx), \ + NPCM8XX_GRP(pwm0), \ + NPCM8XX_GRP(pwm1), \ + NPCM8XX_GRP(pwm2), \ + NPCM8XX_GRP(pwm3), \ + NPCM8XX_GRP(pwm4), \ + NPCM8XX_GRP(pwm5), \ + NPCM8XX_GRP(pwm6), \ + NPCM8XX_GRP(pwm7), \ + NPCM8XX_GRP(pwm8), \ + NPCM8XX_GRP(pwm9), \ + NPCM8XX_GRP(pwm10), \ + NPCM8XX_GRP(pwm11), \ + NPCM8XX_GRP(sg1mdio), \ + NPCM8XX_GRP(rg2), \ + NPCM8XX_GRP(rg2mdio), \ + NPCM8XX_GRP(ddr), \ + NPCM8XX_GRP(uart1), \ + NPCM8XX_GRP(uart2), \ + NPCM8XX_GRP(bmcuart0a), \ + NPCM8XX_GRP(bmcuart0b), \ + NPCM8XX_GRP(bmcuart1), \ + NPCM8XX_GRP(iox1), \ + NPCM8XX_GRP(iox2), \ + NPCM8XX_GRP(ioxh), \ + NPCM8XX_GRP(gspi), \ + NPCM8XX_GRP(mmc), \ + NPCM8XX_GRP(mmcwp), \ + NPCM8XX_GRP(mmccd), \ + NPCM8XX_GRP(mmcrst), \ + NPCM8XX_GRP(mmc8), \ + NPCM8XX_GRP(r1), \ + NPCM8XX_GRP(r1err), \ + NPCM8XX_GRP(r1md), \ + NPCM8XX_GRP(r2), \ + NPCM8XX_GRP(r2err), \ + NPCM8XX_GRP(r2md), \ + NPCM8XX_GRP(sd1), \ + NPCM8XX_GRP(sd1pwr), \ + NPCM8XX_GRP(wdog1), \ + NPCM8XX_GRP(wdog2), \ + NPCM8XX_GRP(scipme), \ + NPCM8XX_GRP(smi), \ + NPCM8XX_GRP(serirq), \ + NPCM8XX_GRP(jtag2), \ + NPCM8XX_GRP(spix), \ + NPCM8XX_GRP(spixcs1), \ + NPCM8XX_GRP(spi1), \ + NPCM8XX_GRP(pspi), \ + NPCM8XX_GRP(ddc), \ + NPCM8XX_GRP(clkreq), \ + NPCM8XX_GRP(clkout), \ + NPCM8XX_GRP(spi3), \ + NPCM8XX_GRP(spi3cs1), \ + NPCM8XX_GRP(spi3quad), \ + NPCM8XX_GRP(spi3cs2), \ + NPCM8XX_GRP(spi3cs3), \ + NPCM8XX_GRP(spi0cs1), \ + NPCM8XX_GRP(lpc), \ + NPCM8XX_GRP(lpcclk), \ + NPCM8XX_GRP(espi), \ + NPCM8XX_GRP(lkgpo0), \ + NPCM8XX_GRP(lkgpo1), \ + NPCM8XX_GRP(lkgpo2), \ + NPCM8XX_GRP(nprd_smi), \ + NPCM8XX_GRP(hgpio0), \ + NPCM8XX_GRP(hgpio1), \ + NPCM8XX_GRP(hgpio2), \ + NPCM8XX_GRP(hgpio3), \ + NPCM8XX_GRP(hgpio4), \ + NPCM8XX_GRP(hgpio5), \ + NPCM8XX_GRP(hgpio6), \ + NPCM8XX_GRP(hgpio7), \ + \ + +enum { +#define NPCM8XX_GRP(x) fn_ ## x + NPCM8XX_GRPS + NPCM8XX_GRP(none), + NPCM8XX_GRP(gpio), +#undef NPCM8XX_GRP +}; + +static struct npcm8xx_pingroup npcm8xx_pingroups[] = { +#define NPCM8XX_GRP(x) { .name = #x, .pins = x ## _pins, \ + .npins = ARRAY_SIZE(x ## _pins) } + NPCM8XX_GRPS +#undef NPCM8XX_GRP +}; + +#define NPCM8XX_SFUNC(a) NPCM8XX_FUNC(a, #a) +#define NPCM8XX_FUNC(a, b...) static const char *a ## _grp[] = { b } +#define NPCM8XX_MKFUNC(nm) { .name = #nm, .ngroups = ARRAY_SIZE(nm ## _grp), \ + .groups = nm ## _grp } +struct npcm8xx_func { + const char *name; + const unsigned int ngroups; + const char *const *groups; +}; + +NPCM8XX_SFUNC(gpi36); +NPCM8XX_SFUNC(gpi35); +NPCM8XX_SFUNC(tp_jtag3); +NPCM8XX_SFUNC(tp_uart); +NPCM8XX_SFUNC(tp_smb2); +NPCM8XX_SFUNC(tp_smb1); +NPCM8XX_SFUNC(tp_gpio7); +NPCM8XX_SFUNC(tp_gpio6); +NPCM8XX_SFUNC(tp_gpio5); +NPCM8XX_SFUNC(tp_gpio4); +NPCM8XX_SFUNC(tp_gpio3); +NPCM8XX_SFUNC(tp_gpio2); +NPCM8XX_SFUNC(tp_gpio1); +NPCM8XX_SFUNC(tp_gpio0); +NPCM8XX_SFUNC(tp_gpio2b); +NPCM8XX_SFUNC(tp_gpio1b); +NPCM8XX_SFUNC(tp_gpio0b); +NPCM8XX_SFUNC(vgadig); +NPCM8XX_SFUNC(nbu1crts); +NPCM8XX_SFUNC(fm2); +NPCM8XX_SFUNC(fm1); +NPCM8XX_SFUNC(fm0); +NPCM8XX_SFUNC(gpio1836); +NPCM8XX_SFUNC(gpio1889); +NPCM8XX_SFUNC(gpo187); +NPCM8XX_SFUNC(cp1urxd); +NPCM8XX_SFUNC(r3rxer); +NPCM8XX_SFUNC(cp1gpio2c); +NPCM8XX_SFUNC(cp1gpio3c); +NPCM8XX_SFUNC(cp1gpio0b); +NPCM8XX_SFUNC(cp1gpio1b); +NPCM8XX_SFUNC(cp1gpio2b); +NPCM8XX_SFUNC(cp1gpio3b); +NPCM8XX_SFUNC(cp1gpio4b); +NPCM8XX_SFUNC(cp1gpio5b); +NPCM8XX_SFUNC(cp1gpio6b); +NPCM8XX_SFUNC(cp1gpio7b); +NPCM8XX_SFUNC(cp1gpio0); +NPCM8XX_SFUNC(cp1gpio1); +NPCM8XX_SFUNC(cp1gpio2); +NPCM8XX_SFUNC(cp1gpio3); +NPCM8XX_SFUNC(cp1gpio4); +NPCM8XX_SFUNC(cp1gpio5); +NPCM8XX_SFUNC(cp1gpio6); +NPCM8XX_SFUNC(cp1gpio7); +NPCM8XX_SFUNC(cp1utxd); +NPCM8XX_SFUNC(spi1cs3); +NPCM8XX_SFUNC(spi1cs2); +NPCM8XX_SFUNC(spi1cs1); +NPCM8XX_SFUNC(spi1cs0); +NPCM8XX_SFUNC(spi1d23); +NPCM8XX_SFUNC(j2j3); +NPCM8XX_SFUNC(r3oen); +NPCM8XX_SFUNC(r2oen); +NPCM8XX_SFUNC(r1oen); +NPCM8XX_SFUNC(bu4b); +NPCM8XX_SFUNC(bu4); +NPCM8XX_SFUNC(bu5b); +NPCM8XX_SFUNC(bu5); +NPCM8XX_SFUNC(bu6); +NPCM8XX_SFUNC(rmii3); +NPCM8XX_SFUNC(jm1); +NPCM8XX_SFUNC(jm2); +NPCM8XX_SFUNC(tpgpio5b); +NPCM8XX_SFUNC(tpgpio4b); +NPCM8XX_SFUNC(clkrun); +NPCM8XX_SFUNC(i3c5); +NPCM8XX_SFUNC(i3c4); +NPCM8XX_SFUNC(i3c3); +NPCM8XX_SFUNC(i3c2); +NPCM8XX_SFUNC(i3c1); +NPCM8XX_SFUNC(i3c0); +NPCM8XX_SFUNC(hsi1a); +NPCM8XX_SFUNC(hsi2a); +NPCM8XX_SFUNC(hsi1b); +NPCM8XX_SFUNC(hsi2b); +NPCM8XX_SFUNC(hsi1c); +NPCM8XX_SFUNC(hsi2c); +NPCM8XX_SFUNC(smb0); +NPCM8XX_SFUNC(smb0b); +NPCM8XX_SFUNC(smb0c); +NPCM8XX_SFUNC(smb0d); +NPCM8XX_SFUNC(smb0den); +NPCM8XX_SFUNC(smb1); +NPCM8XX_SFUNC(smb1b); +NPCM8XX_SFUNC(smb1c); +NPCM8XX_SFUNC(smb1d); +NPCM8XX_SFUNC(smb2); +NPCM8XX_SFUNC(smb2b); +NPCM8XX_SFUNC(smb2c); +NPCM8XX_SFUNC(smb2d); +NPCM8XX_SFUNC(smb3); +NPCM8XX_SFUNC(smb3b); +NPCM8XX_SFUNC(smb3c); +NPCM8XX_SFUNC(smb3d); +NPCM8XX_SFUNC(smb4); +NPCM8XX_SFUNC(smb4b); +NPCM8XX_SFUNC(smb4c); +NPCM8XX_SFUNC(smb4d); +NPCM8XX_SFUNC(smb4den); +NPCM8XX_SFUNC(smb5); +NPCM8XX_SFUNC(smb5b); +NPCM8XX_SFUNC(smb5c); +NPCM8XX_SFUNC(smb5d); +NPCM8XX_SFUNC(ga20kbc); +NPCM8XX_SFUNC(smb6); +NPCM8XX_SFUNC(smb6b); +NPCM8XX_SFUNC(smb6c); +NPCM8XX_SFUNC(smb6d); +NPCM8XX_SFUNC(smb7); +NPCM8XX_SFUNC(smb7b); +NPCM8XX_SFUNC(smb7c); +NPCM8XX_SFUNC(smb7d); +NPCM8XX_SFUNC(smb8); +NPCM8XX_SFUNC(smb9); +NPCM8XX_SFUNC(smb10); +NPCM8XX_SFUNC(smb11); +NPCM8XX_SFUNC(smb12); +NPCM8XX_SFUNC(smb13); +NPCM8XX_SFUNC(smb14); +NPCM8XX_SFUNC(smb14b); +NPCM8XX_SFUNC(smb15); +NPCM8XX_SFUNC(smb16); +NPCM8XX_SFUNC(smb16b); +NPCM8XX_SFUNC(smb17); +NPCM8XX_SFUNC(smb18); +NPCM8XX_SFUNC(smb19); +NPCM8XX_SFUNC(smb20); +NPCM8XX_SFUNC(smb21); +NPCM8XX_SFUNC(smb22); +NPCM8XX_SFUNC(smb23); +NPCM8XX_SFUNC(smb23b); +NPCM8XX_SFUNC(fanin0); +NPCM8XX_SFUNC(fanin1); +NPCM8XX_SFUNC(fanin2); +NPCM8XX_SFUNC(fanin3); +NPCM8XX_SFUNC(fanin4); +NPCM8XX_SFUNC(fanin5); +NPCM8XX_SFUNC(fanin6); +NPCM8XX_SFUNC(fanin7); +NPCM8XX_SFUNC(fanin8); +NPCM8XX_SFUNC(fanin9); +NPCM8XX_SFUNC(fanin10); +NPCM8XX_SFUNC(fanin11); +NPCM8XX_SFUNC(fanin12); +NPCM8XX_SFUNC(fanin13); +NPCM8XX_SFUNC(fanin14); +NPCM8XX_SFUNC(fanin15); +NPCM8XX_SFUNC(faninx); +NPCM8XX_SFUNC(pwm0); +NPCM8XX_SFUNC(pwm1); +NPCM8XX_SFUNC(pwm2); +NPCM8XX_SFUNC(pwm3); +NPCM8XX_SFUNC(pwm4); +NPCM8XX_SFUNC(pwm5); +NPCM8XX_SFUNC(pwm6); +NPCM8XX_SFUNC(pwm7); +NPCM8XX_SFUNC(pwm8); +NPCM8XX_SFUNC(pwm9); +NPCM8XX_SFUNC(pwm10); +NPCM8XX_SFUNC(pwm11); +NPCM8XX_SFUNC(sg1mdio); +NPCM8XX_SFUNC(rg2); +NPCM8XX_SFUNC(rg2mdio); +NPCM8XX_SFUNC(ddr); +NPCM8XX_SFUNC(uart1); +NPCM8XX_SFUNC(uart2); +NPCM8XX_SFUNC(bmcuart0a); +NPCM8XX_SFUNC(bmcuart0b); +NPCM8XX_SFUNC(bmcuart1); +NPCM8XX_SFUNC(iox1); +NPCM8XX_SFUNC(iox2); +NPCM8XX_SFUNC(ioxh); +NPCM8XX_SFUNC(gspi); +NPCM8XX_SFUNC(mmc); +NPCM8XX_SFUNC(mmcwp); +NPCM8XX_SFUNC(mmccd); +NPCM8XX_SFUNC(mmcrst); +NPCM8XX_SFUNC(mmc8); +NPCM8XX_SFUNC(r1); +NPCM8XX_SFUNC(r1err); +NPCM8XX_SFUNC(r1md); +NPCM8XX_SFUNC(r2); +NPCM8XX_SFUNC(r2err); +NPCM8XX_SFUNC(r2md); +NPCM8XX_SFUNC(sd1); +NPCM8XX_SFUNC(sd1pwr); +NPCM8XX_SFUNC(wdog1); +NPCM8XX_SFUNC(wdog2); +NPCM8XX_SFUNC(scipme); +NPCM8XX_SFUNC(smi); +NPCM8XX_SFUNC(serirq); +NPCM8XX_SFUNC(jtag2); +NPCM8XX_SFUNC(spix); +NPCM8XX_SFUNC(spixcs1); +NPCM8XX_SFUNC(spi1); +NPCM8XX_SFUNC(pspi); +NPCM8XX_SFUNC(ddc); +NPCM8XX_SFUNC(clkreq); +NPCM8XX_SFUNC(clkout); +NPCM8XX_SFUNC(spi3); +NPCM8XX_SFUNC(spi3cs1); +NPCM8XX_SFUNC(spi3quad); +NPCM8XX_SFUNC(spi3cs2); +NPCM8XX_SFUNC(spi3cs3); +NPCM8XX_SFUNC(spi0cs1); +NPCM8XX_SFUNC(lpc); +NPCM8XX_SFUNC(lpcclk); +NPCM8XX_SFUNC(espi); +NPCM8XX_SFUNC(lkgpo0); +NPCM8XX_SFUNC(lkgpo1); +NPCM8XX_SFUNC(lkgpo2); +NPCM8XX_SFUNC(nprd_smi); +NPCM8XX_SFUNC(hgpio0); +NPCM8XX_SFUNC(hgpio1); +NPCM8XX_SFUNC(hgpio2); +NPCM8XX_SFUNC(hgpio3); +NPCM8XX_SFUNC(hgpio4); +NPCM8XX_SFUNC(hgpio5); +NPCM8XX_SFUNC(hgpio6); +NPCM8XX_SFUNC(hgpio7); + +/* Function names */ +static struct npcm8xx_func npcm8xx_funcs[] = { + NPCM8XX_MKFUNC(gpi36), + NPCM8XX_MKFUNC(gpi35), + NPCM8XX_MKFUNC(tp_jtag3), + NPCM8XX_MKFUNC(tp_uart), + NPCM8XX_MKFUNC(tp_smb2), + NPCM8XX_MKFUNC(tp_smb1), + NPCM8XX_MKFUNC(tp_gpio7), + NPCM8XX_MKFUNC(tp_gpio6), + NPCM8XX_MKFUNC(tp_gpio5), + NPCM8XX_MKFUNC(tp_gpio4), + NPCM8XX_MKFUNC(tp_gpio3), + NPCM8XX_MKFUNC(tp_gpio2), + NPCM8XX_MKFUNC(tp_gpio1), + NPCM8XX_MKFUNC(tp_gpio0), + NPCM8XX_MKFUNC(tp_gpio2b), + NPCM8XX_MKFUNC(tp_gpio1b), + NPCM8XX_MKFUNC(tp_gpio0b), + NPCM8XX_MKFUNC(vgadig), + NPCM8XX_MKFUNC(nbu1crts), + NPCM8XX_MKFUNC(fm2), + NPCM8XX_MKFUNC(fm1), + NPCM8XX_MKFUNC(fm0), + NPCM8XX_MKFUNC(gpio1836), + NPCM8XX_MKFUNC(gpio1889), + NPCM8XX_MKFUNC(gpo187), + NPCM8XX_MKFUNC(cp1urxd), + NPCM8XX_MKFUNC(r3rxer), + NPCM8XX_MKFUNC(cp1gpio2c), + NPCM8XX_MKFUNC(cp1gpio3c), + NPCM8XX_MKFUNC(cp1gpio0b), + NPCM8XX_MKFUNC(cp1gpio1b), + NPCM8XX_MKFUNC(cp1gpio2b), + NPCM8XX_MKFUNC(cp1gpio3b), + NPCM8XX_MKFUNC(cp1gpio4b), + NPCM8XX_MKFUNC(cp1gpio5b), + NPCM8XX_MKFUNC(cp1gpio6b), + NPCM8XX_MKFUNC(cp1gpio7b), + NPCM8XX_MKFUNC(cp1gpio0), + NPCM8XX_MKFUNC(cp1gpio1), + NPCM8XX_MKFUNC(cp1gpio2), + NPCM8XX_MKFUNC(cp1gpio3), + NPCM8XX_MKFUNC(cp1gpio4), + NPCM8XX_MKFUNC(cp1gpio5), + NPCM8XX_MKFUNC(cp1gpio6), + NPCM8XX_MKFUNC(cp1gpio7), + NPCM8XX_MKFUNC(cp1utxd), + NPCM8XX_MKFUNC(spi1cs3), + NPCM8XX_MKFUNC(spi1cs2), + NPCM8XX_MKFUNC(spi1cs1), + NPCM8XX_MKFUNC(spi1cs0), + NPCM8XX_MKFUNC(spi1d23), + NPCM8XX_MKFUNC(j2j3), + NPCM8XX_MKFUNC(r3oen), + NPCM8XX_MKFUNC(r2oen), + NPCM8XX_MKFUNC(r1oen), + NPCM8XX_MKFUNC(bu4b), + NPCM8XX_MKFUNC(bu4), + NPCM8XX_MKFUNC(bu5b), + NPCM8XX_MKFUNC(bu5), + NPCM8XX_MKFUNC(bu6), + NPCM8XX_MKFUNC(rmii3), + NPCM8XX_MKFUNC(jm1), + NPCM8XX_MKFUNC(jm2), + NPCM8XX_MKFUNC(tpgpio5b), + NPCM8XX_MKFUNC(tpgpio4b), + NPCM8XX_MKFUNC(clkrun), + NPCM8XX_MKFUNC(i3c5), + NPCM8XX_MKFUNC(i3c4), + NPCM8XX_MKFUNC(i3c3), + NPCM8XX_MKFUNC(i3c2), + NPCM8XX_MKFUNC(i3c1), + NPCM8XX_MKFUNC(i3c0), + NPCM8XX_MKFUNC(hsi1a), + NPCM8XX_MKFUNC(hsi2a), + NPCM8XX_MKFUNC(hsi1b), + NPCM8XX_MKFUNC(hsi2b), + NPCM8XX_MKFUNC(hsi1c), + NPCM8XX_MKFUNC(hsi2c), + NPCM8XX_MKFUNC(smb0), + NPCM8XX_MKFUNC(smb0b), + NPCM8XX_MKFUNC(smb0c), + NPCM8XX_MKFUNC(smb0d), + NPCM8XX_MKFUNC(smb0den), + NPCM8XX_MKFUNC(smb1), + NPCM8XX_MKFUNC(smb1b), + NPCM8XX_MKFUNC(smb1c), + NPCM8XX_MKFUNC(smb1d), + NPCM8XX_MKFUNC(smb2), + NPCM8XX_MKFUNC(smb2b), + NPCM8XX_MKFUNC(smb2c), + NPCM8XX_MKFUNC(smb2d), + NPCM8XX_MKFUNC(smb3), + NPCM8XX_MKFUNC(smb3b), + NPCM8XX_MKFUNC(smb3c), + NPCM8XX_MKFUNC(smb3d), + NPCM8XX_MKFUNC(smb4), + NPCM8XX_MKFUNC(smb4b), + NPCM8XX_MKFUNC(smb4c), + NPCM8XX_MKFUNC(smb4d), + NPCM8XX_MKFUNC(smb4den), + NPCM8XX_MKFUNC(smb5), + NPCM8XX_MKFUNC(smb5b), + NPCM8XX_MKFUNC(smb5c), + NPCM8XX_MKFUNC(smb5d), + NPCM8XX_MKFUNC(ga20kbc), + NPCM8XX_MKFUNC(smb6), + NPCM8XX_MKFUNC(smb6b), + NPCM8XX_MKFUNC(smb6c), + NPCM8XX_MKFUNC(smb6d), + NPCM8XX_MKFUNC(smb7), + NPCM8XX_MKFUNC(smb7b), + NPCM8XX_MKFUNC(smb7c), + NPCM8XX_MKFUNC(smb7d), + NPCM8XX_MKFUNC(smb8), + NPCM8XX_MKFUNC(smb9), + NPCM8XX_MKFUNC(smb10), + NPCM8XX_MKFUNC(smb11), + NPCM8XX_MKFUNC(smb12), + NPCM8XX_MKFUNC(smb13), + NPCM8XX_MKFUNC(smb14), + NPCM8XX_MKFUNC(smb14b), + NPCM8XX_MKFUNC(smb15), + NPCM8XX_MKFUNC(smb16), + NPCM8XX_MKFUNC(smb16b), + NPCM8XX_MKFUNC(smb17), + NPCM8XX_MKFUNC(smb18), + NPCM8XX_MKFUNC(smb19), + NPCM8XX_MKFUNC(smb20), + NPCM8XX_MKFUNC(smb21), + NPCM8XX_MKFUNC(smb22), + NPCM8XX_MKFUNC(smb23), + NPCM8XX_MKFUNC(smb23b), + NPCM8XX_MKFUNC(fanin0), + NPCM8XX_MKFUNC(fanin1), + NPCM8XX_MKFUNC(fanin2), + NPCM8XX_MKFUNC(fanin3), + NPCM8XX_MKFUNC(fanin4), + NPCM8XX_MKFUNC(fanin5), + NPCM8XX_MKFUNC(fanin6), + NPCM8XX_MKFUNC(fanin7), + NPCM8XX_MKFUNC(fanin8), + NPCM8XX_MKFUNC(fanin9), + NPCM8XX_MKFUNC(fanin10), + NPCM8XX_MKFUNC(fanin11), + NPCM8XX_MKFUNC(fanin12), + NPCM8XX_MKFUNC(fanin13), + NPCM8XX_MKFUNC(fanin14), + NPCM8XX_MKFUNC(fanin15), + NPCM8XX_MKFUNC(faninx), + NPCM8XX_MKFUNC(pwm0), + NPCM8XX_MKFUNC(pwm1), + NPCM8XX_MKFUNC(pwm2), + NPCM8XX_MKFUNC(pwm3), + NPCM8XX_MKFUNC(pwm4), + NPCM8XX_MKFUNC(pwm5), + NPCM8XX_MKFUNC(pwm6), + NPCM8XX_MKFUNC(pwm7), + NPCM8XX_MKFUNC(pwm8), + NPCM8XX_MKFUNC(pwm9), + NPCM8XX_MKFUNC(pwm10), + NPCM8XX_MKFUNC(pwm11), + NPCM8XX_MKFUNC(sg1mdio), + NPCM8XX_MKFUNC(rg2), + NPCM8XX_MKFUNC(rg2mdio), + NPCM8XX_MKFUNC(ddr), + NPCM8XX_MKFUNC(uart1), + NPCM8XX_MKFUNC(uart2), + NPCM8XX_MKFUNC(bmcuart0a), + NPCM8XX_MKFUNC(bmcuart0b), + NPCM8XX_MKFUNC(bmcuart1), + NPCM8XX_MKFUNC(iox1), + NPCM8XX_MKFUNC(iox2), + NPCM8XX_MKFUNC(ioxh), + NPCM8XX_MKFUNC(gspi), + NPCM8XX_MKFUNC(mmc), + NPCM8XX_MKFUNC(mmcwp), + NPCM8XX_MKFUNC(mmccd), + NPCM8XX_MKFUNC(mmcrst), + NPCM8XX_MKFUNC(mmc8), + NPCM8XX_MKFUNC(r1), + NPCM8XX_MKFUNC(r1err), + NPCM8XX_MKFUNC(r1md), + NPCM8XX_MKFUNC(r2), + NPCM8XX_MKFUNC(r2err), + NPCM8XX_MKFUNC(r2md), + NPCM8XX_MKFUNC(sd1), + NPCM8XX_MKFUNC(sd1pwr), + NPCM8XX_MKFUNC(wdog1), + NPCM8XX_MKFUNC(wdog2), + NPCM8XX_MKFUNC(scipme), + NPCM8XX_MKFUNC(smi), + NPCM8XX_MKFUNC(serirq), + NPCM8XX_MKFUNC(jtag2), + NPCM8XX_MKFUNC(spix), + NPCM8XX_MKFUNC(spixcs1), + NPCM8XX_MKFUNC(spi1), + NPCM8XX_MKFUNC(pspi), + NPCM8XX_MKFUNC(ddc), + NPCM8XX_MKFUNC(clkreq), + NPCM8XX_MKFUNC(clkout), + NPCM8XX_MKFUNC(spi3), + NPCM8XX_MKFUNC(spi3cs1), + NPCM8XX_MKFUNC(spi3quad), + NPCM8XX_MKFUNC(spi3cs2), + NPCM8XX_MKFUNC(spi3cs3), + NPCM8XX_MKFUNC(spi0cs1), + NPCM8XX_MKFUNC(lpc), + NPCM8XX_MKFUNC(lpcclk), + NPCM8XX_MKFUNC(espi), + NPCM8XX_MKFUNC(lkgpo0), + NPCM8XX_MKFUNC(lkgpo1), + NPCM8XX_MKFUNC(lkgpo2), + NPCM8XX_MKFUNC(nprd_smi), + NPCM8XX_MKFUNC(hgpio0), + NPCM8XX_MKFUNC(hgpio1), + NPCM8XX_MKFUNC(hgpio2), + NPCM8XX_MKFUNC(hgpio3), + NPCM8XX_MKFUNC(hgpio4), + NPCM8XX_MKFUNC(hgpio5), + NPCM8XX_MKFUNC(hgpio6), + NPCM8XX_MKFUNC(hgpio7), +}; + +#define NPCM8XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q) \ + [a] { .fn0 = fn_ ## b, .reg0 = NPCM8XX_GCR_ ## c, .bit0 = d, \ + .fn1 = fn_ ## e, .reg1 = NPCM8XX_GCR_ ## f, .bit1 = g, \ + .fn2 = fn_ ## h, .reg2 = NPCM8XX_GCR_ ## i, .bit2 = j, \ + .fn3 = fn_ ## k, .reg3 = NPCM8XX_GCR_ ## l, .bit3 = m, \ + .fn4 = fn_ ## n, .reg4 = NPCM8XX_GCR_ ## o, .bit4 = p, \ + .flag = q } + +/* Drive strength controlled by NPCM8XX_GP_N_ODSC */ +#define DRIVE_STRENGTH_LO_SHIFT 8 +#define DRIVE_STRENGTH_HI_SHIFT 12 +#define DRIVE_STRENGTH_MASK GENMASK(15, 8) + +#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ + ((hi) << DRIVE_STRENGTH_HI_SHIFT)) +#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & GENMASK(3, 0)) +#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & GENMASK(3, 0)) + +#define GPI BIT(0) /* Not GPO */ +#define GPO BIT(1) /* Not GPI */ +#define SLEW BIT(2) /* Has Slew Control, NPCM8XX_GP_N_OSRC */ +#define SLEWLPC BIT(3) /* Has Slew Control, SRCNT.3 */ + +struct npcm8xx_pincfg { + int flag; + int fn0, reg0, bit0; + int fn1, reg1, bit1; + int fn2, reg2, bit2; + int fn3, reg3, bit3; + int fn4, reg4, bit4; +}; + +static const struct npcm8xx_pincfg pincfg[] = { + /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 FUNCTION 5 FLAGS */ + NPCM8XX_PINCFG(0, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(1, iox1, MFSEL1, 30, smb6c, I2CSEGSEL, 25, smb18, MFSEL5, 26, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(2, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(3, iox1, MFSEL1, 30, smb6b, I2CSEGSEL, 24, smb17, MFSEL5, 25, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(8, lkgpo1, FLOCKR1, 4, tp_gpio0b, MFSEL7, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM8XX_PINCFG(9, lkgpo2, FLOCKR1, 8, tp_gpio1b, MFSEL7, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM8XX_PINCFG(10, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(11, ioxh, MFSEL3, 18, smb6d, I2CSEGSEL, 26, smb16, MFSEL5, 24, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(16, lkgpo0, FLOCKR1, 0, smb7b, I2CSEGSEL, 27, tp_gpio2b, MFSEL7, 10, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(17, pspi, MFSEL3, 13, cp1gpio5, MFSEL6, 7, smb4den, I2CSEGSEL, 23, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(18, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(19, pspi, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(20, hgpio0, MFSEL2, 24, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(21, hgpio1, MFSEL2, 25, smb15, MFSEL3, 8, smb4c, I2CSEGSEL, 15, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(22, hgpio2, MFSEL2, 26, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(23, hgpio3, MFSEL2, 27, smb14, MFSEL3, 7, smb4d, I2CSEGSEL, 16, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(24, hgpio4, MFSEL2, 28, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(25, hgpio5, MFSEL2, 29, ioxh, MFSEL3, 18, smb7c, I2CSEGSEL, 28, tp_smb2, MFSEL7, 28, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(32, spi0cs1, MFSEL1, 3, smb14b, MFSEL7, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(33, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(34, i3c4, MFSEL6, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(37, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(38, smb3c, I2CSEGSEL, 12, smb23, MFSEL5, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(39, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(40, smb3b, I2CSEGSEL, 11, smb22, MFSEL5, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(41, bmcuart0a, MFSEL1, 9, cp1urxd, MFSEL6, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(42, bmcuart0a, MFSEL1, 9, cp1utxd, MFSEL6, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO), + NPCM8XX_PINCFG(43, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(44, hsi1b, MFSEL1, 28, nbu1crts, MFSEL6, 15, jtag2, MFSEL4, 0, tp_jtag3, MFSEL7, 13, j2j3, MFSEL5, 2, GPO), + NPCM8XX_PINCFG(45, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO), + NPCM8XX_PINCFG(46, hsi1c, MFSEL1, 4, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, tp_jtag3, MFSEL7, 13, none, NONE, 0, GPO), + NPCM8XX_PINCFG(47, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 8)), + NPCM8XX_PINCFG(48, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(49, hsi2a, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(50, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(51, hsi2b, MFSEL1, 29, bu6, MFSEL5, 6, tp_uart, MFSEL7, 12, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(52, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(53, hsi2c, MFSEL1, 5, bu5, MFSEL5, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(54, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(55, hsi2c, MFSEL1, 5, bu4, MFSEL5, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(56, r1err, MFSEL1, 12, r1oen, MFSEL5, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(57, r1md, MFSEL1, 13, tpgpio4b, MFSEL5, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM8XX_PINCFG(58, r1md, MFSEL1, 13, tpgpio5b, MFSEL5, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM8XX_PINCFG(59, hgpio6, MFSEL2, 30, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(60, hgpio7, MFSEL2, 31, smb3d, I2CSEGSEL, 13, smb19, MFSEL5, 27, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(61, hsi1c, MFSEL1, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(62, hsi1b, MFSEL1, 28, jtag2, MFSEL4, 0, j2j3, MFSEL5, 2, nbu1crts, MFSEL6, 15, tp_jtag3, MFSEL7, 13, GPO), + NPCM8XX_PINCFG(63, hsi1a, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(90, r2err, MFSEL1, 15, r2oen, MFSEL5, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(91, r2md, MFSEL1, 16, cp1gpio6, MFSEL6, 8, tp_gpio0, MFSEL7, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM8XX_PINCFG(92, r2md, MFSEL1, 16, cp1gpio7, MFSEL6, 9, tp_gpio1, MFSEL7, 1, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM8XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(95, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(96, cp1gpio7b, MFSEL6, 24, tp_gpio7, MFSEL7, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(97, cp1gpio6b, MFSEL6, 25, tp_gpio6, MFSEL7, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(98, bu4b, MFSEL5, 13, cp1gpio5b, MFSEL6, 26, tp_gpio5, MFSEL7, 5, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(99, bu4b, MFSEL5, 13, cp1gpio4b, MFSEL6, 27, tp_gpio4, MFSEL7, 4, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(100, bu5b, MFSEL5, 12, cp1gpio3c, MFSEL6, 28, tp_gpio3, MFSEL7, 3, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(101, bu5b, MFSEL5, 12, cp1gpio2c, MFSEL6, 29, tp_gpio2, MFSEL7, 2, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(102, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(103, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(104, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(105, vgadig, MFSEL7, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(106, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(107, i3c5, MFSEL3, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(108, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(109, sg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(124, smb1c, I2CSEGSEL, 6, cp1gpio3b, MFSEL6, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(125, smb1c, I2CSEGSEL, 6, cp1gpio2b, MFSEL6, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(126, smb1b, I2CSEGSEL, 5, cp1gpio1b, MFSEL6, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(127, smb1b, I2CSEGSEL, 5, cp1gpio0b, MFSEL6, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(134, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(135, smb11, MFSEL4, 14, smb23b, MFSEL6, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(136, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(137, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(138, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(139, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(140, jm1, MFSEL5, 15, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(141, smb7b, I2CSEGSEL, 27, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(142, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(143, smb7d, I2CSEGSEL, 29, tp_smb1, MFSEL7, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), + NPCM8XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(161, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(162, serirq, MFSEL1, 31, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM8XX_PINCFG(163, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(164, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(165, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(166, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(167, lpc, MFSEL1, 26, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(168, lpcclk, MFSEL1, 31, espi, MFSEL4, 8, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(169, scipme, MFSEL3, 0, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(170, smi, MFSEL1, 22, smb21, MFSEL5, 29, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(175, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM8XX_PINCFG(176, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM8XX_PINCFG(177, spi1, MFSEL3, 4, faninx, MFSEL3, 3, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM8XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(183, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(184, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(185, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(186, gpio1836, MFSEL6, 19, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM8XX_PINCFG(187, gpo187, MFSEL7, 24, smb14b, MFSEL7, 26, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(188, gpio1889, MFSEL7, 25, spi3cs2, MFSEL4, 18, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(189, gpio1889, MFSEL7, 25, spi3cs3, MFSEL4, 19, spi3quad, MFSEL4, 20, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(190, nprd_smi, FLOCKR1, 20, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), + NPCM8XX_PINCFG(191, spi1d23, MFSEL5, 3, spi1cs2, MFSEL5, 4, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */ + NPCM8XX_PINCFG(192, spi1d23, MFSEL5, 3, spi1cs3, MFSEL5, 5, fm1, MFSEL6, 17, smb15, MFSEL7, 27, none, NONE, 0, DSTR(0, 2)), /* XX */ + NPCM8XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(194, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), + NPCM8XX_PINCFG(195, smb0b, I2CSEGSEL, 0, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), + NPCM8XX_PINCFG(196, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), + NPCM8XX_PINCFG(197, smb0den, I2CSEGSEL, 22, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), + NPCM8XX_PINCFG(198, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), + NPCM8XX_PINCFG(199, smb0d, I2CSEGSEL, 2, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), + NPCM8XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO), + NPCM8XX_PINCFG(202, smb0c, I2CSEGSEL, 1, fm0, MFSEL6, 16, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(0, 1)), + NPCM8XX_PINCFG(203, faninx, MFSEL3, 3, spi1cs0, MFSEL3, 4, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), + NPCM8XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ + NPCM8XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, SLEW), /* DSCNT */ + NPCM8XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3rxer, MFSEL6, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, r3oen, MFSEL5, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, rmii3, MFSEL5, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(218, wdog1, MFSEL3, 19, smb16b, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(219, wdog2, MFSEL3, 20, smb16b, MFSEL7, 30, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(220, smb12, MFSEL3, 5, pwm8, MFSEL6, 11, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(221, smb12, MFSEL3, 5, pwm9, MFSEL6, 12, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(224, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(225, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(226, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPO | DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(227, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(228, spixcs1, MFSEL4, 28, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(229, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(230, spix, MFSEL4, 27, fm2, MFSEL6, 18, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), + NPCM8XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(4, 12) | SLEW), + NPCM8XX_PINCFG(233, spi1cs1, MFSEL5, 0, fm1, MFSEL6, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEWLPC), /* slewlpc ? */ + NPCM8XX_PINCFG(234, pwm10, MFSEL6, 13, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, 0), + NPCM8XX_PINCFG(235, pwm11, MFSEL6, 14, smb20, MFSEL5, 28, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(240, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(241, i3c0, MFSEL5, 17, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(242, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(243, i3c1, MFSEL5, 19, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(244, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(245, i3c2, MFSEL5, 21, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(246, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(247, i3c3, MFSEL5, 23, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(251, jm2, MFSEL5, 1, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM8XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ + NPCM8XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */ + NPCM8XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */ +}; + +/* number, name, drv_data */ +static const struct pinctrl_pin_desc npcm8xx_pins[] = { + PINCTRL_PIN(0, "GPIO0/IOX1_DI/SMB6C_SDA/SMB18_SDA"), + PINCTRL_PIN(1, "GPIO1/IOX1_LD/SMB6C_SCL/SMB18_SCL"), + PINCTRL_PIN(2, "GPIO2/IOX1_CK/SMB6B_SDA/SMB17_SDA"), + PINCTRL_PIN(3, "GPIO3/IOX1_DO/SMB6B_SCL/SMB17_SCL"), + PINCTRL_PIN(4, "GPIO4/IOX2_DI/SMB1D_SDA"), + PINCTRL_PIN(5, "GPIO5/IOX2_LD/SMB1D_SCL"), + PINCTRL_PIN(6, "GPIO6/IOX2_CK/SMB2D_SDA"), + PINCTRL_PIN(7, "GPIO7/IOX2_D0/SMB2D_SCL"), + PINCTRL_PIN(8, "GPIO8/LKGPO1/TP_GPIO0"), + PINCTRL_PIN(9, "GPIO9/LKGPO2/TP_GPIO1"), + PINCTRL_PIN(10, "GPIO10/IOXH_LD/SMB6D_SCL/SMB16_SCL"), + PINCTRL_PIN(11, "GPIO11/IOXH_CK/SMB6D_SDA/SMB16_SDA"), + PINCTRL_PIN(12, "GPIO12/GSPI_CK/SMB5B_SCL"), + PINCTRL_PIN(13, "GPIO13/GSPI_DO/SMB5B_SDA"), + PINCTRL_PIN(14, "GPIO14/GSPI_DI/SMB5C_SCL"), + PINCTRL_PIN(15, "GPIO15/GSPI_CS/SMB5C_SDA"), + PINCTRL_PIN(16, "GPIO16/SMB7B_SDA/LKGPO0/TP_GPIO2"), + PINCTRL_PIN(17, "GPIO17/PSPI_DI/CP1_GPIO5"), + PINCTRL_PIN(18, "GPIO18/PSPI_D0/SMB4B_SDA"), + PINCTRL_PIN(19, "GPIO19/PSPI_CK/SMB4B_SCL"), + PINCTRL_PIN(20, "GPIO20/H_GPIO0/SMB4C_SDA/SMB15_SDA"), + PINCTRL_PIN(21, "GPIO21/H_GPIO1/SMB4C_SCL/SMB15_SCL"), + PINCTRL_PIN(22, "GPIO22/H_GPIO2/SMB4D_SDA/SMB14_SDA"), + PINCTRL_PIN(23, "GPIO23/H_GPIO3/SMB4D_SCL/SMB14_SCL"), + PINCTRL_PIN(24, "GPIO24/IOXH_DO/H_GPIO4/SMB7C_SCL/TP_SMB2_SCL"), + PINCTRL_PIN(25, "GPIO25/IOXH_DI/H_GPIO4/SMB7C_SDA/TP_SMB2_SDA"), + PINCTRL_PIN(26, "GPIO26/SMB5_SDA"), + PINCTRL_PIN(27, "GPIO27/SMB5_SCL"), + PINCTRL_PIN(28, "GPIO28/SMB4_SDA"), + PINCTRL_PIN(29, "GPIO29/SMB4_SCL"), + PINCTRL_PIN(30, "GPIO30/SMB3_SDA"), + PINCTRL_PIN(31, "GPIO31/SMB3_SCL"), + PINCTRL_PIN(32, "GPIO32/SMB14B_SCL/SPI0_nCS1"), + PINCTRL_PIN(33, "GPIO33/I3C4_SCL"), + PINCTRL_PIN(34, "GPIO34/I3C4_SDA"), + PINCTRL_PIN(37, "GPIO37/SMB3C_SDA/SMB23_SDA"), + PINCTRL_PIN(38, "GPIO38/SMB3C_SCL/SMB23_SCL"), + PINCTRL_PIN(39, "GPIO39/SMB3B_SDA/SMB22_SDA"), + PINCTRL_PIN(40, "GPIO40/SMB3B_SCL/SMB22_SCL"), + PINCTRL_PIN(41, "GPIO41/BU0_RXD/CP1U_RXD"), + PINCTRL_PIN(42, "GPIO42/BU0_TXD/CP1U_TXD"), + PINCTRL_PIN(43, "GPIO43/SI1_RXD/BU1_RXD"), + PINCTRL_PIN(44, "GPIO44/SI1_nCTS/BU1_nCTS/CP_TDI/TP_TDI/CP_TP_TDI"), + PINCTRL_PIN(45, "GPIO45/SI1_nDCD/CP_TMS_SWIO/TP_TMS_SWIO/CP_TP_TMS_SWIO"), + PINCTRL_PIN(46, "GPIO46/SI1_nDSR/CP_TCK_SWCLK/TP_TCK_SWCLK/CP_TP_TCK_SWCLK"), + PINCTRL_PIN(47, "GPIO47/SI1n_RI1"), + PINCTRL_PIN(48, "GPIO48/SI2_TXD/BU0_TXD/STRAP5"), + PINCTRL_PIN(49, "GPIO49/SI2_RXD/BU0_RXD"), + PINCTRL_PIN(50, "GPIO50/SI2_nCTS/BU6_TXD/TPU_TXD"), + PINCTRL_PIN(51, "GPIO51/SI2_nRTS/BU6_RXD/TPU_RXD"), + PINCTRL_PIN(52, "GPIO52/SI2_nDCD/BU5_RXD"), + PINCTRL_PIN(53, "GPIO53/SI2_nDTR_BOUT2/BU5_TXD"), + PINCTRL_PIN(54, "GPIO54/SI2_nDSR/BU4_TXD"), + PINCTRL_PIN(55, "GPIO55/SI2_RI2/BU4_RXD"), + PINCTRL_PIN(56, "GPIO56/R1_RXERR/R1_OEN"), + PINCTRL_PIN(57, "GPIO57/R1_MDC/TP_GPIO4"), + PINCTRL_PIN(58, "GPIO58/R1_MDIO/TP_GPIO5"), + PINCTRL_PIN(59, "GPIO59/H_GPIO06/SMB3D_SDA/SMB19_SDA"), + PINCTRL_PIN(60, "GPIO60/H_GPIO07/SMB3D_SCL/SMB19_SCL"), + PINCTRL_PIN(61, "GPIO61/SI1_nDTR_BOUT"), + PINCTRL_PIN(62, "GPIO62/SI1_nRTS/BU1_nRTS/CP_TDO_SWO/TP_TDO_SWO/CP_TP_TDO_SWO"), + PINCTRL_PIN(63, "GPIO63/BU1_TXD1/SI1_TXD"), + PINCTRL_PIN(64, "GPIO64/FANIN0"), + PINCTRL_PIN(65, "GPIO65/FANIN1"), + PINCTRL_PIN(66, "GPIO66/FANIN2"), + PINCTRL_PIN(67, "GPIO67/FANIN3"), + PINCTRL_PIN(68, "GPIO68/FANIN4"), + PINCTRL_PIN(69, "GPIO69/FANIN5"), + PINCTRL_PIN(70, "GPIO70/FANIN6"), + PINCTRL_PIN(71, "GPIO71/FANIN7"), + PINCTRL_PIN(72, "GPIO72/FANIN8"), + PINCTRL_PIN(73, "GPIO73/FANIN9"), + PINCTRL_PIN(74, "GPIO74/FANIN10"), + PINCTRL_PIN(75, "GPIO75/FANIN11"), + PINCTRL_PIN(76, "GPIO76/FANIN12"), + PINCTRL_PIN(77, "GPIO77/FANIN13"), + PINCTRL_PIN(78, "GPIO78/FANIN14"), + PINCTRL_PIN(79, "GPIO79/FANIN15"), + PINCTRL_PIN(80, "GPIO80/PWM0"), + PINCTRL_PIN(81, "GPIO81/PWM1"), + PINCTRL_PIN(82, "GPIO82/PWM2"), + PINCTRL_PIN(83, "GPIO83/PWM3"), + PINCTRL_PIN(84, "GPIO84/R2_TXD0"), + PINCTRL_PIN(85, "GPIO85/R2_TXD1"), + PINCTRL_PIN(86, "GPIO86/R2_TXEN"), + PINCTRL_PIN(87, "GPIO87/R2_RXD0"), + PINCTRL_PIN(88, "GPIO88/R2_RXD1"), + PINCTRL_PIN(89, "GPIO89/R2_CRSDV"), + PINCTRL_PIN(90, "GPIO90/R2_RXERR/R2_OEN"), + PINCTRL_PIN(91, "GPIO91/R2_MDC/CP1_GPIO6/TP_GPIO0"), + PINCTRL_PIN(92, "GPIO92/R2_MDIO/CP1_GPIO7/TP_GPIO1"), + PINCTRL_PIN(93, "GPIO93/GA20/SMB5D_SCL"), + PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5D_SDA"), + PINCTRL_PIN(95, "GPIO95/nESPIRST/LPC_nLRESET"), + PINCTRL_PIN(96, "GPIO96/CP1_GPIO7/BU2_TXD/TP_GPIO7"), + PINCTRL_PIN(97, "GPIO97/CP1_GPIO6/BU2_RXD/TP_GPIO6"), + PINCTRL_PIN(98, "GPIO98/CP1_GPIO5/BU4_TXD/TP_GPIO5"), + PINCTRL_PIN(99, "GPIO99/CP1_GPIO4/BU4_RXD/TP_GPIO4"), + PINCTRL_PIN(100, "GPIO100/CP1_GPIO3/BU5_TXD/TP_GPIO3"), + PINCTRL_PIN(101, "GPIO101/CP1_GPIO2/BU5_RXD/TP_GPIO2"), + PINCTRL_PIN(102, "GPIO102/HSYNC"), + PINCTRL_PIN(103, "GPIO103/VSYNC"), + PINCTRL_PIN(104, "GPIO104/DDC_SCL"), + PINCTRL_PIN(105, "GPIO105/DDC_SDA"), + PINCTRL_PIN(106, "GPIO106/I3C5_SCL"), + PINCTRL_PIN(107, "GPIO107/I3C5_SDA"), + PINCTRL_PIN(108, "GPIO108/SG1_MDC"), + PINCTRL_PIN(109, "GPIO109/SG1_MDIO"), + PINCTRL_PIN(110, "GPIO110/RG2_TXD0/DDRV0/R3_TXD0"), + PINCTRL_PIN(111, "GPIO111/RG2_TXD1/DDRV1/R3_TXD1"), + PINCTRL_PIN(112, "GPIO112/RG2_TXD2/DDRV2"), + PINCTRL_PIN(113, "GPIO113/RG2_TXD3/DDRV3"), + PINCTRL_PIN(114, "GPIO114/SMB0_SCL"), + PINCTRL_PIN(115, "GPIO115/SMB0_SDA"), + PINCTRL_PIN(116, "GPIO116/SMB1_SCL"), + PINCTRL_PIN(117, "GPIO117/SMB1_SDA"), + PINCTRL_PIN(118, "GPIO118/SMB2_SCL"), + PINCTRL_PIN(119, "GPIO119/SMB2_SDA"), + PINCTRL_PIN(120, "GPIO120/SMB2C_SDA"), + PINCTRL_PIN(121, "GPIO121/SMB2C_SCL"), + PINCTRL_PIN(122, "GPIO122/SMB2B_SDA"), + PINCTRL_PIN(123, "GPIO123/SMB2B_SCL"), + PINCTRL_PIN(124, "GPIO124/SMB1C_SDA/CP1_GPIO3"), + PINCTRL_PIN(125, "GPIO125/SMB1C_SCL/CP1_GPIO2"), + PINCTRL_PIN(126, "GPIO126/SMB1B_SDA/CP1_GPIO1"), + PINCTRL_PIN(127, "GPIO127/SMB1B_SCL/CP1_GPIO0"), + PINCTRL_PIN(128, "GPIO128/SMB824_SCL"), + PINCTRL_PIN(129, "GPIO129/SMB824_SDA"), + PINCTRL_PIN(130, "GPIO130/SMB925_SCL"), + PINCTRL_PIN(131, "GPIO131/SMB925_SDA"), + PINCTRL_PIN(132, "GPIO132/SMB1026_SCL"), + PINCTRL_PIN(133, "GPIO133/SMB1026_SDA"), + PINCTRL_PIN(134, "GPIO134/SMB11_SCL/SMB23B_SCL"), + PINCTRL_PIN(135, "GPIO135/SMB11_SDA/SMB23B_SDA"), + PINCTRL_PIN(136, "GPIO136/JM1_TCK"), + PINCTRL_PIN(137, "GPIO137/JM1_TDO"), + PINCTRL_PIN(138, "GPIO138/JM1_TMS"), + PINCTRL_PIN(139, "GPIO139/JM1_TDI"), + PINCTRL_PIN(140, "GPIO140/JM1_nTRST"), + PINCTRL_PIN(141, "GPIO141/SMB7B_SCL"), + PINCTRL_PIN(142, "GPIO142/SMB7D_SCL/TPSMB1_SCL"), + PINCTRL_PIN(143, "GPIO143/SMB7D_SDA/TPSMB1_SDA"), + PINCTRL_PIN(144, "GPIO144/PWM4"), + PINCTRL_PIN(145, "GPIO145/PWM5"), + PINCTRL_PIN(146, "GPIO146/PWM6"), + PINCTRL_PIN(147, "GPIO147/PWM7"), + PINCTRL_PIN(148, "GPIO148/MMC_DT4"), + PINCTRL_PIN(149, "GPIO149/MMC_DT5"), + PINCTRL_PIN(150, "GPIO150/MMC_DT6"), + PINCTRL_PIN(151, "GPIO151/MMC_DT7"), + PINCTRL_PIN(152, "GPIO152/MMC_CLK"), + PINCTRL_PIN(153, "GPIO153/MMC_WP"), + PINCTRL_PIN(154, "GPIO154/MMC_CMD"), + PINCTRL_PIN(155, "GPIO155/MMC_nCD/MMC_nRSTLK"), + PINCTRL_PIN(156, "GPIO156/MMC_DT0"), + PINCTRL_PIN(157, "GPIO157/MMC_DT1"), + PINCTRL_PIN(158, "GPIO158/MMC_DT2"), + PINCTRL_PIN(159, "GPIO159/MMC_DT3"), + PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT/GFXBYPCK"), + PINCTRL_PIN(161, "GPIO161/ESPI_nCS/LPC_nLFRAME"), + PINCTRL_PIN(162, "GPIO162/SERIRQ"), + PINCTRL_PIN(163, "GPIO163/ESPI_CK/LPC_LCLK"), + PINCTRL_PIN(164, "GPIO164/ESPI_IO0/LPC_LAD0"), + PINCTRL_PIN(165, "GPIO165/ESPI_IO1/LPC_LAD1"), + PINCTRL_PIN(166, "GPIO166/ESPI_IO2/LPC_LAD2"), + PINCTRL_PIN(167, "GPIO167/ESPI_IO3/LPC_LAD3"), + PINCTRL_PIN(168, "GPIO168/ESPI_nALERT/LPC_nCLKRUN"), + PINCTRL_PIN(169, "GPIO169/nSCIPME/SMB21_SCL"), + PINCTRL_PIN(170, "GPIO170/nSMI/SMB21_SDA"), + PINCTRL_PIN(171, "GPIO171/SMB6_SCL"), + PINCTRL_PIN(172, "GPIO172/SMB6_SDA"), + PINCTRL_PIN(173, "GPIO173/SMB7_SCL"), + PINCTRL_PIN(174, "GPIO174/SMB7_SDA"), + PINCTRL_PIN(175, "GPIO175/SPI1_CK/FANIN19/FM1_CK"), + PINCTRL_PIN(176, "GPIO176/SPI1_DO/FANIN18/FM1_DO/STRAP9"), + PINCTRL_PIN(177, "GPIO177/SPI1_DI/FANIN17/FM1_D1/STRAP10"), + PINCTRL_PIN(178, "GPIO178/R1_TXD0"), + PINCTRL_PIN(179, "GPIO179/R1_TXD1"), + PINCTRL_PIN(180, "GPIO180/R1_TXEN"), + PINCTRL_PIN(181, "GPIO181/R1_RXD0"), + PINCTRL_PIN(182, "GPIO182/R1_RXD1"), + PINCTRL_PIN(183, "GPIO183/SPI3_SEL"), + PINCTRL_PIN(184, "GPIO184/SPI3_D0/STRAP13"), + PINCTRL_PIN(185, "GPIO185/SPI3_D1"), + PINCTRL_PIN(186, "GPIO186/SPI3_nCS0"), + PINCTRL_PIN(187, "GPO187/SPI3_nCS1_SMB14B_SDA"), + PINCTRL_PIN(188, "GPIO188/SPI3_D2/SPI3_nCS2"), + PINCTRL_PIN(189, "GPIO189/SPI3_D3/SPI3_nCS3"), + PINCTRL_PIN(190, "GPIO190/nPRD_SMI"), + PINCTRL_PIN(191, "GPIO191/SPI1_D1/FANIN17/FM1_D1/STRAP10"), + PINCTRL_PIN(192, "GPIO192/SPI1_D3/SPI_nCS3/FM1_D3/SMB15_SCL"), + PINCTRL_PIN(193, "GPIO193/R1_CRSDV"), + PINCTRL_PIN(194, "GPIO194/SMB0B_SCL/FM0_CK"), + PINCTRL_PIN(195, "GPIO195/SMB0B_SDA/FM0_D0"), + PINCTRL_PIN(196, "GPIO196/SMB0C_SCL/FM0_D1"), + PINCTRL_PIN(197, "GPIO197/SMB0DEN/FM0_D3"), + PINCTRL_PIN(198, "GPIO198/SMB0D_SDA/FM0_D2"), + PINCTRL_PIN(199, "GPIO199/SMB0D_SCL/FM0_CSO"), + PINCTRL_PIN(200, "GPIO200/R2_CK"), + PINCTRL_PIN(201, "GPIO201/R1_CK"), + PINCTRL_PIN(202, "GPIO202/SMB0C_SDA/FM0_CSI"), + PINCTRL_PIN(203, "GPIO203/SPI1_nCS0/FANIN16/FM1_CSI"), + PINCTRL_PIN(208, "GPIO208/RG2_TXC/DVCK"), + PINCTRL_PIN(209, "GPIO209/RG2_TXCTL/DDRV4/R3_TXEN"), + PINCTRL_PIN(210, "GPIO210/RG2_RXD0/DDRV5/R3_RXD0"), + PINCTRL_PIN(211, "GPIO211/RG2_RXD1/DDRV6/R3_RXD1"), + PINCTRL_PIN(212, "GPIO212/RG2_RXD2/DDRV7/R3_RXD2"), + PINCTRL_PIN(213, "GPIO213/RG2_RXD3/DDRV8/R3_OEN"), + PINCTRL_PIN(214, "GPIO214/RG2_RXC/DDRV9/R3_CK"), + PINCTRL_PIN(215, "GPIO215/RG2_RXCTL/DDRV10/R3_CRSDV"), + PINCTRL_PIN(216, "GPIO216/RG2_MDC/DDRV11"), + PINCTRL_PIN(217, "GPIO217/RG2_MDIO/DVHSYNC"), + PINCTRL_PIN(218, "GPIO218/nWDO1/SMB16_SCL"), + PINCTRL_PIN(219, "GPIO219/nWDO2/SMB16_SDA"), + PINCTRL_PIN(220, "GPIO220/SMB12_SCL/PWM8"), + PINCTRL_PIN(221, "GPIO221/SMB12_SDA/PWM9"), + PINCTRL_PIN(222, "GPIO222/SMB13_SCL"), + PINCTRL_PIN(223, "GPIO223/SMB13_SDA"), + PINCTRL_PIN(224, "GPIO224/SPIX_CK/FM2_CK"), + PINCTRL_PIN(225, "GPO225/SPIX_D0/FM2_D0/STRAP1"), + PINCTRL_PIN(226, "GPO226/SPIX_D1/FM2_D1/STRAP2"), + PINCTRL_PIN(227, "GPIO227/SPIX_nCS0/FM2_CSI"), + PINCTRL_PIN(228, "GPIO228/SPIX_nCS1/FM2_CSO"), + PINCTRL_PIN(229, "GPO229/SPIX_D2/FM2_D2/STRAP3"), + PINCTRL_PIN(230, "GPO230/SPIX_D3/FM2_D3/STRAP6"), + PINCTRL_PIN(231, "GPIO231/EP_nCLKREQ"), + PINCTRL_PIN(233, "GPIO233/SPI1_nCS1/FM1_CSO"), + PINCTRL_PIN(234, "GPIO234/PWM10/SMB20_SCL"), + PINCTRL_PIN(235, "GPIO235/PWM11/SMB20_SDA"), + PINCTRL_PIN(240, "GPIO240/I3C0_SCL"), + PINCTRL_PIN(241, "GPIO241/I3C0_SDA"), + PINCTRL_PIN(242, "GPIO242/I3C1_SCL"), + PINCTRL_PIN(243, "GPIO243/I3C1_SDA"), + PINCTRL_PIN(244, "GPIO244/I3C2_SCL"), + PINCTRL_PIN(245, "GPIO245/I3C2_SDA"), + PINCTRL_PIN(246, "GPIO246/I3C3_SCL"), + PINCTRL_PIN(247, "GPIO247/I3C3_SDA"), + PINCTRL_PIN(250, "GPIO250/RG2_REFCK/DVVSYNC"), + PINCTRL_PIN(251, "JM2/CP1_GPIO"), + }; + +/* Enable mode in pin group */ +static void npcm8xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, + int pin_number, int mode) +{ + const struct npcm8xx_pincfg *cfg; + int i; + + for (i = 0 ; i < pin_number ; i++) { + cfg = &pincfg[pin[i]]; + if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || + cfg->fn2 == mode || cfg->fn3 == mode || cfg->fn4 == mode) { + if (cfg->reg0) + regmap_update_bits(gcr_regmap, cfg->reg0, + BIT(cfg->bit0), + (cfg->fn0 == mode) ? + BIT(cfg->bit0) : 0); + if (cfg->reg1) + regmap_update_bits(gcr_regmap, cfg->reg1, + BIT(cfg->bit1), + (cfg->fn1 == mode) ? + BIT(cfg->bit1) : 0); + if (cfg->reg2) + regmap_update_bits(gcr_regmap, cfg->reg2, + BIT(cfg->bit2), + (cfg->fn2 == mode) ? + BIT(cfg->bit2) : 0); + if (cfg->reg3) + regmap_update_bits(gcr_regmap, cfg->reg3, + BIT(cfg->bit3), + (cfg->fn3 == mode) ? + BIT(cfg->bit3) : 0); + if (cfg->reg4) + regmap_update_bits(gcr_regmap, cfg->reg4, + BIT(cfg->bit4), + (cfg->fn4 == mode) ? + BIT(cfg->bit4) : 0); + } + } +} + +static int npcm8xx_get_slew_rate(struct npcm8xx_gpio *bank, + struct regmap *gcr_regmap, unsigned int pin) +{ + int gpio = pin % bank->gc.ngpio; + unsigned long pinmask = BIT(gpio); + u32 val; + + if (pincfg[pin].flag & SLEW) + return ioread32(bank->base + NPCM8XX_GP_N_OSRC) & pinmask; + /* LPC Slew rate in SRCNT register */ + if (pincfg[pin].flag & SLEWLPC) { + regmap_read(gcr_regmap, NPCM8XX_GCR_SRCNT, &val); + return !!(val & SRCNT_ESPI); + } + + return -EINVAL; +} + +static int npcm8xx_set_slew_rate(struct npcm8xx_gpio *bank, + struct regmap *gcr_regmap, unsigned int pin, + int arg) +{ + void __iomem *OSRC_Offset = bank->base + NPCM8XX_GP_N_OSRC; + int gpio = BIT(pin % bank->gc.ngpio); + + if (pincfg[pin].flag & SLEW) { + switch (arg) { + case 0: + npcm_gpio_clr(&bank->gc, OSRC_Offset, gpio); + return 0; + case 1: + npcm_gpio_set(&bank->gc, OSRC_Offset, gpio); + return 0; + default: + return -EINVAL; + } + } + + if (!(pincfg[pin].flag & SLEWLPC)) + return -EINVAL; + + switch (arg) { + case 0: + regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT, + SRCNT_ESPI, 0); + break; + case 1: + regmap_update_bits(gcr_regmap, NPCM8XX_GCR_SRCNT, + SRCNT_ESPI, SRCNT_ESPI); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int npcm8xx_get_drive_strength(struct pinctrl_dev *pctldev, + unsigned int pin) +{ + struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + struct npcm8xx_gpio *bank = + &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; + int gpio = pin % bank->gc.ngpio; + unsigned long pinmask = BIT(gpio); + int flg, val; + u32 ds = 0; + + flg = pincfg[pin].flag; + if (!(flg & DRIVE_STRENGTH_MASK)) + return -EINVAL; + + val = ioread32(bank->base + NPCM8XX_GP_N_ODSC) & pinmask; + ds = val ? DSHI(flg) : DSLO(flg); + dev_dbg(bank->gc.parent, "pin %d strength %d = %d\n", pin, val, ds); + + return ds; +} + +static int npcm8xx_set_drive_strength(struct npcm8xx_pinctrl *npcm, + unsigned int pin, int nval) +{ + struct npcm8xx_gpio *bank = + &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; + int gpio = BIT(pin % bank->gc.ngpio); + int v; + + v = pincfg[pin].flag & DRIVE_STRENGTH_MASK; + + if (DSLO(v) == nval) + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); + else if (DSHI(v) == nval) + npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_ODSC, gpio); + else + return -ENOTSUPP; + + return 0; +} + +/* pinctrl_ops */ +static int npcm8xx_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(npcm8xx_pingroups); +} + +static const char *npcm8xx_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return npcm8xx_pingroups[selector].name; +} + +static int npcm8xx_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *npins) +{ + *npins = npcm8xx_pingroups[selector].npins; + *pins = npcm8xx_pingroups[selector].pins; + + return 0; +} + +static int npcm8xx_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, + u32 *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, + map, num_maps, + PIN_MAP_TYPE_INVALID); +} + +static void npcm8xx_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, u32 num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops npcm8xx_pinctrl_ops = { + .get_groups_count = npcm8xx_get_groups_count, + .get_group_name = npcm8xx_get_group_name, + .get_group_pins = npcm8xx_get_group_pins, + .dt_node_to_map = npcm8xx_dt_node_to_map, + .dt_free_map = npcm8xx_dt_free_map, +}; + +static int npcm8xx_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(npcm8xx_funcs); +} + +static const char *npcm8xx_get_function_name(struct pinctrl_dev *pctldev, + unsigned int function) +{ + return npcm8xx_funcs[function].name; +} + +static int npcm8xx_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int function, + const char * const **groups, + unsigned int * const ngroups) +{ + *ngroups = npcm8xx_funcs[function].ngroups; + *groups = npcm8xx_funcs[function].groups; + + return 0; +} + +static int npcm8xx_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, + unsigned int group) +{ + struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + + npcm8xx_setfunc(npcm->gcr_regmap, npcm8xx_pingroups[group].pins, + npcm8xx_pingroups[group].npins, group); + + return 0; +} + +static int npcm8xx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pin = &offset; + int mode = fn_gpio; + + if (pin[0] >= 183 && pin[0] <= 189) + mode = pincfg[pin[0]].fn0; + + npcm8xx_setfunc(npcm->gcr_regmap, &offset, 1, mode); + + return 0; +} + +static void npcm8xx_gpio_request_free(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + int virq; + + virq = irq_find_mapping(npcm->domain, offset); + if (virq) + irq_dispose_mapping(virq); +} + +static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + struct npcm8xx_gpio *bank = + &npcm->gpio_bank[offset / NPCM8XX_GPIO_PER_BANK]; + int gpio = BIT(offset % bank->gc.ngpio); + + if (input) + iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); + else + iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); + + return 0; +} + +static const struct pinmux_ops npcm8xx_pinmux_ops = { + .get_functions_count = npcm8xx_get_functions_count, + .get_function_name = npcm8xx_get_function_name, + .get_function_groups = npcm8xx_get_function_groups, + .set_mux = npcm8xx_pinmux_set_mux, + .gpio_request_enable = npcm8xx_gpio_request_enable, + .gpio_disable_free = npcm8xx_gpio_request_free, + .gpio_set_direction = npcm_gpio_set_direction, +}; + +static int debounce_timing_setting(struct npcm8xx_gpio *bank, u32 gpio, + u32 nanosecs) +{ + void __iomem *DBNCS_offset = bank->base + NPCM8XX_GP_N_DBNCS0 + (gpio / 4); + int gpio_debounce = (gpio % 16) * 2, debounce_select, i; + u32 dbncp_val, dbncp_val_mod; + + for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) { + if (bank->debounce.set_val[i]) { + if (bank->debounce.nanosec_val[i] == nanosecs) { + debounce_select = i << gpio_debounce; + npcm_gpio_set(&bank->gc, DBNCS_offset, + debounce_select); + break; + } + } else { + bank->debounce.set_val[i] = true; + bank->debounce.nanosec_val[i] = nanosecs; + debounce_select = i << gpio_debounce; + npcm_gpio_set(&bank->gc, DBNCS_offset, debounce_select); + switch (nanosecs) { + case 1 ... 1040: + iowrite32(0, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); + break; + case 1041 ... 1640: + iowrite32(0x10, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); + break; + case 1641 ... 2280: + iowrite32(0x20, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); + break; + case 2281 ... 2700: + iowrite32(0x30, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); + break; + case 2701 ... 2856: + iowrite32(0x40, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); + break; + case 2857 ... 3496: + iowrite32(0x50, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); + break; + case 3497 ... 4136: + iowrite32(0x60, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); + break; + case 4137 ... 5025: + iowrite32(0x70, bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); + break; + default: + dbncp_val = DIV_ROUND_CLOSEST(nanosecs, NPCM8XX_DEBOUNCE_NSEC); + if (dbncp_val > NPCM8XX_DEBOUNCE_MAX_VAL) + return -ENOTSUPP; + dbncp_val_mod = dbncp_val & GENMASK(3, 0); + if (dbncp_val_mod > GENMASK(2, 0)) + dbncp_val += 0x10; + iowrite32(dbncp_val & NPCM8XX_DEBOUNCE_VAL_MASK, + bank->base + NPCM8XX_GP_N_DBNCP0 + (i * 4)); + break; + } + break; + } + } + + if (i == 4) + return -ENOTSUPP; + + return 0; +} + +static int npcm_set_debounce(struct npcm8xx_pinctrl *npcm, unsigned int pin, + u32 nanosecs) +{ + struct npcm8xx_gpio *bank = + &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; + int gpio = BIT(pin % bank->gc.ngpio); + int ret; + + if (nanosecs) { + ret = debounce_timing_setting(bank, pin % bank->gc.ngpio, + nanosecs); + if (ret) + dev_err(npcm->dev, "Pin %d, All four debounce timing values are used, please use one of exist debounce values\n", pin); + else + npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, + gpio); + return ret; + } + + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_DBNC, gpio); + + return 0; +} + +/* pinconf_ops */ +static int npcm8xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + enum pin_config_param param = pinconf_to_config_param(*config); + struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + struct npcm8xx_gpio *bank = + &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; + int gpio = pin % bank->gc.ngpio; + unsigned long pinmask = BIT(gpio); + u32 ie, oe, pu, pd; + int rc = 0; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + pu = ioread32(bank->base + NPCM8XX_GP_N_PU) & pinmask; + pd = ioread32(bank->base + NPCM8XX_GP_N_PD) & pinmask; + if (param == PIN_CONFIG_BIAS_DISABLE) + rc = !pu && !pd; + else if (param == PIN_CONFIG_BIAS_PULL_UP) + rc = pu && !pd; + else if (param == PIN_CONFIG_BIAS_PULL_DOWN) + rc = !pu && pd; + break; + case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_INPUT_ENABLE: + ie = ioread32(bank->base + NPCM8XX_GP_N_IEM) & pinmask; + oe = ioread32(bank->base + NPCM8XX_GP_N_OE) & pinmask; + if (param == PIN_CONFIG_INPUT_ENABLE) + rc = (ie && !oe); + else if (param == PIN_CONFIG_OUTPUT) + rc = (!ie && oe); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + rc = !(ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + rc = ioread32(bank->base + NPCM8XX_GP_N_OTYP) & pinmask; + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + rc = ioread32(bank->base + NPCM8XX_GP_N_DBNC) & pinmask; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + rc = npcm8xx_get_drive_strength(pctldev, pin); + if (rc) + *config = pinconf_to_config_packed(param, rc); + break; + case PIN_CONFIG_SLEW_RATE: + rc = npcm8xx_get_slew_rate(bank, npcm->gcr_regmap, pin); + if (rc >= 0) + *config = pinconf_to_config_packed(param, rc); + break; + default: + return -ENOTSUPP; + } + + if (!rc) + return -EINVAL; + + return 0; +} + +static int npcm8xx_config_set_one(struct npcm8xx_pinctrl *npcm, + unsigned int pin, unsigned long config) +{ + enum pin_config_param param = pinconf_to_config_param(config); + struct npcm8xx_gpio *bank = + &npcm->gpio_bank[pin / NPCM8XX_GPIO_PER_BANK]; + u32 arg = pinconf_to_config_argument(config); + int gpio = BIT(pin % bank->gc.ngpio); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); + npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); + break; + case PIN_CONFIG_BIAS_PULL_UP: + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_PD, gpio); + npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_PU, gpio); + break; + case PIN_CONFIG_INPUT_ENABLE: + iowrite32(gpio, bank->base + NPCM8XX_GP_N_OEC); + bank->direction_input(&bank->gc, pin % bank->gc.ngpio); + break; + case PIN_CONFIG_OUTPUT: + bank->direction_output(&bank->gc, pin % bank->gc.ngpio, arg); + iowrite32(gpio, bank->base + NPCM8XX_GP_N_OES); + break; + case PIN_CONFIG_DRIVE_PUSH_PULL: + npcm_gpio_clr(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + npcm_gpio_set(&bank->gc, bank->base + NPCM8XX_GP_N_OTYP, gpio); + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + return npcm_set_debounce(npcm, pin, arg * 1000); + case PIN_CONFIG_SLEW_RATE: + return npcm8xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); + case PIN_CONFIG_DRIVE_STRENGTH: + return npcm8xx_set_drive_strength(npcm, pin, arg); + default: + return -ENOTSUPP; + } + + return 0; +} + +static int npcm8xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct npcm8xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); + int rc; + + while (num_configs--) { + rc = npcm8xx_config_set_one(npcm, pin, *configs++); + if (rc) + return rc; + } + + return 0; +} + +static const struct pinconf_ops npcm8xx_pinconf_ops = { + .is_generic = true, + .pin_config_get = npcm8xx_config_get, + .pin_config_set = npcm8xx_config_set, +}; + +/* pinctrl_desc */ +static struct pinctrl_desc npcm8xx_pinctrl_desc = { + .name = "npcm8xx-pinctrl", + .pins = npcm8xx_pins, + .npins = ARRAY_SIZE(npcm8xx_pins), + .pctlops = &npcm8xx_pinctrl_ops, + .pmxops = &npcm8xx_pinmux_ops, + .confops = &npcm8xx_pinconf_ops, + .owner = THIS_MODULE, +}; + +static int npcmgpio_add_pin_ranges(struct gpio_chip *chip) +{ + struct npcm8xx_gpio *bank = gpiochip_get_data(chip); + + return gpiochip_add_pin_range(&bank->gc, dev_name(chip->parent), + bank->pinctrl_id, bank->gc.base, + bank->gc.ngpio); +} + +static int npcm8xx_gpio_fw(struct npcm8xx_pinctrl *pctrl) +{ + struct fwnode_reference_args args; + struct device *dev = pctrl->dev; + struct fwnode_handle *child; + int ret = -ENXIO; + int id = 0, i; + + for_each_gpiochip_node(dev, child) { + pctrl->gpio_bank[id].base = fwnode_iomap(child, 0); + if (!pctrl->gpio_bank[id].base) + return dev_err_probe(dev, -ENXIO, "fwnode_iomap id %d failed\n", id); + + ret = bgpio_init(&pctrl->gpio_bank[id].gc, dev, 4, + pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DIN, + pctrl->gpio_bank[id].base + NPCM8XX_GP_N_DOUT, + NULL, + NULL, + pctrl->gpio_bank[id].base + NPCM8XX_GP_N_IEM, + BGPIOF_READ_OUTPUT_REG_SET); + if (ret) + return dev_err_probe(dev, ret, "bgpio_init() failed\n"); + + ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args); + if (ret < 0) + return dev_err_probe(dev, ret, "gpio-ranges fail for GPIO bank %u\n", id); + + ret = fwnode_irq_get(child, 0); + if (!ret) + return dev_err_probe(dev, ret, "No IRQ for GPIO bank %u\n", id); + + pctrl->gpio_bank[id].irq = ret; + pctrl->gpio_bank[id].irq_chip = npcmgpio_irqchip; + pctrl->gpio_bank[id].irqbase = id * NPCM8XX_GPIO_PER_BANK; + pctrl->gpio_bank[id].pinctrl_id = args.args[0]; + pctrl->gpio_bank[id].gc.base = -1; + pctrl->gpio_bank[id].gc.ngpio = args.args[2]; + pctrl->gpio_bank[id].gc.owner = THIS_MODULE; + pctrl->gpio_bank[id].gc.parent = dev; + pctrl->gpio_bank[id].gc.fwnode = child; + pctrl->gpio_bank[id].gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); + pctrl->gpio_bank[id].gc.dbg_show = npcmgpio_dbg_show; + pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].gc.direction_input; + pctrl->gpio_bank[id].gc.direction_input = npcmgpio_direction_input; + pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].gc.direction_output; + pctrl->gpio_bank[id].gc.direction_output = npcmgpio_direction_output; + pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].gc.request; + pctrl->gpio_bank[id].gc.request = npcmgpio_gpio_request; + pctrl->gpio_bank[id].gc.free = npcmgpio_gpio_free; + for (i = 0 ; i < NPCM8XX_DEBOUNCE_MAX ; i++) + pctrl->gpio_bank[id].debounce.set_val[i] = false; + pctrl->gpio_bank[id].gc.add_pin_ranges = npcmgpio_add_pin_ranges; + id++; + } + + pctrl->bank_num = id; + return ret; +} + +static int npcm8xx_gpio_register(struct npcm8xx_pinctrl *pctrl) +{ + int ret, id; + + for (id = 0 ; id < pctrl->bank_num ; id++) { + struct gpio_irq_chip *girq; + + girq = &pctrl->gpio_bank[id].gc.irq; + girq->chip = &pctrl->gpio_bank[id].irq_chip; + girq->parent_handler = npcmgpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(pctrl->dev, girq->num_parents, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + + girq->parents[0] = pctrl->gpio_bank[id].irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + ret = devm_gpiochip_add_data(pctrl->dev, + &pctrl->gpio_bank[id].gc, + &pctrl->gpio_bank[id]); + if (ret) + return dev_err_probe(pctrl->dev, ret, "Failed to add GPIO chip %u\n", id); + } + + return 0; +} + +static int npcm8xx_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct npcm8xx_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->dev = dev; + platform_set_drvdata(pdev, pctrl); + + pctrl->gcr_regmap = + syscon_regmap_lookup_by_phandle(dev->of_node, "nuvoton,sysgcr"); + if (IS_ERR(pctrl->gcr_regmap)) + return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap), + "Failed to find nuvoton,sysgcr property\n"); + + ret = npcm8xx_gpio_fw(pctrl); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to gpio dt-binding\n"); + + pctrl->pctldev = devm_pinctrl_register(dev, &npcm8xx_pinctrl_desc, pctrl); + if (IS_ERR(pctrl->pctldev)) + return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), + "Failed to register pinctrl device\n"); + + ret = npcm8xx_gpio_register(pctrl); + if (ret < 0) + dev_err_probe(dev, ret, "Failed to register gpio\n"); + + return 0; +} + +static const struct of_device_id npcm8xx_pinctrl_match[] = { + { .compatible = "nuvoton,npcm845-pinctrl" }, + { } +}; +MODULE_DEVICE_TABLE(of, npcm8xx_pinctrl_match); + +static struct platform_driver npcm8xx_pinctrl_driver = { + .probe = npcm8xx_pinctrl_probe, + .driver = { + .name = "npcm8xx-pinctrl", + .of_match_table = npcm8xx_pinctrl_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init npcm8xx_pinctrl_register(void) +{ + return platform_driver_register(&npcm8xx_pinctrl_driver); +} +arch_initcall(npcm8xx_pinctrl_register); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("[email protected]"); +MODULE_DESCRIPTION("Nuvoton NPCM8XX Pinctrl and GPIO driver"); diff --git a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c index 2d1c1652cfd9..6e88ef1ed020 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c +++ b/drivers/pinctrl/nuvoton/pinctrl-wpcm450.c @@ -858,16 +858,6 @@ static int wpcm450_get_group_pins(struct pinctrl_dev *pctldev, return 0; } -static int wpcm450_dt_node_to_map(struct pinctrl_dev *pctldev, - struct device_node *np_config, - struct pinctrl_map **map, - u32 *num_maps) -{ - return pinconf_generic_dt_node_to_map(pctldev, np_config, - map, num_maps, - PIN_MAP_TYPE_INVALID); -} - static void wpcm450_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, u32 num_maps) { @@ -878,7 +868,7 @@ static const struct pinctrl_ops wpcm450_pinctrl_ops = { .get_groups_count = wpcm450_get_groups_count, .get_group_name = wpcm450_get_group_name, .get_group_pins = wpcm450_get_group_pins, - .dt_node_to_map = wpcm450_dt_node_to_map, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, .dt_free_map = wpcm450_dt_free_map, }; diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 58ca6fac7849..fae80b52a6fc 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1346,9 +1346,7 @@ static int cy8c95x0_probe(struct i2c_client *client) chip->dev = &client->dev; /* Set the device type */ - chip->driver_data = (unsigned long)device_get_match_data(&client->dev); - if (!chip->driver_data) - chip->driver_data = i2c_match_id(cy8c95x0_id, client)->driver_data; + chip->driver_data = (uintptr_t)i2c_get_match_data(client); if (!chip->driver_data) return -ENODEV; diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 461a7c02d4a3..68dc94da777a 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -239,32 +239,32 @@ static struct lock_class_key pcs_request_class; * does not help in this case. */ -static unsigned __maybe_unused pcs_readb(void __iomem *reg) +static unsigned int pcs_readb(void __iomem *reg) { return readb(reg); } -static unsigned __maybe_unused pcs_readw(void __iomem *reg) +static unsigned int pcs_readw(void __iomem *reg) { return readw(reg); } -static unsigned __maybe_unused pcs_readl(void __iomem *reg) +static unsigned int pcs_readl(void __iomem *reg) { return readl(reg); } -static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) +static void pcs_writeb(unsigned int val, void __iomem *reg) { writeb(val, reg); } -static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) +static void pcs_writew(unsigned int val, void __iomem *reg) { writew(val, reg); } -static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) +static void pcs_writel(unsigned int val, void __iomem *reg) { writel(val, reg); } diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index fef1ee7b7945..fd0331a87cda 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -1116,7 +1116,6 @@ static const struct regmap_config sx150x_regmap_config = { static int sx150x_probe(struct i2c_client *client) { - const struct i2c_device_id *id = i2c_client_get_device_id(client); static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA; struct device *dev = &client->dev; @@ -1135,11 +1134,7 @@ static int sx150x_probe(struct i2c_client *client) pctl->dev = dev; pctl->client = client; - if (dev->of_node) - pctl->data = of_device_get_match_data(dev); - else - pctl->data = (struct sx150x_device_data *)id->driver_data; - + pctl->data = i2c_get_match_data(client); if (!pctl->data) return -EINVAL; diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 2a180a5d64a4..301fe0157b02 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -173,10 +173,8 @@ static int pin_request(struct pinctrl_dev *pctldev, else status = 0; - if (status) { - dev_err(pctldev->dev, "request() failed for pin %d\n", pin); + if (status) module_put(pctldev->owner); - } out_free_pin: if (status) { diff --git a/drivers/pinctrl/qcom/pinctrl-msm8996.c b/drivers/pinctrl/qcom/pinctrl-msm8996.c index 46cc0b49dbab..1b5d80eaab83 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8996.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8996.c @@ -1880,6 +1880,18 @@ static const struct msm_pingroup msm8996_groups[] = { SDC_QDSD_PINGROUP(sdc1_rclk, 0x12c000, 15, 0), }; +static const struct msm_gpio_wakeirq_map msm8996_mpm_map[] = { + { 1, 3 }, { 5, 4 }, { 9, 5 }, { 11, 6 }, { 66, 7 }, { 22, 8 }, { 24, 9 }, { 26, 10 }, + { 34, 11 }, { 36, 12 }, { 37, 13 }, { 38, 14 }, { 40, 15 }, { 42, 16 }, { 46, 17 }, + { 50, 18 }, { 53, 19 }, { 54, 20 }, { 56, 21 }, { 57, 22 }, { 58, 23 }, { 59, 24 }, + { 60, 25 }, { 61, 26 }, { 62, 27 }, { 63, 28 }, { 64, 29 }, { 71, 30 }, { 73, 31 }, + { 77, 32 }, { 78, 33 }, { 79, 34 }, { 80, 35 }, { 82, 36 }, { 86, 37 }, { 91, 38 }, + { 92, 39 }, { 95, 40 }, { 97, 41 }, { 101, 42 }, { 104, 43 }, { 106, 44 }, { 108, 45 }, + { 112, 46 }, { 113, 47 }, { 110, 48 }, { 127, 50 }, { 115, 51 }, { 116, 54 }, { 117, 55 }, + { 118, 56 }, { 119, 57 }, { 120, 58 }, { 121, 59 }, { 122, 60 }, { 123, 61 }, { 124, 62 }, + { 125, 63 }, { 126, 64 }, { 129, 65 }, { 131, 66 }, { 132, 67 }, { 133, 68 }, { 145, 69 }, +}; + static const struct msm_pinctrl_soc_data msm8996_pinctrl = { .pins = msm8996_pins, .npins = ARRAY_SIZE(msm8996_pins), @@ -1888,6 +1900,8 @@ static const struct msm_pinctrl_soc_data msm8996_pinctrl = { .groups = msm8996_groups, .ngroups = ARRAY_SIZE(msm8996_groups), .ngpios = 150, + .wakeirq_map = msm8996_mpm_map, + .nwakeirq_map = ARRAY_SIZE(msm8996_mpm_map), }; static int msm8996_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660.c b/drivers/pinctrl/qcom/pinctrl-sdm660.c index c2e0d5c034ac..907e4ffca5e7 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm660.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm660.c @@ -1399,6 +1399,18 @@ static const struct msm_pingroup sdm660_groups[] = { SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0), }; +static const struct msm_gpio_wakeirq_map sdm660_mpm_map[] = { + { 1, 3 }, { 5, 4 }, { 9, 5 }, { 10, 6 }, { 66, 7 }, { 22, 8 }, { 25, 9 }, { 28, 10 }, + { 58, 11 }, { 41, 13 }, { 43, 14 }, { 40, 15 }, { 42, 16 }, { 46, 17 }, { 50, 18 }, + { 44, 19 }, { 56, 21 }, { 45, 22 }, { 68, 23 }, { 69, 24 }, { 70, 25 }, { 71, 26 }, + { 72, 27 }, { 73, 28 }, { 64, 29 }, { 2, 30 }, { 13, 31 }, { 111, 32 }, { 74, 33 }, + { 75, 34 }, { 76, 35 }, { 82, 36 }, { 17, 37 }, { 77, 38 }, { 47, 39 }, { 54, 40 }, + { 48, 41 }, { 101, 42 }, { 49, 43 }, { 51, 44 }, { 86, 45 }, { 90, 46 }, { 91, 47 }, + { 52, 48 }, { 55, 50 }, { 6, 51 }, { 65, 53 }, { 67, 55 }, { 83, 56 }, { 84, 57 }, + { 85, 58 }, { 87, 59 }, { 21, 63 }, { 78, 64 }, { 113, 65 }, { 60, 66 }, { 98, 67 }, + { 30, 68 }, { 31, 70 }, { 29, 71 }, { 107, 76 }, { 109, 83 }, { 103, 84 }, { 105, 85 }, +}; + static const struct msm_pinctrl_soc_data sdm660_pinctrl = { .pins = sdm660_pins, .npins = ARRAY_SIZE(sdm660_pins), @@ -1409,6 +1421,8 @@ static const struct msm_pinctrl_soc_data sdm660_pinctrl = { .ngpios = 114, .tiles = sdm660_tiles, .ntiles = ARRAY_SIZE(sdm660_tiles), + .wakeirq_map = sdm660_mpm_map, + .nwakeirq_map = ARRAY_SIZE(sdm660_mpm_map), }; static int sdm660_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115.c b/drivers/pinctrl/qcom/pinctrl-sm6115.c index 2a06025f4885..4e91c75ad952 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115.c @@ -867,6 +867,16 @@ static const struct msm_pingroup sm6115_groups[] = { [120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0), }; +static const struct msm_gpio_wakeirq_map sm6115_mpm_map[] = { + { 0, 84 }, { 3, 75 }, { 4, 16 }, { 6, 59 }, { 8, 63 }, { 11, 17 }, { 13, 18 }, + { 14, 51 }, { 17, 20 }, { 18, 52 }, { 19, 53 }, { 24, 6 }, { 25, 71 }, { 27, 73 }, + { 28, 41 }, { 31, 27 }, { 32, 54 }, { 33, 55 }, { 34, 56 }, { 35, 57 }, { 36, 58 }, + { 39, 28 }, { 46, 29 }, { 62, 60 }, { 63, 61 }, { 64, 62 }, { 65, 30 }, { 66, 31 }, + { 67, 32 }, { 69, 33 }, { 70, 34 }, { 72, 72 }, { 75, 35 }, { 79, 36 }, { 80, 21 }, + { 81, 38 }, { 83, 9 }, { 84, 39 }, { 85, 40 }, { 86, 19 }, { 87, 42 }, { 88, 43 }, + { 89, 45 }, { 91, 74 }, { 93, 46 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, { 97, 50 }, +}; + static const struct msm_pinctrl_soc_data sm6115_tlmm = { .pins = sm6115_pins, .npins = ARRAY_SIZE(sm6115_pins), @@ -877,6 +887,8 @@ static const struct msm_pinctrl_soc_data sm6115_tlmm = { .ngpios = 114, .tiles = sm6115_tiles, .ntiles = ARRAY_SIZE(sm6115_tiles), + .wakeirq_map = sm6115_mpm_map, + .nwakeirq_map = ARRAY_SIZE(sm6115_mpm_map), }; static int sm6115_tlmm_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c index d5e2b896954c..c188842047aa 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6125.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -1221,6 +1221,21 @@ static const struct msm_pingroup sm6125_groups[] = { [140] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x58b000, 9, 0), }; +static const struct msm_gpio_wakeirq_map sm6125_mpm_map[] = { + { 1, 14 }, { 3, 15 }, { 4, 16 }, { 9, 17 }, { 13, 18 }, { 14, 23 }, + { 15, 19 }, { 17, 20 }, { 19, 21 }, { 21, 22 }, { 22, 84 }, { 25, 24 }, + { 26, 25 }, { 27, 26 }, { 29, 27 }, { 33, 28 }, { 36, 29 }, { 42, 30 }, + { 43, 5 }, { 44, 31 }, { 45, 6 }, { 47, 32 }, { 50, 33 }, { 59, 7 }, + { 70, 34 }, { 72, 8 }, { 75, 35 }, { 79, 36 }, { 80, 37 }, { 81, 38 }, + { 82, 39 }, { 83, 9 }, { 85, 40 }, { 86, 41 }, { 88, 42 }, { 89, 43 }, + { 91, 44 }, { 92, 45 }, { 93, 46 }, { 94, 47 }, { 95, 48 }, { 96, 49 }, + { 97, 70 }, { 98, 50 }, { 99, 51 }, { 100, 64 }, { 101, 52 }, + { 102, 53 }, { 105, 54 }, { 107, 55 }, { 110, 56 }, { 111, 57 }, + { 112, 58 }, { 118, 59 }, { 120, 71 }, { 122, 60 }, { 123, 61 }, + { 124, 13 }, { 126, 62 }, { 128, 63 }, { 130, 65 }, { 131, 66 }, + { 132, 67 }, +}; + static const struct msm_pinctrl_soc_data sm6125_tlmm = { .pins = sm6125_pins, .npins = ARRAY_SIZE(sm6125_pins), @@ -1231,6 +1246,8 @@ static const struct msm_pinctrl_soc_data sm6125_tlmm = { .ngpios = 134, .tiles = sm6125_tiles, .ntiles = ARRAY_SIZE(sm6125_tiles), + .wakeirq_map = sm6125_mpm_map, + .nwakeirq_map = ARRAY_SIZE(sm6125_mpm_map), }; static int sm6125_tlmm_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/realtek/Kconfig b/drivers/pinctrl/realtek/Kconfig new file mode 100644 index 000000000000..0fc6bd4fcb7e --- /dev/null +++ b/drivers/pinctrl/realtek/Kconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config PINCTRL_RTD + tristate "Realtek DHC core pin controller driver" + depends on ARCH_REALTEK + default y + select PINMUX + select GENERIC_PINCONF + +config PINCTRL_RTD1619B + tristate "Realtek DHC 1619B pin controller driver" + depends on PINCTRL_RTD + default y + +config PINCTRL_RTD1319D + tristate "Realtek DHC 1319D pin controller driver" + depends on PINCTRL_RTD + default y + +config PINCTRL_RTD1315E + tristate "Realtek DHC 1315E pin controller driver" + depends on PINCTRL_RTD + default y diff --git a/drivers/pinctrl/realtek/Makefile b/drivers/pinctrl/realtek/Makefile new file mode 100644 index 000000000000..c7bace0001e9 --- /dev/null +++ b/drivers/pinctrl/realtek/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Realtek DHC pin control drivers +obj-$(CONFIG_PINCTRL_RTD) += pinctrl-rtd.o +obj-$(CONFIG_PINCTRL_RTD1619B) += pinctrl-rtd1619b.o +obj-$(CONFIG_PINCTRL_RTD1319D) += pinctrl-rtd1319d.o +obj-$(CONFIG_PINCTRL_RTD1315E) += pinctrl-rtd1315e.o diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c new file mode 100644 index 000000000000..bafe27face80 --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd.c @@ -0,0 +1,580 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC pin controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + */ + +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/seq_file.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-rtd.h" + +struct rtd_pinctrl { + struct device *dev; + struct pinctrl_dev *pcdev; + void __iomem *base; + struct pinctrl_desc desc; + const struct rtd_pinctrl_desc *info; + struct regmap *regmap_pinctrl; +}; + +/* custom pinconf parameters */ +#define RTD_DRIVE_STRENGH_P (PIN_CONFIG_END + 1) +#define RTD_DRIVE_STRENGH_N (PIN_CONFIG_END + 2) +#define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3) + +static const struct pinconf_generic_params rtd_custom_bindings[] = { + {"realtek,drive-strength-p", RTD_DRIVE_STRENGH_P, 0}, + {"realtek,drive-strength-n", RTD_DRIVE_STRENGH_N, 0}, + {"realtek,duty-cycle", RTD_DUTY_CYCLE, 0}, +}; + +static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + return data->info->num_groups; +} + +static const char *rtd_pinctrl_get_group_name(struct pinctrl_dev *pcdev, + unsigned int selector) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + return data->info->groups[selector].name; +} + +static int rtd_pinctrl_get_group_pins(struct pinctrl_dev *pcdev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + *pins = data->info->groups[selector].pins; + *num_pins = data->info->groups[selector].num_pins; + + return 0; +} + +static void rtd_pinctrl_dbg_show(struct pinctrl_dev *pcdev, + struct seq_file *s, + unsigned int offset) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const struct rtd_pin_desc *mux = &data->info->muxes[offset]; + const struct rtd_pin_mux_desc *func; + u32 val; + u32 mask; + u32 pin_val; + int is_map; + + if (!mux->name) { + seq_puts(s, "[not defined]"); + return; + } + val = readl_relaxed(data->base + mux->mux_offset); + mask = mux->mux_mask; + pin_val = val & mask; + + is_map = 0; + func = &mux->functions[0]; + seq_puts(s, "function: "); + while (func->name) { + if (func->mux_value == pin_val) { + is_map = 1; + seq_printf(s, "[%s] ", func->name); + } else { + seq_printf(s, "%s ", func->name); + } + func++; + } + if (!is_map) + seq_puts(s, "[not defined]"); +} + +static const struct pinctrl_ops rtd_pinctrl_ops = { + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, + .get_groups_count = rtd_pinctrl_get_groups_count, + .get_group_name = rtd_pinctrl_get_group_name, + .get_group_pins = rtd_pinctrl_get_group_pins, + .pin_dbg_show = rtd_pinctrl_dbg_show, +}; + +static int rtd_pinctrl_get_functions_count(struct pinctrl_dev *pcdev) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + return data->info->num_functions; +} + +static const char *rtd_pinctrl_get_function_name(struct pinctrl_dev *pcdev, + unsigned int selector) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + return data->info->functions[selector].name; +} + +static int rtd_pinctrl_get_function_groups(struct pinctrl_dev *pcdev, + unsigned int selector, + const char * const **groups, + unsigned int * const num_groups) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + + *groups = data->info->functions[selector].groups; + *num_groups = data->info->functions[selector].num_groups; + + return 0; +} + +static const struct rtd_pin_desc *rtd_pinctrl_find_mux(struct rtd_pinctrl *data, unsigned int pin) +{ + if (!data->info->muxes[pin].name) + return &data->info->muxes[pin]; + + return NULL; +} + +static int rtd_pinctrl_set_one_mux(struct pinctrl_dev *pcdev, + unsigned int pin, const char *func_name) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const struct rtd_pin_desc *mux; + int ret = 0; + int i; + + mux = rtd_pinctrl_find_mux(data, pin); + if (!mux) + return 0; + + if (!mux->functions) { + dev_err(pcdev->dev, "No functions available for pin %s\n", mux->name); + return -ENOTSUPP; + } + + for (i = 0; mux->functions[i].name; i++) { + if (strcmp(mux->functions[i].name, func_name) != 0) + continue; + ret = regmap_update_bits(data->regmap_pinctrl, mux->mux_offset, mux->mux_mask, + mux->functions[i].mux_value); + return ret; + } + + dev_err(pcdev->dev, "No function %s available for pin %s\n", func_name, mux->name); + + return -EINVAL; +} + +static int rtd_pinctrl_set_mux(struct pinctrl_dev *pcdev, + unsigned int function, unsigned int group) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const unsigned int *pins; + unsigned int num_pins; + const char *func_name; + const char *group_name; + int i, ret; + + func_name = data->info->functions[function].name; + group_name = data->info->groups[group].name; + + ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins); + if (ret) { + dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name); + return ret; + } + + for (i = 0; i < num_pins; i++) { + ret = rtd_pinctrl_set_one_mux(pcdev, pins[i], func_name); + if (ret) + return ret; + } + + return 0; +} + +static int rtd_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + return rtd_pinctrl_set_one_mux(pcdev, offset, "gpio"); +} + +static const struct pinmux_ops rtd_pinmux_ops = { + .get_functions_count = rtd_pinctrl_get_functions_count, + .get_function_name = rtd_pinctrl_get_function_name, + .get_function_groups = rtd_pinctrl_get_function_groups, + .set_mux = rtd_pinctrl_set_mux, + .gpio_request_enable = rtd_pinctrl_gpio_request_enable, +}; + +static const struct pinctrl_pin_desc + *rtd_pinctrl_get_pin_by_number(struct rtd_pinctrl *data, int number) +{ + int i; + + for (i = 0; i < data->info->num_pins; i++) { + if (data->info->pins[i].number == number) + return &data->info->pins[i]; + } + + return NULL; +} + +static const struct rtd_pin_config_desc + *rtd_pinctrl_find_config(struct rtd_pinctrl *data, unsigned int pin) +{ + if (!data->info->configs[pin].name) + return &data->info->configs[pin]; + + return NULL; +} + +static const struct rtd_pin_sconfig_desc *rtd_pinctrl_find_sconfig(struct rtd_pinctrl *data, + unsigned int pin) +{ + int i; + const struct pinctrl_pin_desc *pin_desc; + const char *pin_name; + + pin_desc = rtd_pinctrl_get_pin_by_number(data, pin); + if (!pin_desc) + return NULL; + + pin_name = pin_desc->name; + + for (i = 0; i < data->info->num_sconfigs; i++) { + if (strcmp(data->info->sconfigs[i].name, pin_name) == 0) + return &data->info->sconfigs[i]; + } + + return NULL; +} + +static int rtd_pconf_parse_conf(struct rtd_pinctrl *data, + unsigned int pinnr, + enum pin_config_param param, + enum pin_config_param arg) +{ + const struct rtd_pin_config_desc *config_desc; + const struct rtd_pin_sconfig_desc *sconfig_desc; + u8 set_val = 0; + u16 strength; + u32 val; + u32 mask; + u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off; + const char *name = data->info->pins[pinnr].name; + int ret = 0; + + config_desc = rtd_pinctrl_find_config(data, pinnr); + if (!config_desc) { + dev_err(data->dev, "Not support pin config for pin: %s\n", name); + return -ENOTSUPP; + } + switch ((u32)param) { + case PIN_CONFIG_INPUT_SCHMITT: + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (config_desc->smt_offset == NA) { + dev_err(data->dev, "Not support input schmitt for pin: %s\n", name); + return -ENOTSUPP; + } + smt_off = config_desc->base_bit + config_desc->smt_offset; + reg_off = config_desc->reg_offset; + set_val = arg; + + mask = BIT(smt_off); + val = set_val ? BIT(smt_off) : 0; + break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (config_desc->pud_en_offset == NA) { + dev_err(data->dev, "Not support push pull for pin: %s\n", name); + return -ENOTSUPP; + } + pulen_off = config_desc->base_bit + config_desc->pud_en_offset; + reg_off = config_desc->reg_offset; + + mask = BIT(pulen_off); + val = 0; + break; + + case PIN_CONFIG_BIAS_DISABLE: + if (config_desc->pud_en_offset == NA) { + dev_err(data->dev, "Not support bias disable for pin: %s\n", name); + return -ENOTSUPP; + } + pulen_off = config_desc->base_bit + config_desc->pud_en_offset; + reg_off = config_desc->reg_offset; + + mask = BIT(pulen_off); + val = 0; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if (config_desc->pud_en_offset == NA) { + dev_err(data->dev, "Not support bias pull up for pin:%s\n", name); + return -ENOTSUPP; + } + pulen_off = config_desc->base_bit + config_desc->pud_en_offset; + pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset; + reg_off = config_desc->reg_offset; + + mask = BIT(pulen_off) | BIT(pulsel_off); + val = mask; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (config_desc->pud_en_offset == NA) { + dev_err(data->dev, "Not support bias pull down for pin: %s\n", name); + return -ENOTSUPP; + } + pulen_off = config_desc->base_bit + config_desc->pud_en_offset; + pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset; + reg_off = config_desc->reg_offset; + + mask = BIT(pulen_off) | BIT(pulsel_off); + val = BIT(pulen_off); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + curr_off = config_desc->base_bit + config_desc->curr_offset; + reg_off = config_desc->reg_offset; + strength = arg; + val = 0; + switch (config_desc->curr_type) { + case PADDRI_4_8: + if (strength == 4) + val = 0; + else if (strength == 8) + val = BIT(curr_off); + else + return -EINVAL; + break; + case PADDRI_2_4: + if (strength == 2) + val = 0; + else if (strength == 4) + val = BIT(curr_off); + else + return -EINVAL; + break; + case NA: + dev_err(data->dev, "Not support drive strength for pin: %s\n", name); + return -ENOTSUPP; + default: + return -EINVAL; + } + mask = BIT(curr_off); + break; + + case PIN_CONFIG_POWER_SOURCE: + if (config_desc->power_offset == NA) { + dev_err(data->dev, "Not support power source for pin: %s\n", name); + return -ENOTSUPP; + } + reg_off = config_desc->reg_offset; + pow_off = config_desc->base_bit + config_desc->power_offset; + if (pow_off >= 32) { + reg_off += 0x4; + pow_off -= 32; + } + set_val = arg; + mask = BIT(pow_off); + val = set_val ? mask : 0; + break; + + case RTD_DRIVE_STRENGH_P: + sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); + if (!sconfig_desc) { + dev_err(data->dev, "Not support P driving for pin: %s\n", name); + return -ENOTSUPP; + } + set_val = arg; + reg_off = sconfig_desc->reg_offset; + p_off = sconfig_desc->pdrive_offset; + if (p_off >= 32) { + reg_off += 0x4; + p_off -= 32; + } + mask = GENMASK(p_off + sconfig_desc->pdrive_maskbits - 1, p_off); + val = set_val << p_off; + break; + + case RTD_DRIVE_STRENGH_N: + sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); + if (!sconfig_desc) { + dev_err(data->dev, "Not support N driving for pin: %s\n", name); + return -ENOTSUPP; + } + set_val = arg; + reg_off = sconfig_desc->reg_offset; + n_off = sconfig_desc->ndrive_offset; + if (n_off >= 32) { + reg_off += 0x4; + n_off -= 32; + } + mask = GENMASK(n_off + sconfig_desc->ndrive_maskbits - 1, n_off); + val = set_val << n_off; + break; + + case RTD_DUTY_CYCLE: + sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr); + if (!sconfig_desc || sconfig_desc->dcycle_offset == NA) { + dev_err(data->dev, "Not support duty cycle for pin: %s\n", name); + return -ENOTSUPP; + } + set_val = arg; + reg_off = config_desc->reg_offset; + mask = GENMASK(sconfig_desc->dcycle_offset + + sconfig_desc->dcycle_maskbits - 1, sconfig_desc->dcycle_offset); + val = set_val << sconfig_desc->dcycle_offset; + break; + + default: + dev_err(data->dev, "unsupported pinconf: %d\n", (u32)param); + return -EINVAL; + } + + ret = regmap_update_bits(data->regmap_pinctrl, reg_off, mask, val); + if (ret) + dev_err(data->dev, "could not update pinconf(%d) for pin(%s)\n", (u32)param, name); + + return ret; +} + +static int rtd_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr, + unsigned long *config) +{ + unsigned int param = pinconf_to_config_param(*config); + unsigned int arg = 0; + + switch (param) { + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int rtd_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr, + unsigned long *configs, unsigned int num_configs) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + int i; + int ret = 0; + + for (i = 0; i < num_configs; i++) { + ret = rtd_pconf_parse_conf(data, pinnr, + pinconf_to_config_param(configs[i]), + pinconf_to_config_argument(configs[i])); + if (ret < 0) + return ret; + } + + return 0; +} + +static int rtd_pin_config_group_set(struct pinctrl_dev *pcdev, unsigned int group, + unsigned long *configs, unsigned int num_configs) +{ + struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev); + const unsigned int *pins; + unsigned int num_pins; + const char *group_name; + int i, ret; + + group_name = data->info->groups[group].name; + + ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins); + if (ret) { + dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name); + return ret; + } + + for (i = 0; i < num_pins; i++) { + ret = rtd_pin_config_set(pcdev, pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static const struct pinconf_ops rtd_pinconf_ops = { + .is_generic = true, + .pin_config_get = rtd_pin_config_get, + .pin_config_set = rtd_pin_config_set, + .pin_config_group_set = rtd_pin_config_group_set, +}; + +static struct regmap_config rtd_pinctrl_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .use_relaxed_mmio = true, +}; + +int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc) +{ + struct rtd_pinctrl *data; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->base = of_iomap(pdev->dev.of_node, 0); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + + data->dev = &pdev->dev; + data->info = desc; + data->desc.name = dev_name(&pdev->dev); + data->desc.pins = data->info->pins; + data->desc.npins = data->info->num_pins; + data->desc.pctlops = &rtd_pinctrl_ops; + data->desc.pmxops = &rtd_pinmux_ops; + data->desc.confops = &rtd_pinconf_ops; + data->desc.custom_params = rtd_custom_bindings; + data->desc.num_custom_params = ARRAY_SIZE(rtd_custom_bindings); + data->desc.owner = THIS_MODULE; + data->regmap_pinctrl = devm_regmap_init_mmio(data->dev, data->base, + &rtd_pinctrl_regmap_config); + + if (IS_ERR(data->regmap_pinctrl)) { + dev_err(data->dev, "failed to init regmap: %ld\n", + PTR_ERR(data->regmap_pinctrl)); + return PTR_ERR(data->regmap_pinctrl); + } + + data->pcdev = pinctrl_register(&data->desc, &pdev->dev, data); + if (!data->pcdev) + return -ENOMEM; + + platform_set_drvdata(pdev, data); + + dev_dbg(&pdev->dev, "probed\n"); + + return 0; +} +EXPORT_SYMBOL(rtd_pinctrl_probe); + +MODULE_DESCRIPTION("Realtek DHC SoC pinctrl driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.h b/drivers/pinctrl/realtek/pinctrl-rtd.h new file mode 100644 index 000000000000..e15130896abc --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023 Realtek Semiconductor Corp. + */ + +#define NA 0xffffffff +#define PADDRI_4_8 1 +#define PADDRI_2_4 0 + +struct rtd_pin_group_desc { + const char *name; + const unsigned int *pins; + unsigned int num_pins; +}; + +struct rtd_pin_func_desc { + const char *name; + const char * const *groups; + unsigned int num_groups; +}; + +struct rtd_pin_mux_desc { + const char *name; + u32 mux_value; +}; + +struct rtd_pin_config_desc { + const char *name; + unsigned int reg_offset; + unsigned int base_bit; + unsigned int pud_en_offset; + unsigned int pud_sel_offset; + unsigned int curr_offset; + unsigned int smt_offset; + unsigned int power_offset; + unsigned int curr_type; +}; + +struct rtd_pin_sconfig_desc { + const char *name; + unsigned int reg_offset; + unsigned int dcycle_offset; + unsigned int dcycle_maskbits; + unsigned int ndrive_offset; + unsigned int ndrive_maskbits; + unsigned int pdrive_offset; + unsigned int pdrive_maskbits; +}; + +struct rtd_pin_desc { + const char *name; + unsigned int mux_offset; + u32 mux_mask; + const struct rtd_pin_mux_desc *functions; +}; + +struct rtd_pin_reg_list { + unsigned int reg_offset; + unsigned int val; +}; + +#define SHIFT_LEFT(_val, _shift) ((_val) << (_shift)) + +#define RTK_PIN_MUX(_name, _mux_off, _mux_mask, ...) \ + { \ + .name = # _name, \ + .mux_offset = _mux_off, \ + .mux_mask = _mux_mask, \ + .functions = (const struct rtd_pin_mux_desc []) { \ + __VA_ARGS__, { } \ + }, \ + } + +#define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \ + _pud_sel_off, _curr_off, _smt_off, _pow_off, _curr_type) \ + { \ + .name = # _name, \ + .reg_offset = _reg_off, \ + .base_bit = _base_bit, \ + .pud_en_offset = _pud_en_off, \ + .pud_sel_offset = _pud_sel_off, \ + .curr_offset = _curr_off, \ + .smt_offset = _smt_off, \ + .power_offset = _pow_off, \ + .curr_type = _curr_type, \ + } + +#define RTK_PIN_SCONFIG(_name, _reg_off, _d_offset, _d_mask, \ + _n_offset, _n_mask, _p_offset, _p_mask) \ + { \ + .name = # _name, \ + .reg_offset = _reg_off, \ + .dcycle_offset = _d_offset, \ + .dcycle_maskbits = _d_mask, \ + .ndrive_offset = _n_offset, \ + .ndrive_maskbits = _n_mask, \ + .pdrive_offset = _p_offset, \ + .pdrive_maskbits = _p_mask, \ + } + +#define RTK_PIN_FUNC(_mux_val, _name) \ + { \ + .name = _name, \ + .mux_value = _mux_val, \ + } + +struct rtd_pinctrl_desc { + const struct pinctrl_pin_desc *pins; + unsigned int num_pins; + const struct rtd_pin_group_desc *groups; + unsigned int num_groups; + const struct rtd_pin_func_desc *functions; + unsigned int num_functions; + const struct rtd_pin_desc *muxes; + unsigned int num_muxes; + const struct rtd_pin_config_desc *configs; + unsigned int num_configs; + const struct rtd_pin_sconfig_desc *sconfigs; + unsigned int num_sconfigs; + struct rtd_pin_reg_list *lists; + unsigned int num_regs; +}; + +int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1315e.c b/drivers/pinctrl/realtek/pinctrl-rtd1315e.c new file mode 100644 index 000000000000..5ab35d73e6f4 --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd1315e.c @@ -0,0 +1,1439 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC 1315E pin controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + * + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-rtd.h" + +enum rtd13xxe_iso_pins { + RTD1315E_ISO_GPIO_0 = 0, + RTD1315E_ISO_GPIO_1, + RTD1315E_ISO_EMMC_RST_N, + RTD1315E_ISO_EMMC_DD_SB, + RTD1315E_ISO_EMMC_CLK, + RTD1315E_ISO_EMMC_CMD, + RTD1315E_ISO_GPIO_6, + RTD1315E_ISO_GPIO_7, + RTD1315E_ISO_GPIO_8, + RTD1315E_ISO_GPIO_9, + RTD1315E_ISO_GPIO_10, + RTD1315E_ISO_GPIO_11, + RTD1315E_ISO_GPIO_12, + RTD1315E_ISO_GPIO_13, + RTD1315E_ISO_GPIO_14, + RTD1315E_ISO_GPIO_15, + RTD1315E_ISO_GPIO_16, + RTD1315E_ISO_GPIO_17, + RTD1315E_ISO_GPIO_18, + RTD1315E_ISO_GPIO_19, + RTD1315E_ISO_GPIO_20, + RTD1315E_ISO_EMMC_DATA_0, + RTD1315E_ISO_EMMC_DATA_1, + RTD1315E_ISO_EMMC_DATA_2, + RTD1315E_ISO_USB_CC2, + RTD1315E_ISO_GPIO_25, + RTD1315E_ISO_GPIO_26, + RTD1315E_ISO_GPIO_27, + RTD1315E_ISO_GPIO_28, + RTD1315E_ISO_GPIO_29, + RTD1315E_ISO_GPIO_30, + RTD1315E_ISO_GPIO_31, + RTD1315E_ISO_GPIO_32, + RTD1315E_ISO_GPIO_33, + RTD1315E_ISO_GPIO_34, + RTD1315E_ISO_GPIO_35, + RTD1315E_ISO_HIF_DATA, + RTD1315E_ISO_HIF_EN, + RTD1315E_ISO_HIF_RDY, + RTD1315E_ISO_HIF_CLK, + RTD1315E_ISO_GPIO_DUMMY_40, + RTD1315E_ISO_GPIO_DUMMY_41, + RTD1315E_ISO_GPIO_DUMMY_42, + RTD1315E_ISO_GPIO_DUMMY_43, + RTD1315E_ISO_GPIO_DUMMY_44, + RTD1315E_ISO_GPIO_DUMMY_45, + RTD1315E_ISO_GPIO_46, + RTD1315E_ISO_GPIO_47, + RTD1315E_ISO_GPIO_48, + RTD1315E_ISO_GPIO_49, + RTD1315E_ISO_GPIO_50, + RTD1315E_ISO_USB_CC1, + RTD1315E_ISO_EMMC_DATA_3, + RTD1315E_ISO_EMMC_DATA_4, + RTD1315E_ISO_IR_RX, + RTD1315E_ISO_UR0_RX, + RTD1315E_ISO_UR0_TX, + RTD1315E_ISO_GPIO_57, + RTD1315E_ISO_GPIO_58, + RTD1315E_ISO_GPIO_59, + RTD1315E_ISO_GPIO_60, + RTD1315E_ISO_GPIO_61, + RTD1315E_ISO_GPIO_62, + RTD1315E_ISO_GPIO_DUMMY_63, + RTD1315E_ISO_GPIO_DUMMY_64, + RTD1315E_ISO_GPIO_DUMMY_65, + RTD1315E_ISO_GPIO_66, + RTD1315E_ISO_GPIO_67, + RTD1315E_ISO_GPIO_68, + RTD1315E_ISO_GPIO_69, + RTD1315E_ISO_GPIO_70, + RTD1315E_ISO_GPIO_71, + RTD1315E_ISO_GPIO_72, + RTD1315E_ISO_GPIO_DUMMY_73, + RTD1315E_ISO_EMMC_DATA_5, + RTD1315E_ISO_EMMC_DATA_6, + RTD1315E_ISO_EMMC_DATA_7, + RTD1315E_ISO_GPIO_DUMMY_77, + RTD1315E_ISO_GPIO_78, + RTD1315E_ISO_GPIO_79, + RTD1315E_ISO_GPIO_80, + RTD1315E_ISO_GPIO_81, + RTD1315E_ISO_UR2_LOC, + RTD1315E_ISO_GSPI_LOC, + RTD1315E_ISO_HI_WIDTH, + RTD1315E_ISO_SF_EN, + RTD1315E_ISO_ARM_TRACE_DBG_EN, + RTD1315E_ISO_EJTAG_AUCPU_LOC, + RTD1315E_ISO_EJTAG_ACPU_LOC, + RTD1315E_ISO_EJTAG_VCPU_LOC, + RTD1315E_ISO_EJTAG_SCPU_LOC, + RTD1315E_ISO_DMIC_LOC, + RTD1315E_ISO_VTC_DMIC_LOC, + RTD1315E_ISO_VTC_TDM_LOC, + RTD1315E_ISO_VTC_I2SI_LOC, + RTD1315E_ISO_TDM_AI_LOC, + RTD1315E_ISO_AI_LOC, + RTD1315E_ISO_SPDIF_LOC, + RTD1315E_ISO_HIF_EN_LOC, + RTD1315E_ISO_SCAN_SWITCH, + RTD1315E_ISO_WD_RSET, + RTD1315E_ISO_BOOT_SEL, + RTD1315E_ISO_RESET_N, + RTD1315E_ISO_TESTMODE, +}; + +static const struct pinctrl_pin_desc rtd1315e_iso_pins[] = { + PINCTRL_PIN(RTD1315E_ISO_GPIO_0, "gpio_0"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_1, "gpio_1"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_RST_N, "emmc_rst_n"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DD_SB, "emmc_dd_sb"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_CLK, "emmc_clk"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_CMD, "emmc_cmd"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_6, "gpio_6"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_7, "gpio_7"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_8, "gpio_8"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_9, "gpio_9"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_10, "gpio_10"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_11, "gpio_11"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_12, "gpio_12"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_13, "gpio_13"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_14, "gpio_14"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_15, "gpio_15"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_16, "gpio_16"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_17, "gpio_17"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_18, "gpio_18"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_19, "gpio_19"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_20, "gpio_20"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_0, "emmc_data_0"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_1, "emmc_data_1"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_2, "emmc_data_2"), + PINCTRL_PIN(RTD1315E_ISO_USB_CC2, "usb_cc2"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_25, "gpio_25"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_26, "gpio_26"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_27, "gpio_27"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_28, "gpio_28"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_29, "gpio_29"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_30, "gpio_30"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_31, "gpio_31"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_32, "gpio_32"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_33, "gpio_33"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_34, "gpio_34"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_35, "gpio_35"), + PINCTRL_PIN(RTD1315E_ISO_HIF_DATA, "hif_data"), + PINCTRL_PIN(RTD1315E_ISO_HIF_EN, "hif_en"), + PINCTRL_PIN(RTD1315E_ISO_HIF_RDY, "hif_rdy"), + PINCTRL_PIN(RTD1315E_ISO_HIF_CLK, "hif_clk"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_40, "gpio_dummy_40"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_41, "gpio_dummy_41"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_42, "gpio_dummy_42"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_43, "gpio_dummy_43"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_44, "gpio_dummy_44"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_45, "gpio_dummy_45"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_46, "gpio_46"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_47, "gpio_47"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_48, "gpio_48"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_49, "gpio_49"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_50, "gpio_50"), + PINCTRL_PIN(RTD1315E_ISO_USB_CC1, "usb_cc1"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_3, "emmc_data_3"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_4, "emmc_data_4"), + PINCTRL_PIN(RTD1315E_ISO_IR_RX, "ir_rx"), + PINCTRL_PIN(RTD1315E_ISO_UR0_RX, "ur0_rx"), + PINCTRL_PIN(RTD1315E_ISO_UR0_TX, "ur0_tx"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_57, "gpio_57"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_58, "gpio_58"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_59, "gpio_59"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_60, "gpio_60"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_61, "gpio_61"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_62, "gpio_62"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_63, "gpio_dummy_63"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_64, "gpio_dummy_64"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_65, "gpio_dummy_65"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_66, "gpio_66"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_67, "gpio_67"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_68, "gpio_68"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_69, "gpio_69"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_70, "gpio_70"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_71, "gpio_71"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_72, "gpio_72"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_73, "gpio_dummy_73"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_5, "emmc_data_5"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_6, "emmc_data_6"), + PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_7, "emmc_data_7"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_77, "gpio_dummy_77"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_78, "gpio_78"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_79, "gpio_79"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_80, "gpio_80"), + PINCTRL_PIN(RTD1315E_ISO_GPIO_81, "gpio_81"), + PINCTRL_PIN(RTD1315E_ISO_UR2_LOC, "ur2_loc"), + PINCTRL_PIN(RTD1315E_ISO_GSPI_LOC, "gspi_loc"), + PINCTRL_PIN(RTD1315E_ISO_HI_WIDTH, "hi_width"), + PINCTRL_PIN(RTD1315E_ISO_SF_EN, "sf_en"), + PINCTRL_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"), + PINCTRL_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, "ejtag_aucpu_loc"), + PINCTRL_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"), + PINCTRL_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"), + PINCTRL_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), + PINCTRL_PIN(RTD1315E_ISO_DMIC_LOC, "dmic_loc"), + PINCTRL_PIN(RTD1315E_ISO_VTC_DMIC_LOC, "vtc_dmic_loc"), + PINCTRL_PIN(RTD1315E_ISO_VTC_TDM_LOC, "vtc_tdm_loc"), + PINCTRL_PIN(RTD1315E_ISO_VTC_I2SI_LOC, "vtc_i2si_loc"), + PINCTRL_PIN(RTD1315E_ISO_TDM_AI_LOC, "tdm_ai_loc"), + PINCTRL_PIN(RTD1315E_ISO_AI_LOC, "ai_loc"), + PINCTRL_PIN(RTD1315E_ISO_SPDIF_LOC, "spdif_loc"), + PINCTRL_PIN(RTD1315E_ISO_HIF_EN_LOC, "hif_en_loc"), + PINCTRL_PIN(RTD1315E_ISO_SCAN_SWITCH, "scan_switch"), + PINCTRL_PIN(RTD1315E_ISO_WD_RSET, "wd_rset"), + PINCTRL_PIN(RTD1315E_ISO_BOOT_SEL, "boot_sel"), + PINCTRL_PIN(RTD1315E_ISO_RESET_N, "reset_n"), + PINCTRL_PIN(RTD1315E_ISO_TESTMODE, "testmode"), +}; + +#define DECLARE_RTD1315E_PIN(_pin, _name) \ + static const unsigned int rtd1315e_## _name ##_pins[] = { _pin } + +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_0, gpio_0); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_1, gpio_1); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_RST_N, emmc_rst_n); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DD_SB, emmc_dd_sb); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CLK, emmc_clk); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CMD, emmc_cmd); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_6, gpio_6); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_7, gpio_7); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_8, gpio_8); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_9, gpio_9); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_10, gpio_10); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_11, gpio_11); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_12, gpio_12); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_13, gpio_13); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_14, gpio_14); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_15, gpio_15); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_16, gpio_16); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_17, gpio_17); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_18, gpio_18); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_19, gpio_19); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_20, gpio_20); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_0, emmc_data_0); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_1, emmc_data_1); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_2, emmc_data_2); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC2, usb_cc2); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_25, gpio_25); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_26, gpio_26); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_27, gpio_27); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_28, gpio_28); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_29, gpio_29); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_30, gpio_30); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_31, gpio_31); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_32, gpio_32); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_33, gpio_33); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_34, gpio_34); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_35, gpio_35); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_DATA, hif_data); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN, hif_en); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_RDY, hif_rdy); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_CLK, hif_clk); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_40, gpio_dummy_40); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_41, gpio_dummy_41); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_42, gpio_dummy_42); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_43, gpio_dummy_43); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_44, gpio_dummy_44); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_45, gpio_dummy_45); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_46, gpio_46); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_47, gpio_47); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_48, gpio_48); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_49, gpio_49); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_50, gpio_50); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC1, usb_cc1); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_3, emmc_data_3); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_4, emmc_data_4); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_IR_RX, ir_rx); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_RX, ur0_rx); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_TX, ur0_tx); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_57, gpio_57); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_58, gpio_58); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_59, gpio_59); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_60, gpio_60); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_61, gpio_61); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_62, gpio_62); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_63, gpio_dummy_63); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_64, gpio_dummy_64); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_65, gpio_dummy_65); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_66, gpio_66); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_67, gpio_67); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_68, gpio_68); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_69, gpio_69); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_70, gpio_70); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_71, gpio_71); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_72, gpio_72); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_73, gpio_dummy_73); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_5, emmc_data_5); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_6, emmc_data_6); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_7, emmc_data_7); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_77, gpio_dummy_77); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_78, gpio_78); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_79, gpio_79); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_80, gpio_80); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_81, gpio_81); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR2_LOC, ur2_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_GSPI_LOC, gspi_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HI_WIDTH, hi_width); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_SF_EN, sf_en); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, ejtag_aucpu_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_DMIC_LOC, dmic_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_DMIC_LOC, vtc_dmic_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_TDM_LOC, vtc_tdm_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_I2SI_LOC, vtc_i2si_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_TDM_AI_LOC, tdm_ai_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_AI_LOC, ai_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_SPDIF_LOC, spdif_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN_LOC, hif_en_loc); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_SCAN_SWITCH, scan_switch); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_WD_RSET, wd_rset); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_BOOT_SEL, boot_sel); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_RESET_N, reset_n); +DECLARE_RTD1315E_PIN(RTD1315E_ISO_TESTMODE, testmode); + +#define RTD1315E_GROUP(_name) \ + { \ + .name = # _name, \ + .pins = rtd1315e_ ## _name ## _pins, \ + .num_pins = ARRAY_SIZE(rtd1315e_ ## _name ## _pins), \ + } + +static const struct rtd_pin_group_desc rtd1315e_pin_groups[] = { + RTD1315E_GROUP(gpio_0), + RTD1315E_GROUP(gpio_1), + RTD1315E_GROUP(emmc_rst_n), + RTD1315E_GROUP(emmc_dd_sb), + RTD1315E_GROUP(emmc_clk), + RTD1315E_GROUP(emmc_cmd), + RTD1315E_GROUP(gpio_6), + RTD1315E_GROUP(gpio_7), + RTD1315E_GROUP(gpio_8), + RTD1315E_GROUP(gpio_9), + RTD1315E_GROUP(gpio_10), + RTD1315E_GROUP(gpio_11), + RTD1315E_GROUP(gpio_12), + RTD1315E_GROUP(gpio_13), + RTD1315E_GROUP(gpio_14), + RTD1315E_GROUP(gpio_15), + RTD1315E_GROUP(gpio_16), + RTD1315E_GROUP(gpio_17), + RTD1315E_GROUP(gpio_18), + RTD1315E_GROUP(gpio_19), + RTD1315E_GROUP(gpio_20), + RTD1315E_GROUP(emmc_data_0), + RTD1315E_GROUP(emmc_data_1), + RTD1315E_GROUP(emmc_data_2), + RTD1315E_GROUP(usb_cc2), + RTD1315E_GROUP(gpio_25), + RTD1315E_GROUP(gpio_26), + RTD1315E_GROUP(gpio_27), + RTD1315E_GROUP(gpio_28), + RTD1315E_GROUP(gpio_29), + RTD1315E_GROUP(gpio_30), + RTD1315E_GROUP(gpio_31), + RTD1315E_GROUP(gpio_32), + RTD1315E_GROUP(gpio_33), + RTD1315E_GROUP(gpio_34), + RTD1315E_GROUP(gpio_35), + RTD1315E_GROUP(hif_data), + RTD1315E_GROUP(hif_en), + RTD1315E_GROUP(hif_rdy), + RTD1315E_GROUP(hif_clk), + RTD1315E_GROUP(gpio_dummy_40), + RTD1315E_GROUP(gpio_dummy_41), + RTD1315E_GROUP(gpio_dummy_42), + RTD1315E_GROUP(gpio_dummy_43), + RTD1315E_GROUP(gpio_dummy_44), + RTD1315E_GROUP(gpio_dummy_45), + RTD1315E_GROUP(gpio_46), + RTD1315E_GROUP(gpio_47), + RTD1315E_GROUP(gpio_48), + RTD1315E_GROUP(gpio_49), + RTD1315E_GROUP(gpio_50), + RTD1315E_GROUP(usb_cc1), + RTD1315E_GROUP(emmc_data_3), + RTD1315E_GROUP(emmc_data_4), + RTD1315E_GROUP(ir_rx), + RTD1315E_GROUP(ur0_rx), + RTD1315E_GROUP(ur0_tx), + RTD1315E_GROUP(gpio_57), + RTD1315E_GROUP(gpio_58), + RTD1315E_GROUP(gpio_59), + RTD1315E_GROUP(gpio_60), + RTD1315E_GROUP(gpio_61), + RTD1315E_GROUP(gpio_62), + RTD1315E_GROUP(gpio_dummy_63), + RTD1315E_GROUP(gpio_dummy_64), + RTD1315E_GROUP(gpio_dummy_65), + RTD1315E_GROUP(gpio_66), + RTD1315E_GROUP(gpio_67), + RTD1315E_GROUP(gpio_68), + RTD1315E_GROUP(gpio_69), + RTD1315E_GROUP(gpio_70), + RTD1315E_GROUP(gpio_71), + RTD1315E_GROUP(gpio_72), + RTD1315E_GROUP(gpio_dummy_73), + RTD1315E_GROUP(emmc_data_5), + RTD1315E_GROUP(emmc_data_6), + RTD1315E_GROUP(emmc_data_7), + RTD1315E_GROUP(gpio_dummy_77), + RTD1315E_GROUP(gpio_78), + RTD1315E_GROUP(gpio_79), + RTD1315E_GROUP(gpio_80), + RTD1315E_GROUP(gpio_81), + RTD1315E_GROUP(ur2_loc), + RTD1315E_GROUP(gspi_loc), + RTD1315E_GROUP(hi_width), + RTD1315E_GROUP(sf_en), + RTD1315E_GROUP(arm_trace_dbg_en), + RTD1315E_GROUP(ejtag_aucpu_loc), + RTD1315E_GROUP(ejtag_acpu_loc), + RTD1315E_GROUP(ejtag_vcpu_loc), + RTD1315E_GROUP(ejtag_scpu_loc), + RTD1315E_GROUP(dmic_loc), + RTD1315E_GROUP(vtc_dmic_loc), + RTD1315E_GROUP(vtc_tdm_loc), + RTD1315E_GROUP(vtc_i2si_loc), + RTD1315E_GROUP(tdm_ai_loc), + RTD1315E_GROUP(ai_loc), + RTD1315E_GROUP(spdif_loc), + RTD1315E_GROUP(hif_en_loc), + +}; + +static const char * const rtd1315e_gpio_groups[] = { + "gpio_0", "gpio_1", "emmc_rst_n", "emmc_dd_sb", "emmc_clk", + "emmc_cmd", "gpio_6", "gpio_7", "gpio_8", "gpio_9", + "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14", + "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19", + "gpio_20", "emmc_data_0", "emmc_data_1", "emmc_data_2", "usb_cc2", + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29", + "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", + "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "gpio_46", "gpio_47", "gpio_48", "gpio_49", + "gpio_50", "usb_cc1", "emmc_data_3", "emmc_data_4", "ir_rx", + "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "gpio_61", "gpio_62", "gpio_66", "gpio_67", + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1315e_nf_groups[] = { + "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0", + "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1315e_emmc_groups[] = { + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7" }; + +static const char * const rtd1315e_ao_groups[] = { + "gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70", + "gpio_71", "gpio_72" }; +static const char * const rtd1315e_gspi_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" }; +static const char * const rtd1315e_gspi_loc1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" }; +static const char * const rtd1315e_uart0_groups[] = { "ur0_rx", "ur0_tx"}; +static const char * const rtd1315e_uart1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11" }; +static const char * const rtd1315e_uart2_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" }; +static const char * const rtd1315e_uart2_loc1_groups[] = { + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" }; +static const char * const rtd1315e_i2c0_groups[] = { "gpio_12", "gpio_13" }; +static const char * const rtd1315e_i2c1_groups[] = { "gpio_16", "gpio_17" }; +static const char * const rtd1315e_i2c4_groups[] = { "gpio_34", "gpio_35" }; +static const char * const rtd1315e_i2c5_groups[] = { "gpio_29", "gpio_46" }; +static const char * const rtd1315e_pcie1_groups[] = { "gpio_25" }; +static const char * const rtd1315e_etn_led_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1315e_etn_phy_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1315e_spi_groups[] = { + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1315e_pwm0_loc0_groups[] = { "gpio_26" }; +static const char * const rtd1315e_pwm0_loc1_groups[] = { "gpio_20" }; +static const char * const rtd1315e_pwm1_loc0_groups[] = { "gpio_27" }; +static const char * const rtd1315e_pwm1_loc1_groups[] = { "gpio_29" }; + +static const char * const rtd1315e_pwm2_loc0_groups[] = { "gpio_28" }; +static const char * const rtd1315e_pwm2_loc1_groups[] = { "gpio_30" }; +static const char * const rtd1315e_pwm3_loc0_groups[] = { "gpio_47" }; +static const char * const rtd1315e_pwm3_loc1_groups[] = { "gpio_31" }; +static const char * const rtd1315e_spdif_optical_loc0_groups[] = { "gpio_20", "spdif_loc" }; +static const char * const rtd1315e_spdif_optical_loc1_groups[] = { "gpio_6", "spdif_loc" }; +static const char * const rtd1315e_usb_cc1_groups[] = { "usb_cc1" }; +static const char * const rtd1315e_usb_cc2_groups[] = { "usb_cc2" }; + +static const char * const rtd1315e_sd_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1315e_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_1", "gpio_6", "dmic_loc" }; +static const char * const rtd1315e_dmic_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "dmic_loc" }; +static const char * const rtd1315e_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_1", "ai_loc" }; +static const char * const rtd1315e_ai_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "hif_data", + "hif_en", "hif_rdy", "hif_clk", "ai_loc" }; +static const char * const rtd1315e_tdm_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "tdm_ai_loc" }; +static const char * const rtd1315e_tdm_ai_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", "tdm_ai_loc" }; +static const char * const rtd1315e_hi_loc0_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1315e_hi_m_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1315e_vtc_i2so_groups[] = { + "gpio_67", "gpio_68", "gpio_69", "gpio_70"}; +static const char * const rtd1315e_vtc_i2si_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "vtc_i2si_loc" }; +static const char * const rtd1315e_vtc_i2si_loc1_groups[] = { + "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_i2si_loc" }; +static const char * const rtd1315e_vtc_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", + "vtc_dmic_loc" }; +static const char * const rtd1315e_vtc_dmic_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_dmic_loc" }; +static const char * const rtd1315e_vtc_tdm_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", + "vtc_tdm_loc" }; +static const char * const rtd1315e_vtc_tdm_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_tdm_loc" }; +static const char * const rtd1315e_dc_fan_groups[] = { "gpio_47" }; +static const char * const rtd1315e_pll_test_loc0_groups[] = { "gpio_0", "gpio_1" }; +static const char * const rtd1315e_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" }; +static const char * const rtd1315e_spdif_groups[] = { "gpio_50" }; +static const char * const rtd1315e_ir_rx_groups[] = { "ir_rx" }; +static const char * const rtd1315e_uart2_disable_groups[] = { "ur2_loc" }; +static const char * const rtd1315e_gspi_disable_groups[] = { "gspi_loc" }; +static const char * const rtd1315e_hi_width_disable_groups[] = { "hi_width" }; +static const char * const rtd1315e_hi_width_1bit_groups[] = { "hi_width" }; +static const char * const rtd1315e_sf_disable_groups[] = { "sf_en" }; +static const char * const rtd1315e_sf_enable_groups[] = { "sf_en" }; +static const char * const rtd1315e_scpu_ejtag_loc0_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "ejtag_scpu_loc" }; +static const char * const rtd1315e_scpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_scpu_loc" }; +static const char * const rtd1315e_scpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_scpu_loc" }; +static const char * const rtd1315e_scpu_ejtag_loc3_groups[] = { + "hif_data" }; +static const char * const rtd1315e_acpu_ejtag_loc0_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "ejtag_acpu_loc" }; +static const char * const rtd1315e_acpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_acpu_loc" }; +static const char * const rtd1315e_acpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_acpu_loc" }; +static const char * const rtd1315e_vcpu_ejtag_loc0_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "ejtag_vcpu_loc" }; +static const char * const rtd1315e_vcpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_vcpu_loc" }; +static const char * const rtd1315e_vcpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_vcpu_loc" }; +static const char * const rtd1315e_aucpu_ejtag_loc0_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72", + "ejtag_aucpu_loc" }; +static const char * const rtd1315e_aucpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_aucpu_loc" }; +static const char * const rtd1315e_aucpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_aucpu_loc" }; +static const char * const rtd1315e_gpu_ejtag_groups[] = { + "gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72" }; + +static const char * const rtd1315e_iso_tristate_groups[] = { + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_1", "gpio_7", "gpio_8", "gpio_9", "gpio_10", + "gpio_11", "usb_cc2", "gpio_32", "gpio_33", "hif_data", + "hif_en", "hif_rdy", "hif_clk", "ir_rx", "ur0_rx", + "ur0_tx", "gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70", + "gpio_71", "gpio_72", "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1315e_dbg_out0_groups[] = { + "gpio_0", "gpio_12", "gpio_13", "gpio_16", "gpio_17", "gpio_26", + "gpio_27", "gpio_28", "gpio_29", "gpio_30", "gpio_34", "gpio_35", + "gpio_46", "gpio_48", "gpio_49", "usb_cc1", "gpio_57", "gpio_58", "gpio_59", "gpio_60" }; +static const char * const rtd1315e_dbg_out1_groups[] = { + "gpio_6", "gpio_14", "gpio_15", "gpio_18", "gpio_19", "gpio_20", + "gpio_25", "gpio_31", "gpio_47", "gpio_50", "gpio_59", "gpio_61", + "gpio_62" }; +static const char * const rtd1315e_standby_dbg_groups[] = { + "gpio_1", "gpio_6", "ir_rx" }; +static const char * const rtd1315e_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1315e_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1315e_aucpu_ejtag_disable_groups[] = { "ejtag_aucpu_loc" }; +static const char * const rtd1315e_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" }; +static const char * const rtd1315e_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" }; +static const char * const rtd1315e_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" }; +static const char * const rtd1315e_vtc_dmic_loc_disable_groups[] = { "vtc_dmic_loc" }; +static const char * const rtd1315e_vtc_tdm_disable_groups[] = { "vtc_tdm_loc" }; +static const char * const rtd1315e_vtc_i2si_disable_groups[] = { "vtc_i2si_loc" }; +static const char * const rtd1315e_tdm_ai_disable_groups[] = { "tdm_ai_loc" }; +static const char * const rtd1315e_ai_disable_groups[] = { "ai_loc" }; +static const char * const rtd1315e_spdif_disable_groups[] = { "spdif_loc" }; +static const char * const rtd1315e_hif_disable_groups[] = { "hif_en_loc" }; +static const char * const rtd1315e_hif_enable_groups[] = { "hif_en_loc" }; +static const char * const rtd1315e_test_loop_groups[] = { "gpio_50" }; +static const char * const rtd1315e_pmic_pwrup_groups[] = { "gpio_78" }; + +#define RTD1315E_FUNC(_name) \ + { \ + .name = # _name, \ + .groups = rtd1315e_ ## _name ## _groups, \ + .num_groups = ARRAY_SIZE(rtd1315e_ ## _name ## _groups), \ + } + +static const struct rtd_pin_func_desc rtd1315e_pin_functions[] = { + RTD1315E_FUNC(gpio), + RTD1315E_FUNC(nf), + RTD1315E_FUNC(emmc), + RTD1315E_FUNC(ao), + RTD1315E_FUNC(gspi_loc0), + RTD1315E_FUNC(gspi_loc1), + RTD1315E_FUNC(uart0), + RTD1315E_FUNC(uart1), + RTD1315E_FUNC(uart2_loc0), + RTD1315E_FUNC(uart2_loc1), + RTD1315E_FUNC(i2c0), + RTD1315E_FUNC(i2c1), + RTD1315E_FUNC(i2c4), + RTD1315E_FUNC(i2c5), + RTD1315E_FUNC(pcie1), + RTD1315E_FUNC(etn_led), + RTD1315E_FUNC(etn_phy), + RTD1315E_FUNC(spi), + RTD1315E_FUNC(pwm0_loc0), + RTD1315E_FUNC(pwm0_loc1), + RTD1315E_FUNC(pwm1_loc0), + RTD1315E_FUNC(pwm1_loc1), + RTD1315E_FUNC(pwm2_loc0), + RTD1315E_FUNC(pwm2_loc1), + RTD1315E_FUNC(pwm3_loc0), + RTD1315E_FUNC(pwm3_loc1), + RTD1315E_FUNC(spdif_optical_loc0), + RTD1315E_FUNC(spdif_optical_loc1), + RTD1315E_FUNC(usb_cc1), + RTD1315E_FUNC(usb_cc2), + RTD1315E_FUNC(sd), + RTD1315E_FUNC(dmic_loc0), + RTD1315E_FUNC(dmic_loc1), + RTD1315E_FUNC(ai_loc0), + RTD1315E_FUNC(ai_loc1), + RTD1315E_FUNC(tdm_ai_loc0), + RTD1315E_FUNC(tdm_ai_loc1), + RTD1315E_FUNC(hi_loc0), + RTD1315E_FUNC(hi_m), + RTD1315E_FUNC(vtc_i2so), + RTD1315E_FUNC(vtc_i2si_loc0), + RTD1315E_FUNC(vtc_i2si_loc1), + RTD1315E_FUNC(vtc_dmic_loc0), + RTD1315E_FUNC(vtc_dmic_loc1), + RTD1315E_FUNC(vtc_tdm_loc0), + RTD1315E_FUNC(vtc_tdm_loc1), + RTD1315E_FUNC(dc_fan), + RTD1315E_FUNC(pll_test_loc0), + RTD1315E_FUNC(pll_test_loc1), + RTD1315E_FUNC(ir_rx), + RTD1315E_FUNC(uart2_disable), + RTD1315E_FUNC(gspi_disable), + RTD1315E_FUNC(hi_width_disable), + RTD1315E_FUNC(hi_width_1bit), + RTD1315E_FUNC(sf_disable), + RTD1315E_FUNC(sf_enable), + RTD1315E_FUNC(scpu_ejtag_loc0), + RTD1315E_FUNC(scpu_ejtag_loc1), + RTD1315E_FUNC(scpu_ejtag_loc2), + RTD1315E_FUNC(scpu_ejtag_loc3), + RTD1315E_FUNC(acpu_ejtag_loc0), + RTD1315E_FUNC(acpu_ejtag_loc1), + RTD1315E_FUNC(acpu_ejtag_loc2), + RTD1315E_FUNC(vcpu_ejtag_loc0), + RTD1315E_FUNC(vcpu_ejtag_loc1), + RTD1315E_FUNC(vcpu_ejtag_loc2), + RTD1315E_FUNC(aucpu_ejtag_loc0), + RTD1315E_FUNC(aucpu_ejtag_loc1), + RTD1315E_FUNC(aucpu_ejtag_loc2), + RTD1315E_FUNC(gpu_ejtag), + RTD1315E_FUNC(iso_tristate), + RTD1315E_FUNC(dbg_out0), + RTD1315E_FUNC(dbg_out1), + RTD1315E_FUNC(standby_dbg), + RTD1315E_FUNC(spdif), + RTD1315E_FUNC(arm_trace_debug_disable), + RTD1315E_FUNC(arm_trace_debug_enable), + RTD1315E_FUNC(aucpu_ejtag_disable), + RTD1315E_FUNC(acpu_ejtag_disable), + RTD1315E_FUNC(vcpu_ejtag_disable), + RTD1315E_FUNC(scpu_ejtag_disable), + RTD1315E_FUNC(vtc_dmic_loc_disable), + RTD1315E_FUNC(vtc_tdm_disable), + RTD1315E_FUNC(vtc_i2si_disable), + RTD1315E_FUNC(tdm_ai_disable), + RTD1315E_FUNC(ai_disable), + RTD1315E_FUNC(spdif_disable), + RTD1315E_FUNC(hif_disable), + RTD1315E_FUNC(hif_enable), + RTD1315E_FUNC(test_loop), + RTD1315E_FUNC(pmic_pwrup), +}; + +#undef RTD1315E_FUNC + +static const struct rtd_pin_desc rtd1315e_iso_muxes[ARRAY_SIZE(rtd1315e_iso_pins)] = { + [RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), + [RTD1315E_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "spdif_optical_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1315E_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1315E_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x8, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1315E_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x8, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), + [RTD1315E_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), + [RTD1315E_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1315E_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1315E_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0xc, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1315E_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0xc, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1315E_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0xc, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1315E_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0xc, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), + [RTD1315E_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0xc, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm0_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1315E_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0xc, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "usb_cc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcie1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1315E_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "pwm0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), + + [RTD1315E_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x10, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "pwm1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1315E_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x10, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "pwm2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1315E_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x10, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "pwm1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1315E_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x10, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pwm2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")), + [RTD1315E_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x10, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm3_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1315E_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x10, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x10, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1315E_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x10, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 28), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), + + [RTD1315E_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x14, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1315E_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x14, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc3"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x14, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 8), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x14, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x14, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x14, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), + [RTD1315E_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "dc_fan"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "pwm3_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1315E_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), + + [RTD1315E_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x18, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1315E_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x18, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "spdif"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "test_loop"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out1")), + [RTD1315E_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x18, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "usb_cc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1315E_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x18, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ir_rx"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x18, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x18, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x18, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out0")), + [RTD1315E_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x18, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 28), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")), + + [RTD1315E_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x1c, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 0), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")), + [RTD1315E_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x1c, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1315E_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x1c, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1315E_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x1c, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), + [RTD1315E_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x1c, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x1c, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 20), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x1c, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1315E_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x1c, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1315E_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x20, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1315E_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x20, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1315E_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x20, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "gpu_ejtag"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1315E_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x20, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "pmic_pwrup"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1315E_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x20, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1315E_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x20, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1315E_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x20, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + + [RTD1315E_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")), + [RTD1315E_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")), + [RTD1315E_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")), + [RTD1315E_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")), + [RTD1315E_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")), + [RTD1315E_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "aucpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu_ejtag_loc2")), + [RTD1315E_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")), + [RTD1315E_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")), + [RTD1315E_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")), + [RTD1315E_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")), + + [RTD1315E_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "vtc_dmic_loc_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vtc_dmic_loc1")), + [RTD1315E_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "vtc_tdm_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vtc_tdm_loc1")), + [RTD1315E_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "vtc_i2si_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vtc_i2si_loc1")), + [RTD1315E_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "tdm_ai_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "tdm_ai_loc1")), + [RTD1315E_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "ai_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc1")), + [RTD1315E_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "spdif_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "spdif_optical_loc1")), + + [RTD1315E_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "hif_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "hif_enable")), +}; + +static const struct rtd_pin_config_desc rtd1315e_iso_configs[ARRAY_SIZE(rtd1315e_iso_pins)] = { + [RTD1315E_ISO_BOOT_SEL] = RTK_PIN_CONFIG(boot_sel, 0x24, 0, 0, 1, NA, 2, 3, NA), + [RTD1315E_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x24, 4, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x24, 17, 0, 1, NA, 2, 13, NA), + [RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x28, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x28, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x2c, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x2c, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x30, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x30, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x34, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x34, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x38, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x38, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x3c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x3c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x3c, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x3c, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x3c, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x3c, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x40, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x40, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x40, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x40, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x40, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x40, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x44, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x44, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x44, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x44, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x44, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x44, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x48, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x48, 6, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x48, 12, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x48, 17, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x4c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x4c, 5, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x4c, 18, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x50, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x50, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x50, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x50, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x50, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x50, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x54, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x54, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x54, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x54, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x54, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x54, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x58, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x58, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x58, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_68] = RTK_PIN_CONFIG(gpio_68, 0x58, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_69] = RTK_PIN_CONFIG(gpio_69, 0x58, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_70] = RTK_PIN_CONFIG(gpio_70, 0x58, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_71] = RTK_PIN_CONFIG(gpio_71, 0x5c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_72] = RTK_PIN_CONFIG(gpio_72, 0x5c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_GPIO_78] = RTK_PIN_CONFIG(gpio_78, 0x5c, 10, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_79] = RTK_PIN_CONFIG(gpio_79, 0x60, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x60, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x64, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x64, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x68, 0, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x68, 13, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x68, 26, 0, 1, NA, 2, 12, NA), + [RTD1315E_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x6c, 7, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_RESET_N] = RTK_PIN_CONFIG(reset_n, 0x6c, 12, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1315E_ISO_SCAN_SWITCH] = RTK_PIN_CONFIG(scan_switch, 0x6c, 16, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1315E_ISO_TESTMODE] = RTK_PIN_CONFIG(testmode, 0x6c, 19, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1315E_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x6c, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x6c, 28, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1315E_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x70, 1, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1315E_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x70, 4, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1315E_ISO_WD_RSET] = RTK_PIN_CONFIG(wd_rset, 0x70, 7, 1, 2, 0, 3, 4, PADDRI_4_8), +}; + +static const struct rtd_pin_sconfig_desc rtd1315e_iso_sconfigs[] = { + RTK_PIN_SCONFIG(emmc_clk, 0x24, 7, 3, 10, 3, 13, 3), + RTK_PIN_SCONFIG(emmc_cmd, 0x24, 20, 3, 23, 3, 26, 3), + RTK_PIN_SCONFIG(emmc_data_0, 0x28, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_1, 0x28, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_2, 0x2c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_3, 0x2c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_4, 0x30, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_5, 0x30, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_6, 0x34, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_7, 0x34, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_dd_sb, 0x38, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_rst_n, 0x38, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_32, 0x4c, 8, 3, 11, 3, 14, 3), + RTK_PIN_SCONFIG(gpio_33, 0x4c, 21, 3, 24, 3, 27, 3), + RTK_PIN_SCONFIG(gpio_78, 0x5c, 13, 3, 16, 3, 19, 3), + RTK_PIN_SCONFIG(gpio_79, 0x60, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_80, 0x60, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_81, 0x64, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_clk, 0x64, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(hif_data, 0x68, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_en, 0x68, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(hif_rdy, 0x68, 29, 3, 32, 3, 35, 3), + +}; + +static const struct rtd_pinctrl_desc rtd1315e_iso_pinctrl_desc = { + .pins = rtd1315e_iso_pins, + .num_pins = ARRAY_SIZE(rtd1315e_iso_pins), + .groups = rtd1315e_pin_groups, + .num_groups = ARRAY_SIZE(rtd1315e_pin_groups), + .functions = rtd1315e_pin_functions, + .num_functions = ARRAY_SIZE(rtd1315e_pin_functions), + .muxes = rtd1315e_iso_muxes, + .num_muxes = ARRAY_SIZE(rtd1315e_iso_muxes), + .configs = rtd1315e_iso_configs, + .num_configs = ARRAY_SIZE(rtd1315e_iso_configs), + .sconfigs = rtd1315e_iso_sconfigs, + .num_sconfigs = ARRAY_SIZE(rtd1315e_iso_sconfigs), +}; + +static int rtd1315e_pinctrl_probe(struct platform_device *pdev) +{ + return rtd_pinctrl_probe(pdev, &rtd1315e_iso_pinctrl_desc); +} + +static const struct of_device_id rtd1315e_pinctrl_of_match[] = { + { .compatible = "realtek,rtd1315e-pinctrl", }, + {}, +}; + +static struct platform_driver rtd1315e_pinctrl_driver = { + .driver = { + .name = "rtd1315e-pinctrl", + .of_match_table = rtd1315e_pinctrl_of_match, + }, + .probe = rtd1315e_pinctrl_probe, +}; + +static int __init rtd1315e_pinctrl_init(void) +{ + return platform_driver_register(&rtd1315e_pinctrl_driver); +} +arch_initcall(rtd1315e_pinctrl_init); + +static void __exit rtd1315e_pinctrl_exit(void) +{ + platform_driver_unregister(&rtd1315e_pinctrl_driver); +} +module_exit(rtd1315e_pinctrl_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Realtek Semiconductor Corporation"); +MODULE_DESCRIPTION("Realtek DHC SoC RTD1315E pinctrl driver"); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1319d.c b/drivers/pinctrl/realtek/pinctrl-rtd1319d.c new file mode 100644 index 000000000000..838a447776ba --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd1319d.c @@ -0,0 +1,1609 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC 1319D pin controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + * + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-rtd.h" + +enum rtd13xxd_iso_pins { + RTD1319D_ISO_GPIO_0 = 0, + RTD1319D_ISO_GPIO_1, + RTD1319D_ISO_GPIO_2, + RTD1319D_ISO_GPIO_3, + RTD1319D_ISO_GPIO_4, + RTD1319D_ISO_GPIO_5, + RTD1319D_ISO_GPIO_6, + RTD1319D_ISO_GPIO_7, + RTD1319D_ISO_GPIO_8, + RTD1319D_ISO_GPIO_9, + RTD1319D_ISO_GPIO_10, + RTD1319D_ISO_GPIO_11, + RTD1319D_ISO_GPIO_12, + RTD1319D_ISO_GPIO_13, + RTD1319D_ISO_GPIO_14, + RTD1319D_ISO_GPIO_15, + RTD1319D_ISO_GPIO_16, + RTD1319D_ISO_GPIO_17, + RTD1319D_ISO_GPIO_18, + RTD1319D_ISO_GPIO_19, + RTD1319D_ISO_GPIO_20, + RTD1319D_ISO_GPIO_21, + RTD1319D_ISO_GPIO_22, + RTD1319D_ISO_GPIO_23, + RTD1319D_ISO_USB_CC2, + RTD1319D_ISO_GPIO_25, + RTD1319D_ISO_GPIO_26, + RTD1319D_ISO_GPIO_27, + RTD1319D_ISO_GPIO_28, + RTD1319D_ISO_GPIO_29, + RTD1319D_ISO_GPIO_30, + RTD1319D_ISO_GPIO_31, + RTD1319D_ISO_GPIO_32, + RTD1319D_ISO_GPIO_33, + RTD1319D_ISO_GPIO_34, + RTD1319D_ISO_GPIO_35, + RTD1319D_ISO_HIF_DATA, + RTD1319D_ISO_HIF_EN, + RTD1319D_ISO_HIF_RDY, + RTD1319D_ISO_HIF_CLK, + RTD1319D_ISO_GPIO_40, + RTD1319D_ISO_GPIO_41, + RTD1319D_ISO_GPIO_42, + RTD1319D_ISO_GPIO_43, + RTD1319D_ISO_GPIO_44, + RTD1319D_ISO_GPIO_45, + RTD1319D_ISO_GPIO_46, + RTD1319D_ISO_GPIO_47, + RTD1319D_ISO_GPIO_48, + RTD1319D_ISO_GPIO_49, + RTD1319D_ISO_GPIO_50, + RTD1319D_ISO_USB_CC1, + RTD1319D_ISO_GPIO_52, + RTD1319D_ISO_GPIO_53, + RTD1319D_ISO_IR_RX, + RTD1319D_ISO_UR0_RX, + RTD1319D_ISO_UR0_TX, + RTD1319D_ISO_GPIO_57, + RTD1319D_ISO_GPIO_58, + RTD1319D_ISO_GPIO_59, + RTD1319D_ISO_GPIO_60, + RTD1319D_ISO_GPIO_61, + RTD1319D_ISO_GPIO_62, + RTD1319D_ISO_GPIO_63, + RTD1319D_ISO_GPIO_64, + RTD1319D_ISO_EMMC_RST_N, + RTD1319D_ISO_EMMC_DD_SB, + RTD1319D_ISO_EMMC_CLK, + RTD1319D_ISO_EMMC_CMD, + RTD1319D_ISO_EMMC_DATA_0, + RTD1319D_ISO_EMMC_DATA_1, + RTD1319D_ISO_EMMC_DATA_2, + RTD1319D_ISO_EMMC_DATA_3, + RTD1319D_ISO_EMMC_DATA_4, + RTD1319D_ISO_EMMC_DATA_5, + RTD1319D_ISO_EMMC_DATA_6, + RTD1319D_ISO_EMMC_DATA_7, + RTD1319D_ISO_GPIO_DUMMY_77, + RTD1319D_ISO_GPIO_78, + RTD1319D_ISO_GPIO_79, + RTD1319D_ISO_GPIO_80, + RTD1319D_ISO_GPIO_81, + RTD1319D_ISO_UR2_LOC, + RTD1319D_ISO_GSPI_LOC, + RTD1319D_ISO_HI_WIDTH, + RTD1319D_ISO_SF_EN, + RTD1319D_ISO_ARM_TRACE_DBG_EN, + RTD1319D_ISO_EJTAG_AUCPU_LOC, + RTD1319D_ISO_EJTAG_ACPU_LOC, + RTD1319D_ISO_EJTAG_VCPU_LOC, + RTD1319D_ISO_EJTAG_SCPU_LOC, + RTD1319D_ISO_DMIC_LOC, + RTD1319D_ISO_EJTAG_SECPU_LOC, + RTD1319D_ISO_VTC_DMIC_LOC, + RTD1319D_ISO_VTC_TDM_LOC, + RTD1319D_ISO_VTC_I2SI_LOC, + RTD1319D_ISO_TDM_AI_LOC, + RTD1319D_ISO_AI_LOC, + RTD1319D_ISO_SPDIF_LOC, + RTD1319D_ISO_HIF_EN_LOC, + RTD1319D_ISO_SC0_LOC, + RTD1319D_ISO_SC1_LOC, + RTD1319D_ISO_SCAN_SWITCH, + RTD1319D_ISO_WD_RSET, + RTD1319D_ISO_BOOT_SEL, + RTD1319D_ISO_RESET_N, + RTD1319D_ISO_TESTMODE, +}; + +static const struct pinctrl_pin_desc rtd1319d_iso_pins[] = { + PINCTRL_PIN(RTD1319D_ISO_GPIO_0, "gpio_0"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_1, "gpio_1"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_2, "gpio_2"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_3, "gpio_3"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_4, "gpio_4"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_5, "gpio_5"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_6, "gpio_6"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_7, "gpio_7"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_8, "gpio_8"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_9, "gpio_9"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_10, "gpio_10"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_11, "gpio_11"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_12, "gpio_12"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_13, "gpio_13"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_14, "gpio_14"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_15, "gpio_15"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_16, "gpio_16"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_17, "gpio_17"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_18, "gpio_18"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_19, "gpio_19"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_20, "gpio_20"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_21, "gpio_21"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_22, "gpio_22"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_23, "gpio_23"), + PINCTRL_PIN(RTD1319D_ISO_USB_CC2, "usb_cc2"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_25, "gpio_25"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_26, "gpio_26"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_27, "gpio_27"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_28, "gpio_28"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_29, "gpio_29"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_30, "gpio_30"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_31, "gpio_31"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_32, "gpio_32"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_33, "gpio_33"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_34, "gpio_34"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_35, "gpio_35"), + PINCTRL_PIN(RTD1319D_ISO_HIF_DATA, "hif_data"), + PINCTRL_PIN(RTD1319D_ISO_HIF_EN, "hif_en"), + PINCTRL_PIN(RTD1319D_ISO_HIF_RDY, "hif_rdy"), + PINCTRL_PIN(RTD1319D_ISO_HIF_CLK, "hif_clk"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_40, "gpio_40"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_41, "gpio_41"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_42, "gpio_42"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_43, "gpio_43"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_44, "gpio_44"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_45, "gpio_45"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_46, "gpio_46"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_47, "gpio_47"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_48, "gpio_48"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_49, "gpio_49"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_50, "gpio_50"), + PINCTRL_PIN(RTD1319D_ISO_USB_CC1, "usb_cc1"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_52, "gpio_52"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_53, "gpio_53"), + PINCTRL_PIN(RTD1319D_ISO_IR_RX, "ir_rx"), + PINCTRL_PIN(RTD1319D_ISO_UR0_RX, "ur0_rx"), + PINCTRL_PIN(RTD1319D_ISO_UR0_TX, "ur0_tx"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_57, "gpio_57"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_58, "gpio_58"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_59, "gpio_59"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_60, "gpio_60"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_61, "gpio_61"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_62, "gpio_62"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_63, "gpio_63"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_64, "gpio_64"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_RST_N, "emmc_rst_n"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DD_SB, "emmc_dd_sb"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_CLK, "emmc_clk"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_CMD, "emmc_cmd"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_0, "emmc_data_0"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_1, "emmc_data_1"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_2, "emmc_data_2"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_3, "emmc_data_3"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_4, "emmc_data_4"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_5, "emmc_data_5"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_6, "emmc_data_6"), + PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_7, "emmc_data_7"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_DUMMY_77, "dummy"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_78, "gpio_78"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_79, "gpio_79"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_80, "gpio_80"), + PINCTRL_PIN(RTD1319D_ISO_GPIO_81, "gpio_81"), + PINCTRL_PIN(RTD1319D_ISO_UR2_LOC, "ur2_loc"), + PINCTRL_PIN(RTD1319D_ISO_GSPI_LOC, "gspi_loc"), + PINCTRL_PIN(RTD1319D_ISO_HI_WIDTH, "hi_width"), + PINCTRL_PIN(RTD1319D_ISO_SF_EN, "sf_en"), + PINCTRL_PIN(RTD1319D_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_AUCPU_LOC, "ejtag_aucpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_DMIC_LOC, "dmic_loc"), + PINCTRL_PIN(RTD1319D_ISO_EJTAG_SECPU_LOC, "ejtag_secpu_loc"), + PINCTRL_PIN(RTD1319D_ISO_VTC_DMIC_LOC, "vtc_dmic_loc"), + PINCTRL_PIN(RTD1319D_ISO_VTC_TDM_LOC, "vtc_tdm_loc"), + PINCTRL_PIN(RTD1319D_ISO_VTC_I2SI_LOC, "vtc_i2si_loc"), + PINCTRL_PIN(RTD1319D_ISO_TDM_AI_LOC, "tdm_ai_loc"), + PINCTRL_PIN(RTD1319D_ISO_AI_LOC, "ai_loc"), + PINCTRL_PIN(RTD1319D_ISO_SPDIF_LOC, "spdif_loc"), + PINCTRL_PIN(RTD1319D_ISO_HIF_EN_LOC, "hif_en_loc"), + PINCTRL_PIN(RTD1319D_ISO_SC0_LOC, "sc0_loc"), + PINCTRL_PIN(RTD1319D_ISO_SC1_LOC, "sc1_loc"), + PINCTRL_PIN(RTD1319D_ISO_SCAN_SWITCH, "scan_switch"), + PINCTRL_PIN(RTD1319D_ISO_WD_RSET, "wd_rset"), + PINCTRL_PIN(RTD1319D_ISO_BOOT_SEL, "boot_sel"), + PINCTRL_PIN(RTD1319D_ISO_RESET_N, "reset_n"), + PINCTRL_PIN(RTD1319D_ISO_TESTMODE, "testmode"), +}; + +#define DECLARE_RTD1319D_PIN(_pin, _name) \ + static const unsigned int rtd1319d_## _name ##_pins[] = { _pin } + +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_0, gpio_0); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_1, gpio_1); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_2, gpio_2); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_3, gpio_3); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_4, gpio_4); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_5, gpio_5); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_6, gpio_6); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_7, gpio_7); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_8, gpio_8); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_9, gpio_9); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_10, gpio_10); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_11, gpio_11); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_12, gpio_12); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_13, gpio_13); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_14, gpio_14); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_15, gpio_15); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_16, gpio_16); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_17, gpio_17); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_18, gpio_18); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_19, gpio_19); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_20, gpio_20); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_21, gpio_21); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_22, gpio_22); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_23, gpio_23); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_USB_CC2, usb_cc2); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_25, gpio_25); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_26, gpio_26); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_27, gpio_27); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_28, gpio_28); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_29, gpio_29); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_30, gpio_30); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_31, gpio_31); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_32, gpio_32); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_33, gpio_33); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_34, gpio_34); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_35, gpio_35); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_DATA, hif_data); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_EN, hif_en); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_RDY, hif_rdy); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_CLK, hif_clk); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_40, gpio_40); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_41, gpio_41); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_42, gpio_42); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_43, gpio_43); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_44, gpio_44); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_45, gpio_45); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_46, gpio_46); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_47, gpio_47); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_48, gpio_48); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_49, gpio_49); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_50, gpio_50); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_USB_CC1, usb_cc1); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_52, gpio_52); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_53, gpio_53); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_IR_RX, ir_rx); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR0_RX, ur0_rx); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR0_TX, ur0_tx); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_57, gpio_57); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_58, gpio_58); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_59, gpio_59); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_60, gpio_60); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_61, gpio_61); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_62, gpio_62); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_63, gpio_63); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_64, gpio_64); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_RST_N, emmc_rst_n); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DD_SB, emmc_dd_sb); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_CLK, emmc_clk); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_CMD, emmc_cmd); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_0, emmc_data_0); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_1, emmc_data_1); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_2, emmc_data_2); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_3, emmc_data_3); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_4, emmc_data_4); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_5, emmc_data_5); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_6, emmc_data_6); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_7, emmc_data_7); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_78, gpio_78); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_79, gpio_79); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_80, gpio_80); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_81, gpio_81); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR2_LOC, ur2_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_GSPI_LOC, gspi_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HI_WIDTH, hi_width); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SF_EN, sf_en); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_AUCPU_LOC, ejtag_aucpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_DMIC_LOC, dmic_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_SECPU_LOC, ejtag_secpu_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_DMIC_LOC, vtc_dmic_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_TDM_LOC, vtc_tdm_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_I2SI_LOC, vtc_i2si_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_TDM_AI_LOC, tdm_ai_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_AI_LOC, ai_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SPDIF_LOC, spdif_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_EN_LOC, hif_en_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SC0_LOC, sc0_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SC1_LOC, sc1_loc); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_SCAN_SWITCH, scan_switch); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_WD_RSET, wd_rset); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_BOOT_SEL, boot_sel); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_RESET_N, reset_n); +DECLARE_RTD1319D_PIN(RTD1319D_ISO_TESTMODE, testmode); + +#define RTD1319D_GROUP(_name) \ + { \ + .name = # _name, \ + .pins = rtd1319d_ ## _name ## _pins, \ + .num_pins = ARRAY_SIZE(rtd1319d_ ## _name ## _pins), \ + } + +static const struct rtd_pin_group_desc rtd1319d_pin_groups[] = { + RTD1319D_GROUP(gpio_0), + RTD1319D_GROUP(gpio_1), + RTD1319D_GROUP(gpio_2), + RTD1319D_GROUP(gpio_3), + RTD1319D_GROUP(gpio_4), + RTD1319D_GROUP(gpio_5), + RTD1319D_GROUP(gpio_6), + RTD1319D_GROUP(gpio_7), + RTD1319D_GROUP(gpio_8), + RTD1319D_GROUP(gpio_9), + RTD1319D_GROUP(gpio_10), + RTD1319D_GROUP(gpio_11), + RTD1319D_GROUP(gpio_12), + RTD1319D_GROUP(gpio_13), + RTD1319D_GROUP(gpio_14), + RTD1319D_GROUP(gpio_15), + RTD1319D_GROUP(gpio_16), + RTD1319D_GROUP(gpio_17), + RTD1319D_GROUP(gpio_18), + RTD1319D_GROUP(gpio_19), + RTD1319D_GROUP(gpio_20), + RTD1319D_GROUP(gpio_21), + RTD1319D_GROUP(gpio_22), + RTD1319D_GROUP(gpio_23), + RTD1319D_GROUP(usb_cc2), + RTD1319D_GROUP(gpio_25), + RTD1319D_GROUP(gpio_26), + RTD1319D_GROUP(gpio_27), + RTD1319D_GROUP(gpio_28), + RTD1319D_GROUP(gpio_29), + RTD1319D_GROUP(gpio_30), + RTD1319D_GROUP(gpio_31), + RTD1319D_GROUP(gpio_32), + RTD1319D_GROUP(gpio_33), + RTD1319D_GROUP(gpio_34), + RTD1319D_GROUP(gpio_35), + RTD1319D_GROUP(hif_data), + RTD1319D_GROUP(hif_en), + RTD1319D_GROUP(hif_rdy), + RTD1319D_GROUP(hif_clk), + RTD1319D_GROUP(gpio_40), + RTD1319D_GROUP(gpio_41), + RTD1319D_GROUP(gpio_42), + RTD1319D_GROUP(gpio_43), + RTD1319D_GROUP(gpio_44), + RTD1319D_GROUP(gpio_45), + RTD1319D_GROUP(gpio_46), + RTD1319D_GROUP(gpio_47), + RTD1319D_GROUP(gpio_48), + RTD1319D_GROUP(gpio_49), + RTD1319D_GROUP(gpio_50), + RTD1319D_GROUP(usb_cc1), + RTD1319D_GROUP(gpio_52), + RTD1319D_GROUP(gpio_53), + RTD1319D_GROUP(ir_rx), + RTD1319D_GROUP(ur0_rx), + RTD1319D_GROUP(ur0_tx), + RTD1319D_GROUP(gpio_57), + RTD1319D_GROUP(gpio_58), + RTD1319D_GROUP(gpio_59), + RTD1319D_GROUP(gpio_60), + RTD1319D_GROUP(gpio_61), + RTD1319D_GROUP(gpio_62), + RTD1319D_GROUP(gpio_63), + RTD1319D_GROUP(gpio_64), + RTD1319D_GROUP(emmc_rst_n), + RTD1319D_GROUP(emmc_dd_sb), + RTD1319D_GROUP(emmc_clk), + RTD1319D_GROUP(emmc_cmd), + RTD1319D_GROUP(emmc_data_0), + RTD1319D_GROUP(emmc_data_1), + RTD1319D_GROUP(emmc_data_2), + RTD1319D_GROUP(emmc_data_3), + RTD1319D_GROUP(emmc_data_4), + RTD1319D_GROUP(emmc_data_5), + RTD1319D_GROUP(emmc_data_6), + RTD1319D_GROUP(emmc_data_7), + RTD1319D_GROUP(gpio_78), + RTD1319D_GROUP(gpio_79), + RTD1319D_GROUP(gpio_80), + RTD1319D_GROUP(gpio_81), + RTD1319D_GROUP(ur2_loc), + RTD1319D_GROUP(gspi_loc), + RTD1319D_GROUP(hi_width), + RTD1319D_GROUP(sf_en), + RTD1319D_GROUP(arm_trace_dbg_en), + RTD1319D_GROUP(ejtag_aucpu_loc), + RTD1319D_GROUP(ejtag_acpu_loc), + RTD1319D_GROUP(ejtag_vcpu_loc), + RTD1319D_GROUP(ejtag_scpu_loc), + RTD1319D_GROUP(dmic_loc), + RTD1319D_GROUP(ejtag_secpu_loc), + RTD1319D_GROUP(vtc_dmic_loc), + RTD1319D_GROUP(vtc_tdm_loc), + RTD1319D_GROUP(vtc_i2si_loc), + RTD1319D_GROUP(tdm_ai_loc), + RTD1319D_GROUP(ai_loc), + RTD1319D_GROUP(spdif_loc), + RTD1319D_GROUP(hif_en_loc), + RTD1319D_GROUP(sc0_loc), + RTD1319D_GROUP(sc1_loc), +}; + +static const char * const rtd1319d_gpio_groups[] = { + "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9", + "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14", + "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19", + "gpio_20", "gpio_21", "gpio_22", "gpio_23", "usb_cc2", + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29", + "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", + "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44", + "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", + "gpio_50", "usb_cc1", "gpio_52", "gpio_53", "ir_rx", + "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_64", + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1319d_nf_groups[] = { + "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0", + "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81" }; +static const char * const rtd1319d_emmc_groups[] = { + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7" }; +static const char * const rtd1319d_tp0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_57", "gpio_58", + "gpio_59", "gpio_60", "gpio_61", "gpio_62", "gpio_63", + "gpio_64" }; +static const char * const rtd1319d_tp1_groups[] = { + "gpio_61", "gpio_62", "gpio_63", "gpio_64" }; +static const char * const rtd1319d_sc0_groups[] = { + "gpio_18", "gpio_19", "gpio_31" }; +static const char * const rtd1319d_sc0_data0_groups[] = { "gpio_20", "sc0_loc" }; +static const char * const rtd1319d_sc0_data1_groups[] = { "gpio_30", "sc0_loc" }; +static const char * const rtd1319d_sc0_data2_groups[] = { "gpio_47", "sc0_loc" }; +static const char * const rtd1319d_sc1_groups[] = { + "gpio_2", "gpio_3", "gpio_5" }; +static const char * const rtd1319d_sc1_data0_groups[] = { "gpio_52", "sc1_loc" }; +static const char * const rtd1319d_sc1_data1_groups[] = { "gpio_34", "sc1_loc" }; +static const char * const rtd1319d_sc1_data2_groups[] = { "gpio_35", "sc1_loc" }; +static const char * const rtd1319d_ao_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_61", "gpio_62", + "gpio_63", "gpio_64" }; +static const char * const rtd1319d_gspi_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" }; +static const char * const rtd1319d_gspi_loc1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" }; +static const char * const rtd1319d_uart0_groups[] = { "ur0_rx", "ur0_tx"}; +static const char * const rtd1319d_uart1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11" }; +static const char * const rtd1319d_uart2_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" }; +static const char * const rtd1319d_uart2_loc1_groups[] = { + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" }; +static const char * const rtd1319d_i2c0_groups[] = { "gpio_12", "gpio_13" }; +static const char * const rtd1319d_i2c1_groups[] = { "gpio_16", "gpio_17" }; +static const char * const rtd1319d_i2c3_groups[] = { "gpio_26", "gpio_27" }; +static const char * const rtd1319d_i2c4_groups[] = { "gpio_34", "gpio_35" }; +static const char * const rtd1319d_i2c5_groups[] = { "gpio_29", "gpio_46" }; +static const char * const rtd1319d_pcie1_groups[] = { "gpio_22" }; +static const char * const rtd1319d_sdio_groups[] = { + "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44", + "gpio_45" }; +static const char * const rtd1319d_etn_led_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1319d_etn_phy_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1319d_spi_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31" }; +static const char * const rtd1319d_pwm0_loc0_groups[] = { "gpio_26" }; +static const char * const rtd1319d_pwm0_loc1_groups[] = { "gpio_20" }; +static const char * const rtd1319d_pwm1_loc0_groups[] = { "gpio_27" }; +static const char * const rtd1319d_pwm1_loc1_groups[] = { "gpio_21" }; + +static const char * const rtd1319d_pwm2_loc0_groups[] = { "gpio_28" }; +static const char * const rtd1319d_pwm2_loc1_groups[] = { "gpio_22" }; +static const char * const rtd1319d_pwm3_loc0_groups[] = { "gpio_47" }; +static const char * const rtd1319d_pwm3_loc1_groups[] = { "gpio_23" }; +static const char * const rtd1319d_qam_agc_if0_groups[] = { "gpio_21" }; +static const char * const rtd1319d_qam_agc_if1_groups[] = { "gpio_23" }; +static const char * const rtd1319d_spdif_optical_loc0_groups[] = { "gpio_21", "spdif_loc" }; +static const char * const rtd1319d_spdif_optical_loc1_groups[] = { "gpio_6", "spdif_loc" }; +static const char * const rtd1319d_usb_cc1_groups[] = { "usb_cc1" }; +static const char * const rtd1319d_usb_cc2_groups[] = { "usb_cc2" }; +static const char * const rtd1319d_vfd_groups[] = { + "gpio_26", "gpio_27", "gpio_28" }; +static const char * const rtd1319d_sd_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1319d_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_63", "gpio_64", "dmic_loc" }; +static const char * const rtd1319d_dmic_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "dmic_loc" }; +static const char * const rtd1319d_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_63", "ai_loc" }; +static const char * const rtd1319d_ai_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "hif_data", + "hif_en", "hif_rdy", "hif_clk", "ai_loc" }; +static const char * const rtd1319d_tdm_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "tdm_ai_loc" }; +static const char * const rtd1319d_tdm_ai_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", "tdm_ai_loc" }; +static const char * const rtd1319d_hi_loc0_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1319d_hi_m_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1319d_vtc_i2so_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_64"}; +static const char * const rtd1319d_vtc_i2si_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "vtc_i2si_loc" }; +static const char * const rtd1319d_vtc_i2si_loc1_groups[] = { + "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_i2si_loc" }; +static const char * const rtd1319d_vtc_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", + "vtc_dmic_loc" }; +static const char * const rtd1319d_vtc_dmic_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_dmic_loc" }; +static const char * const rtd1319d_vtc_tdm_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", + "vtc_tdm_loc" }; +static const char * const rtd1319d_vtc_tdm_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk", + "vtc_tdm_loc" }; +static const char * const rtd1319d_dc_fan_groups[] = { "gpio_47" }; +static const char * const rtd1319d_pll_test_loc0_groups[] = { "gpio_52", "gpio_53" }; +static const char * const rtd1319d_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" }; +static const char * const rtd1319d_spdif_groups[] = { "gpio_50" }; +static const char * const rtd1319d_ir_rx_groups[] = { "ir_rx" }; +static const char * const rtd1319d_uart2_disable_groups[] = { "ur2_loc" }; +static const char * const rtd1319d_gspi_disable_groups[] = { "gspi_loc" }; +static const char * const rtd1319d_hi_width_disable_groups[] = { "hi_width" }; +static const char * const rtd1319d_hi_width_1bit_groups[] = { "hi_width" }; +static const char * const rtd1319d_sf_disable_groups[] = { "sf_en" }; +static const char * const rtd1319d_sf_enable_groups[] = { "sf_en" }; +static const char * const rtd1319d_scpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_scpu_loc" }; +static const char * const rtd1319d_scpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_scpu_loc" }; +static const char * const rtd1319d_scpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_scpu_loc" }; +static const char * const rtd1319d_acpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_acpu_loc" }; +static const char * const rtd1319d_acpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_acpu_loc" }; +static const char * const rtd1319d_acpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_acpu_loc" }; +static const char * const rtd1319d_vcpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_vcpu_loc" }; +static const char * const rtd1319d_vcpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_vcpu_loc" }; +static const char * const rtd1319d_vcpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_vcpu_loc" }; +static const char * const rtd1319d_secpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_secpu_loc" }; +static const char * const rtd1319d_secpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_secpu_loc" }; +static const char * const rtd1319d_secpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_secpu_loc" }; +static const char * const rtd1319d_aucpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "ejtag_aucpu_loc" }; +static const char * const rtd1319d_aucpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk", + "ejtag_aucpu_loc" }; +static const char * const rtd1319d_aucpu_ejtag_loc2_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "ejtag_aucpu_loc" }; +static const char * const rtd1319d_iso_tristate_groups[] = { + "emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd", + "emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", + "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7", + "gpio_78", "gpio_79", "gpio_80", "gpio_81", "gpio_1", + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gpio_22", + "gpio_23", "usb_cc2", "gpio_25", "gpio_28", "gpio_29", + "gpio_30", "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_rdy", "hif_clk", "gpio_40", "gpio_41", "gpio_42", + "gpio_43", "gpio_44", "gpio_45", "gpio_46", "usb_cc1", + "ir_rx", "ur0_rx", "ur0_tx", "gpio_62", "gpio_63", "gpio_64" }; +static const char * const rtd1319d_dbg_out0_groups[] = { + "gpio_12", "gpio_13", "gpio_16", "gpio_17", "gpio_26", "gpio_27", + "gpio_34", "gpio_35", "gpio_48", "gpio_49", "gpio_57", "gpio_58", + "gpio_59", "gpio_60", "gpio_61" }; +static const char * const rtd1319d_dbg_out1_groups[] = { + "gpio_0", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", + "gpio_7", "gpio_14", "gpio_15", "gpio_18", "gpio_19", "gpio_20", + "gpio_21", "gpio_31", "gpio_47", "gpio_50", "gpio_52", "gpio_53" }; +static const char * const rtd1319d_standby_dbg_groups[] = { + "gpio_2", "gpio_3", "ir_rx" }; +static const char * const rtd1319d_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1319d_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1319d_aucpu_ejtag_disable_groups[] = { "ejtag_aucpu_loc" }; +static const char * const rtd1319d_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" }; +static const char * const rtd1319d_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" }; +static const char * const rtd1319d_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" }; +static const char * const rtd1319d_secpu_ejtag_disable_groups[] = { "ejtag_secpu_loc" }; +static const char * const rtd1319d_vtc_dmic_loc_disable_groups[] = { "vtc_dmic_loc" }; +static const char * const rtd1319d_vtc_tdm_disable_groups[] = { "vtc_tdm_loc" }; +static const char * const rtd1319d_vtc_i2si_disable_groups[] = { "vtc_i2si_loc" }; +static const char * const rtd1319d_tdm_ai_disable_groups[] = { "tdm_ai_loc" }; +static const char * const rtd1319d_ai_disable_groups[] = { "ai_loc" }; +static const char * const rtd1319d_spdif_disable_groups[] = { "spdif_loc" }; +static const char * const rtd1319d_hif_disable_groups[] = { "hif_en_loc" }; +static const char * const rtd1319d_hif_enable_groups[] = { "hif_en_loc" }; +static const char * const rtd1319d_test_loop_groups[] = { "gpio_27" }; +static const char * const rtd1319d_pmic_pwrup_groups[] = { "gpio_78" }; + +#define RTD1319D_FUNC(_name) \ + { \ + .name = # _name, \ + .groups = rtd1319d_ ## _name ## _groups, \ + .num_groups = ARRAY_SIZE(rtd1319d_ ## _name ## _groups), \ + } + +static const struct rtd_pin_func_desc rtd1319d_pin_functions[] = { + RTD1319D_FUNC(gpio), + RTD1319D_FUNC(nf), + RTD1319D_FUNC(emmc), + RTD1319D_FUNC(tp0), + RTD1319D_FUNC(tp1), + RTD1319D_FUNC(sc0), + RTD1319D_FUNC(sc0_data0), + RTD1319D_FUNC(sc0_data1), + RTD1319D_FUNC(sc0_data2), + RTD1319D_FUNC(sc1), + RTD1319D_FUNC(sc1_data0), + RTD1319D_FUNC(sc1_data1), + RTD1319D_FUNC(sc1_data2), + RTD1319D_FUNC(ao), + RTD1319D_FUNC(gspi_loc0), + RTD1319D_FUNC(gspi_loc1), + RTD1319D_FUNC(uart0), + RTD1319D_FUNC(uart1), + RTD1319D_FUNC(uart2_loc0), + RTD1319D_FUNC(uart2_loc1), + RTD1319D_FUNC(i2c0), + RTD1319D_FUNC(i2c1), + RTD1319D_FUNC(i2c3), + RTD1319D_FUNC(i2c4), + RTD1319D_FUNC(i2c5), + RTD1319D_FUNC(pcie1), + RTD1319D_FUNC(sdio), + RTD1319D_FUNC(etn_led), + RTD1319D_FUNC(etn_phy), + RTD1319D_FUNC(spi), + RTD1319D_FUNC(pwm0_loc0), + RTD1319D_FUNC(pwm0_loc1), + RTD1319D_FUNC(pwm1_loc0), + RTD1319D_FUNC(pwm1_loc1), + RTD1319D_FUNC(pwm2_loc0), + RTD1319D_FUNC(pwm2_loc1), + RTD1319D_FUNC(pwm3_loc0), + RTD1319D_FUNC(pwm3_loc1), + RTD1319D_FUNC(qam_agc_if0), + RTD1319D_FUNC(qam_agc_if1), + RTD1319D_FUNC(spdif_optical_loc0), + RTD1319D_FUNC(spdif_optical_loc1), + RTD1319D_FUNC(usb_cc1), + RTD1319D_FUNC(usb_cc2), + RTD1319D_FUNC(vfd), + RTD1319D_FUNC(sd), + RTD1319D_FUNC(dmic_loc0), + RTD1319D_FUNC(dmic_loc1), + RTD1319D_FUNC(ai_loc0), + RTD1319D_FUNC(ai_loc1), + RTD1319D_FUNC(tdm_ai_loc0), + RTD1319D_FUNC(tdm_ai_loc1), + RTD1319D_FUNC(hi_loc0), + RTD1319D_FUNC(hi_m), + RTD1319D_FUNC(vtc_i2so), + RTD1319D_FUNC(vtc_i2si_loc0), + RTD1319D_FUNC(vtc_i2si_loc1), + RTD1319D_FUNC(vtc_dmic_loc0), + RTD1319D_FUNC(vtc_dmic_loc1), + RTD1319D_FUNC(vtc_tdm_loc0), + RTD1319D_FUNC(vtc_tdm_loc1), + RTD1319D_FUNC(dc_fan), + RTD1319D_FUNC(pll_test_loc0), + RTD1319D_FUNC(pll_test_loc1), + RTD1319D_FUNC(ir_rx), + RTD1319D_FUNC(uart2_disable), + RTD1319D_FUNC(gspi_disable), + RTD1319D_FUNC(hi_width_disable), + RTD1319D_FUNC(hi_width_1bit), + RTD1319D_FUNC(sf_disable), + RTD1319D_FUNC(sf_enable), + RTD1319D_FUNC(scpu_ejtag_loc0), + RTD1319D_FUNC(scpu_ejtag_loc1), + RTD1319D_FUNC(scpu_ejtag_loc2), + RTD1319D_FUNC(acpu_ejtag_loc0), + RTD1319D_FUNC(acpu_ejtag_loc1), + RTD1319D_FUNC(acpu_ejtag_loc2), + RTD1319D_FUNC(vcpu_ejtag_loc0), + RTD1319D_FUNC(vcpu_ejtag_loc1), + RTD1319D_FUNC(vcpu_ejtag_loc2), + RTD1319D_FUNC(secpu_ejtag_loc0), + RTD1319D_FUNC(secpu_ejtag_loc1), + RTD1319D_FUNC(secpu_ejtag_loc2), + RTD1319D_FUNC(aucpu_ejtag_loc0), + RTD1319D_FUNC(aucpu_ejtag_loc1), + RTD1319D_FUNC(aucpu_ejtag_loc2), + RTD1319D_FUNC(iso_tristate), + RTD1319D_FUNC(dbg_out0), + RTD1319D_FUNC(dbg_out1), + RTD1319D_FUNC(standby_dbg), + RTD1319D_FUNC(spdif), + RTD1319D_FUNC(arm_trace_debug_disable), + RTD1319D_FUNC(arm_trace_debug_enable), + RTD1319D_FUNC(aucpu_ejtag_disable), + RTD1319D_FUNC(acpu_ejtag_disable), + RTD1319D_FUNC(vcpu_ejtag_disable), + RTD1319D_FUNC(scpu_ejtag_disable), + RTD1319D_FUNC(secpu_ejtag_disable), + RTD1319D_FUNC(vtc_dmic_loc_disable), + RTD1319D_FUNC(vtc_tdm_disable), + RTD1319D_FUNC(vtc_i2si_disable), + RTD1319D_FUNC(tdm_ai_disable), + RTD1319D_FUNC(ai_disable), + RTD1319D_FUNC(spdif_disable), + RTD1319D_FUNC(hif_disable), + RTD1319D_FUNC(hif_enable), + RTD1319D_FUNC(test_loop), + RTD1319D_FUNC(pmic_pwrup), +}; + +#undef RTD1319D_FUNC + +static const struct rtd_pin_desc rtd1319d_iso_muxes[] = { + [RTD1319D_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1319D_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1319D_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x4, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "pmic_pwrup"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x4, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x4, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x4, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x8, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")), + [RTD1319D_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x8, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x8, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1319D_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x8, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), + [RTD1319D_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x8, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1319D_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x8, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")), + [RTD1319D_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x8, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "spdif_optical_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1319D_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x8, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1319D_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0xc, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0xc, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0xc, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1319D_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0xc, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0xc, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), + [RTD1319D_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0xc, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), + [RTD1319D_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0xc, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")), + [RTD1319D_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0xc, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1319D_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x10, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1319D_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x10, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "i2c1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1319D_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x10, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1319D_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x10, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")), + [RTD1319D_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x10, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm0_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc0_data0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1319D_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x10, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "pwm1_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "qam_agc_if0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")), + [RTD1319D_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x10, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "pwm2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcie1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x10, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "pwm3_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "qam_agc_if1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x14, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "usb_cc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0x14, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0x14, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "pwm0_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1319D_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x14, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "pwm1_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "test_loop"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")), + [RTD1319D_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x14, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "pwm2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x14, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x14, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "sc0_data1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x14, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1319D_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x18, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x18, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x18, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "sc1_data1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1319D_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x18, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "i2c4"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "sc1_data2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")), + [RTD1319D_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x18, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x18, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 20), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 20), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x18, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x18, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 28), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 28), "hi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "vtc_dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x1c, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x1c, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")), + [RTD1319D_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x1c, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")), + [RTD1319D_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x1c, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x1c, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")), + [RTD1319D_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x1c, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "sdio"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")), + [RTD1319D_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x1c, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "i2c5"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x1c, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "dc_fan"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "pwm3_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "sc0_data2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")), + + [RTD1319D_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x20, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")), + [RTD1319D_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x20, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "pll_test_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1319D_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x20, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "spdif"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")), + [RTD1319D_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x20, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "usb_cc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")), + [RTD1319D_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x20, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc1_data0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")), + [RTD1319D_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x20, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")), + [RTD1319D_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x20, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ir_rx"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x20, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x24, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + [RTD1319D_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x24, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")), + [RTD1319D_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x24, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 8), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")), + [RTD1319D_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x24, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")), + [RTD1319D_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x24, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")), + [RTD1319D_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x24, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "secpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "aucpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")), + [RTD1319D_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x24, GENMASK(27, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")), + [RTD1319D_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x24, GENMASK(31, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")), + + [RTD1319D_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x28, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2so"), + RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")), + + [RTD1319D_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")), + [RTD1319D_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")), + [RTD1319D_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")), + [RTD1319D_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")), + [RTD1319D_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")), + [RTD1319D_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "aucpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu_ejtag_loc2")), + [RTD1319D_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")), + [RTD1319D_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")), + [RTD1319D_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")), + [RTD1319D_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")), + + [RTD1319D_ISO_EJTAG_SECPU_LOC] = RTK_PIN_MUX(ejtag_secpu_loc, 0x124, GENMASK(20, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "secpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "secpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "secpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "secpu_ejtag_loc2")), + + [RTD1319D_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "vtc_dmic_loc_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vtc_dmic_loc1")), + [RTD1319D_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "vtc_tdm_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vtc_tdm_loc1")), + [RTD1319D_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "vtc_i2si_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vtc_i2si_loc1")), + [RTD1319D_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "tdm_ai_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "tdm_ai_loc1")), + [RTD1319D_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "ai_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc1")), + [RTD1319D_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "spdif_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "spdif_optical_loc1")), + + [RTD1319D_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "hif_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "hif_enable")), + [RTD1319D_ISO_SC0_LOC] = RTK_PIN_MUX(sc0_loc, 0x188, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "sc0_data0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sc0_data1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sc0_data2")), + [RTD1319D_ISO_SC1_LOC] = RTK_PIN_MUX(sc1_loc, 0x188, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "sc1_data0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "sc1_data1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sc1_data2")), + + [RTD1319D_ISO_TESTMODE] = {0}, +}; + +static const struct rtd_pin_config_desc rtd1319d_iso_configs[] = { + [RTD1319D_ISO_SCAN_SWITCH] = RTK_PIN_CONFIG(scan_switch, 0x2c, 0, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1319D_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x2c, 3, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x2c, 8, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x2c, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x2c, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x2c, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x30, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x30, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x30, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_0] = RTK_PIN_CONFIG(gpio_0, 0x30, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x30, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_5] = RTK_PIN_CONFIG(gpio_5, 0x30, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x34, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x34, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x34, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_22] = RTK_PIN_CONFIG(gpio_22, 0x34, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x34, 20, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1319D_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x34, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x38, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x38, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x38, 10, NA, NA, 0, 1, 2, PADDRI_4_8), + [RTD1319D_ISO_WD_RSET] = RTK_PIN_CONFIG(wd_rset, 0x38, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x38, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_BOOT_SEL] = RTK_PIN_CONFIG(boot_sel, 0x38, 23, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1319D_ISO_RESET_N] = RTK_PIN_CONFIG(reset_n, 0x38, 27, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1319D_ISO_TESTMODE] = RTK_PIN_CONFIG(testmode, 0x3c, 0, 0, 1, NA, 2, 3, PADDRI_4_8), + [RTD1319D_ISO_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x3c, 4, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x3c, 17, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_42] = RTK_PIN_CONFIG(gpio_42, 0x40, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_43] = RTK_PIN_CONFIG(gpio_43, 0x40, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_44] = RTK_PIN_CONFIG(gpio_44, 0x44, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x44, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x48, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x48, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x4c, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x4c, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x50, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x50, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x54, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x54, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x58, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x58, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x5c, 0, 0, 1, NA, 2, 13, NA), + [RTD1319D_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x5c, 14, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x60, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_78] = RTK_PIN_CONFIG(gpio_78, 0x60, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_79] = RTK_PIN_CONFIG(gpio_79, 0x64, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x64, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_2] = RTK_PIN_CONFIG(gpio_2, 0x64, 26, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_3] = RTK_PIN_CONFIG(gpio_3, 0x68, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_4] = RTK_PIN_CONFIG(gpio_4, 0x68, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x68, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x68, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x68, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x68, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x6c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x6c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_63] = RTK_PIN_CONFIG(gpio_63, 0x6c, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x6c, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x6c, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x6c, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x70, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_21] = RTK_PIN_CONFIG(gpio_21, 0x70, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_23] = RTK_PIN_CONFIG(gpio_23, 0x70, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x70, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x74, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x74, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x78, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x78, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x7c, 0, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x7c, 13, 0, 1, NA, 2, 12, NA), + [RTD1319D_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x7c, 26, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x80, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x80, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x80, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x80, 16, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x80, 22, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x84, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x84, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x84, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x84, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x84, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x84, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x88, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_52] = RTK_PIN_CONFIG(gpio_52, 0x88, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1319D_ISO_GPIO_53] = RTK_PIN_CONFIG(gpio_53, 0x88, 10, 1, 2, 0, 3, 4, PADDRI_4_8), +}; + +static const struct rtd_pin_sconfig_desc rtd1319d_iso_sconfigs[] = { + RTK_PIN_SCONFIG(gpio_40, 0x3c, 7, 3, 10, 3, 13, 3), + RTK_PIN_SCONFIG(gpio_41, 0x3c, 20, 3, 23, 3, 26, 3), + RTK_PIN_SCONFIG(gpio_42, 0x40, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_43, 0x40, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_44, 0x44, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_45, 0x44, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_0, 0x48, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_1, 0x48, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_2, 0x4c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_3, 0x4c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_4, 0x50, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_5, 0x50, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_6, 0x54, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_7, 0x54, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_dd_sb, 0x58, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_rst_n, 0x58, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_cmd, 0x5c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_clk, 0x5c, 17, 3, 20, 3, 23, 3), + RTK_PIN_SCONFIG(gpio_80, 0x60, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_78, 0x60, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_79, 0x64, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_81, 0x64, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(hif_en, 0x74, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_data, 0x74, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_33, 0x78, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_32, 0x78, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(hif_clk, 0x7c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_rdy, 0x7c, 16, 3, 19, 3, 22, 3), +}; + +static const struct rtd_pinctrl_desc rtd1319d_iso_pinctrl_desc = { + .pins = rtd1319d_iso_pins, + .num_pins = ARRAY_SIZE(rtd1319d_iso_pins), + .groups = rtd1319d_pin_groups, + .num_groups = ARRAY_SIZE(rtd1319d_pin_groups), + .functions = rtd1319d_pin_functions, + .num_functions = ARRAY_SIZE(rtd1319d_pin_functions), + .muxes = rtd1319d_iso_muxes, + .num_muxes = ARRAY_SIZE(rtd1319d_iso_muxes), + .configs = rtd1319d_iso_configs, + .num_configs = ARRAY_SIZE(rtd1319d_iso_configs), + .sconfigs = rtd1319d_iso_sconfigs, + .num_sconfigs = ARRAY_SIZE(rtd1319d_iso_sconfigs), +}; + +static int rtd1319d_pinctrl_probe(struct platform_device *pdev) +{ + return rtd_pinctrl_probe(pdev, &rtd1319d_iso_pinctrl_desc); +} + +static const struct of_device_id rtd1319d_pinctrl_of_match[] = { + { .compatible = "realtek,rtd1319d-pinctrl", }, + {}, +}; + +static struct platform_driver rtd1319d_pinctrl_driver = { + .driver = { + .name = "rtd1319d-pinctrl", + .of_match_table = rtd1319d_pinctrl_of_match, + }, + .probe = rtd1319d_pinctrl_probe, +}; + +static int __init rtd1319d_pinctrl_init(void) +{ + return platform_driver_register(&rtd1319d_pinctrl_driver); +} +arch_initcall(rtd1319d_pinctrl_init); + +static void __exit rtd1319d_pinctrl_exit(void) +{ + platform_driver_unregister(&rtd1319d_pinctrl_driver); +} +module_exit(rtd1319d_pinctrl_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Realtek Semiconductor Corporation"); +MODULE_DESCRIPTION("Realtek DHC SoC RTD1319D pinctrl driver"); diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1619b.c b/drivers/pinctrl/realtek/pinctrl-rtd1619b.c new file mode 100644 index 000000000000..b07e50d6356d --- /dev/null +++ b/drivers/pinctrl/realtek/pinctrl-rtd1619b.c @@ -0,0 +1,1601 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Realtek DHC 1619B pin controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corp. + * + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-rtd.h" + +enum rtd16xxb_iso_pins { + RTD1619B_ISO_GPIO_0 = 0, + RTD1619B_ISO_GPIO_1, + RTD1619B_ISO_GPIO_2, + RTD1619B_ISO_GPIO_3, + RTD1619B_ISO_GPIO_4, + RTD1619B_ISO_GPIO_5, + RTD1619B_ISO_GPIO_6, + RTD1619B_ISO_GPIO_7, + RTD1619B_ISO_GPIO_8, + RTD1619B_ISO_GPIO_9, + RTD1619B_ISO_GPIO_10, + RTD1619B_ISO_GPIO_11, + RTD1619B_ISO_GPIO_12, + RTD1619B_ISO_GPIO_13, + RTD1619B_ISO_GPIO_14, + RTD1619B_ISO_GPIO_15, + RTD1619B_ISO_GPIO_16, + RTD1619B_ISO_GPIO_17, + RTD1619B_ISO_GPIO_18, + RTD1619B_ISO_GPIO_19, + RTD1619B_ISO_GPIO_20, + RTD1619B_ISO_GPIO_21, + RTD1619B_ISO_GPIO_22, + RTD1619B_ISO_GPIO_23, + RTD1619B_ISO_USB_CC2, + RTD1619B_ISO_GPIO_25, + RTD1619B_ISO_GPIO_26, + RTD1619B_ISO_GPIO_27, + RTD1619B_ISO_GPIO_28, + RTD1619B_ISO_GPIO_29, + RTD1619B_ISO_GPIO_30, + RTD1619B_ISO_GPIO_31, + RTD1619B_ISO_GPIO_32, + RTD1619B_ISO_GPIO_33, + RTD1619B_ISO_GPIO_34, + RTD1619B_ISO_GPIO_35, + RTD1619B_ISO_HIF_DATA, + RTD1619B_ISO_HIF_EN, + RTD1619B_ISO_HIF_RDY, + RTD1619B_ISO_HIF_CLK, + RTD1619B_ISO_GPIO_40, + RTD1619B_ISO_GPIO_41, + RTD1619B_ISO_GPIO_42, + RTD1619B_ISO_GPIO_43, + RTD1619B_ISO_GPIO_44, + RTD1619B_ISO_GPIO_45, + RTD1619B_ISO_GPIO_46, + RTD1619B_ISO_GPIO_47, + RTD1619B_ISO_GPIO_48, + RTD1619B_ISO_GPIO_49, + RTD1619B_ISO_GPIO_50, + RTD1619B_ISO_USB_CC1, + RTD1619B_ISO_GPIO_52, + RTD1619B_ISO_GPIO_53, + RTD1619B_ISO_IR_RX, + RTD1619B_ISO_UR0_RX, + RTD1619B_ISO_UR0_TX, + RTD1619B_ISO_GPIO_57, + RTD1619B_ISO_GPIO_58, + RTD1619B_ISO_GPIO_59, + RTD1619B_ISO_GPIO_60, + RTD1619B_ISO_GPIO_61, + RTD1619B_ISO_GPIO_62, + RTD1619B_ISO_GPIO_63, + RTD1619B_ISO_GPIO_64, + RTD1619B_ISO_GPIO_65, + RTD1619B_ISO_GPIO_66, + RTD1619B_ISO_GPIO_67, + RTD1619B_ISO_GPIO_68, + RTD1619B_ISO_GPIO_69, + RTD1619B_ISO_GPIO_70, + RTD1619B_ISO_GPIO_71, + RTD1619B_ISO_GPIO_72, + RTD1619B_ISO_GPIO_73, + RTD1619B_ISO_GPIO_74, + RTD1619B_ISO_GPIO_75, + RTD1619B_ISO_GPIO_76, + RTD1619B_ISO_EMMC_CMD, + RTD1619B_ISO_SPI_CE_N, + RTD1619B_ISO_SPI_SCK, + RTD1619B_ISO_SPI_SO, + RTD1619B_ISO_SPI_SI, + RTD1619B_ISO_EMMC_RST_N, + RTD1619B_ISO_EMMC_DD_SB, + RTD1619B_ISO_EMMC_CLK, + RTD1619B_ISO_EMMC_DATA_0, + RTD1619B_ISO_EMMC_DATA_1, + RTD1619B_ISO_EMMC_DATA_2, + RTD1619B_ISO_EMMC_DATA_3, + RTD1619B_ISO_EMMC_DATA_4, + RTD1619B_ISO_EMMC_DATA_5, + RTD1619B_ISO_EMMC_DATA_6, + RTD1619B_ISO_EMMC_DATA_7, + RTD1619B_ISO_UR2_LOC, + RTD1619B_ISO_GSPI_LOC, + RTD1619B_ISO_SDIO_LOC, + RTD1619B_ISO_HI_LOC, + RTD1619B_ISO_HI_WIDTH, + RTD1619B_ISO_SF_EN, + RTD1619B_ISO_ARM_TRACE_DBG_EN, + RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, + RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, + RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, + RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, + RTD1619B_ISO_EJTAG_ACPU_LOC, + RTD1619B_ISO_EJTAG_VCPU_LOC, + RTD1619B_ISO_EJTAG_SCPU_LOC, + RTD1619B_ISO_DMIC_LOC, + RTD1619B_ISO_ISO_GSPI_LOC, + RTD1619B_ISO_EJTAG_VE3_LOC, + RTD1619B_ISO_EJTAG_AUCPU0_LOC, + RTD1619B_ISO_EJTAG_AUCPU1_LOC, +}; + +static const struct pinctrl_pin_desc rtd1619b_iso_pins[] = { + PINCTRL_PIN(RTD1619B_ISO_GPIO_0, "gpio_0"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_1, "gpio_1"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_2, "gpio_2"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_3, "gpio_3"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_4, "gpio_4"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_5, "gpio_5"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_6, "gpio_6"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_7, "gpio_7"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_8, "gpio_8"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_9, "gpio_9"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_10, "gpio_10"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_11, "gpio_11"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_12, "gpio_12"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_13, "gpio_13"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_14, "gpio_14"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_15, "gpio_15"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_16, "gpio_16"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_17, "gpio_17"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_18, "gpio_18"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_19, "gpio_19"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_20, "gpio_20"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_21, "gpio_21"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_22, "gpio_22"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_23, "gpio_23"), + PINCTRL_PIN(RTD1619B_ISO_USB_CC2, "usb_cc2"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_25, "gpio_25"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_26, "gpio_26"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_27, "gpio_27"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_28, "gpio_28"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_29, "gpio_29"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_30, "gpio_30"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_31, "gpio_31"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_32, "gpio_32"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_33, "gpio_33"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_34, "gpio_34"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_35, "gpio_35"), + PINCTRL_PIN(RTD1619B_ISO_HIF_DATA, "hif_data"), + PINCTRL_PIN(RTD1619B_ISO_HIF_EN, "hif_en"), + PINCTRL_PIN(RTD1619B_ISO_HIF_RDY, "hif_rdy"), + PINCTRL_PIN(RTD1619B_ISO_HIF_CLK, "hif_clk"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_40, "gpio_40"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_41, "gpio_41"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_42, "gpio_42"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_43, "gpio_43"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_44, "gpio_44"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_45, "gpio_45"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_46, "gpio_46"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_47, "gpio_47"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_48, "gpio_48"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_49, "gpio_49"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_50, "gpio_50"), + PINCTRL_PIN(RTD1619B_ISO_USB_CC1, "usb_cc1"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_52, "gpio_52"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_53, "gpio_53"), + PINCTRL_PIN(RTD1619B_ISO_IR_RX, "ir_rx"), + PINCTRL_PIN(RTD1619B_ISO_UR0_RX, "ur0_rx"), + PINCTRL_PIN(RTD1619B_ISO_UR0_TX, "ur0_tx"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_57, "gpio_57"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_58, "gpio_58"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_59, "gpio_59"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_60, "gpio_60"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_61, "gpio_61"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_62, "gpio_62"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_63, "gpio_63"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_64, "gpio_64"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_65, "gpio_65"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_66, "gpio_66"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_67, "gpio_67"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_68, "gpio_68"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_69, "gpio_69"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_70, "gpio_70"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_71, "gpio_71"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_72, "gpio_72"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_73, "gpio_73"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_74, "gpio_74"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_75, "gpio_75"), + PINCTRL_PIN(RTD1619B_ISO_GPIO_76, "gpio_76"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_CMD, "emmc_cmd"), + PINCTRL_PIN(RTD1619B_ISO_SPI_CE_N, "spi_ce_n"), + PINCTRL_PIN(RTD1619B_ISO_SPI_SCK, "spi_sck"), + PINCTRL_PIN(RTD1619B_ISO_SPI_SO, "spi_so"), + PINCTRL_PIN(RTD1619B_ISO_SPI_SI, "spi_si"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_RST_N, "emmc_rst_n"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DD_SB, "emmc_dd_sb"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_CLK, "emmc_clk"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_0, "emmc_data_0"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_1, "emmc_data_1"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_2, "emmc_data_2"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_3, "emmc_data_3"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_4, "emmc_data_4"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_5, "emmc_data_5"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_6, "emmc_data_6"), + PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_7, "emmc_data_7"), + PINCTRL_PIN(RTD1619B_ISO_UR2_LOC, "ur2_loc"), + PINCTRL_PIN(RTD1619B_ISO_GSPI_LOC, "gspi_loc"), + PINCTRL_PIN(RTD1619B_ISO_SDIO_LOC, "sdio_loc"), + PINCTRL_PIN(RTD1619B_ISO_HI_LOC, "hi_loc"), + PINCTRL_PIN(RTD1619B_ISO_HI_WIDTH, "hi_width"), + PINCTRL_PIN(RTD1619B_ISO_SF_EN, "sf_en"), + PINCTRL_PIN(RTD1619B_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"), + PINCTRL_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, "pwm_01_open_drain_en_loc0"), + PINCTRL_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, "pwm_23_open_drain_en_loc0"), + PINCTRL_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, "pwm_01_open_drain_en_loc1"), + PINCTRL_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, "pwm_23_open_drain_en_loc1"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"), + PINCTRL_PIN(RTD1619B_ISO_DMIC_LOC, "dmic_loc"), + PINCTRL_PIN(RTD1619B_ISO_ISO_GSPI_LOC, "iso_gspi_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_VE3_LOC, "ejtag_ve3_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_AUCPU0_LOC, "ejtag_aucpu0_loc"), + PINCTRL_PIN(RTD1619B_ISO_EJTAG_AUCPU1_LOC, "ejtag_aucpu1_loc"), +}; + +#define DECLARE_RTD1619B_PIN(_pin, _name) \ + static const unsigned int rtd1619b_## _name ##_pins[] = { _pin } + +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_0, gpio_0); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_1, gpio_1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_2, gpio_2); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_3, gpio_3); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_4, gpio_4); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_5, gpio_5); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_6, gpio_6); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_7, gpio_7); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_8, gpio_8); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_9, gpio_9); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_10, gpio_10); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_11, gpio_11); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_12, gpio_12); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_13, gpio_13); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_14, gpio_14); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_15, gpio_15); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_16, gpio_16); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_17, gpio_17); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_18, gpio_18); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_19, gpio_19); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_20, gpio_20); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_21, gpio_21); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_22, gpio_22); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_23, gpio_23); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_USB_CC2, usb_cc2); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_25, gpio_25); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_26, gpio_26); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_27, gpio_27); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_28, gpio_28); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_29, gpio_29); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_30, gpio_30); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_31, gpio_31); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_32, gpio_32); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_33, gpio_33); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_34, gpio_34); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_35, gpio_35); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_DATA, hif_data); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_EN, hif_en); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_RDY, hif_rdy); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_CLK, hif_clk); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_40, gpio_40); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_41, gpio_41); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_42, gpio_42); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_43, gpio_43); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_44, gpio_44); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_45, gpio_45); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_46, gpio_46); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_47, gpio_47); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_48, gpio_48); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_49, gpio_49); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_50, gpio_50); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_USB_CC1, usb_cc1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_52, gpio_52); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_53, gpio_53); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_IR_RX, ir_rx); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR0_RX, ur0_rx); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR0_TX, ur0_tx); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_57, gpio_57); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_58, gpio_58); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_59, gpio_59); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_60, gpio_60); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_61, gpio_61); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_62, gpio_62); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_63, gpio_63); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_64, gpio_64); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_65, gpio_65); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_66, gpio_66); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_67, gpio_67); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_68, gpio_68); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_69, gpio_69); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_70, gpio_70); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_71, gpio_71); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_72, gpio_72); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_73, gpio_73); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_74, gpio_74); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_75, gpio_75); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_76, gpio_76); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_CMD, emmc_cmd); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_CE_N, spi_ce_n); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SCK, spi_sck); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SO, spi_so); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SI, spi_si); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_RST_N, emmc_rst_n); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DD_SB, emmc_dd_sb); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_CLK, emmc_clk); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_0, emmc_data_0); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_1, emmc_data_1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_2, emmc_data_2); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_3, emmc_data_3); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_4, emmc_data_4); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_5, emmc_data_5); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_6, emmc_data_6); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_7, emmc_data_7); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR2_LOC, ur2_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_GSPI_LOC, gspi_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SDIO_LOC, sdio_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HI_LOC, hi_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_HI_WIDTH, hi_width); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_SF_EN, sf_en); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, pwm_01_open_drain_en_loc0); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, pwm_23_open_drain_en_loc0); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, pwm_01_open_drain_en_loc1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, pwm_23_open_drain_en_loc1); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_DMIC_LOC, dmic_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_ISO_GSPI_LOC, iso_gspi_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_VE3_LOC, ejtag_ve3_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_AUCPU0_LOC, ejtag_aucpu0_loc); +DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_AUCPU1_LOC, ejtag_aucpu1_loc); + +#define RTD1619B_GROUP(_name) \ + { \ + .name = # _name, \ + .pins = rtd1619b_ ## _name ## _pins, \ + .num_pins = ARRAY_SIZE(rtd1619b_ ## _name ## _pins), \ + } + +static const struct rtd_pin_group_desc rtd1619b_pin_groups[] = { + RTD1619B_GROUP(gpio_0), + RTD1619B_GROUP(gpio_1), + RTD1619B_GROUP(gpio_2), + RTD1619B_GROUP(gpio_3), + RTD1619B_GROUP(gpio_4), + RTD1619B_GROUP(gpio_5), + RTD1619B_GROUP(gpio_6), + RTD1619B_GROUP(gpio_7), + RTD1619B_GROUP(gpio_8), + RTD1619B_GROUP(gpio_9), + RTD1619B_GROUP(gpio_10), + RTD1619B_GROUP(gpio_11), + RTD1619B_GROUP(gpio_12), + RTD1619B_GROUP(gpio_13), + RTD1619B_GROUP(gpio_14), + RTD1619B_GROUP(gpio_15), + RTD1619B_GROUP(gpio_16), + RTD1619B_GROUP(gpio_17), + RTD1619B_GROUP(gpio_18), + RTD1619B_GROUP(gpio_19), + RTD1619B_GROUP(gpio_20), + RTD1619B_GROUP(gpio_21), + RTD1619B_GROUP(gpio_22), + RTD1619B_GROUP(gpio_23), + RTD1619B_GROUP(usb_cc2), + RTD1619B_GROUP(gpio_25), + RTD1619B_GROUP(gpio_26), + RTD1619B_GROUP(gpio_27), + RTD1619B_GROUP(gpio_28), + RTD1619B_GROUP(gpio_29), + RTD1619B_GROUP(gpio_30), + RTD1619B_GROUP(gpio_31), + RTD1619B_GROUP(gpio_32), + RTD1619B_GROUP(gpio_33), + RTD1619B_GROUP(gpio_34), + RTD1619B_GROUP(gpio_35), + RTD1619B_GROUP(hif_data), + RTD1619B_GROUP(hif_en), + RTD1619B_GROUP(hif_rdy), + RTD1619B_GROUP(hif_clk), + RTD1619B_GROUP(gpio_40), + RTD1619B_GROUP(gpio_41), + RTD1619B_GROUP(gpio_42), + RTD1619B_GROUP(gpio_43), + RTD1619B_GROUP(gpio_44), + RTD1619B_GROUP(gpio_45), + RTD1619B_GROUP(gpio_46), + RTD1619B_GROUP(gpio_47), + RTD1619B_GROUP(gpio_48), + RTD1619B_GROUP(gpio_49), + RTD1619B_GROUP(gpio_50), + RTD1619B_GROUP(usb_cc1), + RTD1619B_GROUP(gpio_52), + RTD1619B_GROUP(gpio_53), + RTD1619B_GROUP(ir_rx), + RTD1619B_GROUP(ur0_rx), + RTD1619B_GROUP(ur0_tx), + RTD1619B_GROUP(gpio_57), + RTD1619B_GROUP(gpio_58), + RTD1619B_GROUP(gpio_59), + RTD1619B_GROUP(gpio_60), + RTD1619B_GROUP(gpio_61), + RTD1619B_GROUP(gpio_62), + RTD1619B_GROUP(gpio_63), + RTD1619B_GROUP(gpio_64), + RTD1619B_GROUP(gpio_65), + RTD1619B_GROUP(gpio_66), + RTD1619B_GROUP(gpio_67), + RTD1619B_GROUP(gpio_68), + RTD1619B_GROUP(gpio_69), + RTD1619B_GROUP(gpio_70), + RTD1619B_GROUP(gpio_71), + RTD1619B_GROUP(gpio_72), + RTD1619B_GROUP(gpio_73), + RTD1619B_GROUP(gpio_74), + RTD1619B_GROUP(gpio_75), + RTD1619B_GROUP(gpio_76), + RTD1619B_GROUP(emmc_cmd), + RTD1619B_GROUP(spi_ce_n), + RTD1619B_GROUP(spi_sck), + RTD1619B_GROUP(spi_so), + RTD1619B_GROUP(spi_si), + RTD1619B_GROUP(emmc_rst_n), + RTD1619B_GROUP(emmc_dd_sb), + RTD1619B_GROUP(emmc_clk), + RTD1619B_GROUP(emmc_data_0), + RTD1619B_GROUP(emmc_data_1), + RTD1619B_GROUP(emmc_data_2), + RTD1619B_GROUP(emmc_data_3), + RTD1619B_GROUP(emmc_data_4), + RTD1619B_GROUP(emmc_data_5), + RTD1619B_GROUP(emmc_data_6), + RTD1619B_GROUP(emmc_data_7), + RTD1619B_GROUP(ur2_loc), + RTD1619B_GROUP(gspi_loc), + RTD1619B_GROUP(sdio_loc), + RTD1619B_GROUP(hi_loc), + RTD1619B_GROUP(hi_width), + RTD1619B_GROUP(sf_en), + RTD1619B_GROUP(arm_trace_dbg_en), + RTD1619B_GROUP(pwm_01_open_drain_en_loc0), + RTD1619B_GROUP(pwm_23_open_drain_en_loc0), + RTD1619B_GROUP(pwm_01_open_drain_en_loc1), + RTD1619B_GROUP(pwm_23_open_drain_en_loc1), + RTD1619B_GROUP(ejtag_acpu_loc), + RTD1619B_GROUP(ejtag_vcpu_loc), + RTD1619B_GROUP(ejtag_scpu_loc), + RTD1619B_GROUP(dmic_loc), + RTD1619B_GROUP(iso_gspi_loc), + RTD1619B_GROUP(ejtag_ve3_loc), + RTD1619B_GROUP(ejtag_aucpu0_loc), + RTD1619B_GROUP(ejtag_aucpu1_loc), +}; + +static const char * const rtd1619b_gpio_groups[] = { + "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9", + "gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14", + "gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19", + "gpio_20", "gpio_21", "gpio_22", "gpio_23", "usb_cc2", + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29", + "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", + "gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk", + "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44", + "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", + "gpio_50", "usb_cc1", "gpio_52", "gpio_53", "ir_rx", + "ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59", + "gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_64", + "gpio_65", "gpio_66", "gpio_67", "gpio_68", "gpio_69", + "gpio_70", "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "emmc_cmd", "spi_ce_n", "spi_sck", + "spi_so", "spi_si"}; +static const char * const rtd1619b_nf_groups[] = { + "emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", + "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5", "emmc_data_6", "emmc_data_7", "spi_ce_n", + "spi_sck", "spi_so", "spi_si" }; +static const char * const rtd1619b_nf_spi_groups[] = { + "emmc_data_0", "emmc_data_1", + "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5" }; +static const char * const rtd1619b_spi_groups[] = { + "spi_ce_n", "spi_sck", "spi_so", "spi_si" }; +static const char * const rtd1619b_emmc_groups[] = { + "emmc_rst_n", "emmc_clk", "emmc_data_0", "emmc_data_1", + "emmc_data_2", "emmc_data_3", "emmc_data_4", + "emmc_data_5", "emmc_data_6", "emmc_data_7", + "emmc_dd_sb", "emmc_cmd"}; + +static const char * const rtd1619b_pmic_groups[] = { "spi_ce_n" }; +static const char * const rtd1619b_spdif_groups[] = { "gpio_50" }; +static const char * const rtd1619b_spdif_coaxial_groups[] = { "gpio_1" }; +static const char * const rtd1619b_spdif_optical_loc0_groups[] = { "gpio_6" }; +static const char * const rtd1619b_spdif_optical_loc1_groups[] = { "gpio_21" }; + +static const char * const rtd1619b_emmc_spi_groups[] = { + "gpio_1", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6" }; +static const char * const rtd1619b_sc1_groups[] = { + "gpio_2", "gpio_3", "gpio_4", "gpio_5" }; +static const char * const rtd1619b_uart0_groups[] = { "ur0_rx", "ur0_tx" }; +static const char * const rtd1619b_uart1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11" }; +static const char * const rtd1619b_uart2_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" }; +static const char * const rtd1619b_uart2_loc1_groups[] = { + "gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" }; +static const char * const rtd1619b_gspi_loc1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" }; +static const char * const rtd1619b_iso_gspi_loc1_groups[] = { + "gpio_8", "gpio_9", "gpio_10", "gpio_11", "iso_gspi_loc" }; +static const char * const rtd1619b_i2c0_groups[] = { "gpio_12", "gpio_13" }; +static const char * const rtd1619b_i2c1_groups[] = { "gpio_16", "gpio_17" }; +static const char * const rtd1619b_i2c3_groups[] = { "gpio_63", "gpio_64" }; +static const char * const rtd1619b_i2c4_groups[] = { "gpio_34", "gpio_35" }; +static const char * const rtd1619b_i2c5_groups[] = { "gpio_29", "gpio_46" }; +static const char * const rtd1619b_pwm0_groups[] = { "gpio_20", "gpio_26" }; +static const char * const rtd1619b_pwm1_groups[] = { "gpio_21", "gpio_27" }; +static const char * const rtd1619b_pwm2_groups[] = { "gpio_22", "gpio_28" }; +static const char * const rtd1619b_pwm3_groups[] = { "gpio_23", "gpio_47" }; +static const char * const rtd1619b_etn_led_groups[] = { "gpio_14", "gpio_15", "gpio_23" }; +static const char * const rtd1619b_etn_phy_groups[] = { "gpio_14", "gpio_15" }; +static const char * const rtd1619b_etn_clk_groups[] = { "gpio_14" }; +static const char * const rtd1619b_sc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31" }; +static const char * const rtd1619b_vfd_groups[] = { + "gpio_26", "gpio_27", "gpio_28" }; + +static const char * const rtd1619b_gspi_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" }; +static const char * const rtd1619b_iso_gspi_loc0_groups[] = { + "gpio_18", "gpio_19", "gpio_20", "gpio_31", "iso_gspi_loc" }; +static const char * const rtd1619b_pcie1_groups[] = { "gpio_25" }; +static const char * const rtd1619b_pcie2_groups[] = { "gpio_52" }; +static const char * const rtd1619b_sd_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", "hif_data", + "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_sdio_loc0_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_rdy", "hif_clk", "sdio_loc" }; +static const char * const rtd1619b_sdio_loc1_groups[] = { + "gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44", + "gpio_45", "sdio_loc" }; +static const char * const rtd1619b_hi_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_hi_m_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_dc_fan_groups[] = { "gpio_47" }; +static const char * const rtd1619b_pll_test_loc0_groups[] = { "gpio_52", "gpio_53" }; +static const char * const rtd1619b_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" }; +static const char * const rtd1619b_tdm_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60" }; +static const char * const rtd1619b_tdm_ai_loc1_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_dmic_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_63", "gpio_64", "dmic_loc"}; +static const char * const rtd1619b_dmic_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "gpio_35", "hif_data", + "hif_en", "hif_rdy", "hif_clk", "dmic_loc" }; +static const char * const rtd1619b_ai_loc0_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61", + "gpio_62", "gpio_63" }; +static const char * const rtd1619b_ai_loc1_groups[] = { + "gpio_32", "gpio_33", "gpio_34", "hif_data", + "hif_en", "hif_rdy", "hif_clk"}; +static const char * const rtd1619b_tp0_groups[] = { + "gpio_66", "gpio_67", "gpio_68", "gpio_69", + "gpio_70", "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76" }; +static const char * const rtd1619b_tp1_groups[] = { + "gpio_69", "gpio_70", "gpio_71", "gpio_72" }; +static const char * const rtd1619b_ao_groups[] = { + "gpio_66", "gpio_67", "gpio_68", "gpio_69", + "gpio_70", "gpio_71", "gpio_72" }; +static const char * const rtd1619b_uart2_disable_groups[] = { "ur2_loc" }; +static const char * const rtd1619b_gspi_disable_groups[] = { "gspi_loc" }; +static const char * const rtd1619b_sdio_disable_groups[] = { "sdio_loc" }; +static const char * const rtd1619b_hi_loc_disable_groups[] = { "hi_loc" }; +static const char * const rtd1619b_hi_loc0_groups[] = { "hi_loc" }; +static const char * const rtd1619b_hi_width_disable_groups[] = { "hi_width" }; +static const char * const rtd1619b_hi_width_1bit_groups[] = { "hi_width" }; + +static const char * const rtd1619b_vtc_i2si_loc0_groups[] = { + "gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_vtc_tdm_loc0_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_vtc_dmic_loc0_groups[] = { + "hif_data", "hif_en", "hif_rdy", "hif_clk" }; +static const char * const rtd1619b_vtc_i2si_loc1_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61" }; +static const char * const rtd1619b_vtc_tdm_loc1_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60" }; +static const char * const rtd1619b_vtc_dmic_loc1_groups[] = { + "gpio_57", "gpio_58", "gpio_59", "gpio_60" }; +static const char * const rtd1619b_vtc_i2so_groups[] = { + "gpio_66", "gpio_67", "gpio_68", "gpio_69" }; +static const char * const rtd1619b_ve3_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_ve3_loc" }; +static const char * const rtd1619b_aucpu0_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_aucpu0_loc" }; +static const char * const rtd1619b_aucpu1_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_aucpu1_loc" }; +static const char * const rtd1619b_ve3_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_ve3_loc" }; +static const char * const rtd1619b_aucpu0_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_aucpu0_loc" }; +static const char * const rtd1619b_aucpu1_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_aucpu1_loc" }; + +static const char * const rtd1619b_ve3_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_ve3_loc" }; +static const char * const rtd1619b_aucpu0_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_aucpu0_loc" }; +static const char * const rtd1619b_aucpu1_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_aucpu1_loc" }; + +static const char * const rtd1619b_scpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_scpu_loc" }; +static const char * const rtd1619b_acpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_acpu_loc" }; +static const char * const rtd1619b_vcpu_ejtag_loc0_groups[] = { + "gpio_2", "gpio_3", "gpio_4", + "gpio_5", "gpio_6", "ejtag_vcpu_loc" }; +static const char * const rtd1619b_scpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_scpu_loc" }; +static const char * const rtd1619b_acpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_acpu_loc" }; +static const char * const rtd1619b_vcpu_ejtag_loc1_groups[] = { + "gpio_32", "gpio_33", "hif_data", "hif_en", + "hif_clk", "ejtag_vcpu_loc" }; + +static const char * const rtd1619b_scpu_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_scpu_loc" }; +static const char * const rtd1619b_acpu_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_acpu_loc" }; +static const char * const rtd1619b_vcpu_ejtag_loc2_groups[] = { + "gpio_71", "gpio_72", "gpio_73", "gpio_74", + "gpio_75", "gpio_76", "ejtag_vcpu_loc"}; +static const char * const rtd1619b_ve3_ejtag_disable_groups[] = { "ejtag_ve3_loc" }; +static const char * const rtd1619b_aucpu0_ejtag_disable_groups[] = { "ejtag_aucpu0_loc" }; +static const char * const rtd1619b_aucpu1_ejtag_disable_groups[] = { "ejtag_aucpu1_loc" }; + +static const char * const rtd1619b_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" }; +static const char * const rtd1619b_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" }; +static const char * const rtd1619b_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" }; +static const char * const rtd1619b_sf_disable_groups[] = { "sf_en" }; +static const char * const rtd1619b_sf_enable_groups[] = { "sf_en" }; +static const char * const rtd1619b_iso_gspi_disable_groups[] = { "iso_gspi_loc" }; +static const char * const rtd1619b_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1619b_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" }; +static const char * const rtd1619b_pwm_normal_groups[] = { + "pwm_01_open_drain_en_loc0", "pwm_23_open_drain_en_loc0", + "pwm_01_open_drain_en_loc1", "pwm_23_open_drain_en_loc1" }; +static const char * const rtd1619b_pwm_open_drain_groups[] = { + "pwm_01_open_drain_en_loc0", "pwm_23_open_drain_en_loc0", + "pwm_01_open_drain_en_loc1", "pwm_23_open_drain_en_loc1" }; +static const char * const rtd1619b_standby_dbg_groups[] = { + "gpio_2", "gpio_3", "ir_rx" }; + +static const char * const rtd1619b_usb_cc1_groups[] = { "usb_cc1" }; +static const char * const rtd1619b_usb_cc2_groups[] = { "usb_cc2" }; +static const char * const rtd1619b_ir_rx_groups[] = { "ir_rx" }; +static const char * const rtd1619b_test_loop_dis_groups[] = { "gpio_50" }; + +#define RTD1619B_FUNC(_name) \ + { \ + .name = # _name, \ + .groups = rtd1619b_ ## _name ## _groups, \ + .num_groups = ARRAY_SIZE(rtd1619b_ ## _name ## _groups), \ + } + +static const struct rtd_pin_func_desc rtd1619b_pin_functions[] = { + RTD1619B_FUNC(gpio), + RTD1619B_FUNC(nf), + RTD1619B_FUNC(nf_spi), + RTD1619B_FUNC(spi), + RTD1619B_FUNC(pmic), + RTD1619B_FUNC(spdif), + RTD1619B_FUNC(spdif_coaxial), + RTD1619B_FUNC(spdif_optical_loc0), + RTD1619B_FUNC(spdif_optical_loc1), + RTD1619B_FUNC(emmc_spi), + RTD1619B_FUNC(emmc), + RTD1619B_FUNC(sc1), + RTD1619B_FUNC(uart0), + RTD1619B_FUNC(uart1), + RTD1619B_FUNC(uart2_loc0), + RTD1619B_FUNC(uart2_loc1), + RTD1619B_FUNC(gspi_loc1), + RTD1619B_FUNC(iso_gspi_loc1), + RTD1619B_FUNC(i2c0), + RTD1619B_FUNC(i2c1), + RTD1619B_FUNC(i2c3), + RTD1619B_FUNC(i2c4), + RTD1619B_FUNC(i2c5), + RTD1619B_FUNC(pwm0), + RTD1619B_FUNC(pwm1), + RTD1619B_FUNC(pwm2), + RTD1619B_FUNC(pwm3), + RTD1619B_FUNC(etn_led), + RTD1619B_FUNC(etn_phy), + RTD1619B_FUNC(etn_clk), + RTD1619B_FUNC(sc0), + RTD1619B_FUNC(vfd), + RTD1619B_FUNC(gspi_loc0), + RTD1619B_FUNC(iso_gspi_loc0), + RTD1619B_FUNC(pcie1), + RTD1619B_FUNC(pcie2), + RTD1619B_FUNC(sd), + RTD1619B_FUNC(sdio_loc0), + RTD1619B_FUNC(sdio_loc1), + RTD1619B_FUNC(hi), + RTD1619B_FUNC(hi_m), + RTD1619B_FUNC(dc_fan), + RTD1619B_FUNC(pll_test_loc0), + RTD1619B_FUNC(pll_test_loc1), + RTD1619B_FUNC(usb_cc1), + RTD1619B_FUNC(usb_cc2), + RTD1619B_FUNC(ir_rx), + RTD1619B_FUNC(tdm_ai_loc0), + RTD1619B_FUNC(tdm_ai_loc1), + RTD1619B_FUNC(dmic_loc0), + RTD1619B_FUNC(dmic_loc1), + RTD1619B_FUNC(ai_loc0), + RTD1619B_FUNC(ai_loc1), + RTD1619B_FUNC(tp0), + RTD1619B_FUNC(tp1), + RTD1619B_FUNC(ao), + RTD1619B_FUNC(uart2_disable), + RTD1619B_FUNC(gspi_disable), + RTD1619B_FUNC(sdio_disable), + RTD1619B_FUNC(hi_loc_disable), + RTD1619B_FUNC(hi_loc0), + RTD1619B_FUNC(hi_width_disable), + RTD1619B_FUNC(hi_width_1bit), + RTD1619B_FUNC(vtc_i2si_loc0), + RTD1619B_FUNC(vtc_tdm_loc0), + RTD1619B_FUNC(vtc_dmic_loc0), + RTD1619B_FUNC(vtc_i2si_loc1), + RTD1619B_FUNC(vtc_tdm_loc1), + RTD1619B_FUNC(vtc_dmic_loc1), + RTD1619B_FUNC(vtc_i2so), + RTD1619B_FUNC(ve3_ejtag_loc0), + RTD1619B_FUNC(aucpu0_ejtag_loc0), + RTD1619B_FUNC(aucpu1_ejtag_loc0), + RTD1619B_FUNC(ve3_ejtag_loc1), + RTD1619B_FUNC(aucpu0_ejtag_loc1), + RTD1619B_FUNC(aucpu1_ejtag_loc1), + RTD1619B_FUNC(ve3_ejtag_loc2), + RTD1619B_FUNC(aucpu0_ejtag_loc2), + RTD1619B_FUNC(aucpu1_ejtag_loc2), + RTD1619B_FUNC(scpu_ejtag_loc0), + RTD1619B_FUNC(acpu_ejtag_loc0), + RTD1619B_FUNC(vcpu_ejtag_loc0), + RTD1619B_FUNC(scpu_ejtag_loc1), + RTD1619B_FUNC(acpu_ejtag_loc1), + RTD1619B_FUNC(vcpu_ejtag_loc1), + RTD1619B_FUNC(scpu_ejtag_loc2), + RTD1619B_FUNC(acpu_ejtag_loc2), + RTD1619B_FUNC(vcpu_ejtag_loc2), + RTD1619B_FUNC(ve3_ejtag_disable), + RTD1619B_FUNC(aucpu0_ejtag_disable), + RTD1619B_FUNC(aucpu1_ejtag_disable), + RTD1619B_FUNC(acpu_ejtag_disable), + RTD1619B_FUNC(vcpu_ejtag_disable), + RTD1619B_FUNC(scpu_ejtag_disable), + RTD1619B_FUNC(iso_gspi_disable), + RTD1619B_FUNC(sf_disable), + RTD1619B_FUNC(sf_enable), + RTD1619B_FUNC(arm_trace_debug_disable), + RTD1619B_FUNC(arm_trace_debug_enable), + RTD1619B_FUNC(pwm_normal), + RTD1619B_FUNC(pwm_open_drain), + RTD1619B_FUNC(standby_dbg), + RTD1619B_FUNC(test_loop_dis), +}; + +#undef RTD1619B_FUNC + +static const struct rtd_pin_desc rtd1619b_iso_muxes[] = { + [RTD1619B_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc")), + [RTD1619B_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "emmc")), + [RTD1619B_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc")), + [RTD1619B_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "emmc")), + [RTD1619B_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(13, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(15, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x0, GENMASK(17, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x0, GENMASK(19, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "emmc"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "nf_spi")), + [RTD1619B_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x0, GENMASK(21, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc")), + [RTD1619B_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x0, GENMASK(23, 22), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 22), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 22), "emmc")), + [RTD1619B_ISO_SPI_CE_N] = RTK_PIN_MUX(spi_ce_n, 0x0, GENMASK(25, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "pmic")), + [RTD1619B_ISO_SPI_SCK] = RTK_PIN_MUX(spi_sck, 0x0, GENMASK(27, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "spi")), + [RTD1619B_ISO_SPI_SO] = RTK_PIN_MUX(spi_so, 0x0, GENMASK(29, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "spi")), + [RTD1619B_ISO_SPI_SI] = RTK_PIN_MUX(spi_si, 0x0, GENMASK(31, 30), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 30), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 30), "nf"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 30), "spi")), + + [RTD1619B_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(0, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio")), + [RTD1619B_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(3, 1), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 1), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 1), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 1), "spdif_coaxial")), + [RTD1619B_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x4, GENMASK(7, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 4), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x4, GENMASK(11, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "standby_dbg"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 8), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x4, GENMASK(15, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 12), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x4, GENMASK(19, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 16), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(23, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "emmc_spi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "spdif_optical_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 20), "aucpu1_ejtag_loc0")), + [RTD1619B_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(24, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio")), + [RTD1619B_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x4, GENMASK(27, 25), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 25), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 25), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 25), "iso_gspi_loc1")), + [RTD1619B_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x4, GENMASK(30, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "iso_gspi_loc1")), + [RTD1619B_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(2, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "iso_gspi_loc1")), + [RTD1619B_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(5, 3), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 3), "uart1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 3), "gspi_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 3), "iso_gspi_loc1")), + + [RTD1619B_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(6, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "i2c0")), + [RTD1619B_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(7, 7), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 7), "i2c0")), + [RTD1619B_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(10, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "etn_phy"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "etn_clk")), + [RTD1619B_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(12, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 11), "etn_phy")), + [RTD1619B_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x8, GENMASK(13, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "i2c1")), + [RTD1619B_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x8, GENMASK(14, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "i2c1")), + [RTD1619B_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x8, GENMASK(17, 15), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 15), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 15), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 15), "iso_gspi_loc0")), + [RTD1619B_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x8, GENMASK(20, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 18), "iso_gspi_loc0")), + [RTD1619B_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x8, GENMASK(23, 21), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "pwm0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 21), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 21), "iso_gspi_loc0")), + [RTD1619B_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x8, GENMASK(26, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "pwm1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "spdif_optical_loc1")), + [RTD1619B_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x8, GENMASK(28, 27), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "pwm2")), + [RTD1619B_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x8, GENMASK(30, 29), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 29), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 29), "etn_led"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "pwm3")), + [RTD1619B_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x8, GENMASK(31, 31), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 31), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 31), "usb_cc2")), + [RTD1619B_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "pcie1")), + [RTD1619B_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 2), "pwm0")), + [RTD1619B_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0xc, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "pwm1")), + + [RTD1619B_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0xc, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "uart2_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "vfd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 6), "pwm2")), + [RTD1619B_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0xc, GENMASK(8, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "i2c5")), + [RTD1619B_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0xc, GENMASK(9, 9), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio")), + [RTD1619B_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0xc, GENMASK(12, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 10), "iso_gspi_loc0")), + [RTD1619B_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0xc, GENMASK(17, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 13), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 13), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 13), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 13), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 13), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 13), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 13), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 13), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 13), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 13), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0xc, GENMASK(22, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 18), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 18), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 18), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 18), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 18), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 18), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0xc, GENMASK(25, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 23), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 23), "i2c4")), + [RTD1619B_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0xc, GENMASK(28, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 26), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 26), "i2c4")), + [RTD1619B_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x10, GENMASK(4, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 0), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "hi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 0), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 0), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 0), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 0), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 0), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x10, GENMASK(9, 5), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 5), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 5), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 5), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 5), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 5), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 5), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 5), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 5), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 5), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 5), "hi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 5), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 5), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 5), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 5), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 5), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 5), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 5), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x10, GENMASK(13, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 10), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 10), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 10), "hi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 10), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 10), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 10), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 10), "vtc_dmic_loc0")), + + [RTD1619B_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x10, GENMASK(18, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "sd"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "dmic_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "tdm_ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 14), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 14), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 14), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 14), "ai_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 14), "hi"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 14), "hi_m"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 14), "vtc_i2si_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 14), "vtc_tdm_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 14), "vtc_dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x14, 14), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x15, 14), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x16, 14), "aucpu1_ejtag_loc1")), + [RTD1619B_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x10, GENMASK(20, 19), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "sdio_loc1")), + [RTD1619B_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x10, GENMASK(22, 21), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "sdio_loc1")), + [RTD1619B_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x10, GENMASK(24, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "sdio_loc1")), + [RTD1619B_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x10, GENMASK(26, 25), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 25), "sdio_loc1")), + [RTD1619B_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x10, GENMASK(28, 27), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "sdio_loc1")), + [RTD1619B_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x10, GENMASK(30, 29), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 29), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "sdio_loc1")), + [RTD1619B_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x10, GENMASK(31, 31), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 31), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 31), "i2c5")), + [RTD1619B_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "dc_fan"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "pwm3")), + [RTD1619B_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(2, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "pll_test_loc1")), + [RTD1619B_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x14, GENMASK(3, 3), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 3), "pll_test_loc1")), + [RTD1619B_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x14, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "spdif"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "test_loop_dis")), + [RTD1619B_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x14, GENMASK(6, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "usb_cc1")), + [RTD1619B_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x14, GENMASK(8, 7), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 7), "pll_test_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 7), "pcie2")), + [RTD1619B_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x14, GENMASK(9, 9), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 9), "pll_test_loc0")), + [RTD1619B_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x14, GENMASK(11, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "ir_rx"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "standby_dbg")), + [RTD1619B_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x14, GENMASK(12, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart0")), + + [RTD1619B_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x14, GENMASK(13, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "uart0")), + [RTD1619B_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x14, GENMASK(17, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 14), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 14), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 14), "vtc_dmic_loc1")), + [RTD1619B_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x14, GENMASK(21, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 18), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 18), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 18), "vtc_dmic_loc1")), + [RTD1619B_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x14, GENMASK(25, 22), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 22), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 22), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 22), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 22), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 22), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 22), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 22), "vtc_dmic_loc1")), + [RTD1619B_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x14, GENMASK(29, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "tdm_ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 26), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 26), "vtc_i2si_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x12, 26), "vtc_tdm_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x13, 26), "vtc_dmic_loc1")), + [RTD1619B_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x18, GENMASK(3, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "vtc_i2si_loc1")), + [RTD1619B_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x18, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0")), + [RTD1619B_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x18, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "ai_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 6), "dmic_loc0")), + [RTD1619B_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x18, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "i2c3"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0")), + [RTD1619B_ISO_GPIO_65] = RTK_PIN_MUX(gpio_65, 0x18, GENMASK(10, 10), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio")), + [RTD1619B_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x18, GENMASK(14, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 11), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 11), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 11), "vtc_i2so")), + [RTD1619B_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x18, GENMASK(18, 15), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 15), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 15), "vtc_i2so")), + [RTD1619B_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x18, GENMASK(22, 19), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 19), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 19), "vtc_i2so")), + [RTD1619B_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x18, GENMASK(26, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 23), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x11, 23), "vtc_i2so")), + + [RTD1619B_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x18, GENMASK(29, 27), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 27), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 27), "ao")), + [RTD1619B_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x1c, GENMASK(2, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 0), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x1c, GENMASK(6, 3), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 3), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x3, 3), "tp1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 3), "ao"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 3), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 3), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 3), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 3), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 3), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 3), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_73] = RTK_PIN_MUX(gpio_73, 0x1c, GENMASK(10, 7), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 7), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 7), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 7), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 7), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 7), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 7), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 7), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_74] = RTK_PIN_MUX(gpio_74, 0x1c, GENMASK(14, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 11), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 11), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 11), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 11), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 11), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 11), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 11), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_75] = RTK_PIN_MUX(gpio_75, 0x1c, GENMASK(18, 15), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 15), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 15), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 15), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 15), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 15), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 15), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_GPIO_76] = RTK_PIN_MUX(gpio_76, 0x1c, GENMASK(22, 19), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "tp0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x5, 19), "scpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x6, 19), "acpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x7, 19), "vcpu_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x8, 19), "ve3_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x9, 19), "aucpu0_ejtag_loc2"), + RTK_PIN_FUNC(SHIFT_LEFT(0x10, 19), "aucpu1_ejtag_loc2")), + + [RTD1619B_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")), + [RTD1619B_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")), + [RTD1619B_ISO_SDIO_LOC] = RTK_PIN_MUX(sdio_loc, 0x120, GENMASK(5, 4), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "sdio_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sdio_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "sdio_loc1")), + [RTD1619B_ISO_HI_LOC] = RTK_PIN_MUX(hi_loc, 0x120, GENMASK(7, 6), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "hi_loc_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "hi_loc0")), + [RTD1619B_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")), + [RTD1619B_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")), + [RTD1619B_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")), + [RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0] = RTK_PIN_MUX(pwm_01_open_drain_en_loc0, 0x120, + GENMASK(13, 13), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "pwm_normal"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "pwm_open_drain")), + [RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0] = RTK_PIN_MUX(pwm_23_open_drain_en_loc0, 0x120, + GENMASK(14, 14), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "pwm_normal"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "pwm_open_drain")), + [RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1] = RTK_PIN_MUX(pwm_01_open_drain_en_loc1, 0x120, + GENMASK(15, 15), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "pwm_normal"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 15), "pwm_open_drain")), + [RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1] = RTK_PIN_MUX(pwm_23_open_drain_en_loc1, 0x120, + GENMASK(16, 16), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "pwm_normal"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "pwm_open_drain")), + [RTD1619B_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")), + [RTD1619B_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")), + [RTD1619B_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")), + [RTD1619B_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")), + [RTD1619B_ISO_ISO_GSPI_LOC] = RTK_PIN_MUX(iso_gspi_loc, 0x120, GENMASK(29, 28), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "iso_gspi_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "iso_gspi_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "iso_gspi_loc1")), + [RTD1619B_ISO_EJTAG_VE3_LOC] = RTK_PIN_MUX(ejtag_ve3_loc, 0x124, GENMASK(20, 18), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "ve3_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "ve3_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "ve3_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "ve3_ejtag_loc2")), + [RTD1619B_ISO_EJTAG_AUCPU1_LOC] = RTK_PIN_MUX(ejtag_aucpu1_loc, 0x124, GENMASK(23, 21), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "aucpu1_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "aucpu1_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "aucpu1_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "aucpu1_ejtag_loc2")), + [RTD1619B_ISO_EJTAG_AUCPU0_LOC] = RTK_PIN_MUX(ejtag_aucpu0_loc, 0x124, GENMASK(26, 24), + RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "aucpu0_ejtag_disable"), + RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "aucpu0_ejtag_loc0"), + RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "aucpu0_ejtag_loc1"), + RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "aucpu0_ejtag_loc2")), +}; + +static const struct rtd_pin_config_desc rtd1619b_iso_configs[] = { + [RTD1619B_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x20, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x20, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x20, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_21] = RTK_PIN_CONFIG(gpio_21, 0x20, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x20, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x20, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_68] = RTK_PIN_CONFIG(gpio_68, 0x24, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_69] = RTK_PIN_CONFIG(gpio_69, 0x24, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_70] = RTK_PIN_CONFIG(gpio_70, 0x24, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_71] = RTK_PIN_CONFIG(gpio_71, 0x24, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_72] = RTK_PIN_CONFIG(gpio_72, 0x24, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_73] = RTK_PIN_CONFIG(gpio_73, 0x24, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_74] = RTK_PIN_CONFIG(gpio_74, 0x28, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_75] = RTK_PIN_CONFIG(gpio_75, 0x28, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_76] = RTK_PIN_CONFIG(gpio_76, 0x28, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_SPI_SI] = RTK_PIN_CONFIG(spi_si, 0x28, 15, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_SPI_SCK] = RTK_PIN_CONFIG(spi_sck, 0x2c, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_SPI_CE_N] = RTK_PIN_CONFIG(spi_ce_n, 0x2c, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_SPI_SO] = RTK_PIN_CONFIG(spi_so, 0x2c, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x30, 7, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x34, 0, 0, 1, 3, 2, 13, NA), + [RTD1619B_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x34, 14, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x34, 27, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x38, 8, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x3c, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x3c, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x3c, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x40, 7, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x44, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x44, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x44, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x48, 7, NA, NA, 0, 1, 9, PADDRI_4_8), + [RTD1619B_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x48, 10, NA, NA, 0, 1, 9, PADDRI_4_8), + [RTD1619B_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x48, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x48, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x48, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x4c, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x4c, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x4c, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x4c, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_53] = RTK_PIN_CONFIG(gpio_53, 0x4c, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_65] = RTK_PIN_CONFIG(gpio_65, 0x4c, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x50, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x50, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_23] = RTK_PIN_CONFIG(gpio_23, 0x50, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x50, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x50, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x50, 30, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x54, 3, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x54, 8, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x54, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x54, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_63] = RTK_PIN_CONFIG(gpio_63, 0x54, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x58, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x58, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x58, 13, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x58, 18, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x58, 23, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x58, 28, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x5c, 1, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x5c, 6, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x5c, 11, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x5c, 16, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_22] = RTK_PIN_CONFIG(gpio_22, 0x5c, 21, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x5c, 26, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x60, 12, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x60, 17, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x60, 22, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_5] = RTK_PIN_CONFIG(gpio_5, 0x60, 27, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_4] = RTK_PIN_CONFIG(gpio_4, 0x64, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_3] = RTK_PIN_CONFIG(gpio_3, 0x64, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_2] = RTK_PIN_CONFIG(gpio_2, 0x64, 10, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x64, 15, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_0] = RTK_PIN_CONFIG(gpio_0, 0x64, 20, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_52] = RTK_PIN_CONFIG(gpio_52, 0x64, 25, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x68, 0, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x68, 5, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x68, 10, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x6c, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_42] = RTK_PIN_CONFIG(gpio_42, 0x6c, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_43] = RTK_PIN_CONFIG(gpio_43, 0x70, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_44] = RTK_PIN_CONFIG(gpio_44, 0x70, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x70, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x74, 7, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x74, 12, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x74, 17, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x74, 22, 1, 2, 0, 3, 4, PADDRI_4_8), + [RTD1619B_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x78, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x78, 13, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x78, 26, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x7c, 7, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x80, 0, 0, 1, 3, 2, 12, NA), + [RTD1619B_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x80, 13, 0, 1, 3, 2, 12, NA), +}; + +static const struct rtd_pin_sconfig_desc rtd1619b_iso_sconfigs[] = { + RTK_PIN_SCONFIG(spi_si, 0x28, 18, 3, 21, 3, 24, 3), + RTK_PIN_SCONFIG(spi_sck, 0x2c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(spi_ce_n, 0x2c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(spi_so, 0x2c, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(emmc_clk, 0x30, 10, 3, 13, 3, 16, 3), + RTK_PIN_SCONFIG(emmc_cmd, 0x34, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_rst_n, 0x34, 17, 3, 20, 3, 23, 3), + RTK_PIN_SCONFIG(emmc_dd_sb, 0x34, 30, 3, 33, 3, 36, 3), + RTK_PIN_SCONFIG(emmc_data_5, 0x38, 11, 3, 14, 3, 17, 3), + RTK_PIN_SCONFIG(emmc_data_3, 0x3c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_4, 0x3c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_0, 0x3c, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(emmc_data_1, 0x40, 10, 3, 13, 3, 16, 3), + RTK_PIN_SCONFIG(emmc_data_2, 0x44, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(emmc_data_7, 0x44, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(emmc_data_6, 0x44, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(gpio_40, 0x68, 13, 3, 16, 3, 19, 3), + RTK_PIN_SCONFIG(gpio_41, 0x6c, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_42, 0x6c, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_43, 0x70, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(gpio_44, 0x70, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_45, 0x70, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(hif_rdy, 0x78, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_clk, 0x78, 16, 3, 19, 3, 22, 3), + RTK_PIN_SCONFIG(gpio_32, 0x78, 29, 3, 32, 3, 35, 3), + RTK_PIN_SCONFIG(gpio_33, 0x7c, 10, 3, 13, 3, 16, 3), + RTK_PIN_SCONFIG(hif_data, 0x80, 3, 3, 6, 3, 9, 3), + RTK_PIN_SCONFIG(hif_en, 0x80, 16, 3, 19, 3, 22, 3), +}; + +static const struct rtd_pinctrl_desc rtd1619b_iso_pinctrl_desc = { + .pins = rtd1619b_iso_pins, + .num_pins = ARRAY_SIZE(rtd1619b_iso_pins), + .groups = rtd1619b_pin_groups, + .num_groups = ARRAY_SIZE(rtd1619b_pin_groups), + .functions = rtd1619b_pin_functions, + .num_functions = ARRAY_SIZE(rtd1619b_pin_functions), + .muxes = rtd1619b_iso_muxes, + .num_muxes = ARRAY_SIZE(rtd1619b_iso_muxes), + .configs = rtd1619b_iso_configs, + .num_configs = ARRAY_SIZE(rtd1619b_iso_configs), + .sconfigs = rtd1619b_iso_sconfigs, + .num_sconfigs = ARRAY_SIZE(rtd1619b_iso_sconfigs), +}; + +static int rtd1619b_pinctrl_probe(struct platform_device *pdev) +{ + return rtd_pinctrl_probe(pdev, &rtd1619b_iso_pinctrl_desc); +} + +static const struct of_device_id rtd1619b_pinctrl_of_match[] = { + { .compatible = "realtek,rtd1619b-pinctrl", }, + {}, +}; + +static struct platform_driver rtd1619b_pinctrl_driver = { + .driver = { + .name = "rtd1619b-pinctrl", + .of_match_table = rtd1619b_pinctrl_of_match, + }, + .probe = rtd1619b_pinctrl_probe, +}; + +static int __init rtd1619b_pinctrl_init(void) +{ + return platform_driver_register(&rtd1619b_pinctrl_driver); +} +arch_initcall(rtd1619b_pinctrl_init); + +static void __exit rtd1619b_pinctrl_exit(void) +{ + platform_driver_unregister(&rtd1619b_pinctrl_driver); +} +module_exit(rtd1619b_pinctrl_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Realtek Semiconductor Corporation"); +MODULE_DESCRIPTION("Realtek DHC SoC RTD1619B pinctrl driver"); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c index 73f012823a98..ecf6d2438e21 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c @@ -15,33 +15,81 @@ #include "pinctrl-sunxi.h" static const struct sunxi_desc_pin h616_pins[] = { - /* Internal connection to the AC200 part */ + /* Internally connected to the AC200 part in the H616 SoC */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), - SUNXI_FUNCTION(0x2, "emac1")), /* ERXD1 */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ERXD1 */ + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), - SUNXI_FUNCTION(0x2, "emac1")), /* ERXD0 */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ERXD0 */ + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), - SUNXI_FUNCTION(0x2, "emac1")), /* ECRS_DV */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ECRS_DV */ + SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), - SUNXI_FUNCTION(0x2, "emac1")), /* ERXERR */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ERXERR */ + SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), - SUNXI_FUNCTION(0x2, "emac1")), /* ETXD1 */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ETXD1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), - SUNXI_FUNCTION(0x2, "emac1")), /* ETXD0 */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ETXD0 */ + SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), - SUNXI_FUNCTION(0x2, "emac1")), /* ETXCK */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ETXCK */ + SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), - SUNXI_FUNCTION(0x2, "emac1")), /* ETXEN */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ETXEN */ + SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), - SUNXI_FUNCTION(0x2, "emac1")), /* EMDC */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* EMDC */ + SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), - SUNXI_FUNCTION(0x2, "emac1")), /* EMDIO */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* EMDIO */ + SUNXI_FUNCTION(0x3, "i2s0"), /* DIN0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), - SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), - SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), - SUNXI_FUNCTION(0x2, "pwm5")), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm5"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -148,6 +196,310 @@ static const struct sunxi_desc_pin h616_pins[] = { SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PC_EINT16 */ /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */ + SUNXI_FUNCTION(0x4, "ts0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PD_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */ + SUNXI_FUNCTION(0x4, "ts0"), /* ERR */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PD_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */ + SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PD_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */ + SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PD_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PD_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PD_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */ + SUNXI_FUNCTION(0x4, "ts0"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PD_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */ + SUNXI_FUNCTION(0x4, "ts0"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PD_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PD_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PD_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VP0 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D6 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PD_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VN0 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D7 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PD_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VP1 */ + SUNXI_FUNCTION(0x4, "sim"), /* VPPEN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PD_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VN1 */ + SUNXI_FUNCTION(0x4, "sim"), /* VPPPP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PD_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VP2 */ + SUNXI_FUNCTION(0x4, "sim"), /* PWREN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PD_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VN2 */ + SUNXI_FUNCTION(0x4, "sim"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PD_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VPC */ + SUNXI_FUNCTION(0x4, "sim"), /* DATA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PD_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VNC */ + SUNXI_FUNCTION(0x4, "sim"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PD_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VP3 */ + SUNXI_FUNCTION(0x4, "sim"), /* DET */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), /* PD_EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VN3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), /* PD_EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)), /* PD_EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)), /* PD_EINT21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)), /* PD_EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)), /* PD_EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 24)), /* PD_EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 25)), /* PD_EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 26)), /* PD_EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 27)), /* PD_EINT27 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 28)), /* PD_EINT28 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PE_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PE_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PE_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PE_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PE_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PE_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PE_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PE_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PE_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PE_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PE_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PE_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D8 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PE_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D9 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PE_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D10 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PE_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D11 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PE_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D12 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PE_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D13 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PE_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D14 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PE_EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D15 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 19)), /* PE_EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 20)), /* PE_EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 21)), /* PE_EINT21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* FSIN0 */ + SUNXI_FUNCTION(0x4, "tcon0"), /* TRIG0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 22)), /* PE_EINT22 */ + /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), |