diff options
75 files changed, 947 insertions, 1847 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index f79854783c2c..5bf77f6dd19d 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -129,7 +129,7 @@ Optional properties: example: -display@di0 { +disp0 { compatible = "fsl,imx-parallel-display"; edid = [edid-data]; interface-pix-fmt = "rgb24"; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 023bfdb3e63f..c04f44a90392 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -382,6 +382,8 @@ static int acp_hw_init(void *handle) adev->acp.acp_cell[0].name = "acp_audio_dma"; adev->acp.acp_cell[0].num_resources = 4; adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; + adev->acp.acp_cell[0].platform_data = &adev->asic_type; + adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); adev->acp.acp_cell[1].name = "designware-i2s"; adev->acp.acp_cell[1].num_resources = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index c21adf60a7f2..057e1ecd83ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -59,12 +59,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size) return false; } - tmp = bios[0x18] | (bios[0x19] << 8); - if (bios[tmp + 0x14] != 0x0) { - DRM_INFO("Not an x86 BIOS ROM\n"); - return false; - } - bios_header_start = bios[0x48] | (bios[0x49] << 8); if (!bios_header_start) { DRM_INFO("Can't locate bios header\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index f7fceb63413c..bdef497a6a26 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1497,8 +1497,11 @@ out: memset(wait, 0, sizeof(*wait)); wait->out.status = (r > 0); wait->out.first_signaled = first; - /* set return value 0 to indicate success */ - r = array[first]->error; + + if (first < fence_count && array[first]) + r = array[first]->error; + else + r = 0; err_free_fence_array: for (i = 0; i < fence_count; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index efcacb827de7..2c85e0a98608 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1836,6 +1836,9 @@ static int amdgpu_fini(struct amdgpu_device *adev) adev->ip_blocks[i].status.hw = false; } + if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) + amdgpu_ucode_fini_bo(adev); + for (i = adev->num_ip_blocks - 1; i >= 0; i--) { if (!adev->ip_blocks[i].status.sw) continue; @@ -3188,9 +3191,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, pm_pg_lock = (*pos >> 23) & 1; if (*pos & (1ULL << 62)) { - se_bank = (*pos >> 24) & 0x3FF; - sh_bank = (*pos >> 34) & 0x3FF; - instance_bank = (*pos >> 44) & 0x3FF; + se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; + sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; + instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; if (se_bank == 0x3FF) se_bank = 0xFFFFFFFF; @@ -3264,9 +3267,9 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, pm_pg_lock = (*pos >> 23) & 1; if (*pos & (1ULL << 62)) { - se_bank = (*pos >> 24) & 0x3FF; - sh_bank = (*pos >> 34) & 0x3FF; - instance_bank = (*pos >> 44) & 0x3FF; + se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24; + sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34; + instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44; if (se_bank == 0x3FF) se_bank = 0xFFFFFFFF; @@ -3614,12 +3617,12 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, return -EINVAL; /* decode offset */ - offset = (*pos & 0x7F); - se = ((*pos >> 7) & 0xFF); - sh = ((*pos >> 15) & 0xFF); - cu = ((*pos >> 23) & 0xFF); - wave = ((*pos >> 31) & 0xFF); - simd = ((*pos >> 37) & 0xFF); + offset = (*pos & GENMASK_ULL(6, 0)); + se = (*pos & GENMASK_ULL(14, 7)) >> 7; + sh = (*pos & GENMASK_ULL(22, 15)) >> 15; + cu = (*pos & GENMASK_ULL(30, 23)) >> 23; + wave = (*pos & GENMASK_ULL(36, 31)) >> 31; + simd = (*pos & GENMASK_ULL(44, 37)) >> 37; /* switch to the specific se/sh/cu */ mutex_lock(&adev->grbm_idx_mutex); @@ -3664,14 +3667,14 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, return -EINVAL; /* decode offset */ - offset = (*pos & 0xFFF); /* in dwords */ - se = ((*pos >> 12) & 0xFF); - sh = ((*pos >> 20) & 0xFF); - cu = ((*pos >> 28) & 0xFF); - wave = ((*pos >> 36) & 0xFF); - simd = ((*pos >> 44) & 0xFF); - thread = ((*pos >> 52) & 0xFF); - bank = ((*pos >> 60) & 1); + offset = *pos & GENMASK_ULL(11, 0); + se = (*pos & GENMASK_ULL(19, 12)) >> 12; + sh = (*pos & GENMASK_ULL(27, 20)) >> 20; + cu = (*pos & GENMASK_ULL(35, 28)) >> 28; + wave = (*pos & GENMASK_ULL(43, 36)) >> 36; + simd = (*pos & GENMASK_ULL(51, 44)) >> 44; + thread = (*pos & GENMASK_ULL(59, 52)) >> 52; + bank = (*pos & GENMASK_ULL(61, 60)) >> 60; data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL); if (!data) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index fb72edc4c026..14aff2f15a94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -63,6 +63,11 @@ retry: flags, NULL, resv, 0, &bo); if (r) { if (r != -ERESTARTSYS) { + if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) { + flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + goto retry; + } + if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { initial_domain |= AMDGPU_GEM_DOMAIN_GTT; goto retry; @@ -323,7 +328,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, bo->tbo.ttm->pages); if (r) - goto unlock_mmap_sem; + goto release_object; r = amdgpu_bo_reserve(bo, true); if (r) @@ -348,9 +353,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, free_pages: release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages, false); -unlock_mmap_sem: - up_read(¤t->mm->mmap_sem); - release_object: drm_gem_object_put_unlocked(gobj); @@ -556,9 +558,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { dev_err(&dev->pdev->dev, - "va_address 0x%lX is in reserved area 0x%X\n", - (unsigned long)args->va_address, - AMDGPU_VA_RESERVED_SIZE); + "va_address 0x%LX is in reserved area 0x%LX\n", + args->va_address, AMDGPU_VA_RESERVED_SIZE); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 33535d347734..00e0ce10862f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -71,12 +71,6 @@ static int amdgpu_gtt_mgr_fini(struct ttm_mem_type_manager *man) { struct amdgpu_gtt_mgr *mgr = man->priv; - spin_lock(&mgr->lock); - if (!drm_mm_clean(&mgr->mm)) { - spin_unlock(&mgr->lock); - return -EBUSY; - } - drm_mm_takedown(&mgr->mm); spin_unlock(&mgr->lock); kfree(mgr); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index a59e04f3eeba..ce00f629dcce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -946,6 +946,10 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj, struct amdgpu_device *adev = dev_get_drvdata(dev); umode_t effective_mode = attr->mode; + /* no skipping for powerplay */ + if (adev->powerplay.cgs_device) + return effective_mode; + /* Skip limit attributes if DPM is not enabled */ if (!adev->pm.dpm_enabled && (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index 5f5aa5fddc16..033fba2def6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -164,9 +164,6 @@ static int amdgpu_pp_hw_fini(void *handle) ret = adev->powerplay.ip_funcs->hw_fini( adev->powerplay.pp_handle); - if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) - amdgpu_ucode_fini_bo(adev); - return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c index 90af8e82b16a..ae9c106979d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c @@ -169,10 +169,14 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, int flags) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); + struct dma_buf *buf; if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) return ERR_PTR(-EPERM); - return drm_gem_prime_export(dev, gobj, flags); + buf = drm_gem_prime_export(dev, gobj, flags); + if (!IS_ERR(buf)) + buf->file->f_mapping = dev->anon_inode->i_mapping; + return buf; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 447d446b5015..7714f4a6c8b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -442,8 +442,6 @@ static int psp_hw_fini(void *handle) if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) return 0; - amdgpu_ucode_fini_bo(adev); - psp_ring_destroy(psp, PSP_RING_TYPE__KM); amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index e5ece1fae149..a98fbbb4739f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -136,7 +136,8 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring) if (ring->funcs->end_use) ring->funcs->end_use(ring); - amdgpu_ring_lru_touch(ring->adev, ring); + if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) + amdgpu_ring_lru_touch(ring->adev, ring); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index b577b717caa0..1f036af85ba6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1193,9 +1193,6 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, unsigned long num_pages = bo->mem.num_pages; struct drm_mm_node *node = bo->mem.mm_node; - if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET) - return ttm_bo_eviction_valuable(bo, place); - switch (bo->mem.mem_type) { case TTM_PL_TT: return true; @@ -1210,7 +1207,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, num_pages -= node->size; ++node; } - break; + return false; default: break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index b46280c1279f..2918de2f39ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -648,7 +648,7 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx) uint32_t allocated = 0; uint32_t tmp, handle = 0; uint32_t *size = &tmp; - int i, r, idx = 0; + int i, r = 0, idx = 0; p->job->vm = NULL; ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 4e4a476593e8..6738df836a70 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -114,18 +114,19 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) { signed long r; + unsigned long flags; uint32_t val, seq; struct amdgpu_kiq *kiq = &adev->gfx.kiq; struct amdgpu_ring *ring = &kiq->ring; BUG_ON(!ring->funcs->emit_rreg); - spin_lock(&kiq->ring_lock); + spin_lock_irqsave(&kiq->ring_lock, flags); amdgpu_ring_alloc(ring, 32); amdgpu_ring_emit_rreg(ring, reg); amdgpu_fence_emit_polling(ring, &seq); amdgpu_ring_commit(ring); - spin_unlock(&kiq->ring_lock); + spin_unlock_irqrestore(&kiq->ring_lock, flags); r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); if (r < 1) { @@ -140,18 +141,19 @@ uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) { signed long r; + unsigned long flags; uint32_t seq; struct amdgpu_kiq *kiq = &adev->gfx.kiq; struct amdgpu_ring *ring = &kiq->ring; BUG_ON(!ring->funcs->emit_wreg); - spin_lock(&kiq->ring_lock); + spin_lock_irqsave(&kiq->ring_lock, flags); amdgpu_ring_alloc(ring, 32); amdgpu_ring_emit_wreg(ring, reg, v); amdgpu_fence_emit_polling(ring, &seq); amdgpu_ring_commit(ring); - spin_unlock(&kiq->ring_lock); + spin_unlock_irqrestore(&kiq->ring_lock, flags); r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); if (r < 1) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 010d14195a5e..c8c26f21993c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1244,7 +1244,7 @@ static void amdgpu_vm_invalidate_level(struct amdgpu_vm *vm, int amdgpu_vm_update_directories(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - int r; + int r = 0; spin_lock(&vm->status_lock); while (!list_empty(&vm->relocated)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index aa914256b4bc..bae77353447b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -94,7 +94,8 @@ struct amdgpu_bo_list_entry; #define AMDGPU_MMHUB 1 /* hardcode that limit for now */ -#define AMDGPU_VA_RESERVED_SIZE (8 << 20) +#define AMDGPU_VA_RESERVED_SIZE (8ULL << 20) + /* max vmids dedicated for process */ #define AMDGPU_VM_MAX_RESERVED_VMID 1 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 26e900627971..4acca92f6a52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -68,11 +68,6 @@ static int amdgpu_vram_mgr_fini(struct ttm_mem_type_manager *man) struct amdgpu_vram_mgr *mgr = man->priv; spin_lock(&mgr->lock); - if (!drm_mm_clean(&mgr->mm)) { - spin_unlock(&mgr->lock); - return -EBUSY; - } - drm_mm_takedown(&mgr->mm); spin_unlock(&mgr->lock); kfree(mgr); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 00868764a0dd..5c8a7a48a4ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4670,6 +4670,14 @@ static int gfx_v7_0_sw_fini(void *handle) gfx_v7_0_cp_compute_fini(adev); gfx_v7_0_rlc_fini(adev); gfx_v7_0_mec_fini(adev); + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); + if (adev->gfx.rlc.cp_table_size) { + amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, + &adev->gfx.rlc.cp_table_gpu_addr, + (void **)&adev->gfx.rlc.cp_table_ptr); + } gfx_v7_0_free_microcode(adev); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index b8002ac3e536..9ecdf621a74a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -2118,6 +2118,15 @@ static int gfx_v8_0_sw_fini(void *handle) gfx_v8_0_mec_fini(adev); gfx_v8_0_rlc_fini(adev); + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); + if ((adev->asic_type == CHIP_CARRIZO) || + (adev->asic_type == CHIP_STONEY)) { + amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, + &adev->gfx.rlc.cp_table_gpu_addr, + (void **)&adev->gfx.rlc.cp_table_ptr); + } gfx_v8_0_free_microcode(adev); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 7f15bb2c5233..da43813d67a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -207,6 +207,12 @@ static const u32 golden_settings_gc_9_1_rv1[] = SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800 }; +static const u32 golden_settings_gc_9_x_common[] = +{ + SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000, + SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382 +}; + #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042 @@ -242,6 +248,9 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) default: break; } + + amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common, + (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common)); } static void gfx_v9_0_scratch_init(struct amdgpu_device *adev) @@ -988,12 +997,22 @@ static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, start + SQIND_WAVE_SGPRS_OFFSET, size, dst); } +static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, + uint32_t wave, uint32_t thread, + uint32_t start, uint32_t size, + uint32_t *dst) +{ + wave_read_regs( + adev, simd, wave, thread, + start + SQIND_WAVE_VGPRS_OFFSET, size, dst); +} static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, .select_se_sh = &gfx_v9_0_select_se_sh, .read_wave_data = &gfx_v9_0_read_wave_data, .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, + .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, }; static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev) @@ -1449,6 +1468,14 @@ static int gfx_v9_0_sw_fini(void *handle) gfx_v9_0_mec_fini(adev); gfx_v9_0_ngg_fini(adev); + amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, + &adev->gfx.rlc.clear_state_gpu_addr, + (void **)&adev->gfx.rlc.cs_ptr); + if (adev->asic_type == CHIP_RAVEN) { + amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, + &adev->gfx.rlc.cp_table_gpu_addr, + (void **)&adev->gfx.rlc.cp_table_ptr); + } gfx_v9_0_free_microcode(adev); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 621699331e09..c8f1aebeac7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -392,7 +392,16 @@ static int gmc_v9_0_early_init(void *handle) static int gmc_v9_0_late_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 3, 3 }; + /* + * The latest engine allocation on gfx9 is: + * Engine 0, 1: idle + * Engine 2, 3: firmware + * Engine 4~13: amdgpu ring, subject to change when ring number changes + * Engine 14~15: idle + * Engine 16: kfd tlb invalidation + * Engine 17: Gart flushes + */ + unsigned vm_inv_eng[AMDGPU_MAX_VMHUBS] = { 4, 4 }; unsigned i; for(i = 0; i < adev->num_rings; ++i) { @@ -405,9 +414,9 @@ static int gmc_v9_0_late_init(void *handle) ring->funcs->vmhub); } - /* Engine 17 is used for GART flushes */ + /* Engine 16 is used for KFD and 17 for GART flushes */ for(i = 0; i < AMDGPU_MAX_VMHUBS; ++i) - BUG_ON(vm_inv_eng[i] > 17); + BUG_ON(vm_inv_eng[i] > 16); return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); } diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index de6fc2731b98..b72f8a43d86b 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -23,36 +23,11 @@ #ifndef __AMD_SHARED_H__ #define __AMD_SHARED_H__ -#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ +#include <drm/amd_asic_type.h> struct seq_file; -/* - * Supported ASIC types - */ -enum amd_asic_type { - CHIP_TAHITI = 0, - CHIP_PITCAIRN, - CHIP_VERDE, - CHIP_OLAND, - CHIP_HAINAN, - CHIP_BONAIRE, - CHIP_KAVERI, - CHIP_KABINI, - CHIP_HAWAII, - CHIP_MULLINS, - CHIP_TOPAZ, - CHIP_TONGA, - CHIP_FIJI, - CHIP_CARRIZO, - CHIP_STONEY, - CHIP_POLARIS10, - CHIP_POLARIS11, - CHIP_POLARIS12, - CHIP_VEGA10, - CHIP_RAVEN, - CHIP_LAST, -}; +#define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ /* * Chip flags diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c index a129bc5b1844..c6febbf0bf69 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c @@ -1486,7 +1486,7 @@ int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, if (vddci_id_buf[i] == virtual_voltage_id) { for (j = 0; j < profile->ucLeakageBinNum; j++) { if (efuse_voltage_id <= leakage_bin[j]) { - *vddci = vddci_buf[j * profile->ucElbVDDC_Num + i]; + *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; break; } } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c index d1af1483c69b..a651ebcf44fd 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c @@ -830,9 +830,9 @@ static int init_over_drive_limits( const ATOM_Tonga_POWERPLAYTABLE *powerplay_table) { hwmgr->platform_descriptor.overdriveLimit.engineClock = - le16_to_cpu(powerplay_table->ulMaxODEngineClock); + le32_to_cpu(powerplay_table->ulMaxODEngineClock); hwmgr->platform_descriptor.overdriveLimit.memoryClock = - le16_to_cpu(powerplay_table->ulMaxODMemoryClock); + le32_to_cpu(powerplay_table->ulMaxODMemoryClock); hwmgr->platform_descriptor.minOverdriveVDDC = 0; hwmgr->platform_descriptor.maxOverdriveVDDC = 0; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index 4466469cf8ab..e33ec7fc5d09 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -3778,7 +3778,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) "Trying to Unfreeze MCLK DPM when DPM is disabled", ); PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, - PPSMC_MSG_SCLKDPM_UnfreezeLevel), + PPSMC_MSG_MCLKDPM_UnfreezeLevel), "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", return -EINVAL); } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 4239b98cf6db..f8d838c2c8ee 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -753,6 +753,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) uint32_t config_telemetry = 0; struct pp_atomfwctrl_voltage_table vol_table; struct cgs_system_info sys_info = {0}; + uint32_t reg; data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL); if (data == NULL) @@ -859,6 +860,16 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) advanceFanControlParameters.usFanPWMMinLimit * hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100; + reg = soc15_get_register_offset(DF_HWID, 0, + mmDF_CS_AON0_DramBaseAddress0_BASE_IDX, + mmDF_CS_AON0_DramBaseAddress0); + data->mem_channels = (cgs_read_register(hwmgr->device, reg) & + DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> + DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; + PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number), + "Mem Channel Index Exceeded maximum!", + return -EINVAL); + return result; } @@ -1777,7 +1788,7 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) struct vega10_single_dpm_table *dpm_table = &(data->dpm_table.mem_table); int result = 0; - uint32_t i, j, reg, mem_channels; + uint32_t i, j; for (i = 0; i < dpm_table->count; i++) { result = vega10_populate_single_memory_level(hwmgr, @@ -1801,16 +1812,10 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) i++; } - reg = soc15_get_register_offset(DF_HWID, 0, - mmDF_CS_AON0_DramBaseAddress0_BASE_IDX, - mmDF_CS_AON0_DramBaseAddress0); - mem_channels = (cgs_read_register(hwmgr->device, reg) & - DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >> - DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; - pp_table->NumMemoryChannels = cpu_to_le16(mem_channels); + pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels); pp_table->MemoryChannelWidth = - cpu_to_le16(HBM_MEMORY_CHANNEL_WIDTH * - channel_number[mem_channels]); + (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH * + channel_number[data->mem_channels]); pp_table->LowestUclkReservedForUlv = (uint8_t)(data->lowest_uclk_reserved_for_ulv); @@ -3134,6 +3139,8 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, minimum_clocks.memoryClock = hwmgr->display_config.min_mem_set_clock; if (PP_CAP(PHM_PlatformCaps_StablePState)) { + stable_pstate_sclk_dpm_percentage = + data->registry_data.stable_pstate_sclk_dpm_percentage; PP_ASSERT_WITH_CODE( data->registry_data.stable_pstate_sclk_dpm_percentage >= 1 && data->registry_data.stable_pstate_sclk_dpm_percentage <= 100, diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h index b4b461c3b8ee..8f7358cc3327 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h @@ -389,6 +389,7 @@ struct vega10_hwmgr { uint32_t config_telemetry; uint32_t smu_version; uint32_t acg_loop_state; + uint32_t mem_channels; }; #define VEGA10_DPM2_NEAR_TDP_DEC 10 diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c index 704fc8934616..25f4b2e9a44f 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -234,6 +234,10 @@ int drm_connector_init(struct drm_device *dev, config->link_status_property, 0); + drm_object_attach_property(&connector->base, + config->non_desktop_property, + 0); + if (drm_core_check_feature(dev, DRIVER_ATOMIC)) { drm_object_attach_property(&connector->base, config->prop_crtc_id, 0); } @@ -763,6 +767,10 @@ DRM_ENUM_NAME_FN(drm_get_tv_subconnector_name, * value of link-status is "GOOD". If something fails during or after modeset, * the kernel driver may set this to "BAD" and issue a hotplug uevent. Drivers * should update this value using drm_mode_connector_set_link_status_property(). + * non_desktop: + * Indicates the output should be ignored for purposes of displaying a + * standard desktop environment or console. This is most likely because + * the output device is not rectilinear. * * Connectors also have one standardized atomic property: * @@ -811,6 +819,11 @@ int drm_connector_create_standard_properties(struct drm_device *dev) return -ENOMEM; dev->mode_config.link_status_property = prop; + prop = drm_property_create_bool(dev, DRM_MODE_PROP_IMMUTABLE, "non-desktop"); + if (!prop) + return -ENOMEM; + dev->mode_config.non_desktop_property = prop; + return 0; } @@ -1194,6 +1207,10 @@ int drm_mode_connector_update_edid_property(struct drm_connector *connector, if (edid) size = EDID_LENGTH * (1 + edid->extensions); + drm_object_property_set_value(&connector->base, + dev->mode_config.non_desktop_property, + connector->display_info.non_desktop); + ret = drm_property_replace_global_blob(dev, &connector->edid_blob_ptr, size, diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 00ddabfbf980..2e8fb51282ef 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -82,6 +82,8 @@ #define EDID_QUIRK_FORCE_6BPC (1 << 10) /* Force 10bpc */ #define EDID_QUIRK_FORCE_10BPC (1 << 11) +/* Non desktop display (i.e. HMD) */ +#define EDID_QUIRK_NON_DESKTOP (1 << 12) struct detailed_mode_closure { struct drm_connector *connector; @@ -157,6 +159,9 @@ static const struct edid_quirk { /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, + + /* HTC Vive VR Headset */ + { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, }; /* @@ -4393,7 +4398,7 @@ static void drm_parse_cea_ext(struct drm_connector *connector, } static void drm_add_display_info(struct drm_connector *connector, - struct edid *edid) + struct edid *edid, u32 quirks) { struct drm_display_info *info = &connector->display_info; @@ -4407,6 +4412,8 @@ static void drm_add_display_info(struct drm_connector *connector, info->max_tmds_clock = 0; info->dvi_dual = false; + info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); + if (edid->revision < 3) return; @@ -4627,7 +4634,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) * To avoid multiple parsing of same block, lets parse that map * from sink info, before parsing CEA modes. */ - drm_add_display_info(connector, edid); + drm_add_display_info(connector, edid, quirks); /* * EDID spec says modes should be preferred in this order: diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 116d1f1337c7..07374008f146 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -2033,6 +2033,9 @@ static bool drm_connector_enabled(struct drm_connector *connector, bool strict) { bool enable; + if (connector->display_info.non_desktop) + return false; + if (strict) enable = connector->status == connector_status_connected; else @@ -2052,7 +2055,8 @@ static void drm_enable_connectors(struct drm_fb_helper *fb_helper, connector = fb_helper->connector_info[i]->connector; enabled[i] = drm_connector_enabled(connector, true); DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id, - enabled[i] ? "yes" : "no"); + connector->display_info.non_desktop ? "non desktop" : enabled[i] ? "yes" : "no"); + any_enabled |= enabled[i]; } diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c index 2affe53f3fda..279c1035c12d 100644 --- a/drivers/gpu/drm/drm_framebuffer.c +++ b/drivers/gpu/drm/drm_framebuffer.c @@ -681,6 +681,7 @@ EXPORT_SYMBOL(drm_framebuffer_init); /** * drm_framebuffer_lookup - look up a drm framebuffer and grab a reference * @dev: drm device + * @file_priv: drm file to check for lease against. * @id: id of the fb object * * If successful, this grabs an additional reference to the framebuffer - diff --git a/drivers/gpu/drm/drm_mode_object.c b/drivers/gpu/drm/drm_mode_object.c index 7c8b2698c6a7..ce4d2fb32810 100644 --- a/drivers/gpu/drm/drm_mode_object.c +++ b/drivers/gpu/drm/drm_mode_object.c @@ -151,6 +151,7 @@ struct drm_mode_object *__drm_mode_object_find(struct drm_device *dev, /** * drm_mode_object_find - look up a drm object with static lifetime + * @dev: drm device * @file_priv: drm file * @id: id of the mode object * @type: type of the mode object diff --git a/drivers/gpu/drm/drm_modeset_lock.c b/drivers/gpu/drm/drm_modeset_lock.c index e123497da0ca..963e23db0fe7 100644 --- a/drivers/gpu/drm/drm_modeset_lock.c +++ b/drivers/gpu/drm/drm_modeset_lock.c @@ -93,7 +93,7 @@ void drm_modeset_lock_all(struct drm_device *dev) struct drm_modeset_acquire_ctx *ctx; int ret; - ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL | __GFP_NOFAIL); if (WARN_ON(!ctx)) return; diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index 19404e34cd59..37a93cdffb4a 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -1030,6 +1030,7 @@ retry: e->event.base.type = DRM_EVENT_FLIP_COMPLETE; e->event.base.length = sizeof(e->event); e->event.vbl.user_data = page_flip->user_data; + e->event.vbl.crtc_id = crtc->base.id; ret = drm_event_reserve_init(dev, file_priv, &e->base, &e->event.base); if (ret) { kfree(e); diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c index 57cc6e37c810..09c1c4ff93ca 100644 --- a/drivers/gpu/drm/drm_vblank.c +++ b/drivers/gpu/drm/drm_vblank.c @@ -299,8 +299,8 @@ u32 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc) u32 vblank; unsigned long flags; - WARN(!dev->driver->get_vblank_timestamp, - "This function requires support for accurate vblank timestamps."); + WARN_ONCE(drm_debug & DRM_UT_VBL && !dev->driver->get_vblank_timestamp, + "This function requires support for accurate vblank timestamps."); spin_lock_irqsave(&dev->vblank_time_lock, flags); diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index 305dc3d4ff77..5a7c9d8abd6b 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -3,6 +3,7 @@ config DRM_EXYNOS depends on OF && DRM && (ARCH_S3C64XX || ARCH_EXYNOS || ARCH_MULTIPLATFORM) select DRM_KMS_HELPER select VIDEOMODE_HELPERS + select SND_SOC_HDMI_CODEC if SND_SOC help Choose this option if you have a Samsung SoC EXYNOS chipset. If M is selected the module will be called exynosdrm. diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 6ce0821590df..dc01342e759a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -95,8 +95,23 @@ static enum drm_mode_status exynos_crtc_mode_valid(struct drm_crtc *crtc, return MODE_OK; } +static bool exynos_crtc_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); + + if (exynos_crtc->ops->mode_fixup) + return exynos_crtc->ops->mode_fixup(exynos_crtc, mode, + adjusted_mode); + + return true; +} + + static const struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = { .mode_valid = exynos_crtc_mode_valid, + .mode_fixup = exynos_crtc_mode_fixup, .atomic_check = exynos_crtc_atomic_check, .atomic_begin = exynos_crtc_atomic_begin, .atomic_flush = exynos_crtc_atomic_flush, diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index f8bae4cb4823..c6847fa708fa 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -136,6 +136,9 @@ struct exynos_drm_crtc_ops { u32 (*get_vblank_counter)(struct exynos_drm_crtc *crtc); enum drm_mode_status (*mode_valid)(struct exynos_drm_crtc *crtc, const struct drm_display_mode *mode); + bool (*mode_fixup)(struct exynos_drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode); int (*atomic_check)(struct exynos_drm_crtc *crtc, struct drm_crtc_state *state); void (*atomic_begin)(struct exynos_drm_crtc *crtc); diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 0109ff40b1db..82d1b7e2febe 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -40,7 +40,7 @@ #include <linux/component.h> #include <linux/mfd/syscon.h> #include <linux/regmap.h> - +#include <sound/hdmi-codec.h> #include <drm/exynos_drm.h> #include <media/cec-notifier.h> @@ -111,15 +111,20 @@ struct hdmi_driver_data { struct string_array_spec clk_muxes; }; +struct hdmi_audio { + struct platform_device *pdev; + struct hdmi_audio_infoframe infoframe; + struct hdmi_codec_params params; + bool mute; +}; + struct hdmi_context { struct drm_encoder encoder; struct device *dev; struct drm_device *drm_dev; struct drm_connector connector; - bool powered; bool dvi_mode; struct delayed_work hotplug_work; - struct drm_display_mode current_mode; struct cec_notifier *notifier; const struct hdmi_driver_data *drv_data; @@ -137,6 +142,11 @@ struct hdmi_context { struct regulator *reg_hdmi_en; struct exynos_drm_clk phy_clk; struct drm_bridge *bridge; + + /* mutex protecting subsequent fields below */ + struct mutex mutex; + struct hdmi_audio audio; + bool powered; }; static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) @@ -298,6 +308,15 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] = { }, }, { + .pixel_clock = 85500000, + .conf = { + 0x01, 0xd1, 0x24, 0x11, 0x40, 0x40, 0xd0, 0x08, + 0x84, 0xa0, 0xd6, 0xd8, 0x45, 0xa0, 0xac, 0x80, + 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, + 0x54, 0x90, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, + }, + }, + { .pixel_clock = 106500000, .conf = { 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08, @@ -768,8 +787,25 @@ static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy) return ret; } +static int hdmi_audio_infoframe_apply(struct hdmi_context *hdata) +{ + struct hdmi_audio_infoframe *infoframe = &hdata->audio.infoframe; + u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)]; + int len; + + len = hdmi_audio_infoframe_pack(infoframe, buf, sizeof(buf)); + if (len < 0) + return len; + + hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC); + hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, len); + + return 0; +} + static void hdmi_reg_infoframes(struct hdmi_context *hdata) { + struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; union hdmi_infoframe frm; u8 buf[25]; int ret; @@ -783,8 +819,7 @@ static void hdmi_reg_infoframes(struct hdmi_context *hdata) return; } - ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, - &hdata->current_mode, false); + ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, m, false); if (!ret) ret = hdmi_avi_infoframe_pack(&frm.avi, buf, sizeof(buf)); if (ret > 0) { @@ -794,8 +829,7 @@ static void hdmi_reg_infoframes(struct hdmi_context *hdata) DRM_INFO("%s: invalid AVI infoframe (%d)\n", __func__, ret); } - ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, - &hdata->current_mode); + ret = drm_hdmi_vendor_infoframe_from_display_mode(&frm.vendor.hdmi, m); if (!ret) ret = hdmi_vendor_infoframe_pack(&frm.vendor.hdmi, buf, sizeof(buf)); @@ -805,15 +839,7 @@ static void hdmi_reg_infoframes(struct hdmi_context *hdata) hdmi_reg_write_buf(hdata, HDMI_VSI_DATA(0), buf + 3, ret - 3); } - ret = hdmi_audio_infoframe_init(&frm.audio); - if (!ret) { - frm.audio.channels = 2; - ret = hdmi_audio_infoframe_pack(&frm.audio, buf, sizeof(buf)); - } - if (ret > 0) { - hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_EVERY_VSYNC); - hdmi_reg_write_buf(hdata, HDMI_AUI_HEADER0, buf, ret); - } + hdmi_audio_infoframe_apply(hdata); } static enum drm_connector_status hdmi_detect(struct drm_connector *connector, @@ -1003,23 +1029,18 @@ static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq) hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); } -static void hdmi_audio_init(struct hdmi_context *hdata) +static void hdmi_audio_config(struct hdmi_context *hdata) { - u32 sample_rate, bits_per_sample; - u32 data_num, bit_ch, sample_frq; - u32 val; - - sample_rate = 44100; - bits_per_sample = 16; + u32 bit_ch = 1; + u32 data_num, val; + int i; - switch (bits_per_sample) { + switch (hdata->audio.params.sample_width) { case 20: data_num = 2; - bit_ch = 1; break; case 24: data_num = 3; - bit_ch = 1; break; default: data_num = 1; @@ -1027,7 +1048,7 @@ static void hdmi_audio_init(struct hdmi_context *hdata) break; } - hdmi_reg_acr(hdata, sample_rate); + hdmi_reg_acr(hdata, hdata->audio.params.sample_rate); hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE @@ -1037,12 +1058,6 @@ static void hdmi_audio_init(struct hdmi_context *hdata) | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN); hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN); - - sample_frq = (sample_rate == 44100) ? 0 : - (sample_rate == 48000) ? 2 : - (sample_rate == 32000) ? 3 : - (sample_rate == 96000) ? 0xa : 0x0; - hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS); hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN); @@ -1066,39 +1081,33 @@ static void hdmi_audio_init(struct hdmi_context *hdata) | HDMI_I2S_SET_SDATA_BIT(data_num) | HDMI_I2S_BASIC_FORMAT); - /* Configure register related to CUV information */ - hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0 - | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH - | HDMI_I2S_COPYRIGHT - | HDMI_I2S_LINEAR_PCM - | HDMI_I2S_CONSUMER_FORMAT); - hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER); - hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0)); - hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2 - | HDMI_I2S_SET_SMP_FREQ(sample_frq)); - hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4, - HDMI_I2S_ORG_SMP_FREQ_44_1 - | HDMI_I2S_WORD_LEN_MAX24_24BITS - | HDMI_I2S_WORD_LEN_MAX_24BITS); + /* Configuration of the audio channel status registers */ + for (i = 0; i < HDMI_I2S_CH_ST_MAXNUM; i++) + hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST(i), + hdata->audio.params.iec.status[i]); hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD); } -static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff) +static void hdmi_audio_control(struct hdmi_context *hdata) { + bool enable = !hdata->audio.mute; + if (hdata->dvi_mode) return; - hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0); - hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ? + hdmi_reg_writeb(hdata, HDMI_AUI_CON, enable ? + HDMI_AVI_CON_EVERY_VSYNC : HDMI_AUI_CON_NO_TRAN); + hdmi_reg_writemask(hdata, HDMI_CON_0, enable ? HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK); } static void hdmi_start(struct hdmi_context *hdata, bool start) { + struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; u32 val = start ? HDMI_TG_EN : 0; - if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE) + if (m->flags & DRM_MODE_FLAG_INTERLACE) val |= HDMI_FIELD_EN; hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN); @@ -1168,7 +1177,7 @@ static void hdmiphy_wait_for_pll(struct hdmi_context *hdata) static void hdmi_v13_mode_apply(struct hdmi_context *hdata) { - struct drm_display_mode *m = &hdata->current_mode; + struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; unsigned int val; hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); @@ -1247,7 +1256,19 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata) static void hdmi_v14_mode_apply(struct hdmi_context *hdata) { - struct drm_display_mode *m = &hdata->current_mode; + struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; + struct drm_display_mode *am = + &hdata->encoder.crtc->state->adjusted_mode; + int hquirk = 0; + + /* + * In case video mode coming from CRTC differs from requested one HDMI + * sometimes is able to almost properly perform conversion - only + * first line is distorted. + */ + if ((m->vdisplay != am->vdisplay) && + (m->hdisplay == 1280 || m->hdisplay == 1024 || m->hdisplay == 1366)) + hquirk = 258; hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal); @@ -1341,8 +1362,9 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata) hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff); hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal); - hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay); - hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay); + hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, + m->htotal - m->hdisplay - hquirk); + hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay + hquirk); hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal); if (hdata->drv_data == &exynos5433_hdmi_driver_data) hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1); @@ -1380,10 +1402,11 @@ static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable) static void hdmiphy_conf_apply(struct hdmi_context *hdata) { + struct drm_display_mode *m = &hdata->encoder.crtc->state->mode; int ret; const u8 *phy_conf; - ret = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000); + ret = hdmi_find_phy_conf(hdata, m->clock * 1000); if (ret < 0) { DRM_ERROR("failed to find hdmiphy conf\n"); return; @@ -1406,28 +1429,14 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) hdmiphy_wait_for_pll(hdata); } +/* Should be called with hdata->mutex mutex held */ static void hdmi_conf_apply(struct hdmi_context *hdata) { hdmi_start(hdata, false); hdmi_conf_init(hdata); - hdmi_audio_init(hdata); + hdmi_audio_config(hdata); hdmi_mode_apply(hdata); - hdmi_audio_control(hdata, true); -} - -static void hdmi_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct hdmi_context *hdata = encoder_to_hdmi(encoder); - struct drm_display_mode *m = adjusted_mode; - - DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n", - m->hdisplay, m->vdisplay, - m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ? - "INTERLACED" : "PROGRESSIVE"); - - drm_mode_copy(&hdata->current_mode, m); + hdmi_audio_control(hdata); } static void hdmi_set_refclk(struct hdmi_context *hdata, bool on) @@ -1439,6 +1448,7 @@ static void hdmi_set_refclk(struct hdmi_context *hdata, bool on) SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0); } +/* Should be called with hdata->mutex mutex held. */ static void hdmiphy_enable(struct hdmi_context *hdata) { if (hdata->powered) @@ -1461,6 +1471,7 @@ static void hdmiphy_enable(struct hdmi_context *hdata) hdata->powered = true; } +/* Should be called with hdata->mutex mutex held. */ static void hdmiphy_disable(struct hdmi_context *hdata) { if (!hdata->powered) @@ -1486,33 +1497,42 @@ static void hdmi_enable(struct drm_encoder *encoder) { struct hdmi_context *hdata = encoder_to_hdmi(encoder); + mutex_lock(&hdata->mutex); + hdmiphy_enable(hdata); hdmi_conf_apply(hdata); + + mutex_unlock(&hdata->mutex); } static void hdmi_disable(struct drm_encoder *encoder) { struct hdmi_context *hdata = encoder_to_hdmi(encoder); - if (!hdata->powered) + mutex_lock(&hdata->mutex); + + if (hdata->powered) { + /* + * The SFRs of VP and Mixer are updated by Vertical Sync of + * Timing generator which is a part of HDMI so the sequence + * to disable TV Subsystem should be as following, + * VP -> Mixer -> HDMI + * + * To achieve such sequence HDMI is disabled together with + * HDMI PHY, via pipe clock callback. + */ + mutex_unlock(&hdata->mutex); + cancel_delayed_work(&hdata->hotplug_work); + cec_notifier_set_phys_addr(hdata->notifier, + CEC_PHYS_ADDR_INVALID); return; + } - /* - * The SFRs of VP and Mixer are updated by Vertical Sync of - * Timing generator which is a part of HDMI so the sequence - * to disable TV Subsystem should be as following, - * VP -> Mixer -> HDMI - * - * To achieve such sequence HDMI is disabled together with HDMI PHY, via - * pipe clock callback. - */ - cancel_delayed_work(&hdata->hotplug_work); - cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID); + mutex_unlock(&hdata->mutex); } static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = { .mode_fixup = hdmi_mode_fixup, - .mode_set = hdmi_mode_set, .enable = hdmi_enable, .disable = hdmi_disable, }; @@ -1521,6 +1541,99 @@ static const struct drm_encoder_funcs exynos_hdmi_encoder_funcs = { .destroy = drm_encoder_cleanup, }; +static void hdmi_audio_shutdown(struct device *dev, void *data) +{ + struct hdmi_context *hdata = dev_get_drvdata(dev); + + mutex_lock(&hdata->mutex); + + hdata->audio.mute = true; + + if (hdata->powered) + hdmi_audio_control(hdata); + + mutex_unlock(&hdata->mutex); +} + +static int hdmi_audio_hw_params(struct device *dev, void *data, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct hdmi_context *hdata = dev_get_drvdata(dev); + + if (daifmt->fmt != HDMI_I2S || daifmt->bit_clk_inv || + daifmt->frame_clk_inv || daifmt->bit_clk_master || + daifmt->frame_clk_master) { + dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, + daifmt->bit_clk_inv, daifmt->frame_clk_inv, + daifmt->bit_clk_master, + daifmt->frame_clk_master); + return -EINVAL; + } + + mutex_lock(&hdata->mutex); + + hdata->audio.params = *params; + + if (hdata->powered) { + hdmi_audio_config(hdata); + hdmi_audio_infoframe_apply(hdata); + } + + mutex_unlock(&hdata->mutex); + + return 0; +} + +static int hdmi_audio_digital_mute(struct device *dev, void *data, bool mute) +{ + struct hdmi_context *hdata = dev_get_drvdata(dev); + + mutex_lock(&hdata->mutex); + + hdata->audio.mute = mute; + + if (hdata->powered) + hdmi_audio_control(hdata); + + mutex_unlock(&hdata->mutex); + + return 0; +} + +static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, + size_t len) +{ + struct hdmi_context *hdata = dev_get_drvdata(dev); + struct drm_connector *connector = &hdata->connector; + + memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); + + return 0; +} + +static const struct hdmi_codec_ops audio_codec_ops = { + .hw_params = hdmi_audio_hw_params, + .audio_shutdown = hdmi_audio_shutdown, + .digital_mute = hdmi_audio_digital_mute, + .get_eld = hdmi_audio_get_eld, +}; + +static int hdmi_register_audio_device(struct hdmi_context *hdata) +{ + struct hdmi_codec_pdata codec_data = { + .ops = &audio_codec_ops, + .max_i2s_channels = 6, + .i2s = 1, + }; + + hdata->audio.pdev = platform_device_register_data( + hdata->dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, + &codec_data, sizeof(codec_data)); + + return PTR_ERR_OR_ZERO(hdata->audio.pdev); +} + static void hdmi_hotplug_work_func(struct work_struct *work) { struct hdmi_context *hdata; @@ -1596,11 +1709,14 @@ static void hdmiphy_clk_enable(struct exynos_drm_clk *clk, bool enable) { struct hdmi_context *hdata = container_of(clk, struct hdmi_context, phy_clk); + mutex_lock(&hdata->mutex); if (enable) hdmiphy_enable(hdata); else hdmiphy_disable(hdata); + + mutex_unlock(&hdata->mutex); } static int hdmi_bridge_init(struct hdmi_context *hdata) @@ -1811,6 +1927,7 @@ out: static int hdmi_probe(struct platform_device *pdev) { + struct hdmi_audio_infoframe *audio_infoframe; struct device *dev = &pdev->dev; struct hdmi_context *hdata; struct resource *res; @@ -1826,6 +1943,8 @@ static int hdmi_probe(struct platform_device *pdev) hdata->dev = dev; + mutex_init(&hdata->mutex); + ret = hdmi_resources_init(hdata); if (ret) { if (ret != -EPROBE_DEFER) @@ -1885,12 +2004,26 @@ static int hdmi_probe(struct platform_device *pdev) pm_runtime_enable(dev); - ret = component_add(&pdev->dev, &hdmi_component_ops); + audio_infoframe = &hdata->audio.infoframe; + hdmi_audio_infoframe_init(audio_infoframe); + audio_infoframe->coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; + audio_infoframe->sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; + audio_infoframe->sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; + audio_infoframe->channels = 2; + + ret = hdmi_register_audio_device(hdata); if (ret) goto err_notifier_put; + ret = component_add(&pdev->dev, &hdmi_component_ops); + if (ret) + goto err_unregister_audio; + return ret; +err_unregister_audio: + platform_device_unregister(hdata->audio.pdev); + err_notifier_put: cec_notifier_put(hdata->notifier); pm_runtime_disable(dev); @@ -1914,6 +2047,7 @@ static int hdmi_remove(struct platform_device *pdev) cec_notifier_set_phys_addr(hdata->notifier, CEC_PHYS_ADDR_INVALID); component_del(&pdev->dev, &hdmi_component_ops); + platform_device_unregister(hdata->audio.pdev); cec_notifier_put(hdata->notifier); pm_runtime_disable(&pdev->dev); @@ -1929,6 +2063,8 @@ static int hdmi_remove(struct platform_device *pdev) put_device(&hdata->ddc_adpt->dev); + mutex_destroy(&hdata->mutex); + return 0; } diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 002755415e00..dc5d79465f9b 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -67,19 +67,6 @@ #define MXR_FORMAT_ARGB4444 6 #define MXR_FORMAT_ARGB8888 7 -struct mixer_resources { - int irq; - void __iomem *mixer_regs; - void __iomem *vp_regs; - spinlock_t reg_slock; - struct clk *mixer; - struct clk *vp; - struct clk *hdmi; - struct clk *sclk_mixer; - struct clk *sclk_hdmi; - struct clk *mout_mixer; -}; - enum mixer_version_id { MXR_VER_0_0_0_16, MXR_VER_16_0_33_0, @@ -117,8 +104,18 @@ struct mixer_context { struct exynos_drm_plane planes[MIXER_WIN_NR]; unsigned long flags; - struct mixer_resources mixer_res; + int irq; + void __iomem *mixer_regs; + void __iomem *vp_regs; + spinlock_t reg_slock; + struct clk *mixer; + struct clk *vp; + struct clk *hdmi; + struct clk *sclk_mixer; + struct clk *sclk_hdmi; + struct clk *mout_mixer; enum mixer_version_id mxr_ver; + int scan_value; }; struct mixer_drv_data { @@ -194,44 +191,44 @@ static inline bool is_alpha_format(unsigned int pixel_format) } } -static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id) +static inline u32 vp_reg_read(struct mixer_context *ctx, u32 reg_id) { - return readl(res->vp_regs + reg_id); + return readl(ctx->vp_regs + reg_id); } -static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id, +static inline void vp_reg_write(struct mixer_context *ctx, u32 reg_id, u32 val) { - writel(val, res->vp_regs + reg_id); + writel(val, ctx->vp_regs + reg_id); } -static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id, +static inline void vp_reg_writemask(struct mixer_context *ctx, u32 reg_id, u32 val, u32 mask) { - u32 old = vp_reg_read(res, reg_id); + u32 old = vp_reg_read(ctx, reg_id); val = (val & mask) | (old & ~mask); - writel(val, res->vp_regs + reg_id); + writel(val, ctx->vp_regs + reg_id); } -static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id) +static inline u32 mixer_reg_read(struct mixer_context *ctx, u32 reg_id) { - return readl(res->mixer_regs + reg_id); + return readl(ctx->mixer_regs + reg_id); } -static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id, +static inline void mixer_reg_write(struct mixer_context *ctx, u32 reg_id, u32 val) { - writel(val, res->mixer_regs + reg_id); + writel(val, ctx->mixer_regs + reg_id); } -static inline void mixer_reg_writemask(struct mixer_resources *res, +static inline void mixer_reg_writemask(struct mixer_context *ctx, u32 reg_id, u32 val, u32 mask) { - u32 old = mixer_reg_read(res, reg_id); + u32 old = mixer_reg_read(ctx, reg_id); val = (val & mask) | (old & ~mask); - writel(val, res->mixer_regs + reg_id); + writel(val, ctx->mixer_regs + reg_id); } static void mixer_regs_dump(struct mixer_context *ctx) @@ -239,7 +236,7 @@ static void mixer_regs_dump(struct mixer_context *ctx) #define DUMPREG(reg_id) \ do { \ DRM_DEBUG_KMS(#reg_id " = %08x\n", \ - (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \ + (u32)readl(ctx->mixer_regs + reg_id)); \ } while (0) DUMPREG(MXR_STATUS); @@ -271,7 +268,7 @@ static void vp_regs_dump(struct mixer_context *ctx) #define DUMPREG(reg_id) \ do { \ DRM_DEBUG_KMS(#reg_id " = %08x\n", \ - (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \ + (u32) readl(ctx->vp_regs + reg_id)); \ } while (0) DUMPREG(VP_ENABLE); @@ -301,7 +298,7 @@ do { \ #undef DUMPREG } -static inline void vp_filter_set(struct mixer_resources *res, +static inline void vp_filter_set(struct mixer_context *ctx, int reg_id, const u8 *data, unsigned int size) { /* assure 4-byte align */ @@ -309,24 +306,23 @@ static inline void vp_filter_set(struct mixer_resources *res, for (; size; size -= 4, reg_id += 4, data += 4) { u32 val = (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3]; - vp_reg_write(res, reg_id, val); + vp_reg_write(ctx, reg_id, val); } } -static void vp_default_filter(struct mixer_resources *res) +static void vp_default_filter(struct mixer_context *ctx) { - vp_filter_set(res, VP_POLY8_Y0_LL, + vp_filter_set(ctx, VP_POLY8_Y0_LL, filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8)); - vp_filter_set(res, VP_POLY4_Y0_LL, + vp_filter_set(ctx, VP_POLY4_Y0_LL, filter_y_vert_tap4, sizeof(filter_y_vert_tap4)); - vp_filter_set(res, VP_POLY4_C0_LL, + vp_filter_set(ctx, VP_POLY4_C0_LL, filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4)); } static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win, bool alpha) { - struct mixer_resources *res = &ctx->mixer_res; u32 val; val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ @@ -335,13 +331,12 @@ static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win, val |= MXR_GRP_CFG_BLEND_PRE_MUL; val |= MXR_GRP_CFG_PIXEL_BLEND_EN; } - mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), + mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win), val, MXR_GRP_CFG_MISC_MASK); } static void mixer_cfg_vp_blend(struct mixer_context *ctx) { - struct mixer_resources *res = &ctx->mixer_res; u32 val; /* @@ -351,51 +346,39 @@ static void mixer_cfg_vp_blend(struct mixer_context *ctx) * support blending of the video layer through this. */ val = 0; - mixer_reg_write(res, MXR_VIDEO_CFG, val); + mixer_reg_write(ctx, MXR_VIDEO_CFG, val); } static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable) { - struct mixer_resources *res = &ctx->mixer_res; - /* block update on vsync */ - mixer_reg_writemask(res, MXR_STATUS, enable ? + mixer_reg_writemask(ctx, MXR_STATUS, enable ? MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE); if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) - vp_reg_write(res, VP_SHADOW_UPDATE, enable ? + vp_reg_write(ctx, VP_SHADOW_UPDATE, enable ? VP_SHADOW_UPDATE_ENABLE : 0); } -static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height) +static void mixer_cfg_scan(struct mixer_context *ctx, int width, int height) { - struct mixer_resources *res = &ctx->mixer_res; u32 val; /* choosing between interlace and progressive mode */ val = test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? MXR_CFG_SCAN_INTERLACE : MXR_CFG_SCAN_PROGRESSIVE; - if (ctx->mxr_ver != MXR_VER_128_0_0_184) { - /* choosing between proper HD and SD mode */ - if (height <= 480) - val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD; - else if (height <= 576) - val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD; - else if (height <= 720) - val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; - else if (height <= 1080) - val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD; - else - val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD; - } + if (ctx->mxr_ver == MXR_VER_128_0_0_184) + mixer_reg_write(ctx, MXR_RESOLUTION, + MXR_MXR_RES_HEIGHT(height) | MXR_MXR_RES_WIDTH(width)); + else + val |= ctx->scan_value; - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK); + mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_SCAN_MASK); } static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height) { - struct mixer_resources *res = &ctx->mixer_res; u32 val; switch (height) { @@ -408,45 +391,44 @@ static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height) default: val = MXR_CFG_RGB709_16_235; /* Configure the BT.709 CSC matrix for full range RGB. */ - mixer_reg_write(res, MXR_CM_COEFF_Y, + mixer_reg_write(ctx, MXR_CM_COEFF_Y, MXR_CSC_CT( 0.184, 0.614, 0.063) | MXR_CM_COEFF_RGB_FULL); - mixer_reg_write(res, MXR_CM_COEFF_CB, + mixer_reg_write(ctx, MXR_CM_COEFF_CB, MXR_CSC_CT(-0.102, -0.338, 0.440)); - mixer_reg_write(res, MXR_CM_COEFF_CR, + mixer_reg_write(ctx, MXR_CM_COEFF_CR, MXR_CSC_CT( 0.440, -0.399, -0.040)); break; } - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); + mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK); } static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win, unsigned int priority, bool enable) { - struct mixer_resources *res = &ctx->mixer_res; u32 val = enable ? ~0 : 0; switch (win) { case 0: - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); - mixer_reg_writemask(res, MXR_LAYER_CFG, + mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); + mixer_reg_writemask(ctx, MXR_LAYER_CFG, MXR_LAYER_CFG_GRP0_VAL(priority), MXR_LAYER_CFG_GRP0_MASK); break; case 1: - mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); - mixer_reg_writemask(res, MXR_LAYER_CFG, + mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); + mixer_reg_writemask(ctx, MXR_LAYER_CFG, MXR_LAYER_CFG_GRP1_VAL(priority), MXR_LAYER_CFG_GRP1_MASK); break; case VP_DEFAULT_WIN: if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { - vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON); - mixer_reg_writemask(res, MXR_CFG, val, + vp_reg_writemask(ctx, VP_ENABLE, val, VP_ENABLE_ON); + mixer_reg_writemask(ctx, MXR_CFG, val, MXR_CFG_VP_ENABLE); - mixer_reg_writemask(res, MXR_LAYER_CFG, + mixer_reg_writemask(ctx, MXR_LAYER_CFG, MXR_LAYER_CFG_VP_VAL(priority), MXR_LAYER_CFG_VP_MASK); } @@ -456,30 +438,34 @@ static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win, static void mixer_run(struct mixer_context *ctx) { - struct mixer_resources *res = &ctx->mixer_res; - - mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN); + mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_REG_RUN); } static void mixer_stop(struct mixer_context *ctx) { - struct mixer_resources *res = &ctx->mixer_res; int timeout = 20; - mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN); + mixer_reg_writemask(ctx, MXR_STATUS, 0, MXR_STATUS_REG_RUN); - while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) && + while (!(mixer_reg_read(ctx, MXR_STATUS) & MXR_STATUS_REG_IDLE) && --timeout) usleep_range(10000, 12000); } +static void mixer_commit(struct mixer_context *ctx) +{ + struct drm_display_mode *mode = &ctx->crtc->base.state->adjusted_mode; + + mixer_cfg_scan(ctx, mode->hdisplay, mode->vdisplay); + mixer_cfg_rgb_fmt(ctx, mode->vdisplay); + mixer_run(ctx); +} + static void vp_video_buffer(struct mixer_context *ctx, struct exynos_drm_plane *plane) { struct exynos_drm_plane_state *state = to_exynos_plane_state(plane->base.state); - struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode; - struct mixer_resources *res = &ctx->mixer_res; struct drm_framebuffer *fb = state->base.fb; unsigned int priority = state->base.normalized_zpos + 1; unsigned long flags; @@ -493,8 +479,7 @@ static void vp_video_buffer(struct mixer_context *ctx, luma_addr[0] = exynos_drm_fb_dma_addr(fb, 0); chroma_addr[0] = exynos_drm_fb_dma_addr(fb, 1); - if (mode->flags & DRM_MODE_FLAG_INTERLACE) { - __set_bit(MXR_BIT_INTERLACE, &ctx->flags); + if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { if (is_tiled) { luma_addr[1] = luma_addr[0] + 0x40; chroma_addr[1] = chroma_addr[0] + 0x40; @@ -503,63 +488,59 @@ static void vp_video_buffer(struct mixer_context *ctx, chroma_addr[1] = chroma_addr[0] + fb->pitches[0]; } } else { - __clear_bit(MXR_BIT_INTERLACE, &ctx->flags); luma_addr[1] = 0; chroma_addr[1] = 0; } - spin_lock_irqsave(&res->reg_slock, flags); + spin_lock_irqsave(&ctx->reg_slock, flags); /* interlace or progressive scan mode */ val = (test_bit(MXR_BIT_INTERLACE, &ctx->flags) ? ~0 : 0); - vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP); + vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_LINE_SKIP); /* setup format */ val = (is_nv21 ? VP_MODE_NV21 : VP_MODE_NV12); val |= (is_tiled ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR); - vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK); + vp_reg_writemask(ctx, VP_MODE, val, VP_MODE_FMT_MASK); /* setting size of input image */ - vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) | + vp_reg_write(ctx, VP_IMG_SIZE_Y, VP_IMG_HSIZE(fb->pitches[0]) | VP_IMG_VSIZE(fb->height)); /* chroma plane for NV12/NV21 is half the height of the luma plane */ - vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) | + vp_reg_write(ctx, VP_IMG_SIZE_C, VP_IMG_HSIZE(fb->pitches[0]) | VP_IMG_VSIZE(fb->height / 2)); - vp_reg_write(res, VP_SRC_WIDTH, state->src.w); - vp_reg_write(res, VP_SRC_HEIGHT, state->src.h); - vp_reg_write(res, VP_SRC_H_POSITION, + vp_reg_write(ctx, VP_SRC_WIDTH, state->src.w); + vp_reg_write(ctx, VP_SRC_HEIGHT, state->src.h); + vp_reg_write(ctx, VP_SRC_H_POSITION, VP_SRC_H_POSITION_VAL(state->src.x)); - vp_reg_write(res, VP_SRC_V_POSITION, state->src.y); + vp_reg_write(ctx, VP_SRC_V_POSITION, state->src.y); - vp_reg_write(res, VP_DST_WIDTH, state->crtc.w); - vp_reg_write(res, VP_DST_H_POSITION, state->crtc.x); + vp_reg_write(ctx, VP_DST_WIDTH, state->crtc.w); + vp_reg_write(ctx, VP_DST_H_POSITION, state->crtc.x); if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { - vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h / 2); - vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y / 2); + vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h / 2); + vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y / 2); } else { - vp_reg_write(res, VP_DST_HEIGHT, state->crtc.h); - vp_reg_write(res, VP_DST_V_POSITION, state->crtc.y); + vp_reg_write(ctx, VP_DST_HEIGHT, state->crtc.h); + vp_reg_write(ctx, VP_DST_V_POSITION, state->crtc.y); } - vp_reg_write(res, VP_H_RATIO, state->h_ratio); - vp_reg_write(res, VP_V_RATIO, state->v_ratio); + vp_reg_write(ctx, VP_H_RATIO, state->h_ratio); + vp_reg_write(ctx, VP_V_RATIO, state->v_ratio); - vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE); + vp_reg_write(ctx, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE); /* set buffer address to vp */ - vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]); - vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]); - vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]); - vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]); + vp_reg_write(ctx, VP_TOP_Y_PTR, luma_addr[0]); + vp_reg_write(ctx, VP_BOT_Y_PTR, luma_addr[1]); + vp_reg_write(ctx, VP_TOP_C_PTR, chroma_addr[0]); + vp_reg_write(ctx, VP_BOT_C_PTR, chroma_addr[1]); - mixer_cfg_scan(ctx, mode->vdisplay); - mixer_cfg_rgb_fmt(ctx, mode->vdisplay); mixer_cfg_layer(ctx, plane->index, priority, true); mixer_cfg_vp_blend(ctx); - mixer_run(ctx); - spin_unlock_irqrestore(&res->reg_slock, flags); + spin_unlock_irqrestore(&ctx->reg_slock, flags); mixer_regs_dump(ctx); vp_regs_dump(ctx); @@ -567,9 +548,7 @@ static void vp_video_buffer(struct mixer_context *ctx, static void mixer_layer_update(struct mixer_context *ctx) { - struct mixer_resources *res = &ctx->mixer_res; - - mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); + mixer_reg_writemask(ctx, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE); } static void mixer_graph_buffer(struct mixer_context *ctx, @@ -577,8 +556,6 @@ static void mixer_graph_buffer(struct mixer_context *ctx, { struct exynos_drm_plane_state *state = to_exynos_plane_state(plane->base.state); - struct drm_display_mode *mode = &state->base.crtc->state->adjusted_mode; - struct mixer_resources *res = &ctx->mixer_res; struct drm_framebuffer *fb = state->base.fb; unsigned int priority = state->base.normalized_zpos + 1; unsigned long flags; @@ -623,45 +600,30 @@ static void mixer_graph_buffer(struct mixer_context *ctx, + (state->src.x * fb->format->cpp[0]) + (state->src.y * fb->pitches[0]); - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - __set_bit(MXR_BIT_INTERLACE, &ctx->flags); - else - __clear_bit(MXR_BIT_INTERLACE, &ctx->flags); - - spin_lock_irqsave(&res->reg_slock, flags); + spin_lock_irqsave(&ctx->reg_slock, flags); /* setup format */ - mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win), + mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win), MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK); /* setup geometry */ - mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), + mixer_reg_write(ctx, MXR_GRAPHIC_SPAN(win), fb->pitches[0] / fb->format->cpp[0]); - /* setup display size */ - if (ctx->mxr_ver == MXR_VER_128_0_0_184 && - win == DEFAULT_WIN) { - val = MXR_MXR_RES_HEIGHT(mode->vdisplay); - val |= MXR_MXR_RES_WIDTH(mode->hdisplay); - mixer_reg_write(res, MXR_RESOLUTION, val); - } - val = MXR_GRP_WH_WIDTH(state->src.w); val |= MXR_GRP_WH_HEIGHT(state->src.h); val |= MXR_GRP_WH_H_SCALE(x_ratio); val |= MXR_GRP_WH_V_SCALE(y_ratio); - mixer_reg_write(res, MXR_GRAPHIC_WH(win), val); + mixer_reg_write(ctx, MXR_GRAPHIC_WH(win), val); /* setup offsets in display image */ val = MXR_GRP_DXY_DX(dst_x_offset); val |= MXR_GRP_DXY_DY(dst_y_offset); - mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val); + mixer_reg_write(ctx, MXR_GRAPHIC_DXY(win), val); /* set buffer address to mixer */ - mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr); + mixer_reg_write(ctx, MXR_GRAPHIC_BASE(win), dma_addr); - mixer_cfg_scan(ctx, mode->vdisplay); - mixer_cfg_rgb_fmt(ctx, mode->vdisplay); mixer_cfg_layer(ctx, win, priority, true); mixer_cfg_gfx_blend(ctx, win, is_alpha_format(fb->format->format)); @@ -670,22 +632,19 @@ static void mixer_graph_buffer(struct mixer_context *ctx, ctx->mxr_ver == MXR_VER_128_0_0_184) mixer_layer_update(ctx); - mixer_run(ctx); - - spin_unlock_irqrestore(&res->reg_slock, flags); + spin_unlock_irqrestore(&ctx->reg_slock, flags); mixer_regs_dump(ctx); } static void vp_win_reset(struct mixer_context *ctx) { - struct mixer_resources *res = &ctx->mixer_res; unsigned int tries = 100; - vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING); + vp_reg_write(ctx, VP_SRESET, VP_SRESET_PROCESSING); while (--tries) { /* waiting until VP_SRESET_PROCESSING is 0 */ - if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING) + if (~vp_reg_read(ctx, VP_SRESET) & VP_SRESET_PROCESSING) break; mdelay(10); } @@ -694,57 +653,55 @@ static void vp_win_reset(struct mixer_context *ctx) static void mixer_win_reset(struct mixer_context *ctx) { - struct mixer_resources *res = &ctx->mixer_res; unsigned long flags; - spin_lock_irqsave(&res->reg_slock, flags); + spin_lock_irqsave(&ctx->reg_slock, flags); - mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); + mixer_reg_writemask(ctx, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK); /* set output in RGB888 mode */ - mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK); + mixer_reg_writemask(ctx, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK); /* 16 beat burst in DMA */ - mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST, + mixer_reg_writemask(ctx, MXR_STATUS, MXR_STATUS_16_BURST, MXR_STATUS_BURST_MASK); /* reset default layer priority */ - mixer_reg_write(res, MXR_LAYER_CFG, 0); + mixer_reg_write(ctx, MXR_LAYER_CFG, 0); /* set all background colors to RGB (0,0,0) */ - mixer_reg_write(res, MXR_BG_COLOR0, MXR_YCBCR_VAL(0, 128, 128)); - mixer_reg_write(res, MXR_BG_COLOR1, MXR_YCBCR_VAL(0, 128, 128)); - mixer_reg_write(res, MXR_BG_COLOR2, MXR_YCBCR_VAL(0, 128, 128)); + mixer_reg_write(ctx, MXR_BG_COLOR0, MXR_YCBCR_VAL(0, 128, 128)); + mixer_reg_write(ctx, MXR_BG_COLOR1, MXR_YCBCR_VAL(0, 128, 128)); + mixer_reg_write(ctx, MXR_BG_COLOR2, MXR_YCBCR_VAL(0, 128, 128)); if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { /* configuration of Video Processor Registers */ vp_win_reset(ctx); - vp_default_filter(res); + vp_default_filter(ctx); } /* disable all layers */ - mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE); - mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE); + mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE); + mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE); if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) - mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE); + mixer_reg_writemask(ctx, MXR_CFG, 0, MXR_CFG_VP_ENABLE); /* set all source image offsets to zero */ - mixer_reg_write(res, MXR_GRAPHIC_SXY(0), 0); - mixer_reg_write(res, MXR_GRAPHIC_SXY(1), 0); + mixer_reg_write(ctx, MXR_GRAPHIC_SXY(0), 0); + mixer_reg_write(ctx, MXR_GRAPHIC_SXY(1), 0); - spin_unlock_irqrestore(&res->reg_slock, flags); + spin_unlock_irqrestore(&ctx->reg_slock, flags); } static irqreturn_t mixer_irq_handler(int irq, void *arg) { struct mixer_context *ctx = arg; - struct mixer_resources *res = &ctx->mixer_res; u32 val, base, shadow; - spin_lock(&res->reg_slock); + spin_lock(&ctx->reg_slock); /* read interrupt status for handling and clearing flags for VSYNC */ - val = mixer_reg_read(res, MXR_INT_STATUS); + val = mixer_reg_read(ctx, MXR_INT_STATUS); /* handling VSYNC */ if (val & MXR_INT_STATUS_VSYNC) { @@ -754,13 +711,13 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg) /* interlace scan need to check shadow register */ if (test_bit(MXR_BIT_INTERLACE, &ctx->flags)) { - base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0)); - shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0)); + base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(0)); + shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(0)); if (base != shadow) goto out; - base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1)); - shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1)); + base = mixer_reg_read(ctx, MXR_GRAPHIC_BASE(1)); + shadow = mixer_reg_read(ctx, MXR_GRAPHIC_BASE_S(1)); if (base != shadow) goto out; } @@ -770,9 +727,9 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg) out: /* clear interrupts */ - mixer_reg_write(res, MXR_INT_STATUS, val); + mixer_reg_write(ctx, MXR_INT_STATUS, val); - spin_unlock(&res->reg_slock); + spin_unlock(&ctx->reg_slock); return IRQ_HANDLED; } @@ -780,26 +737,25 @@ out: static int mixer_resources_init(struct mixer_context *mixer_ctx) { struct device *dev = &mixer_ctx->pdev->dev; - struct mixer_resources *mixer_res = &mixer_ctx->mixer_res; struct resource *res; int ret; - spin_lock_init(&mixer_res->reg_slock); + spin_lock_init(&mixer_ctx->reg_slock); - mixer_res->mixer = devm_clk_get(dev, "mixer"); - if (IS_ERR(mixer_res->mixer)) { + mixer_ctx->mixer = devm_clk_get(dev, "mixer"); + if (IS_ERR(mixer_ctx->mixer)) { dev_err(dev, "failed to get clock 'mixer'\n"); return -ENODEV; } - mixer_res->hdmi = devm_clk_get(dev, "hdmi"); - if (IS_ERR(mixer_res->hdmi)) { + mixer_ctx->hdmi = devm_clk_get(dev, "hdmi"); + if (IS_ERR(mixer_ctx->hdmi)) { dev_err(dev, "failed to get clock 'hdmi'\n"); - return PTR_ERR(mixer_res->hdmi); + return PTR_ERR(mixer_ctx->hdmi); } - mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi"); - if (IS_ERR(mixer_res->sclk_hdmi)) { + mixer_ctx->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi"); + if (IS_ERR(mixer_ctx->sclk_hdmi)) { dev_err(dev, "failed to get clock 'sclk_hdmi'\n"); return -ENODEV; } @@ -809,9 +765,9 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx) return -ENXIO; } - mixer_res->mixer_regs = devm_ioremap(dev, res->start, + mixer_ctx->mixer_regs = devm_ioremap(dev, res->start, resource_size(res)); - if (mixer_res->mixer_regs == NULL) { + if (mixer_ctx->mixer_regs == NULL) { dev_err(dev, "register mapping failed.\n"); return -ENXIO; } @@ -828,7 +784,7 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx) dev_err(dev, "request interrupt failed.\n"); return ret; } - mixer_res->irq = res->start; + mixer_ctx->irq = res->start; return 0; } @@ -836,30 +792,29 @@ static int mixer_resources_init(struct mixer_context *mixer_ctx) static int vp_resources_init(struct mixer_context *mixer_ctx) { struct device *dev = &mixer_ctx->pdev->dev; - struct mixer_resources *mixer_res = &mixer_ctx->mixer_res; struct resource *res; - mixer_res->vp = devm_clk_get(dev, "vp"); - if (IS_ERR(mixer_res->vp)) { + mixer_ctx->vp = devm_clk_get(dev, "vp"); + if (IS_ERR(mixer_ctx->vp)) { dev_err(dev, "failed to get clock 'vp'\n"); return -ENODEV; } if (test_bit(MXR_BIT_HAS_SCLK, &mixer_ctx->flags)) { - mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer"); - if (IS_ERR(mixer_res->sclk_mixer)) { + mixer_ctx->sclk_mixer = devm_clk_get(dev, "sclk_mixer"); + if (IS_ERR(mixer_ctx->sclk_mixer)) { dev_err(dev, "failed to get clock 'sclk_mixer'\n"); return -ENODEV; } - mixer_res->mout_mixer = devm_clk_get(dev, "mout_mixer"); - if (IS_ERR(mixer_res->mout_mixer)) { + mixer_ctx->mout_mixer = devm_clk_get(dev, "mout_mixer"); + if (IS_ERR(mixer_ctx->mout_mixer)) { dev_err(dev, "failed to get clock 'mout_mixer'\n"); return -ENODEV; } - if (mixer_res->sclk_hdmi && mixer_res->mout_mixer) - clk_set_parent(mixer_res->mout_mixer, - mixer_res->sclk_hdmi); + if (mixer_ctx->sclk_hdmi && mixer_ctx->mout_mixer) + clk_set_parent(mixer_ctx->mout_mixer, + mixer_ctx->sclk_hdmi); } res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1); @@ -868,9 +823,9 @@ static int vp_resources_init(struct mixer_context *mixer_ctx) return -ENXIO; } - mixer_res->vp_regs = devm_ioremap(dev, res->start, + mixer_ctx->vp_regs = devm_ioremap(dev, res->start, resource_size(res)); - if (mixer_res->vp_regs == NULL) { + if (mixer_ctx->vp_regs == NULL) { dev_err(dev, "register mapping failed.\n"); return -ENXIO; } @@ -914,15 +869,14 @@ static void mixer_ctx_remove(struct mixer_context *mixer_ctx) static int mixer_enable_vblank(struct exynos_drm_crtc *crtc) { struct mixer_context *mixer_ctx = crtc->ctx; - struct mixer_resources *res = &mixer_ctx->mixer_res; __set_bit(MXR_BIT_VSYNC, &mixer_ctx->flags); if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) return 0; /* enable vsync interrupt */ - mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); - mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); + mixer_reg_writemask(mixer_ctx, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); + mixer_reg_writemask(mixer_ctx, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); return 0; } @@ -930,7 +884,6 @@ static int mixer_enable_vblank(struct exynos_drm_crtc *crtc) static void mixer_disable_vblank(struct exynos_drm_crtc *crtc) { struct mixer_context *mixer_ctx = crtc->ctx; - struct mixer_resources *res = &mixer_ctx->mixer_res; __clear_bit(MXR_BIT_VSYNC, &mixer_ctx->flags); @@ -938,8 +891,8 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc) return; /* disable vsync interrupt */ - mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); - mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); + mixer_reg_writemask(mixer_ctx, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); + mixer_reg_writemask(mixer_ctx, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); } static void mixer_atomic_begin(struct exynos_drm_crtc *crtc) @@ -972,7 +925,6 @@ static void mixer_disable_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane) { struct mixer_context *mixer_ctx = crtc->ctx; - struct mixer_resources *res = &mixer_ctx->mixer_res; unsigned long flags; DRM_DEBUG_KMS("win: %d\n", plane->index); @@ -980,9 +932,9 @@ static void mixer_disable_plane(struct exynos_drm_crtc *crtc, if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags)) return; - spin_lock_irqsave(&res->reg_slock, flags); + spin_lock_irqsave(&mixer_ctx->reg_slock, flags); mixer_cfg_layer(mixer_ctx, plane->index, 0, false); - spin_unlock_irqrestore(&res->reg_slock, flags); + spin_unlock_irqrestore(&mixer_ctx->reg_slock, flags); } static void mixer_atomic_flush(struct exynos_drm_crtc *crtc) @@ -999,7 +951,6 @@ static void mixer_atomic_flush(struct exynos_drm_crtc *crtc) static void mixer_enable(struct exynos_drm_crtc *crtc) { struct mixer_context *ctx = crtc->ctx; - struct mixer_resources *res = &ctx->mixer_res; if (test_bit(MXR_BIT_POWERED, &ctx->flags)) return; @@ -1010,14 +961,17 @@ static void mixer_enable(struct exynos_drm_crtc *crtc) mixer_vsync_set_update(ctx, false); - mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); + mixer_reg_writemask(ctx, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); if (test_bit(MXR_BIT_VSYNC, &ctx->flags)) { - mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC); - mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); + mixer_reg_writemask(ctx, MXR_INT_STATUS, ~0, + MXR_INT_CLEAR_VSYNC); + mixer_reg_writemask(ctx, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC); } mixer_win_reset(ctx); + mixer_commit(ctx); + mixer_vsync_set_update(ctx, true); set_bit(MXR_BIT_POWERED, &ctx->flags); @@ -1044,26 +998,75 @@ static void mixer_disable(struct exynos_drm_crtc *crtc) clear_bit(MXR_BIT_POWERED, &ctx->flags); } -/* Only valid for Mixer version 16.0.33.0 */ -static int mixer_atomic_check(struct exynos_drm_crtc *crtc, - struct drm_crtc_state *state) +static int mixer_mode_valid(struct exynos_drm_crtc *crtc, + const struct drm_display_mode *mode) { - struct drm_display_mode *mode = &state->adjusted_mode; - u32 w, h; + struct mixer_context *ctx = crtc->ctx; + u32 w = mode->hdisplay, h = mode->vdisplay; - w = mode->hdisplay; - h = mode->vdisplay; + DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n", w, h, + mode->vrefresh, !!(mode->flags & DRM_MODE_FLAG_INTERLACE)); - DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n", - mode->hdisplay, mode->vdisplay, mode->vrefresh, - (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0); + if (ctx->mxr_ver == MXR_VER_128_0_0_184) + return MODE_OK; if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) || - (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) || - (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080)) - return 0; + (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) || + (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080)) + return MODE_OK; + + if ((w == 1024 && h == 768) || + (w == 1366 && h == 768) || + (w == 1280 && h == 1024)) + return MODE_OK; + + return MODE_BAD; +} + +static bool mixer_mode_fixup(struct exynos_drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct mixer_context *ctx = crtc->ctx; + int width = mode->hdisplay, height = mode->vdisplay, i; + + struct { + int hdisplay, vdisplay, htotal, vtotal, scan_val; + } static const modes[] = { + { 720, 480, 858, 525, MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD }, + { 720, 576, 864, 625, MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD }, + { 1280, 720, 1650, 750, MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD }, + { 1920, 1080, 2200, 1125, MXR_CFG_SCAN_HD_1080 | + MXR_CFG_SCAN_HD } + }; + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + __set_bit(MXR_BIT_INTERLACE, &ctx->flags); + else + __clear_bit(MXR_BIT_INTERLACE, &ctx->flags); + + if (ctx->mxr_ver == MXR_VER_128_0_0_184) + return true; + + for (i = 0; i < ARRAY_SIZE(modes); ++i) + if (width <= modes[i].hdisplay && height <= modes[i].vdisplay) { + ctx->scan_value = modes[i].scan_val; + if (width < modes[i].hdisplay || + height < modes[i].vdisplay) { + adjusted_mode->hdisplay = modes[i].hdisplay; + adjusted_mode->hsync_start = modes[i].hdisplay; + adjusted_mode->hsync_end = modes[i].htotal; + adjusted_mode->htotal = modes[i].htotal; + adjusted_mode->vdisplay = modes[i].vdisplay; + adjusted_mode->vsync_start = modes[i].vdisplay; + adjusted_mode->vsync_end = modes[i].vtotal; + adjusted_mode->vtotal = modes[i].vtotal; + } + + return true; + } - return -EINVAL; + return false; } static const struct exynos_drm_crtc_ops mixer_crtc_ops = { @@ -1075,7 +1078,8 @@ static const struct exynos_drm_crtc_ops mixer_crtc_ops = { .update_plane = mixer_update_plane, .disable_plane = mixer_disable_plane, .atomic_flush = mixer_atomic_flush, - .atomic_check = mixer_atomic_check, + .mode_valid = mixer_mode_valid, + .mode_fixup = mixer_mode_fixup, }; static const struct mixer_drv_data exynos5420_mxr_drv_data = { @@ -1217,14 +1221,13 @@ static int mixer_remove(struct platform_device *pdev) static int __maybe_unused exynos_mixer_suspend(struct device *dev) { struct mixer_context *ctx = dev_get_drvdata(dev); - struct mixer_resources *res = &ctx->mixer_res; - clk_disable_unprepare(res->hdmi); - clk_disable_unprepare(res->mixer); + clk_disable_unprepare(ctx->hdmi); + clk_disable_unprepare(ctx->mixer); if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { - clk_disable_unprepare(res->vp); + clk_disable_unprepare(ctx->vp); if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) - clk_disable_unprepare(res->sclk_mixer); + clk_disable_unprepare(ctx->sclk_mixer); } return 0; @@ -1233,28 +1236,27 @@ static int __maybe_unused exynos_mixer_suspend(struct device *dev) static int __maybe_unused exynos_mixer_resume(struct device *dev) { struct mixer_context *ctx = dev_get_drvdata(dev); - struct mixer_resources *res = &ctx->mixer_res; int ret; - ret = clk_prepare_enable(res->mixer); + ret = clk_prepare_enable(ctx->mixer); if (ret < 0) { DRM_ERROR("Failed to prepare_enable the mixer clk [%d]\n", ret); return ret; } - ret = clk_prepare_enable(res->hdmi); + ret = clk_prepare_enable(ctx->hdmi); if (ret < 0) { DRM_ERROR("Failed to prepare_enable the hdmi clk [%d]\n", ret); return ret; } if (test_bit(MXR_BIT_VP_ENABLED, &ctx->flags)) { - ret = clk_prepare_enable(res->vp); + ret = clk_prepare_enable(ctx->vp); if (ret < 0) { DRM_ERROR("Failed to prepare_enable the vp clk [%d]\n", ret); return ret; } if (test_bit(MXR_BIT_HAS_SCLK, &ctx->flags)) { - ret = clk_prepare_enable(res->sclk_mixer); + ret = clk_prepare_enable(ctx->sclk_mixer); if (ret < 0) { DRM_ERROR("Failed to prepare_enable the " \ "sclk_mixer clk [%d]\n", diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h index a0507dc18d9e..04be0f7e8193 100644 --- a/drivers/gpu/drm/exynos/regs-hdmi.h +++ b/drivers/gpu/drm/exynos/regs-hdmi.h @@ -419,11 +419,9 @@ #define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c) #define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020) #define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024) -#define HDMI_I2S_CH_ST_0 HDMI_I2S_BASE(0x028) -#define HDMI_I2S_CH_ST_1 HDMI_I2S_BASE(0x02c) -#define HDMI_I2S_CH_ST_2 HDMI_I2S_BASE(0x030) -#define HDMI_I2S_CH_ST_3 HDMI_I2S_BASE(0x034) -#define HDMI_I2S_CH_ST_4 HDMI_I2S_BASE(0x038) +/* n must be within range 0...(HDMI_I2S_CH_ST_MAXNUM - 1) */ +#define HDMI_I2S_CH_ST_MAXNUM 5 +#define HDMI_I2S_CH_ST(n) HDMI_I2S_BASE(0x028 + 4 * (n)) #define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c) #define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040) #define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044) diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index 58e9e0601a61..faf17b83b910 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -210,7 +210,6 @@ static int fsl_dcu_drm_pm_suspend(struct device *dev) return PTR_ERR(fsl_dev->state); } - clk_disable_unprepare(fsl_dev->pix_clk); clk_disable_unprepare(fsl_dev->clk); return 0; @@ -233,6 +232,7 @@ static int fsl_dcu_drm_pm_resume(struct device *dev) if (fsl_dev->tcon) fsl_tcon_bypass_enable(fsl_dev->tcon); fsl_dcu_drm_init_planes(fsl_dev->drm); + enable_irq(fsl_dev->irq); drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state); console_lock(); @@ -240,7 +240,6 @@ static int fsl_dcu_drm_pm_resume(struct device *dev) console_unlock(); drm_kms_helper_poll_enable(fsl_dev->drm); - enable_irq(fsl_dev->irq); return 0; } diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c index edd7d8127d19..c54806d08dd7 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c @@ -102,7 +102,6 @@ static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev, { struct drm_encoder *encoder = &fsl_dev->encoder; struct drm_connector *connector = &fsl_dev->connector.base; - struct drm_mode_config *mode_config = &fsl_dev->drm->mode_config; int ret; fsl_dev->connector.encoder = encoder; @@ -122,10 +121,6 @@ static int fsl_dcu_attach_panel(struct fsl_dcu_drm_device *fsl_dev, if (ret < 0) goto err_sysfs; - drm_object_property_set_value(&connector->base, - mode_config->dpms_property, - DRM_MODE_DPMS_OFF); - ret = drm_panel_attach(panel, connector); if (ret) { dev_err(fsl_dev->dev, "failed to attach panel\n"); diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c index 53e0b24beda6..9a9961802f5c 100644 --- a/drivers/gpu/drm/imx/ipuv3-crtc.c +++ b/drivers/gpu/drm/imx/ipuv3-crtc.c @@ -115,7 +115,7 @@ static void imx_drm_crtc_reset(struct drm_crtc *crtc) if (crtc->state) { if (crtc->state->mode_blob) - drm_property_unreference_blob(crtc->state->mode_blob); + drm_property_blob_put(crtc->state->mode_blob); state = to_imx_crtc_state(crtc->state); memset(state, 0, sizeof(*state)); diff --git a/drivers/gpu/drm/imx/parallel-display.c b/drivers/gpu/drm/imx/parallel-display.c index 8def97d75030..aedecda9728a 100644 --- a/drivers/gpu/drm/imx/parallel-display.c +++ b/drivers/gpu/drm/imx/parallel-display.c @@ -183,7 +183,7 @@ static int imx_pd_register(struct drm_device *drm, &imx_pd_connector_helper_funcs); drm_connector_init(drm, &imxpd->connector, &imx_pd_connector_funcs, - DRM_MODE_CONNECTOR_VGA); + DRM_MODE_CONNECTOR_DPI); } if (imxpd->panel) diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c index 74fc9362ecf9..c0fb52c6d4ca 100644 --- a/drivers/gpu/drm/qxl/qxl_cmd.c +++ b/drivers/gpu/drm/qxl/qxl_cmd.c @@ -219,7 +219,7 @@ int qxl_garbage_collect(struct qxl_device *qdev) union qxl_release_info *info; while (qxl_ring_pop(qdev->release_ring, &id)) { - QXL_INFO(qdev, "popped %lld\n", id); + DRM_DEBUG_DRIVER("popped %lld\n", id); while (id) { release = qxl_release_from_id_locked(qdev, id); if (release == NULL) @@ -229,8 +229,8 @@ int qxl_garbage_collect(struct qxl_device *qdev) next_id = info->next; qxl_release_unmap(qdev, release, info); - QXL_INFO(qdev, "popped %lld, next %lld\n", id, - next_id); + DRM_DEBUG_DRIVER("popped %lld, next %lld\n", id, + next_id); switch (release->type) { case QXL_RELEASE_DRAWABLE: @@ -248,7 +248,7 @@ int qxl_garbage_collect(struct qxl_device *qdev) } } - QXL_INFO(qdev, "%s: %d\n", __func__, i); + DRM_DEBUG_DRIVER("%d\n", i); return i; } @@ -381,17 +381,19 @@ void qxl_io_create_primary(struct qxl_device *qdev, { struct qxl_surface_create *create; - QXL_INFO(qdev, "%s: qdev %p, ram_header %p\n", __func__, qdev, - qdev->ram_header); + DRM_DEBUG_DRIVER("qdev %p, ram_header %p\n", qdev, qdev->ram_header); create = &qdev->ram_header->create_surface; create->format = bo->surf.format; create->width = bo->surf.width; create->height = bo->surf.height; create->stride = bo->surf.stride; - create->mem = qxl_bo_physical_address(qdev, bo, offset); + if (bo->shadow) { + create->mem = qxl_bo_physical_address(qdev, bo->shadow, offset); + } else { + create->mem = qxl_bo_physical_address(qdev, bo, offset); + } - QXL_INFO(qdev, "%s: mem = %llx, from %p\n", __func__, create->mem, - bo->kptr); + DRM_DEBUG_DRIVER("mem = %llx, from %p\n", create->mem, bo->kptr); create->flags = QXL_SURF_FLAG_KEEP_DATA; create->type = QXL_SURF_TYPE_PRIMARY; @@ -401,7 +403,7 @@ void qxl_io_create_primary(struct qxl_device *qdev, void qxl_io_memslot_add(struct qxl_device *qdev, uint8_t id) { - QXL_INFO(qdev, "qxl_memslot_add %d\n", id); + DRM_DEBUG_DRIVER("qxl_memslot_add %d\n", id); wait_for_io_cmd(qdev, id, QXL_IO_MEMSLOT_ADD_ASYNC); } diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index afbf50d0c08f..4756b3c9bf2c 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -305,7 +305,9 @@ static const struct drm_crtc_funcs qxl_crtc_funcs = { void qxl_user_framebuffer_destroy(struct drm_framebuffer *fb) { struct qxl_framebuffer *qxl_fb = to_qxl_framebuffer(fb); + struct qxl_bo *bo = gem_to_qxl_bo(qxl_fb->obj); + WARN_ON(bo->shadow); drm_gem_object_unreference_unlocked(qxl_fb->obj); drm_framebuffer_cleanup(fb); kfree(qxl_fb); @@ -508,6 +510,7 @@ static void qxl_primary_atomic_update(struct drm_plane *plane, .x2 = qfb->base.width, .y2 = qfb->base.height }; + bool same_shadow = false; if (old_state->fb) { qfb_old = to_qxl_framebuffer(old_state->fb); @@ -519,15 +522,23 @@ static void qxl_primary_atomic_update(struct drm_plane *plane, if (bo == bo_old) return; + if (bo_old && bo_old->shadow && bo->shadow && + bo_old->shadow == bo->shadow) { + same_shadow = true; + } + if (bo_old && bo_old->is_primary) { - qxl_io_destroy_primary(qdev); + if (!same_shadow) + qxl_io_destroy_primary(qdev); bo_old->is_primary = false; } if (!bo->is_primary) { - qxl_io_create_primary(qdev, 0, bo); + if (!same_shadow) + qxl_io_create_primary(qdev, 0, bo); bo->is_primary = true; } + qxl_draw_dirty_fb(qdev, qfb, bo, 0, 0, &norect, 1, 1); } @@ -679,8 +690,9 @@ static void qxl_cursor_atomic_disable(struct drm_plane *plane, static int qxl_plane_prepare_fb(struct drm_plane *plane, struct drm_plane_state *new_state) { + struct qxl_device *qdev = plane->dev->dev_private; struct drm_gem_object *obj; - struct qxl_bo *user_bo; + struct qxl_bo *user_bo, *old_bo = NULL; int ret; if (!new_state->fb) @@ -689,6 +701,32 @@ static int qxl_plane_prepare_fb(struct drm_plane *plane, obj = to_qxl_framebuffer(new_state->fb)->obj; user_bo = gem_to_qxl_bo(obj); + if (plane->type == DRM_PLANE_TYPE_PRIMARY && + user_bo->is_dumb && !user_bo->shadow) { + if (plane->state->fb) { + obj = to_qxl_framebuffer(plane->state->fb)->obj; + old_bo = gem_to_qxl_bo(obj); + } + if (old_bo && old_bo->shadow && + user_bo->gem_base.size == old_bo->gem_base.size && + plane->state->crtc == new_state->crtc && + plane->state->crtc_w == new_state->crtc_w && + plane->state->crtc_h == new_state->crtc_h && + plane->state->src_x == new_state->src_x && + plane->state->src_y == new_state->src_y && + plane->state->src_w == new_state->src_w && + plane->state->src_h == new_state->src_h && + plane->state->rotation == new_state->rotation && + plane->state->zpos == new_state->zpos) { + drm_gem_object_get(&old_bo->shadow->gem_base); + user_bo->shadow = old_bo->shadow; + } else { + qxl_bo_create(qdev, user_bo->gem_base.size, + true, true, QXL_GEM_DOMAIN_VRAM, NULL, + &user_bo->shadow); + } + } + ret = qxl_bo_pin(user_bo, QXL_GEM_DOMAIN_CPU, NULL); if (ret) return ret; @@ -713,6 +751,11 @@ static void qxl_plane_cleanup_fb(struct drm_plane *plane, obj = to_qxl_framebuffer(old_state->fb)->obj; user_bo = gem_to_qxl_bo(obj); qxl_bo_unpin(user_bo); + + if (user_bo->shadow && !user_bo->is_primary) { + drm_gem_object_put_unlocked(&user_bo->shadow->gem_base); + user_bo->shadow = NULL; + } } static const uint32_t qxl_cursor_plane_formats[] = { diff --git a/drivers/gpu/drm/qxl/qxl_drv.h b/drivers/gpu/drm/qxl/qxl_drv.h index 3397a1907336..08752c0ffb35 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.h +++ b/drivers/gpu/drm/qxl/qxl_drv.h @@ -62,33 +62,9 @@ #define QXL_DEBUGFS_MAX_COMPONENTS 32 -extern int qxl_log_level; extern int qxl_num_crtc; extern int qxl_max_ioctls; -enum { - QXL_INFO_LEVEL = 1, - QXL_DEBUG_LEVEL = 2, -}; - -#define QXL_INFO(qdev, fmt, ...) do { \ - if (qxl_log_level >= QXL_INFO_LEVEL) { \ - qxl_io_log(qdev, fmt, __VA_ARGS__); \ - } \ - } while (0) -#define QXL_DEBUG(qdev, fmt, ...) do { \ - if (qxl_log_level >= QXL_DEBUG_LEVEL) { \ - qxl_io_log(qdev, fmt, __VA_ARGS__); \ - } \ - } while (0) -#define QXL_INFO_ONCE(qdev, fmt, ...) do { \ - static int done; \ - if (!done) { \ - done = 1; \ - QXL_INFO(qdev, fmt, __VA_ARGS__); \ - } \ - } while (0) - #define DRM_FILE_OFFSET 0x100000000ULL #define DRM_FILE_PAGE_OFFSET (DRM_FILE_OFFSET >> PAGE_SHIFT) @@ -113,6 +89,8 @@ struct qxl_bo { /* Constant after initialization */ struct drm_gem_object gem_base; bool is_primary; /* is this now a primary surface */ + bool is_dumb; + struct qxl_bo *shadow; bool hw_surf_alloc; struct qxl_surface surf; uint32_t surface_id; @@ -351,7 +329,7 @@ int qxl_check_idle(struct qxl_ring *ring); static inline void * qxl_fb_virtual_address(struct qxl_device *qdev, unsigned long physical) { - QXL_INFO(qdev, "not implemented (%lu)\n", physical); + DRM_DEBUG_DRIVER("not implemented (%lu)\n", physical); return 0; } diff --git a/drivers/gpu/drm/qxl/qxl_dumb.c b/drivers/gpu/drm/qxl/qxl_dumb.c index 5e65d5d2d937..11085ab01374 100644 --- a/drivers/gpu/drm/qxl/qxl_dumb.c +++ b/drivers/gpu/drm/qxl/qxl_dumb.c @@ -63,6 +63,7 @@ int qxl_mode_dumb_create(struct drm_file *file_priv, &handle); if (r) return r; + qobj->is_dumb = true; args->pitch = pitch; args->handle = handle; return 0; diff --git a/drivers/gpu/drm/qxl/qxl_fb.c b/drivers/gpu/drm/qxl/qxl_fb.c index 844c4a31ca13..23af3e352673 100644 --- a/drivers/gpu/drm/qxl/qxl_fb.c +++ b/drivers/gpu/drm/qxl/qxl_fb.c @@ -240,18 +240,15 @@ static int qxlfb_create(struct qxl_fbdev *qfbdev, return ret; qbo = gem_to_qxl_bo(gobj); - QXL_INFO(qdev, "%s: %dx%d %d\n", __func__, mode_cmd.width, - mode_cmd.height, mode_cmd.pitches[0]); + DRM_DEBUG_DRIVER("%dx%d %d\n", mode_cmd.width, + mode_cmd.height, mode_cmd.pitches[0]); shadow = vmalloc(mode_cmd.pitches[0] * mode_cmd.height); /* TODO: what's the usual response to memory allocation errors? */ BUG_ON(!shadow); - QXL_INFO(qdev, - "surface0 at gpu offset %lld, mmap_offset %lld (virt %p, shadow %p)\n", - qxl_bo_gpu_offset(qbo), - qxl_bo_mmap_offset(qbo), - qbo->kptr, - shadow); + DRM_DEBUG_DRIVER("surface0 at gpu offset %lld, mmap_offset %lld (virt %p, shadow %p)\n", + qxl_bo_gpu_offset(qbo), qxl_bo_mmap_offset(qbo), + qbo->kptr, shadow); size = mode_cmd.pitches[0] * mode_cmd.height; info = drm_fb_helper_alloc_fbi(&qfbdev->helper); diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c index e6ec845b5be0..a6da6fa6ad58 100644 --- a/drivers/gpu/drm/qxl/qxl_release.c +++ b/drivers/gpu/drm/qxl/qxl_release.c @@ -154,7 +154,7 @@ qxl_release_alloc(struct qxl_device *qdev, int type, return handle; } *ret = release; - QXL_INFO(qdev, "allocated release %d\n", handle); + DRM_DEBUG_DRIVER("allocated release %d\n", handle); release->id = handle; return handle; } @@ -179,8 +179,7 @@ void qxl_release_free(struct qxl_device *qdev, struct qxl_release *release) { - QXL_INFO(qdev, "release %d, type %d\n", release->id, - release->type); + DRM_DEBUG_DRIVER("release %d, type %d\n", release->id, release->type); if (release->surface_release_id) qxl_surface_id_dealloc(qdev, release->surface_release_id); diff --git a/drivers/gpu/drm/qxl/qxl_ttm.c b/drivers/gpu/drm/qxl/qxl_ttm.c index 7ecf8a4b9fe6..ab4823875311 100644 --- a/drivers/gpu/drm/qxl/qxl_ttm.c +++ b/drivers/gpu/drm/qxl/qxl_ttm.c @@ -136,8 +136,8 @@ int qxl_mmap(struct file *filp, struct vm_area_struct *vma) "filp->private_data->minor->dev->dev_private == NULL\n"); return -EINVAL; } - QXL_INFO(qdev, "%s: filp->private_data = 0x%p, vma->vm_pgoff = %lx\n", - __func__, filp->private_data, vma->vm_pgoff); + DRM_DEBUG_DRIVER("filp->private_data = 0x%p, vma->vm_pgoff = %lx\n", + filp->private_data, vma->vm_pgoff); r = ttm_bo_mmap(filp, vma, &qdev->mman.bdev); if (unlikely(r != 0)) diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 2fcf805d3a16..33b821d6d018 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -245,7 +245,6 @@ static int radeonfb_create(struct drm_fb_helper *helper, } info->par = rfbdev; - info->skip_vt_switch = true; ret = radeon_framebuffer_init(rdev->ddev, &rfbdev->rfb, &mode_cmd, gobj); if (ret) { diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig index 3c70c6224bd2..0ccc76217ee4 100644 --- a/drivers/gpu/drm/rockchip/Kconfig +++ b/drivers/gpu/drm/rockchip/Kconfig @@ -60,7 +60,7 @@ config ROCKCHIP_INNO_HDMI config ROCKCHIP_LVDS bool "Rockchip LVDS support" depends on DRM_ROCKCHIP - depends on PINCTRL + depends on PINCTRL && OF help Choose this option to enable support for Rockchip LVDS controllers. Rockchip rk3288 SoC has LVDS TX Controller can be used, and it diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 4d3f6ad0abdd..93b7102dd008 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -72,7 +72,7 @@ struct rockchip_dp_device { struct reset_control *rst; struct work_struct psr_work; - spinlock_t psr_lock; + struct mutex psr_lock; unsigned int psr_state; const struct rockchip_dp_chip_data *data; @@ -83,21 +83,20 @@ struct rockchip_dp_device { static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled) { struct rockchip_dp_device *dp = to_dp(encoder); - unsigned long flags; if (!analogix_dp_psr_supported(dp->dev)) return; DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit"); - spin_lock_irqsave(&dp->psr_lock, flags); + mutex_lock(&dp->psr_lock); if (enabled) dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE; else dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE; schedule_work(&dp->psr_work); - spin_unlock_irqrestore(&dp->psr_lock, flags); + mutex_unlock(&dp->psr_lock); } static void analogix_dp_psr_work(struct work_struct *work) @@ -105,7 +104,6 @@ static void analogix_dp_psr_work(struct work_struct *work) struct rockchip_dp_device *dp = container_of(work, typeof(*dp), psr_work); int ret; - unsigned long flags; ret = rockchip_drm_wait_vact_end(dp->encoder.crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS); @@ -114,12 +112,12 @@ static void analogix_dp_psr_work(struct work_struct *work) return; } - spin_lock_irqsave(&dp->psr_lock, flags); + mutex_lock(&dp->psr_lock); if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE) analogix_dp_enable_psr(dp->dev); else analogix_dp_disable_psr(dp->dev); - spin_unlock_irqrestore(&dp->psr_lock, flags); + mutex_unlock(&dp->psr_lock); } static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) @@ -381,7 +379,7 @@ static int rockchip_dp_bind(struct device *dev, struct device *master, dp->plat_data.power_off = rockchip_dp_powerdown; dp->plat_data.get_modes = rockchip_dp_get_modes; - spin_lock_init(&dp->psr_lock); + mutex_init(&dp->psr_lock); dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE; INIT_WORK(&dp->psr_work, analogix_dp_psr_work); diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 4bcacd3f4861..b0a1dedac802 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -174,9 +174,9 @@ struct tegra_sor { struct reset_control *rst; struct clk *clk_parent; - struct clk *clk_brick; struct clk *clk_safe; - struct clk *clk_src; + struct clk *clk_out; + struct clk *clk_pad; struct clk *clk_dp; struct clk *clk; @@ -255,7 +255,7 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) clk_disable_unprepare(sor->clk); - err = clk_set_parent(sor->clk, parent); + err = clk_set_parent(sor->clk_out, parent); if (err < 0) return err; @@ -266,24 +266,24 @@ static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) return 0; } -struct tegra_clk_sor_brick { +struct tegra_clk_sor_pad { struct clk_hw hw; struct tegra_sor *sor; }; -static inline struct tegra_clk_sor_brick *to_brick(struct clk_hw *hw) +static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) { - return container_of(hw, struct tegra_clk_sor_brick, hw); + return container_of(hw, struct tegra_clk_sor_pad, hw); } -static const char * const tegra_clk_sor_brick_parents[] = { +static const char * const tegra_clk_sor_pad_parents[] = { "pll_d2_out0", "pll_dp" }; -static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index) +static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) { - struct tegra_clk_sor_brick *brick = to_brick(hw); - struct tegra_sor *sor = brick->sor; + struct tegra_clk_sor_pad *pad = to_pad(hw); + struct tegra_sor *sor = pad->sor; u32 value; value = tegra_sor_readl(sor, SOR_CLK_CNTRL); @@ -304,10 +304,10 @@ static int tegra_clk_sor_brick_set_parent(struct clk_hw *hw, u8 index) return 0; } -static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw) +static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw) { - struct tegra_clk_sor_brick *brick = to_brick(hw); - struct tegra_sor *sor = brick->sor; + struct tegra_clk_sor_pad *pad = to_pad(hw); + struct tegra_sor *sor = pad->sor; u8 parent = U8_MAX; u32 value; @@ -328,33 +328,33 @@ static u8 tegra_clk_sor_brick_get_parent(struct clk_hw *hw) return parent; } -static const struct clk_ops tegra_clk_sor_brick_ops = { - .set_parent = tegra_clk_sor_brick_set_parent, - .get_parent = tegra_clk_sor_brick_get_parent, +static const struct clk_ops tegra_clk_sor_pad_ops = { + .set_parent = tegra_clk_sor_pad_set_parent, + .get_parent = tegra_clk_sor_pad_get_parent, }; -static struct clk *tegra_clk_sor_brick_register(struct tegra_sor *sor, - const char *name) +static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, + const char *name) { - struct tegra_clk_sor_brick *brick; + struct tegra_clk_sor_pad *pad; struct clk_init_data init; struct clk *clk; - brick = devm_kzalloc(sor->dev, sizeof(*brick), GFP_KERNEL); - if (!brick) + pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); + if (!pad) return ERR_PTR(-ENOMEM); - brick->sor = sor; + pad->sor = sor; init.name = name; init.flags = 0; - init.parent_names = tegra_clk_sor_brick_parents; - init.num_parents = ARRAY_SIZE(tegra_clk_sor_brick_parents); - init.ops = &tegra_clk_sor_brick_ops; + init.parent_names = tegra_clk_sor_pad_parents; + init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents); + init.ops = &tegra_clk_sor_pad_ops; - brick->hw.init = &init; + pad->hw.init = &init; - clk = devm_clk_register(sor->dev, &brick->hw); + clk = devm_clk_register(sor->dev, &pad->hw); return clk; } @@ -998,8 +998,10 @@ static int tegra_sor_power_down(struct tegra_sor *sor) /* switch to safe parent clock */ err = tegra_sor_set_parent_clock(sor, sor->clk_safe); - if (err < 0) + if (err < 0) { dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); + return err; + } value = tegra_sor_readl(sor, SOR_DP_PADCTL0); value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | @@ -2007,8 +2009,10 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) /* switch to safe parent clock */ err = tegra_sor_set_parent_clock(sor, sor->clk_safe); - if (err < 0) + if (err < 0) { dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); + return; + } div = clk_get_rate(sor->clk) / 1000000 * 4; @@ -2111,13 +2115,17 @@ static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) tegra_sor_writel(sor, value, SOR_XBAR_CTRL); /* switch to parent clock */ - err = clk_set_parent(sor->clk_src, sor->clk_parent); - if (err < 0) - dev_err(sor->dev, "failed to set source clock: %d\n", err); - - err = tegra_sor_set_parent_clock(sor, sor->clk_src); - if (err < 0) + err = clk_set_parent(sor->clk, sor->clk_parent); + if (err < 0) { dev_err(sor->dev, "failed to set parent clock: %d\n", err); + return; + } + + err = tegra_sor_set_parent_clock(sor, sor->clk_pad); + if (err < 0) { + dev_err(sor->dev, "failed to set pad clock: %d\n", err); + return; + } value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); @@ -2628,11 +2636,24 @@ static int tegra_sor_probe(struct platform_device *pdev) } if (sor->soc->supports_hdmi || sor->soc->supports_dp) { - sor->clk_src = devm_clk_get(&pdev->dev, "source"); - if (IS_ERR(sor->clk_src)) { - err = PTR_ERR(sor->clk_src); - dev_err(sor->dev, "failed to get source clock: %d\n", - err); + struct device_node *np = pdev->dev.of_node; + const char *name; + + /* + * For backwards compatibility with Tegra210 device trees, + * fall back to the old clock name "source" if the new "out" + * clock is not available. + */ + if (of_property_match_string(np, "clock-names", "out") < 0) + name = "source"; + else + name = "out"; + + sor->clk_out = devm_clk_get(&pdev->dev, name); + if (IS_ERR(sor->clk_out)) { + err = PTR_ERR(sor->clk_out); + dev_err(sor->dev, "failed to get %s clock: %d\n", + name, err); goto remove; } } @@ -2658,16 +2679,60 @@ static int tegra_sor_probe(struct platform_device *pdev) goto remove; } + /* + * Starting with Tegra186, the BPMP provides an implementation for + * the pad output clock, so we have to look it up from device tree. + */ + sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); + if (IS_ERR(sor->clk_pad)) { + if (sor->clk_pad != ERR_PTR(-ENOENT)) { + err = PTR_ERR(sor->clk_pad); + goto remove; + } + + /* + * If the pad output clock is not available, then we assume + * we're on Tegra210 or earlier and have to provide our own + * implementation. + */ + sor->clk_pad = NULL; + } + + /* + * The bootloader may have set up the SOR such that it's module clock + * is sourced by one of the display PLLs. However, that doesn't work + * without properly having set up other bits of the SOR. + */ + err = clk_set_parent(sor->clk_out, sor->clk_safe); + if (err < 0) { + dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); + goto remove; + } + platform_set_drvdata(pdev, sor); pm_runtime_enable(&pdev->dev); - pm_runtime_get_sync(&pdev->dev); - sor->clk_brick = tegra_clk_sor_brick_register(sor, "sor1_brick"); - pm_runtime_put(&pdev->dev); + /* + * On Tegra210 and earlier, provide our own implementation for the + * pad output clock. + */ + if (!sor->clk_pad) { + err = pm_runtime_get_sync(&pdev->dev); + if (err < 0) { + dev_err(&pdev->dev, "failed to get runtime PM: %d\n", + err); + goto remove; + } + + sor->clk_pad = tegra_clk_sor_pad_register(sor, + "sor1_pad_clkout"); + pm_runtime_put(&pdev->dev); + } - if (IS_ERR(sor->clk_brick)) { - err = PTR_ERR(sor->clk_brick); - dev_err(&pdev->dev, "failed to register SOR clock: %d\n", err); + if (IS_ERR(sor->clk_pad)) { + err = PTR_ERR(sor->clk_pad); + dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n", + err); goto remove; } diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig index 28fed7e206d0..81ac82455ce4 100644 --- a/drivers/gpu/drm/tilcdc/Kconfig +++ b/drivers/gpu/drm/tilcdc/Kconfig @@ -12,14 +12,3 @@ config DRM_TILCDC controller, for example AM33xx in beagle-bone, DA8xx, or OMAP-L1xx. This driver replaces the FB_DA8XX fbdev driver. -config DRM_TILCDC_SLAVE_COMPAT - bool "Support device tree blobs using TI LCDC Slave binding" - depends on DRM_TILCDC - default y - select OF_RESOLVE - select OF_OVERLAY - help - Choose this option if you need a kernel that is compatible - with device tree blobs using the obsolete "ti,tilcdc,slave" - binding. If you find "ti,tilcdc,slave"-string from your DTB, - you probably need this. Otherwise you do not. diff --git a/drivers/gpu/drm/tilcdc/Makefile b/drivers/gpu/drm/tilcdc/Makefile index 55ebd516728f..efc2c4f00daa 100644 --- a/drivers/gpu/drm/tilcdc/Makefile +++ b/drivers/gpu/drm/tilcdc/Makefile @@ -2,9 +2,6 @@ ifeq (, $(findstring -W,$(EXTRA_CFLAGS))) ccflags-y += -Werror endif -obj-$(CONFIG_DRM_TILCDC_SLAVE_COMPAT) += tilcdc_slave_compat.o \ - tilcdc_slave_compat.dtb.o - tilcdc-y := \ tilcdc_plane.o \ tilcdc_crtc.o \ diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c deleted file mode 100644 index 482299a6f3b0..000000000000 --- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Copyright (C) 2015 Texas Instruments - * Author: Jyri Sarha <[email protected]> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - */ - -/* - * To support the old "ti,tilcdc,slave" binding the binding has to be - * transformed to the new external encoder binding. - */ - -#include <linux/kernel.h> -#include <linux/of.h> -#include <linux/of_graph.h> -#include <linux/of_fdt.h> -#include <linux/slab.h> -#include <linux/list.h> - -#include "tilcdc_slave_compat.h" - -struct kfree_table { - int total; - int num; - void **table; -}; - -static int __init kfree_table_init(struct kfree_table *kft) -{ - kft->total = 32; - kft->num = 0; - kft->table = kmalloc(kft->total * sizeof(*kft->table), - GFP_KERNEL); - if (!kft->table) - return -ENOMEM; - - return 0; -} - -static int __init kfree_table_add(struct kfree_table *kft, void *p) -{ - if (kft->num == kft->total) { - void **old = kft->table; - - kft->total *= 2; - kft->table = krealloc(old, kft->total * sizeof(*kft->table), - GFP_KERNEL); - if (!kft->table) { - kft->table = old; - kfree(p); - return -ENOMEM; - } - } - kft->table[kft->num++] = p; - return 0; -} - -static void __init kfree_table_free(struct kfree_table *kft) -{ - int i; - - for (i = 0; i < kft->num; i++) - kfree(kft->table[i]); - - kfree(kft->table); -} - -static -struct property * __init tilcdc_prop_dup(const struct property *prop, - struct kfree_table *kft) -{ - struct property *nprop; - - nprop = kzalloc(sizeof(*nprop), GFP_KERNEL); - if (!nprop || kfree_table_add(kft, nprop)) - return NULL; - - nprop->name = kstrdup(prop->name, GFP_KERNEL); - if (!nprop->name || kfree_table_add(kft, nprop->name)) - return NULL; - - nprop->value = kmemdup(prop->value, prop->length, GFP_KERNEL); - if (!nprop->value || kfree_table_add(kft, nprop->value)) - return NULL; - - nprop->length = prop->length; - - return nprop; -} - -static void __init tilcdc_copy_props(struct device_node *from, - struct device_node *to, - const char * const props[], - struct kfree_table *kft) -{ - struct property *prop; - int i; - - for (i = 0; props[i]; i++) { - prop = of_find_property(from, props[i], NULL); - if (!prop) - continue; - - prop = tilcdc_prop_dup(prop, kft); - if (!prop) - continue; - - prop->next = to->properties; - to->properties = prop; - } -} - -static int __init tilcdc_prop_str_update(struct property *prop, - const char *str, - struct kfree_table *kft) -{ - prop->value = kstrdup(str, GFP_KERNEL); - if (kfree_table_add(kft, prop->value) || !prop->value) - return -ENOMEM; - prop->length = strlen(str)+1; - return 0; -} - -static void __init tilcdc_node_disable(struct device_node *node) -{ - struct property *prop; - - prop = kzalloc(sizeof(*prop), GFP_KERNEL); - if (!prop) - return; - - prop->name = "status"; - prop->value = "disabled"; - prop->length = strlen((char *)prop->value)+1; - - of_update_property(node, prop); -} - -static struct device_node * __init tilcdc_get_overlay(struct kfree_table *kft) -{ - const int size = __dtb_tilcdc_slave_compat_end - - __dtb_tilcdc_slave_compat_begin; - static void *overlay_data; - struct device_node *overlay; - int ret; - - if (!size) { - pr_warn("%s: No overlay data\n", __func__); - return NULL; - } - - overlay_data = kmemdup(__dtb_tilcdc_slave_compat_begin, - size, GFP_KERNEL); - if (!overlay_data || kfree_table_add(kft, overlay_data)) - return NULL; - - of_fdt_unflatten_tree(overlay_data, NULL, &overlay); - if (!overlay) { - pr_warn("%s: Unfattening overlay tree failed\n", __func__); - return NULL; - } - - ret = of_resolve_phandles(overlay); - if (ret) { - pr_err("%s: Failed to resolve phandles: %d\n", __func__, ret); - return NULL; - } - - return overlay; -} - -static const struct of_device_id tilcdc_slave_of_match[] __initconst = { - { .compatible = "ti,tilcdc,slave", }, - {}, -}; - -static const struct of_device_id tilcdc_of_match[] __initconst = { - { .compatible = "ti,am33xx-tilcdc", }, - {}, -}; - -static const struct of_device_id tilcdc_tda998x_of_match[] __initconst = { - { .compatible = "nxp,tda998x", }, - {}, -}; - -static const char * const tilcdc_slave_props[] __initconst = { - "pinctrl-names", - "pinctrl-0", - "pinctrl-1", - NULL -}; - -static void __init tilcdc_convert_slave_node(void) -{ - struct device_node *slave = NULL, *lcdc = NULL; - struct device_node *i2c = NULL, *fragment = NULL; - struct device_node *overlay, *encoder; - struct property *prop; - /* For all memory needed for the overlay tree. This memory can - be freed after the overlay has been applied. */ - struct kfree_table kft; - int ret; - - if (kfree_table_init(&kft)) - return; - - lcdc = of_find_matching_node(NULL, tilcdc_of_match); - slave = of_find_matching_node(NULL, tilcdc_slave_of_match); - - if (!slave || !of_device_is_available(lcdc)) - goto out; - - i2c = of_parse_phandle(slave, "i2c", 0); - if (!i2c) { - pr_err("%s: Can't find i2c node trough phandle\n", __func__); - goto out; - } - - overlay = tilcdc_get_overlay(&kft); - if (!overlay) - goto out; - - encoder = of_find_matching_node(overlay, tilcdc_tda998x_of_match); - if (!encoder) { - pr_err("%s: Failed to find tda998x node\n", __func__); - goto out; - } - - tilcdc_copy_props(slave, encoder, tilcdc_slave_props, &kft); - - for_each_child_of_node(overlay, fragment) { - prop = of_find_property(fragment, "target-path", NULL); - if (!prop) - continue; - if (!strncmp("i2c", (char *)prop->value, prop->length)) - if (tilcdc_prop_str_update(prop, i2c->full_name, &kft)) - goto out; - if (!strncmp("lcdc", (char *)prop->value, prop->length)) - if (tilcdc_prop_str_update(prop, lcdc->full_name, &kft)) - goto out; - } - - tilcdc_node_disable(slave); - - ret = of_overlay_create(overlay); - if (ret) - pr_err("%s: Creating overlay failed: %d\n", __func__, ret); - else - pr_info("%s: ti,tilcdc,slave node successfully converted\n", - __func__); -out: - kfree_table_free(&kft); - of_node_put(i2c); - of_node_put(slave); - of_node_put(lcdc); - of_node_put(fragment); -} - -static int __init tilcdc_slave_compat_init(void) -{ - tilcdc_convert_slave_node(); - return 0; -} - -subsys_initcall(tilcdc_slave_compat_init); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts deleted file mode 100644 index 693f8b0aea2d..000000000000 --- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.dts +++ /dev/null @@ -1,72 +0,0 @@ -/* - * DTS overlay for converting ti,tilcdc,slave binding to new binding. - * - * Copyright (C) 2015 Texas Instruments Inc. - * Author: Jyri Sarha <[email protected]> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - */ - -/* - * target-path property values are simple tags that are replaced with - * correct values in tildcdc_slave_compat.c. Some properties are also - * copied over from the ti,tilcdc,slave node. - */ - -/dts-v1/; -/ { - fragment@0 { - target-path = "i2c"; - __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - tda19988 { - compatible = "nxp,tda998x"; - reg = <0x70>; - status = "okay"; - - port { - hdmi_0: endpoint@0 { - remote-endpoint = <&lcd_0>; - }; - }; - }; - }; - }; - - fragment@1 { - target-path = "lcdc"; - __overlay__ { - port { - lcd_0: endpoint@0 { - remote-endpoint = <&hdmi_0>; - }; - }; - }; - }; - - __local_fixups__ { - fragment@0 { - __overlay__ { - tda19988 { - port { - endpoint@0 { - remote-endpoint = <0>; - }; - }; - }; - }; - }; - fragment@1 { - __overlay__ { - port { - endpoint@0 { - remote-endpoint = <0>; - }; - }; - }; - }; - }; -}; diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h b/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h deleted file mode 100644 index 403d35d87d0b..000000000000 --- a/drivers/gpu/drm/tilcdc/tilcdc_slave_compat.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (C) 2015 Texas Instruments - * Author: Jyri Sarha <[email protected]> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ -/* This header declares the symbols defined in tilcdc_slave_compat.dts */ - -#ifndef __TILCDC_SLAVE_COMPAT_H__ -#define __TILCDC_SLAVE_COMPAT_H__ - -extern uint8_t __dtb_tilcdc_slave_compat_begin[]; -extern uint8_t __dtb_tilcdc_slave_compat_end[]; - -#endif /* __TILCDC_SLAVE_COMPAT_H__ */ diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index 316f831ad5f0..b0551aa677b8 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -744,12 +744,14 @@ static void ttm_put_pages(struct page **pages, unsigned npages, int flags, } #ifdef CONFIG_TRANSPARENT_HUGEPAGE - for (j = 0; j < HPAGE_PMD_NR; ++j) - if (p++ != pages[i + j]) - break; + if (!(flags & TTM_PAGE_FLAG_DMA32)) { + for (j = 0; j < HPAGE_PMD_NR; ++j) + if (p++ != pages[i + j]) + break; - if (j == HPAGE_PMD_NR) - order = HPAGE_PMD_ORDER; + if (j == HPAGE_PMD_NR) + order = HPAGE_PMD_ORDER; + } #endif if (page_count(pages[i]) != 1) @@ -865,20 +867,22 @@ static int ttm_get_pages(struct page **pages, unsigned npages, int flags, i = 0; #ifdef CONFIG_TRANSPARENT_HUGEPAGE - while (npages >= HPAGE_PMD_NR) { - gfp_t huge_flags = gfp_flags; + if (!(gfp_flags & GFP_DMA32)) { + while (npages >= HPAGE_PMD_NR) { + gfp_t huge_flags = gfp_flags; - huge_flags |= GFP_TRANSHUGE; - huge_flags &= ~__GFP_MOVABLE; - huge_flags &= ~__GFP_COMP; - p = alloc_pages(huge_flags, HPAGE_PMD_ORDER); - if (!p) - break; + huge_flags |= GFP_TRANSHUGE; + huge_flags &= ~__GFP_MOVABLE; + huge_flags &= ~__GFP_COMP; + p = alloc_pages(huge_flags, HPAGE_PMD_ORDER); + if (!p) + break; - for (j = 0; j < HPAGE_PMD_NR; ++j) - pages[i++] = p++; + for (j = 0; j < HPAGE_PMD_NR; ++j) + pages[i++] = p++; - npages -= HPAGE_PMD_NR; + npages -= HPAGE_PMD_NR; + } } #endif diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c index 01a53ba304f8..98a6cb9f44fc 100644 --- a/drivers/gpu/drm/vc4/vc4_bo.c +++ b/drivers/gpu/drm/vc4/vc4_bo.c @@ -88,11 +88,11 @@ int vc4_bo_stats_debugfs(struct seq_file *m, void *unused) mutex_lock(&vc4->purgeable.lock); if (vc4->purgeable.num) - seq_printf(m, "%30s: %6dkb BOs (%d)\n", "userspace BO cache", + seq_printf(m, "%30s: %6zdkb BOs (%d)\n", "userspace BO cache", vc4->purgeable.size / 1024, vc4->purgeable.num); if (vc4->purgeable.purged_num) - seq_printf(m, "%30s: %6dkb BOs (%d)\n", "total purged BO", + seq_printf(m, "%30s: %6zdkb BOs (%d)\n", "total purged BO", vc4->purgeable.purged_size / 1024, vc4->purgeable.purged_num); mutex_unlock(&vc4->purgeable.lock); diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c index 7a4b8362dda8..49bfe6e7d005 100644 --- a/drivers/gpu/ipu-v3/ipu-dc.c +++ b/drivers/gpu/ipu-v3/ipu-dc.c @@ -249,11 +249,8 @@ EXPORT_SYMBOL_GPL(ipu_dc_enable); void ipu_dc_enable_channel(struct ipu_dc *dc) { - int di; u32 reg; - di = dc->di; - reg = readl(dc->base + DC_WR_CH_CONF); reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL; writel(reg, dc->base + DC_WR_CH_CONF); diff --git a/include/drm/amd_asic_type.h b/include/drm/amd_asic_type.h new file mode 100644 index 000000000000..599028f66585 --- /dev/null +++ b/include/drm/amd_asic_type.h @@ -0,0 +1,52 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __AMD_ASIC_TYPE_H__ +#define __AMD_ASIC_TYPE_H__ +/* + * Supported ASIC types + */ +enum amd_asic_type { + CHIP_TAHITI = 0, + CHIP_PITCAIRN, + CHIP_VERDE, + CHIP_OLAND, + CHIP_HAINAN, + CHIP_BONAIRE, + CHIP_KAVERI, + CHIP_KABINI, + CHIP_HAWAII, + CHIP_MULLINS, + CHIP_TOPAZ, + CHIP_TONGA, + CHIP_FIJI, + CHIP_CARRIZO, + CHIP_STONEY, + CHIP_POLARIS10, + CHIP_POLARIS11, + CHIP_POLARIS12, + CHIP_VEGA10, + CHIP_RAVEN, + CHIP_LAST, +}; + +#endif /*__AMD_ASIC_TYPE_H__ */ diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index b4285c40e1e4..df9807a3caae 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -284,6 +284,11 @@ struct drm_display_info { * @hdmi: advance features of a HDMI sink. */ struct drm_hdmi_info hdmi; + + /** + * @non_desktop: Non desktop display (HMD). + */ + bool non_desktop; }; int drm_display_info_set_bus_formats(struct drm_display_info *info, @@ -933,6 +938,7 @@ static inline unsigned drm_connector_index(struct drm_connector *connector) /** * drm_connector_lookup - lookup connector object * @dev: DRM device + * @file_priv: drm file to check for lease against. * @id: connector object id * * This function looks up the connector object specified by id diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index f7fcceef46d9..a2d81d2907a9 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -952,6 +952,7 @@ struct drm_crtc *drm_crtc_from_index(struct drm_device *dev, int idx); /** * drm_crtc_find - look up a CRTC object from its ID * @dev: DRM device + * @file_priv: drm file to check for lease against. * @id: &drm_mode_object ID * * This can be used to look up a CRTC from its userspace ID. Only used by diff --git a/include/drm/drm_encoder.h b/include/drm/drm_encoder.h index 86db0da8bdcb..ee4cfbe63c52 100644 --- a/include/drm/drm_encoder.h +++ b/include/drm/drm_encoder.h @@ -208,6 +208,7 @@ static inline bool drm_encoder_crtc_ok(struct drm_encoder *encoder, /** * drm_encoder_find - find a &drm_encoder * @dev: DRM device + * @file_priv: drm file to check for lease against. * @id: encoder id * * Returns the encoder with @id, NULL if it doesn't exist. Simple wrapper around diff --git a/include/drm/drm_mode_config.h b/include/drm/drm_mode_config.h index 0b4ac2ebc610..b21e827c5c78 100644 --- a/include/drm/drm_mode_config.h +++ b/include/drm/drm_mode_config.h @@ -728,6 +728,13 @@ struct drm_mode_config { */ struct drm_property *suggested_y_property; + /** + * @non_desktop_property: Optional connector property with a hint + * that device isn't a standard display, and the console/desktop, + * should not be displayed on it. + */ + struct drm_property *non_desktop_property; + /* dumb ioctl parameters */ uint32_t preferred_depth, prefer_shadow; diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h index 069c4c8ce360..571615079230 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -591,6 +591,7 @@ int drm_mode_plane_set_obj_prop(struct drm_plane *plane, /** * drm_plane_find - find a &drm_plane * @dev: DRM device + * @file_priv: drm file to check for lease against. * @id: plane id * * Returns the plane with @id, NULL if it doesn't exist. Simple wrapper around diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h index 429d8218f740..8a522b4bed40 100644 --- a/include/drm/drm_property.h +++ b/include/drm/drm_property.h @@ -305,8 +305,9 @@ drm_property_unreference_blob(struct drm_property_blob *blob) } /** - * drm_connector_find - find property object + * drm_property_find - find property object * @dev: DRM device + * @file_priv: drm file to check for lease against. * @id: property object id * * This function looks up the property object specified by id and returns it. diff --git a/include/dt-bindings/msm/msm-bus-ids.h b/include/dt-bindings/msm/msm-bus-ids.h deleted file mode 100644 index a75d304473d5..000000000000 --- a/include/dt-bindings/msm/msm-bus-ids.h +++ /dev/null @@ -1,887 +0,0 @@ -/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __MSM_BUS_IDS_H -#define __MSM_BUS_IDS_H - -/* Aggregation types */ -#define AGG_SCHEME_NONE 0 -#define AGG_SCHEME_LEG 1 -#define AGG_SCHEME_1 2 - -/* Topology related enums */ -#define MSM_BUS_FAB_DEFAULT 0 -#define MSM_BUS_FAB_APPSS 0 -#define MSM_BUS_FAB_SYSTEM 1024 -#define MSM_BUS_FAB_MMSS 2048 -#define MSM_BUS_FAB_SYSTEM_FPB 3072 -#define MSM_BUS_FAB_CPSS_FPB 4096 - -#define MSM_BUS_FAB_BIMC 0 -#define MSM_BUS_FAB_SYS_NOC 1024 -#define MSM_BUS_FAB_MMSS_NOC 2048 -#define MSM_BUS_FAB_OCMEM_NOC 3072 -#define MSM_BUS_FAB_PERIPH_NOC 4096 -#define MSM_BUS_FAB_CONFIG_NOC 5120 -#define MSM_BUS_FAB_OCMEM_VNOC 6144 -#define MSM_BUS_FAB_MMSS_AHB 2049 -#define MSM_BUS_FAB_A0_NOC 6145 -#define MSM_BUS_FAB_A1_NOC 6146 -#define MSM_BUS_FAB_A2_NOC 6147 -#define MSM_BUS_FAB_GNOC 6148 -#define MSM_BUS_FAB_CR_VIRT 6149 - -#define MSM_BUS_MASTER_FIRST 1 -#define MSM_BUS_MASTER_AMPSS_M0 1 -#define MSM_BUS_MASTER_AMPSS_M1 2 -#define MSM_BUS_APPSS_MASTER_FAB_MMSS 3 -#define MSM_BUS_APPSS_MASTER_FAB_SYSTEM 4 -#define MSM_BUS_SYSTEM_MASTER_FAB_APPSS 5 -#define MSM_BUS_MASTER_SPS 6 -#define MSM_BUS_MASTER_ADM_PORT0 7 -#define MSM_BUS_MASTER_ADM_PORT1 8 -#define MSM_BUS_SYSTEM_MASTER_ADM1_PORT0 9 -#define MSM_BUS_MASTER_ADM1_PORT1 10 -#define MSM_BUS_MASTER_LPASS_PROC 11 -#define MSM_BUS_MASTER_MSS_PROCI 12 -#define MSM_BUS_MASTER_MSS_PROCD 13 -#define MSM_BUS_MASTER_MSS_MDM_PORT0 14 -#define MSM_BUS_MASTER_LPASS 15 -#define MSM_BUS_SYSTEM_MASTER_CPSS_FPB 16 -#define MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB 17 -#define MSM_BUS_SYSTEM_MASTER_MMSS_FPB 18 -#define MSM_BUS_MASTER_ADM1_CI 19 -#define MSM_BUS_MASTER_ADM0_CI 20 -#define MSM_BUS_MASTER_MSS_MDM_PORT1 21 -#define MSM_BUS_MASTER_MDP_PORT0 22 -#define MSM_BUS_MASTER_MDP_PORT1 23 -#define MSM_BUS_MMSS_MASTER_ADM1_PORT0 24 -#define MSM_BUS_MASTER_ROTATOR 25 -#define MSM_BUS_MASTER_GRAPHICS_3D 26 -#define MSM_BUS_MASTER_JPEG_DEC 27 -#define MSM_BUS_MASTER_GRAPHICS_2D_CORE0 28 -#define MSM_BUS_MASTER_VFE 29 -#define MSM_BUS_MASTER_VFE0 MSM_BUS_MASTER_VFE -#define MSM_BUS_MASTER_VPE 30 -#define MSM_BUS_MASTER_JPEG_ENC 31 -#define MSM_BUS_MASTER_GRAPHICS_2D_CORE1 32 -#define MSM_BUS_MMSS_MASTER_APPS_FAB 33 -#define MSM_BUS_MASTER_HD_CODEC_PORT0 34 -#define MSM_BUS_MASTER_HD_CODEC_PORT1 35 -#define MSM_BUS_MASTER_SPDM 36 -#define MSM_BUS_MASTER_RPM 37 -#define MSM_BUS_MASTER_MSS 38 -#define MSM_BUS_MASTER_RIVA 39 -#define MSM_BUS_MASTER_SNOC_VMEM 40 -#define MSM_BUS_MASTER_MSS_SW_PROC 41 -#define MSM_BUS_MASTER_MSS_FW_PROC 42 -#define MSM_BUS_MASTER_HMSS 43 -#define MSM_BUS_MASTER_GSS_NAV 44 -#define MSM_BUS_MASTER_PCIE 45 -#define MSM_BUS_MASTER_SATA 46 -#define MSM_BUS_MASTER_CRYPTO 47 -#define MSM_BUS_MASTER_VIDEO_CAP 48 -#define MSM_BUS_MASTER_GRAPHICS_3D_PORT1 49 -#define MSM_BUS_MASTER_VIDEO_ENC 50 -#define MSM_BUS_MASTER_VIDEO_DEC 51 -#define MSM_BUS_MASTER_LPASS_AHB 52 -#define MSM_BUS_MASTER_QDSS_BAM 53 -#define MSM_BUS_MASTER_SNOC_CFG 54 -#define MSM_BUS_MASTER_CRYPTO_CORE0 55 -#define MSM_BUS_MASTER_CRYPTO_CORE1 56 -#define MSM_BUS_MASTER_MSS_NAV 57 -#define MSM_BUS_MASTER_OCMEM_DMA 58 -#define MSM_BUS_MASTER_WCSS 59 -#define MSM_BUS_MASTER_QDSS_ETR 60 -#define MSM_BUS_MASTER_USB3 61 -#define MSM_BUS_MASTER_JPEG 62 -#define MSM_BUS_MASTER_VIDEO_P0 63 -#define MSM_BUS_MASTER_VIDEO_P1 64 -#define MSM_BUS_MASTER_MSS_PROC 65 -#define MSM_BUS_MASTER_JPEG_OCMEM 66 -#define MSM_BUS_MASTER_MDP_OCMEM 67 -#define MSM_BUS_MASTER_VIDEO_P0_OCMEM 68 -#define MSM_BUS_MASTER_VIDEO_P1_OCMEM 69 -#define MSM_BUS_MASTER_VFE_OCMEM 70 -#define MSM_BUS_MASTER_CNOC_ONOC_CFG 71 -#define MSM_BUS_MASTER_RPM_INST 72 -#define MSM_BUS_MASTER_RPM_DATA 73 -#define MSM_BUS_MASTER_RPM_SYS 74 -#define MSM_BUS_MASTER_DEHR 75 -#define MSM_BUS_MASTER_QDSS_DAP 76 -#define MSM_BUS_MASTER_TIC 77 -#define MSM_BUS_MASTER_SDCC_1 78 -#define MSM_BUS_MASTER_SDCC_3 79 -#define MSM_BUS_MASTER_SDCC_4 80 -#define MSM_BUS_MASTER_SDCC_2 81 -#define MSM_BUS_MASTER_TSIF 82 -#define MSM_BUS_MASTER_BAM_DMA 83 -#define MSM_BUS_MASTER_BLSP_2 84 -#define MSM_BUS_MASTER_USB_HSIC 85 -#define MSM_BUS_MASTER_BLSP_1 86 -#define MSM_BUS_MASTER_USB_HS 87 -#define MSM_BUS_MASTER_PNOC_CFG 88 -#define MSM_BUS_MASTER_V_OCMEM_GFX3D 89 -#define MSM_BUS_MASTER_IPA 90 -#define MSM_BUS_MASTER_QPIC 91 -#define MSM_BUS_MASTER_MDPE 92 -#define MSM_BUS_MASTER_USB_HS2 93 -#define MSM_BUS_MASTER_VPU 94 -#define MSM_BUS_MASTER_UFS 95 -#define MSM_BUS_MASTER_BCAST 96 -#define MSM_BUS_MASTER_CRYPTO_CORE2 97 -#define MSM_BUS_MASTER_EMAC 98 -#define MSM_BUS_MASTER_VPU_1 99 -#define MSM_BUS_MASTER_PCIE_1 100 -#define MSM_BUS_MASTER_USB3_1 101 -#define MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG 102 -#define MSM_BUS_MASTER_CNOC_MNOC_CFG 103 -#define MSM_BUS_MASTER_TCU_0 104 -#define MSM_BUS_MASTER_TCU_1 105 -#define MSM_BUS_MASTER_CPP 106 -#define MSM_BUS_MASTER_AUDIO 107 -#define MSM_BUS_MASTER_PCIE_2 108 -#define MSM_BUS_MASTER_VFE1 109 -#define MSM_BUS_MASTER_XM_USB_HS1 110 -#define MSM_BUS_MASTER_PCNOC_BIMC_1 111 -#define MSM_BUS_MASTER_BIMC_PCNOC 112 -#define MSM_BUS_MASTER_XI_USB_HSIC 113 -#define MSM_BUS_MASTER_SGMII 114 -#define MSM_BUS_SPMI_FETCHER 115 -#define MSM_BUS_MASTER_GNOC_BIMC 116 -#define MSM_BUS_MASTER_CRVIRT_A2NOC 117 -#define MSM_BUS_MASTER_CNOC_A2NOC 118 -#define MSM_BUS_MASTER_WLAN 119 -#define MSM_BUS_MASTER_MSS_CE 120 -#define MSM_BUS_MASTER_CDSP_PROC 121 -#define MSM_BUS_MASTER_GNOC_SNOC 122 -#define MSM_BUS_MASTER_PIMEM 123 -#define MSM_BUS_MASTER_MASTER_LAST 124 - -#define MSM_BUS_SYSTEM_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_SYSTEM_FPB -#define MSM_BUS_CPSS_FPB_MASTER_SYSTEM MSM_BUS_SYSTEM_MASTER_CPSS_FPB - -#define MSM_BUS_SNOC_MM_INT_0 10000 -#define MSM_BUS_SNOC_MM_INT_1 10001 -#define MSM_BUS_SNOC_MM_INT_2 10002 -#define MSM_BUS_SNOC_MM_INT_BIMC 10003 -#define MSM_BUS_SNOC_INT_0 10004 -#define MSM_BUS_SNOC_INT_1 10005 -#define MSM_BUS_SNOC_INT_BIMC 10006 -#define MSM_BUS_SNOC_BIMC_0_MAS 10007 -#define MSM_BUS_SNOC_BIMC_1_MAS 10008 -#define MSM_BUS_SNOC_QDSS_INT 10009 -#define MSM_BUS_PNOC_SNOC_MAS 10010 -#define MSM_BUS_PNOC_SNOC_SLV 10011 -#define MSM_BUS_PNOC_INT_0 10012 -#define MSM_BUS_PNOC_INT_1 10013 -#define MSM_BUS_PNOC_M_0 10014 -#define MSM_BUS_PNOC_M_1 10015 -#define MSM_BUS_BIMC_SNOC_MAS 10016 -#define MSM_BUS_BIMC_SNOC_SLV 10017 -#define MSM_BUS_PNOC_SLV_0 10018 -#define MSM_BUS_PNOC_SLV_1 10019 -#define MSM_BUS_PNOC_SLV_2 10020 -#define MSM_BUS_PNOC_SLV_3 10021 -#define MSM_BUS_PNOC_SLV_4 10022 -#define MSM_BUS_PNOC_SLV_8 10023 -#define MSM_BUS_PNOC_SLV_9 10024 -#define MSM_BUS_SNOC_BIMC_0_SLV 10025 -#define MSM_BUS_SNOC_BIMC_1_SLV 10026 -#define MSM_BUS_MNOC_BIMC_MAS 10027 -#define MSM_BUS_MNOC_BIMC_SLV 10028 -#define MSM_BUS_BIMC_MNOC_MAS 10029 -#define MSM_BUS_BIMC_MNOC_SLV 10030 -#define MSM_BUS_SNOC_BIMC_MAS 10031 -#define MSM_BUS_SNOC_BIMC_SLV 10032 -#define MSM_BUS_CNOC_SNOC_MAS 10033 -#define MSM_BUS_CNOC_SNOC_SLV 10034 -#define MSM_BUS_SNOC_CNOC_MAS 10035 -#define MSM_BUS_SNOC_CNOC_SLV 10036 -#define MSM_BUS_OVNOC_SNOC_MAS 10037 -#define MSM_BUS_OVNOC_SNOC_SLV 10038 -#define MSM_BUS_SNOC_OVNOC_MAS 10039 -#define MSM_BUS_SNOC_OVNOC_SLV 10040 -#define MSM_BUS_SNOC_PNOC_MAS 10041 -#define MSM_BUS_SNOC_PNOC_SLV 10042 -#define MSM_BUS_BIMC_INT_APPS_EBI 10043 -#define MSM_BUS_BIMC_INT_APPS_SNOC 10044 -#define MSM_BUS_SNOC_BIMC_2_MAS 10045 -#define MSM_BUS_SNOC_BIMC_2_SLV 10046 -#define MSM_BUS_PNOC_SLV_5 10047 -#define MSM_BUS_PNOC_SLV_7 10048 -#define MSM_BUS_PNOC_INT_2 10049 -#define MSM_BUS_PNOC_INT_3 10050 -#define MSM_BUS_PNOC_INT_4 10051 -#define MSM_BUS_PNOC_INT_5 10052 -#define MSM_BUS_PNOC_INT_6 10053 -#define MSM_BUS_PNOC_INT_7 10054 -#define MSM_BUS_BIMC_SNOC_1_MAS 10055 -#define MSM_BUS_BIMC_SNOC_1_SLV 10056 -#define MSM_BUS_PNOC_A1NOC_MAS 10057 -#define MSM_BUS_PNOC_A1NOC_SLV 10058 -#define MSM_BUS_CNOC_A1NOC_MAS 10059 -#define MSM_BUS_A0NOC_SNOC_MAS 10060 -#define MSM_BUS_A0NOC_SNOC_SLV 10061 -#define MSM_BUS_A1NOC_SNOC_SLV 10062 -#define MSM_BUS_A1NOC_SNOC_MAS 10063 -#define MSM_BUS_A2NOC_SNOC_MAS 10064 -#define MSM_BUS_A2NOC_SNOC_SLV 10065 -#define MSM_BUS_SNOC_INT_2 10066 -#define MSM_BUS_A0NOC_QDSS_INT 10067 -#define MSM_BUS_INT_LAST 10068 - -#define MSM_BUS_INT_TEST_ID 20000 -#define MSM_BUS_INT_TEST_LAST 20050 - -#define MSM_BUS_SLAVE_FIRST 512 -#define MSM_BUS_SLAVE_EBI_CH0 512 -#define MSM_BUS_SLAVE_EBI_CH1 513 -#define MSM_BUS_SLAVE_AMPSS_L2 514 -#define MSM_BUS_APPSS_SLAVE_FAB_MMSS 515 -#define MSM_BUS_APPSS_SLAVE_FAB_SYSTEM 516 -#define MSM_BUS_SYSTEM_SLAVE_FAB_APPS 517 -#define MSM_BUS_SLAVE_SPS 518 -#define MSM_BUS_SLAVE_SYSTEM_IMEM 519 -#define MSM_BUS_SLAVE_AMPSS 520 -#define MSM_BUS_SLAVE_MSS 521 -#define MSM_BUS_SLAVE_LPASS 522 -#define MSM_BUS_SYSTEM_SLAVE_CPSS_FPB 523 -#define MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB 524 -#define MSM_BUS_SYSTEM_SLAVE_MMSS_FPB 525 -#define MSM_BUS_SLAVE_CORESIGHT 526 -#define MSM_BUS_SLAVE_RIVA 527 -#define MSM_BUS_SLAVE_SMI 528 -#define MSM_BUS_MMSS_SLAVE_FAB_APPS 529 -#define MSM_BUS_MMSS_SLAVE_FAB_APPS_1 530 -#define MSM_BUS_SLAVE_MM_IMEM 531 -#define MSM_BUS_SLAVE_CRYPTO 532 -#define MSM_BUS_SLAVE_SPDM 533 -#define MSM_BUS_SLAVE_RPM 534 -#define MSM_BUS_SLAVE_RPM_MSG_RAM 535 -#define MSM_BUS_SLAVE_MPM 536 -#define MSM_BUS_SLAVE_PMIC1_SSBI1_A 537 -#define MSM_BUS_SLAVE_PMIC1_SSBI1_B 538 -#define MSM_BUS_SLAVE_PMIC1_SSBI1_C 539 -#define MSM_BUS_SLAVE_PMIC2_SSBI2_A 540 -#define MSM_BUS_SLAVE_PMIC2_SSBI2_B 541 -#define MSM_BUS_SLAVE_GSBI1_UART 542 -#define MSM_BUS_SLAVE_GSBI2_UART 543 -#define MSM_BUS_SLAVE_GSBI3_UART 544 -#define MSM_BUS_SLAVE_GSBI4_UART 545 -#define MSM_BUS_SLAVE_GSBI5_UART 546 -#define MSM_BUS_SLAVE_GSBI6_UART 547 -#define MSM_BUS_SLAVE_GSBI7_UART 548 -#define MSM_BUS_SLAVE_GSBI8_UART 549 -#define MSM_BUS_SLAVE_GSBI9_UART 550 -#define MSM_BUS_SLAVE_GSBI10_UART 551 -#define MSM_BUS_SLAVE_GSBI11_UART 552 -#define MSM_BUS_SLAVE_GSBI12_UART 553 -#define MSM_BUS_SLAVE_GSBI1_QUP 554 -#define MSM_BUS_SLAVE_GSBI2_QUP 555 -#define MSM_BUS_SLAVE_GSBI3_QUP 556 -#define MSM_BUS_SLAVE_GSBI4_QUP 557 -#define MSM_BUS_SLAVE_GSBI5_QUP 558 -#define MSM_BUS_SLAVE_GSBI6_QUP 559 -#define MSM_BUS_SLAVE_GSBI7_QUP 560 -#define MSM_BUS_SLAVE_GSBI8_QUP 561 -#define MSM_BUS_SLAVE_GSBI9_QUP 562 -#define MSM_BUS_SLAVE_GSBI10_QUP 563 -#define MSM_BUS_SLAVE_GSBI11_QUP 564 -#define MSM_BUS_SLAVE_GSBI12_QUP 565 -#define MSM_BUS_SLAVE_EBI2_NAND 566 -#define MSM_BUS_SLAVE_EBI2_CS0 567 -#define MSM_BUS_SLAVE_EBI2_CS1 568 -#define MSM_BUS_SLAVE_EBI2_CS2 569 -#define MSM_BUS_SLAVE_EBI2_CS3 570 -#define MSM_BUS_SLAVE_EBI2_CS4 571 -#define MSM_BUS_SLAVE_EBI2_CS5 572 -#define MSM_BUS_SLAVE_USB_FS1 573 -#define MSM_BUS_SLAVE_USB_FS2 574 -#define MSM_BUS_SLAVE_TSIF 575 -#define MSM_BUS_SLAVE_MSM_TSSC 576 -#define MSM_BUS_SLAVE_MSM_PDM 577 -#define MSM_BUS_SLAVE_MSM_DIMEM 578 -#define MSM_BUS_SLAVE_MSM_TCSR 579 -#define MSM_BUS_SLAVE_MSM_PRNG 580 -#define MSM_BUS_SLAVE_GSS 581 -#define MSM_BUS_SLAVE_SATA 582 -#define MSM_BUS_SLAVE_USB3 583 -#define MSM_BUS_SLAVE_WCSS 584 -#define MSM_BUS_SLAVE_OCIMEM 585 -#define MSM_BUS_SLAVE_SNOC_OCMEM 586 -#define MSM_BUS_SLAVE_SERVICE_SNOC 587 -#define MSM_BUS_SLAVE_QDSS_STM 588 -#define MSM_BUS_SLAVE_CAMERA_CFG 589 -#define MSM_BUS_SLAVE_DISPLAY_CFG 590 -#define MSM_BUS_SLAVE_OCMEM_CFG 591 -#define MSM_BUS_SLAVE_CPR_CFG 592 -#define MSM_BUS_SLAVE_CPR_XPU_CFG 593 -#define MSM_BUS_SLAVE_MISC_CFG 594 -#define MSM_BUS_SLAVE_MISC_XPU_CFG 595 -#define MSM_BUS_SLAVE_VENUS_CFG 596 -#define MSM_BUS_SLAVE_MISC_VENUS_CFG 597 -#define MSM_BUS_SLAVE_GRAPHICS_3D_CFG 598 -#define MSM_BUS_SLAVE_MMSS_CLK_CFG 599 -#define MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG 600 -#define MSM_BUS_SLAVE_MNOC_MPU_CFG 601 -#define MSM_BUS_SLAVE_ONOC_MPU_CFG 602 -#define MSM_BUS_SLAVE_SERVICE_MNOC 603 -#define MSM_BUS_SLAVE_OCMEM 604 -#define MSM_BUS_SLAVE_SERVICE_ONOC 605 -#define MSM_BUS_SLAVE_SDCC_1 606 -#define MSM_BUS_SLAVE_SDCC_3 607 -#define MSM_BUS_SLAVE_SDCC_2 608 -#define MSM_BUS_SLAVE_SDCC_4 609 -#define MSM_BUS_SLAVE_BAM_DMA 610 -#define MSM_BUS_SLAVE_BLSP_2 611 -#define MSM_BUS_SLAVE_USB_HSIC 612 -#define MSM_BUS_SLAVE_BLSP_1 613 -#define MSM_BUS_SLAVE_USB_HS 614 -#define MSM_BUS_SLAVE_PDM 615 -#define MSM_BUS_SLAVE_PERIPH_APU_CFG 616 -#define MSM_BUS_SLAVE_PNOC_MPU_CFG 617 -#define MSM_BUS_SLAVE_PRNG 618 -#define MSM_BUS_SLAVE_SERVICE_PNOC 619 -#define MSM_BUS_SLAVE_CLK_CTL 620 -#define MSM_BUS_SLAVE_CNOC_MSS 621 -#define MSM_BUS_SLAVE_SECURITY 622 -#define MSM_BUS_SLAVE_TCSR 623 -#define MSM_BUS_SLAVE_TLMM 624 -#define MSM_BUS_SLAVE_CRYPTO_0_CFG 625 -#define MSM_BUS_SLAVE_CRYPTO_1_CFG 626 -#define MSM_BUS_SLAVE_IMEM_CFG 627 -#define MSM_BUS_SLAVE_MESSAGE_RAM 628 -#define MSM_BUS_SLAVE_BIMC_CFG 629 -#define MSM_BUS_SLAVE_BOOT_ROM 630 -#define MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG 631 -#define MSM_BUS_SLAVE_PMIC_ARB 632 -#define MSM_BUS_SLAVE_SPDM_WRAPPER 633 -#define MSM_BUS_SLAVE_DEHR_CFG 634 -#define MSM_BUS_SLAVE_QDSS_CFG 635 -#define MSM_BUS_SLAVE_RBCPR_CFG 636 -#define MSM_BUS_SLAVE_RBCPR_QDSS_APU_CFG 637 -#define MSM_BUS_SLAVE_SNOC_MPU_CFG 638 -#define MSM_BUS_SLAVE_CNOC_ONOC_CFG 639 -#define MSM_BUS_SLAVE_CNOC_MNOC_CFG 640 -#define MSM_BUS_SLAVE_PNOC_CFG 641 -#define MSM_BUS_SLAVE_SNOC_CFG 642 -#define MSM_BUS_SLAVE_EBI1_DLL_CFG 643 -#define MSM_BUS_SLAVE_PHY_APU_CFG 644 -#define MSM_BUS_SLAVE_EBI1_PHY_CFG 645 -#define MSM_BUS_SLAVE_SERVICE_CNOC 646 -#define MSM_BUS_SLAVE_IPS_CFG 647 -#define MSM_BUS_SLAVE_QPIC 648 -#define MSM_BUS_SLAVE_DSI_CFG 649 -#define MSM_BUS_SLAVE_UFS_CFG 650 -#define MSM_BUS_SLAVE_RBCPR_CX_CFG 651 -#define MSM_BUS_SLAVE_RBCPR_MX_CFG 652 -#define MSM_BUS_SLAVE_PCIE_CFG 653 -#define MSM_BUS_SLAVE_USB_PHYS_CFG 654 -#define MSM_BUS_SLAVE_VIDEO_CAP_CFG 655 -#define MSM_BUS_SLAVE_AVSYNC_CFG 656 -#define MSM_BUS_SLAVE_CRYPTO_2_CFG 657 -#define MSM_BUS_SLAVE_VPU_CFG 658 -#define MSM_BUS_SLAVE_BCAST_CFG 659 -#define MSM_BUS_SLAVE_KLM_CFG 660 -#define MSM_BUS_SLAVE_GENI_IR_CFG 661 -#define MSM_BUS_SLAVE_OCMEM_GFX 662 -#define MSM_BUS_SLAVE_CATS_128 663 -#define MSM_BUS_SLAVE_OCMEM_64 664 -#define MSM_BUS_SLAVE_PCIE_0 665 -#define MSM_BUS_SLAVE_PCIE_1 666 -#define MSM_BUS_SLAVE_PCIE_0_CFG 667 -#define MSM_BUS_SLAVE_PCIE_1_CFG 668 -#define MSM_BUS_SLAVE_SRVC_MNOC 669 -#define MSM_BUS_SLAVE_USB_HS2 670 -#define MSM_BUS_SLAVE_AUDIO 671 -#define MSM_BUS_SLAVE_TCU 672 -#define MSM_BUS_SLAVE_APPSS 673 -#define MSM_BUS_SLAVE_PCIE_PARF 674 -#define MSM_BUS_SLAVE_USB3_PHY_CFG 675 -#define MSM_BUS_SLAVE_IPA_CFG 676 -#define MSM_BUS_SLAVE_A0NOC_SNOC 677 -#define MSM_BUS_SLAVE_A1NOC_SNOC 678 -#define MSM_BUS_SLAVE_A2NOC_SNOC 679 -#define MSM_BUS_SLAVE_HMSS_L3 680 -#define MSM_BUS_SLAVE_PIMEM_CFG 681 -#define MSM_BUS_SLAVE_DCC_CFG 682 -#define MSM_BUS_SLAVE_QDSS_RBCPR_APU_CFG 683 -#define MSM_BUS_SLAVE_PCIE_2_CFG 684 -#define MSM_BUS_SLAVE_PCIE20_AHB2PHY 685 -#define MSM_BUS_SLAVE_A0NOC_CFG 686 -#define MSM_BUS_SLAVE_A1NOC_CFG 687 -#define MSM_BUS_SLAVE_A2NOC_CFG 688 -#define MSM_BUS_SLAVE_A1NOC_MPU_CFG 689 -#define MSM_BUS_SLAVE_A2NOC_MPU_CFG 690 -#define MSM_BUS_SLAVE_A0NOC_SMMU_CFG 691 -#define MSM_BUS_SLAVE_A1NOC_SMMU_CFG 692 -#define MSM_BUS_SLAVE_A2NOC_SMMU_CFG 693 -#define MSM_BUS_SLAVE_LPASS_SMMU_CFG 694 -#define MSM_BUS_SLAVE_MMAGIC_CFG 695 -#define MSM_BUS_SLAVE_VENUS_THROTTLE_CFG 696 -#define MSM_BUS_SLAVE_SSC_CFG 697 -#define MSM_BUS_SLAVE_DSA_CFG 698 -#define MSM_BUS_SLAVE_DSA_MPU_CFG 699 -#define MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG 700 -#define MSM_BUS_SLAVE_SMMU_CPP_CFG 701 -#define MSM_BUS_SLAVE_SMMU_JPEG_CFG 702 -#define MSM_BUS_SLAVE_SMMU_MDP_CFG 703 -#define MSM_BUS_SLAVE_SMMU_ROTATOR_CFG 704 -#define MSM_BUS_SLAVE_SMMU_VENUS_CFG 705 -#define MSM_BUS_SLAVE_SMMU_VFE_CFG 706 -#define MSM_BUS_SLAVE_A0NOC_MPU_CFG 707 -#define MSM_BUS_SLAVE_VMEM_CFG 708 -#define MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG 709 -#define MSM_BUS_SLAVE_VMEM 710 -#define MSM_BUS_SLAVE_AHB2PHY 711 -#define MSM_BUS_SLAVE_PIMEM 712 -#define MSM_BUS_SLAVE_SNOC_VMEM 713 -#define MSM_BUS_SLAVE_PCIE_2 714 -#define MSM_BUS_SLAVE_RBCPR_MX 715 -#define MSM_BUS_SLAVE_RBCPR_CX 716 -#define MSM_BUS_SLAVE_BIMC_PCNOC 717 -#define MSM_BUS_SLAVE_PCNOC_BIMC_1 718 -#define MSM_BUS_SLAVE_SGMII 719 -#define MSM_BUS_SLAVE_SPMI_FETCHER 720 -#define MSM_BUS_PNOC_SLV_6 721 -#define MSM_BUS_SLAVE_MMSS_SMMU_CFG 722 -#define MSM_BUS_SLAVE_WLAN 723 -#define MSM_BUS_SLAVE_CRVIRT_A2NOC 724 -#define MSM_BUS_SLAVE_CNOC_A2NOC 725 -#define MSM_BUS_SLAVE_GLM 726 -#define MSM_BUS_SLAVE_GNOC_BIMC 727 -#define MSM_BUS_SLAVE_GNOC_SNOC 728 -#define MSM_BUS_SLAVE_QM_CFG 729 -#define MSM_BUS_SLAVE_TLMM_EAST 730 -#define MSM_BUS_SLAVE_TLMM_NORTH 731 -#define MSM_BUS_SLAVE_TLMM_WEST 732 -#define MSM_BUS_SLAVE_SKL 733 -#define MSM_BUS_SLAVE_LPASS_TCM 734 -#define MSM_BUS_SLAVE_TLMM_SOUTH 735 -#define MSM_BUS_SLAVE_TLMM_CENTER 736 -#define MSM_BUS_MSS_NAV_CE_MPU_CFG 737 -#define MSM_BUS_SLAVE_A2NOC_THROTTLE_CFG 738 -#define MSM_BUS_SLAVE_CDSP 739 -#define MSM_BUS_SLAVE_CDSP_SMMU_CFG 740 -#define MSM_BUS_SLAVE_LPASS_MPU_CFG 741 -#define MSM_BUS_SLAVE_CSI_PHY_CFG 742 -#define MSM_BUS_SLAVE_LAST 743 - -#define MSM_BUS_SYSTEM_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_SYSTEM_FPB -#define MSM_BUS_CPSS_FPB_SLAVE_SYSTEM MSM_BUS_SYSTEM_SLAVE_CPSS_FPB - -/* - * ID's used in RPM messages - */ -#define ICBID_MASTER_APPSS_PROC 0 -#define ICBID_MASTER_MSS_PROC 1 -#define ICBID_MASTER_MNOC_BIMC 2 -#define ICBID_MASTER_SNOC_BIMC 3 -#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC -#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4 -#define ICBID_MASTER_CNOC_MNOC_CFG 5 -#define ICBID_MASTER_GFX3D 6 -#define ICBID_MASTER_JPEG 7 -#define ICBID_MASTER_MDP 8 -#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP -#define ICBID_MASTER_MDPS ICBID_MASTER_MDP -#define ICBID_MASTER_VIDEO 9 -#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO -#define ICBID_MASTER_VIDEO_P1 10 -#define ICBID_MASTER_VFE 11 -#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE -#define ICBID_MASTER_CNOC_ONOC_CFG 12 -#define ICBID_MASTER_JPEG_OCMEM 13 -#define ICBID_MASTER_MDP_OCMEM 14 -#define ICBID_MASTER_VIDEO_P0_OCMEM 15 -#define ICBID_MASTER_VIDEO_P1_OCMEM 16 -#define ICBID_MASTER_VFE_OCMEM 17 -#define ICBID_MASTER_LPASS_AHB 18 -#define ICBID_MASTER_QDSS_BAM 19 -#define ICBID_MASTER_SNOC_CFG 20 -#define ICBID_MASTER_BIMC_SNOC 21 -#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC -#define ICBID_MASTER_CNOC_SNOC 22 -#define ICBID_MASTER_CRYPTO 23 -#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO -#define ICBID_MASTER_CRYPTO_CORE1 24 -#define ICBID_MASTER_LPASS_PROC 25 -#define ICBID_MASTER_MSS 26 -#define ICBID_MASTER_MSS_NAV 27 -#define ICBID_MASTER_OCMEM_DMA 28 -#define ICBID_MASTER_PNOC_SNOC 29 -#define ICBID_MASTER_WCSS 30 -#define ICBID_MASTER_QDSS_ETR 31 -#define ICBID_MASTER_USB3 32 -#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3 -#define ICBID_MASTER_SDCC_1 33 -#define ICBID_MASTER_SDCC_3 34 -#define ICBID_MASTER_SDCC_2 35 -#define ICBID_MASTER_SDCC_4 36 -#define ICBID_MASTER_TSIF 37 -#define ICBID_MASTER_BAM_DMA 38 -#define ICBID_MASTER_BLSP_2 39 -#define ICBID_MASTER_USB_HSIC 40 -#define ICBID_MASTER_BLSP_1 41 -#define ICBID_MASTER_USB_HS 42 -#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS -#define ICBID_MASTER_PNOC_CFG 43 -#define ICBID_MASTER_SNOC_PNOC 44 -#define ICBID_MASTER_RPM_INST 45 -#define ICBID_MASTER_RPM_DATA 46 -#define ICBID_MASTER_RPM_SYS 47 -#define ICBID_MASTER_DEHR 48 -#define ICBID_MASTER_QDSS_DAP 49 -#define ICBID_MASTER_SPDM 50 -#define ICBID_MASTER_TIC 51 -#define ICBID_MASTER_SNOC_CNOC 52 -#define ICBID_MASTER_GFX3D_OCMEM 53 -#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM -#define ICBID_MASTER_OVIRT_SNOC 54 -#define ICBID_MASTER_SNOC_OVIRT 55 -#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT -#define ICBID_MASTER_ONOC_OVIRT 56 -#define ICBID_MASTER_USB_HS2 57 -#define ICBID_MASTER_QPIC 58 -#define ICBID_MASTER_IPA 59 -#define ICBID_MASTER_DSI 60 -#define ICBID_MASTER_MDP1 61 -#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1 -#define ICBID_MASTER_VPU_PROC 62 -#define ICBID_MASTER_VPU 63 -#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU -#define ICBID_MASTER_CRYPTO_CORE2 64 -#define ICBID_MASTER_PCIE_0 65 -#define ICBID_MASTER_PCIE_1 66 -#define ICBID_MASTER_SATA 67 -#define ICBID_MASTER_UFS 68 -#define ICBID_MASTER_USB3_1 69 -#define ICBID_MASTER_VIDEO_OCMEM 70 -#define ICBID_MASTER_VPU1 71 -#define ICBID_MASTER_VCAP 72 -#define ICBID_MASTER_EMAC 73 -#define ICBID_MASTER_BCAST 74 -#define ICBID_MASTER_MMSS_PROC 75 -#define ICBID_MASTER_SNOC_BIMC_1 76 -#define ICBID_MASTER_SNOC_PCNOC 77 -#define ICBID_MASTER_AUDIO 78 -#define ICBID_MASTER_MM_INT_0 79 -#define ICBID_MASTER_MM_INT_1 80 -#define ICBID_MASTER_MM_INT_2 81 -#define ICBID_MASTER_MM_INT_BIMC 82 -#define ICBID_MASTER_MSS_INT 83 -#define ICBID_MASTER_PCNOC_CFG 84 -#define ICBID_MASTER_PCNOC_INT_0 85 -#define ICBID_MASTER_PCNOC_INT_1 86 -#define ICBID_MASTER_PCNOC_M_0 87 -#define ICBID_MASTER_PCNOC_M_1 88 -#define ICBID_MASTER_PCNOC_S_0 89 -#define ICBID_MASTER_PCNOC_S_1 90 -#define ICBID_MASTER_PCNOC_S_2 91 -#define ICBID_MASTER_PCNOC_S_3 92 -#define ICBID_MASTER_PCNOC_S_4 93 -#define ICBID_MASTER_PCNOC_S_6 94 -#define ICBID_MASTER_PCNOC_S_7 95 -#define ICBID_MASTER_PCNOC_S_8 96 -#define ICBID_MASTER_PCNOC_S_9 97 -#define ICBID_MASTER_QDSS_INT 98 -#define ICBID_MASTER_SNOC_INT_0 99 -#define ICBID_MASTER_SNOC_INT_1 100 -#define ICBID_MASTER_SNOC_INT_BIMC 101 -#define ICBID_MASTER_TCU_0 102 -#define ICBID_MASTER_TCU_1 103 -#define ICBID_MASTER_BIMC_INT_0 104 -#define ICBID_MASTER_BIMC_INT_1 105 -#define ICBID_MASTER_CAMERA 106 -#define ICBID_MASTER_RICA 107 -#define ICBID_MASTER_SNOC_BIMC_2 108 -#define ICBID_MASTER_BIMC_SNOC_1 109 -#define ICBID_MASTER_A0NOC_SNOC 110 -#define ICBID_MASTER_A1NOC_SNOC 111 -#define ICBID_MASTER_A2NOC_SNOC 112 -#define ICBID_MASTER_PIMEM 113 -#define ICBID_MASTER_SNOC_VMEM 114 -#define ICBID_MASTER_CPP 115 -#define ICBID_MASTER_CNOC_A1NOC 116 -#define ICBID_MASTER_PNOC_A1NOC 117 -#define ICBID_MASTER_HMSS 118 -#define ICBID_MASTER_PCIE_2 119 -#define ICBID_MASTER_ROTATOR 120 -#define ICBID_MASTER_VENUS_VMEM 121 -#define ICBID_MASTER_DCC 122 -#define ICBID_MASTER_MCDMA 123 -#define ICBID_MASTER_PCNOC_INT_2 124 -#define ICBID_MASTER_PCNOC_INT_3 125 -#define ICBID_MASTER_PCNOC_INT_4 126 -#define ICBID_MASTER_PCNOC_INT_5 127 -#define ICBID_MASTER_PCNOC_INT_6 128 -#define ICBID_MASTER_PCNOC_S_5 129 -#define ICBID_MASTER_SENSORS_AHB 130 -#define ICBID_MASTER_SENSORS_PROC 131 -#define ICBID_MASTER_QSPI 132 -#define ICBID_MASTER_VFE1 133 -#define ICBID_MASTER_SNOC_INT_2 134 -#define ICBID_MASTER_SMMNOC_BIMC 135 -#define ICBID_MASTER_CRVIRT_A1NOC 136 -#define ICBID_MASTER_XM_USB_HS1 137 -#define ICBID_MASTER_XI_USB_HS1 138 -#define ICBID_MASTER_PCNOC_BIMC_1 139 -#define ICBID_MASTER_BIMC_PCNOC 140 -#define ICBID_MASTER_XI_HSIC 141 -#define ICBID_MASTER_SGMII 142 -#define ICBID_MASTER_SPMI_FETCHER 143 -#define ICBID_MASTER_GNOC_BIMC 144 -#define ICBID_MASTER_CRVIRT_A2NOC 145 -#define ICBID_MASTER_CNOC_A2NOC 146 -#define ICBID_MASTER_WLAN 147 -#define ICBID_MASTER_MSS_CE 148 -#define ICBID_MASTER_CDSP_PROC 149 -#define ICBID_MASTER_GNOC_SNOC 150 - -#define ICBID_SLAVE_EBI1 0 -#define ICBID_SLAVE_APPSS_L2 1 -#define ICBID_SLAVE_BIMC_SNOC 2 -#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC -#define ICBID_SLAVE_CAMERA_CFG 3 -#define ICBID_SLAVE_DISPLAY_CFG 4 -#define ICBID_SLAVE_OCMEM_CFG 5 -#define ICBID_SLAVE_CPR_CFG 6 -#define ICBID_SLAVE_CPR_XPU_CFG 7 -#define ICBID_SLAVE_MISC_CFG 8 -#define ICBID_SLAVE_MISC_XPU_CFG 9 -#define ICBID_SLAVE_VENUS_CFG 10 -#define ICBID_SLAVE_GFX3D_CFG 11 -#define ICBID_SLAVE_MMSS_CLK_CFG 12 -#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13 -#define ICBID_SLAVE_MNOC_MPU_CFG 14 -#define ICBID_SLAVE_ONOC_MPU_CFG 15 -#define ICBID_SLAVE_MNOC_BIMC 16 -#define ICBID_SLAVE_SERVICE_MNOC 17 -#define ICBID_SLAVE_OCMEM 18 -#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM -#define ICBID_SLAVE_SERVICE_ONOC 19 -#define ICBID_SLAVE_APPSS 20 -#define ICBID_SLAVE_LPASS 21 -#define ICBID_SLAVE_USB3 22 -#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3 -#define ICBID_SLAVE_WCSS 23 -#define ICBID_SLAVE_SNOC_BIMC 24 -#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC -#define ICBID_SLAVE_SNOC_CNOC 25 -#define ICBID_SLAVE_IMEM 26 -#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM -#define ICBID_SLAVE_SNOC_OVIRT 27 -#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT -#define ICBID_SLAVE_SNOC_PNOC 28 -#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC -#define ICBID_SLAVE_SERVICE_SNOC 29 -#define ICBID_SLAVE_QDSS_STM 30 -#define ICBID_SLAVE_SDCC_1 31 -#define ICBID_SLAVE_SDCC_3 32 -#define ICBID_SLAVE_SDCC_2 33 -#define ICBID_SLAVE_SDCC_4 34 -#define ICBID_SLAVE_TSIF 35 -#define ICBID_SLAVE_BAM_DMA 36 -#define ICBID_SLAVE_BLSP_2 37 -#define ICBID_SLAVE_USB_HSIC 38 -#define ICBID_SLAVE_BLSP_1 39 -#define ICBID_SLAVE_USB_HS 40 -#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS -#define ICBID_SLAVE_PDM 41 -#define ICBID_SLAVE_PERIPH_APU_CFG 42 -#define ICBID_SLAVE_PNOC_MPU_CFG 43 -#define ICBID_SLAVE_PRNG 44 -#define ICBID_SLAVE_PNOC_SNOC 45 -#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC -#define ICBID_SLAVE_SERVICE_PNOC 46 -#define ICBID_SLAVE_CLK_CTL 47 -#define ICBID_SLAVE_CNOC_MSS 48 -#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS -#define ICBID_SLAVE_SECURITY 49 -#define ICBID_SLAVE_TCSR 50 -#define ICBID_SLAVE_TLMM 51 -#define ICBID_SLAVE_CRYPTO_0_CFG 52 -#define ICBID_SLAVE_CRYPTO_1_CFG 53 -#define ICBID_SLAVE_IMEM_CFG 54 -#define ICBID_SLAVE_MESSAGE_RAM 55 -#define ICBID_SLAVE_BIMC_CFG 56 -#define ICBID_SLAVE_BOOT_ROM 57 -#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58 -#define ICBID_SLAVE_PMIC_ARB 59 -#define ICBID_SLAVE_SPDM_WRAPPER 60 -#define ICBID_SLAVE_DEHR_CFG 61 -#define ICBID_SLAVE_MPM 62 -#define ICBID_SLAVE_QDSS_CFG 63 -#define ICBID_SLAVE_RBCPR_CFG 64 -#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG -#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65 -#define ICBID_SLAVE_CNOC_MNOC_CFG 66 -#define ICBID_SLAVE_SNOC_MPU_CFG 67 -#define ICBID_SLAVE_CNOC_ONOC_CFG 68 -#define ICBID_SLAVE_PNOC_CFG 69 -#define ICBID_SLAVE_SNOC_CFG 70 -#define ICBID_SLAVE_EBI1_DLL_CFG 71 -#define ICBID_SLAVE_PHY_APU_CFG 72 -#define ICBID_SLAVE_EBI1_PHY_CFG 73 -#define ICBID_SLAVE_RPM 74 -#define ICBID_SLAVE_CNOC_SNOC 75 -#define ICBID_SLAVE_SERVICE_CNOC 76 -#define ICBID_SLAVE_OVIRT_SNOC 77 -#define ICBID_SLAVE_OVIRT_OCMEM 78 -#define ICBID_SLAVE_USB_HS2 79 -#define ICBID_SLAVE_QPIC 80 -#define ICBID_SLAVE_IPS_CFG 81 -#define ICBID_SLAVE_DSI_CFG 82 -#define ICBID_SLAVE_USB3_1 83 -#define ICBID_SLAVE_PCIE_0 84 -#define ICBID_SLAVE_PCIE_1 85 -#define ICBID_SLAVE_PSS_SMMU_CFG 86 -#define ICBID_SLAVE_CRYPTO_2_CFG 87 -#define ICBID_SLAVE_PCIE_0_CFG 88 -#define ICBID_SLAVE_PCIE_1_CFG 89 -#define ICBID_SLAVE_SATA_CFG 90 -#define ICBID_SLAVE_SPSS_GENI_IR 91 -#define ICBID_SLAVE_UFS_CFG 92 -#define ICBID_SLAVE_AVSYNC_CFG 93 -#define ICBID_SLAVE_VPU_CFG 94 -#define ICBID_SLAVE_USB_PHY_CFG 95 -#define ICBID_SLAVE_RBCPR_MX_CFG 96 -#define ICBID_SLAVE_PCIE_PARF 97 -#define ICBID_SLAVE_VCAP_CFG 98 -#define ICBID_SLAVE_EMAC_CFG 99 -#define ICBID_SLAVE_BCAST_CFG 100 -#define ICBID_SLAVE_KLM_CFG 101 -#define ICBID_SLAVE_DISPLAY_PWM 102 -#define ICBID_SLAVE_GENI 103 -#define ICBID_SLAVE_SNOC_BIMC_1 104 -#define ICBID_SLAVE_AUDIO 105 -#define ICBID_SLAVE_CATS_0 106 -#define ICBID_SLAVE_CATS_1 107 -#define ICBID_SLAVE_MM_INT_0 108 -#define ICBID_SLAVE_MM_INT_1 109 -#define ICBID_SLAVE_MM_INT_2 110 -#define ICBID_SLAVE_MM_INT_BIMC 111 -#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112 -#define ICBID_SLAVE_MSS_INT 113 -#define ICBID_SLAVE_PCNOC_INT_0 114 -#define ICBID_SLAVE_PCNOC_INT_1 115 -#define ICBID_SLAVE_PCNOC_M_0 116 -#define ICBID_SLAVE_PCNOC_M_1 117 -#define ICBID_SLAVE_PCNOC_S_0 118 -#define ICBID_SLAVE_PCNOC_S_1 119 -#define ICBID_SLAVE_PCNOC_S_2 120 -#define ICBID_SLAVE_PCNOC_S_3 121 -#define ICBID_SLAVE_PCNOC_S_4 122 -#define ICBID_SLAVE_PCNOC_S_6 123 -#define ICBID_SLAVE_PCNOC_S_7 124 -#define ICBID_SLAVE_PCNOC_S_8 125 -#define ICBID_SLAVE_PCNOC_S_9 126 -#define ICBID_SLAVE_PRNG_XPU_CFG 127 -#define ICBID_SLAVE_QDSS_INT 128 -#define ICBID_SLAVE_RPM_XPU_CFG 129 -#define ICBID_SLAVE_SNOC_INT_0 130 -#define ICBID_SLAVE_SNOC_INT_1 131 -#define ICBID_SLAVE_SNOC_INT_BIMC 132 -#define ICBID_SLAVE_TCU 133 -#define ICBID_SLAVE_BIMC_INT_0 134 -#define ICBID_SLAVE_BIMC_INT_1 135 -#define ICBID_SLAVE_RICA_CFG 136 -#define ICBID_SLAVE_SNOC_BIMC_2 137 -#define ICBID_SLAVE_BIMC_SNOC_1 138 -#define ICBID_SLAVE_PNOC_A1NOC 139 -#define ICBID_SLAVE_SNOC_VMEM 140 -#define ICBID_SLAVE_A0NOC_SNOC 141 -#define ICBID_SLAVE_A1NOC_SNOC 142 -#define ICBID_SLAVE_A2NOC_SNOC 143 -#define ICBID_SLAVE_A0NOC_CFG 144 -#define ICBID_SLAVE_A0NOC_MPU_CFG 145 -#define ICBID_SLAVE_A0NOC_SMMU_CFG 146 -#define ICBID_SLAVE_A1NOC_CFG 147 -#define ICBID_SLAVE_A1NOC_MPU_CFG 148 -#define ICBID_SLAVE_A1NOC_SMMU_CFG 149 -#define ICBID_SLAVE_A2NOC_CFG 150 -#define ICBID_SLAVE_A2NOC_MPU_CFG 151 -#define ICBID_SLAVE_A2NOC_SMMU_CFG 152 -#define ICBID_SLAVE_AHB2PHY 153 -#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154 -#define ICBID_SLAVE_DCC_CFG 155 -#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156 -#define ICBID_SLAVE_DSA_CFG 157 -#define ICBID_SLAVE_DSA_MPU_CFG 158 -#define ICBID_SLAVE_SSC_MPU_CFG 159 -#define ICBID_SLAVE_HMSS_L3 160 -#define ICBID_SLAVE_LPASS_SMMU_CFG 161 -#define ICBID_SLAVE_MMAGIC_CFG 162 -#define ICBID_SLAVE_PCIE20_AHB2PHY 163 -#define ICBID_SLAVE_PCIE_2 164 -#define ICBID_SLAVE_PCIE_2_CFG 165 -#define ICBID_SLAVE_PIMEM 166 -#define ICBID_SLAVE_PIMEM_CFG 167 -#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168 -#define ICBID_SLAVE_RBCPR_CX 169 -#define ICBID_SLAVE_RBCPR_MX 170 -#define ICBID_SLAVE_SMMU_CPP_CFG 171 -#define ICBID_SLAVE_SMMU_JPEG_CFG 172 -#define ICBID_SLAVE_SMMU_MDP_CFG 173 -#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174 -#define ICBID_SLAVE_SMMU_VENUS_CFG 175 -#define ICBID_SLAVE_SMMU_VFE_CFG 176 -#define ICBID_SLAVE_SSC_CFG 177 -#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178 -#define ICBID_SLAVE_VMEM 179 -#define ICBID_SLAVE_VMEM_CFG 180 -#define ICBID_SLAVE_QDSS_MPU_CFG 181 -#define ICBID_SLAVE_USB3_PHY_CFG 182 -#define ICBID_SLAVE_IPA_CFG 183 -#define ICBID_SLAVE_PCNOC_INT_2 184 -#define ICBID_SLAVE_PCNOC_INT_3 185 -#define ICBID_SLAVE_PCNOC_INT_4 186 -#define ICBID_SLAVE_PCNOC_INT_5 187 -#define ICBID_SLAVE_PCNOC_INT_6 188 -#define ICBID_SLAVE_PCNOC_S_5 189 -#define ICBID_SLAVE_QSPI 190 -#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191 -#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192 -#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193 -#define ICBID_SLAVE_MSS_MPU_CFG 194 -#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195 -#define ICBID_SLAVE_SKL 196 -#define ICBID_SLAVE_SNOC_INT_2 197 -#define ICBID_SLAVE_SMMNOC_BIMC 198 -#define ICBID_SLAVE_CRVIRT_A1NOC 199 -#define ICBID_SLAVE_SGMII 200 -#define ICBID_SLAVE_QHS4_APPS 201 -#define ICBID_SLAVE_BIMC_PCNOC 202 -#define ICBID_SLAVE_PCNOC_BIMC_1 203 -#define ICBID_SLAVE_SPMI_FETCHER 204 -#define ICBID_SLAVE_MMSS_SMMU_CFG 205 -#define ICBID_SLAVE_WLAN 206 -#define ICBID_SLAVE_CRVIRT_A2NOC 207 -#define ICBID_SLAVE_CNOC_A2NOC 208 -#define ICBID_SLAVE_GLM 209 -#define ICBID_SLAVE_GNOC_BIMC 210 -#define ICBID_SLAVE_GNOC_SNOC 211 -#define ICBID_SLAVE_QM_CFG 212 -#define ICBID_SLAVE_TLMM_EAST 213 -#define ICBID_SLAVE_TLMM_NORTH 214 -#define ICBID_SLAVE_TLMM_WEST 215 -#define ICBID_SLAVE_LPASS_TCM 216 -#define ICBID_SLAVE_TLMM_SOUTH 217 -#define ICBID_SLAVE_TLMM_CENTER 218 -#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 219 -#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 220 -#define ICBID_SLAVE_CDSP 221 -#define ICBID_SLAVE_CDSP_SMMU_CFG 222 -#define ICBID_SLAVE_LPASS_MPU_CFG 223 -#define ICBID_SLAVE_CSI_PHY_CFG 224 -#endif diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c index 08b1399d1da2..dcbf9973884d 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c @@ -73,12 +73,6 @@ static const struct snd_pcm_hardware acp_pcm_hardware_capture = { .periods_max = CAPTURE_MAX_NUM_PERIODS, }; -struct audio_drv_data { - struct snd_pcm_substream *play_stream; - struct snd_pcm_substream *capture_stream; - void __iomem *acp_mmio; -}; - static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) { return readl(acp_mmio + (reg * 4)); @@ -916,6 +910,7 @@ static int acp_audio_probe(struct platform_device *pdev) int status; struct audio_drv_data *audio_drv_data; struct resource *res; + const u32 *pdata = pdev->dev.platform_data; audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), GFP_KERNEL); @@ -932,6 +927,7 @@ static int acp_audio_probe(struct platform_device *pdev) audio_drv_data->play_stream = NULL; audio_drv_data->capture_stream = NULL; + audio_drv_data->asic_type = *pdata; res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!res) { diff --git a/sound/soc/amd/acp.h b/sound/soc/amd/acp.h index 330832ef4e5e..28cf9140f49c 100644 --- a/sound/soc/amd/acp.h +++ b/sound/soc/amd/acp.h @@ -84,6 +84,13 @@ struct audio_substream_data { void __iomem *acp_mmio; }; +struct audio_drv_data { + struct snd_pcm_substream *play_stream; + struct snd_pcm_substream *capture_stream; + void __iomem *acp_mmio; + u32 asic_type; +}; + enum { ACP_TILE_P1 = 0, ACP_TILE_P2, |