diff options
| -rw-r--r-- | drivers/clk/rockchip/clk-cpu.c | 5 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-pll.c | 8 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3128.c | 24 | ||||
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3188.c | 18 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3128-cru.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/clock/rk3188-cru-common.h | 2 |
6 files changed, 41 insertions, 20 deletions
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c index 6ea7fba9f9e5..398a226ad34e 100644 --- a/drivers/clk/rockchip/clk-cpu.c +++ b/drivers/clk/rockchip/clk-cpu.c @@ -369,9 +369,8 @@ struct clk *rockchip_clk_register_cpuclk(const char *name, if (nrates > 0) { cpuclk->rate_count = nrates; - cpuclk->rate_table = kmemdup(rates, - sizeof(*rates) * nrates, - GFP_KERNEL); + cpuclk->rate_table = kmemdup_array(rates, nrates, sizeof(*rates), + GFP_KERNEL); if (!cpuclk->rate_table) { ret = -ENOMEM; goto unregister_notifier; diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 2d42eb628926..606ce5458f54 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1136,10 +1136,10 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, len++; pll->rate_count = len; - pll->rate_table = kmemdup(rate_table, - pll->rate_count * - sizeof(struct rockchip_pll_rate_table), - GFP_KERNEL); + pll->rate_table = kmemdup_array(rate_table, + pll->rate_count, + sizeof(*pll->rate_table), + GFP_KERNEL); WARN(!pll->rate_table, "%s: could not allocate rate table for %s\n", __func__, name); diff --git a/drivers/clk/rockchip/clk-rk3128.c b/drivers/clk/rockchip/clk-rk3128.c index 75071e0cd321..7c3d92af12df 100644 --- a/drivers/clk/rockchip/clk-rk3128.c +++ b/drivers/clk/rockchip/clk-rk3128.c @@ -526,7 +526,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS), GATE(0, "pclk_ddrupctl", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 7, GFLAGS), GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS), - GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS), + GATE(PCLK_MIPIPHY, "pclk_mipiphy", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, GFLAGS), GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS), GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS), @@ -553,6 +553,7 @@ static struct rockchip_clk_branch rk3128_clk_branches[] __initdata = { RK2928_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS, RK2928_CLKGATE_CON(3), 15, GFLAGS), + GATE(HCLK_SFC, "hclk_sfc", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS), GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(3), 14, GFLAGS), GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS), }; @@ -563,23 +564,28 @@ static const char *const rk3128_critical_clocks[] __initconst = { "pclk_cpu", "aclk_peri", "hclk_peri", + "hclk_vio_h2p", "pclk_peri", "pclk_pmu", "sclk_timer5", }; -static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np) +static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np, + unsigned long soc_nr_clks) { struct rockchip_clk_provider *ctx; + unsigned long common_nr_clks; void __iomem *reg_base; + common_nr_clks = rockchip_clk_find_max_clk_id(common_clk_branches, + ARRAY_SIZE(common_clk_branches)) + 1; reg_base = of_iomap(np, 0); if (!reg_base) { pr_err("%s: could not map cru region\n", __func__); return ERR_PTR(-ENOMEM); } - ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + ctx = rockchip_clk_init(np, reg_base, max(common_nr_clks, soc_nr_clks)); if (IS_ERR(ctx)) { pr_err("%s: rockchip clk init failed\n", __func__); iounmap(reg_base); @@ -608,8 +614,12 @@ static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device static void __init rk3126_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; + unsigned long soc_nr_clks; - ctx = rk3128_common_clk_init(np); + soc_nr_clks = rockchip_clk_find_max_clk_id(rk3126_clk_branches, + ARRAY_SIZE(rk3126_clk_branches)) + 1; + + ctx = rk3128_common_clk_init(np, soc_nr_clks); if (IS_ERR(ctx)) return; @@ -626,8 +636,12 @@ CLK_OF_DECLARE(rk3126_cru, "rockchip,rk3126-cru", rk3126_clk_init); static void __init rk3128_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; + unsigned long soc_nr_clks; + + soc_nr_clks = rockchip_clk_find_max_clk_id(rk3128_clk_branches, + ARRAY_SIZE(rk3128_clk_branches)) + 1; - ctx = rk3128_common_clk_init(np); + ctx = rk3128_common_clk_init(np, soc_nr_clks); if (IS_ERR(ctx)) return; diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c index 9c8af4d1dae0..30e670c8afba 100644 --- a/drivers/clk/rockchip/clk-rk3188.c +++ b/drivers/clk/rockchip/clk-rk3188.c @@ -757,9 +757,11 @@ static const char *const rk3188_critical_clocks[] __initconst = { "sclk_mac_lbtest", }; -static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np) +static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np, + unsigned long soc_nr_clks) { struct rockchip_clk_provider *ctx; + unsigned long common_nr_clks; void __iomem *reg_base; reg_base = of_iomap(np, 0); @@ -768,7 +770,9 @@ static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device return ERR_PTR(-ENOMEM); } - ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); + common_nr_clks = rockchip_clk_find_max_clk_id(common_clk_branches, + ARRAY_SIZE(common_clk_branches)) + 1; + ctx = rockchip_clk_init(np, reg_base, max(common_nr_clks, soc_nr_clks)); if (IS_ERR(ctx)) { pr_err("%s: rockchip clk init failed\n", __func__); iounmap(reg_base); @@ -789,8 +793,11 @@ static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device static void __init rk3066a_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; + unsigned long soc_nr_clks; - ctx = rk3188_common_clk_init(np); + soc_nr_clks = rockchip_clk_find_max_clk_id(rk3066a_clk_branches, + ARRAY_SIZE(rk3066a_clk_branches)) + 1; + ctx = rk3188_common_clk_init(np, soc_nr_clks); if (IS_ERR(ctx)) return; @@ -812,11 +819,14 @@ CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init); static void __init rk3188a_clk_init(struct device_node *np) { struct rockchip_clk_provider *ctx; + unsigned long soc_nr_clks; struct clk *clk1, *clk2; unsigned long rate; int ret; - ctx = rk3188_common_clk_init(np); + soc_nr_clks = rockchip_clk_find_max_clk_id(rk3188_clk_branches, + ARRAY_SIZE(rk3188_clk_branches)) + 1; + ctx = rk3188_common_clk_init(np, soc_nr_clks); if (IS_ERR(ctx)) return; diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h index 6a47825dac5d..b609fcf96508 100644 --- a/include/dt-bindings/clock/rk3128-cru.h +++ b/include/dt-bindings/clock/rk3128-cru.h @@ -116,6 +116,7 @@ #define PCLK_GMAC 367 #define PCLK_PMU_PRE 368 #define PCLK_SIM_CARD 369 +#define PCLK_MIPIPHY 370 /* hclk gates */ #define HCLK_SPDIF 440 @@ -143,8 +144,7 @@ #define HCLK_TSP 475 #define HCLK_CRYPTO 476 #define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) +#define HCLK_SFC 479 /* soft-reset indices */ #define SRST_CORE0_PO 0 diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index afad90680fce..01e14ab252a7 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -132,8 +132,6 @@ #define HCLK_VDPU 472 #define HCLK_HDMI 473 -#define CLK_NR_CLKS (HCLK_HDMI + 1) - /* soft-reset indices */ #define SRST_MCORE 2 #define SRST_CORE0 3 |