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authorRobert Richter <[email protected]>2023-06-22 15:55:07 -0500
committerDan Williams <[email protected]>2023-06-25 11:51:36 -0700
commitf1d0525effc4fffe821905671ea24c30a4bfa393 (patch)
tree476d2207ce182887cae01e8cb94cedd95b7efd1a /tools/perf/util/scripting-engines/trace-event-python.c
parentd8bffff2016f7aef1c1dbe01125720475507b6f2 (diff)
cxl/regs: Remove early capability checks in Component Register setup
When probing the Component Registers in function cxl_probe_regs() there are also checks for the existence of the HDM and RAS capabilities. The checks may fail for components that do not implement the HDM capability causing the Component Registers setup to fail too. Remove the checks for a generalized use of cxl_probe_regs() and check them directly before mapping the RAS or HDM capabilities. This allows it to setup other Component Registers esp. of an RCH Downstream Port, which will be implemented in a follow-on patch. Signed-off-by: Robert Richter <[email protected]> Signed-off-by: Terry Bowman <[email protected]> Reviewed-by: Jonathan Cameron <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dan Williams <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
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