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authorIrina Tirdea <[email protected]>2016-08-12 16:27:57 -0500
committerMark Brown <[email protected]>2016-08-15 15:14:57 +0100
commitdf1a2776a795848f4dbc7c0cb396158b43eb8aa3 (patch)
treeddcd5d5cf15b8702744bb61b2089776d80b2dbd1 /tools/perf/util/scripting-engines/trace-event-python.c
parent59e8b6520c6e2e867b35bc402d9a3f28aef3b2bc (diff)
ASoC: Intel: bytcr_rt5640: add MCLK support
Use platform clocks "pmc_plt_clk_3" when MCLK quirk is defined. By default always enable the 19.2 MHz PLL. Signed-off-by: Pierre-Louis Bossart <[email protected]> Signed-off-by: Irina Tirdea <[email protected]> Signed-off-by: Mark Brown <[email protected]>
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