diff options
| author | Gabriel FERNANDEZ <[email protected]> | 2014-02-27 16:24:15 +0100 |
|---|---|---|
| committer | Mike Turquette <[email protected]> | 2014-03-25 15:58:56 -0700 |
| commit | b9b8e614b5805a99a5484c3d44fbfebaa8de4c65 (patch) | |
| tree | abbc02277f367a476806f2a61bf1a89a86912210 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | 94885faf9dbcc2ca704d60e7db2f2b87e0b0fe6e (diff) | |
clk: st: Support for PLLs inside ClockGenA(s)
The patch supports the c65/c32 type PLLs used by ClockGenA(s)
PLL clock : It includes support for all c65/c32 type PLLs
inside ClockGenA(s) : implemented as Fixed Parent / Fixed Rate clock,
with clock rate calculated reading H/w settings done at BOOT.
c65 PLLs have 2 outputs : HS and LS
c32 PLLs have 1-4 outputs : ODFx
Signed-off-by: Pankaj Dev <[email protected]>
Signed-off-by: Gabriel Fernandez <[email protected]>
Signed-off-by: Mike Turquette <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions