diff options
author | Huacai Chen <[email protected]> | 2014-03-21 18:44:05 +0800 |
---|---|---|
committer | Ralf Baechle <[email protected]> | 2014-03-31 18:17:12 +0200 |
commit | 7546d2f48d5bc8479de135d80c74b0c08dbeb467 (patch) | |
tree | 081e833d521a9da36f56067e55f7c8a5b59945f4 /tools/perf/util/scripting-engines/trace-event-python.c | |
parent | d788bfa900748f3325894d18a763d1ba42326c28 (diff) |
MIPS: Loongson 3: Add serial port support
Loongson family machines has three types of serial port: PCI UART, LPC
UART and CPU internal UART. Loongson-2E and parts of Loongson-2F based
machines use PCI UART; most Loongson-2F based machines use LPC UART;
Loongson-2G/3A has both LPC and CPU UART but usually use CPU UART.
Port address of UARTs:
CPU UART: REG_BASE + OFFSET;
LPC UART: LIO1_BASE + OFFSET;
PCI UART: PCIIO_BASE + OFFSET.
Since LPC UART are linked in "Local Bus", both CPU UART and LPC UART
are called "CPU provided serial port".
Signed-off-by: Huacai Chen <[email protected]>
Signed-off-by: Hongliang Tao <[email protected]>
Signed-off-by: Hua Yan <[email protected]>
Tested-by: Alex Smith <[email protected]>
Reviewed-by: Alex Smith <[email protected]>
Cc: John Crispin <[email protected]>
Cc: Steven J. Hill <[email protected]>
Cc: Aurelien Jarno <[email protected]>
Cc: [email protected]
Cc: Fuxin Zhang <[email protected]>
Cc: Zhangjin Wu <[email protected]>
Patchwork: https://patchwork.linux-mips.org/patch/6635
Signed-off-by: Ralf Baechle <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
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