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| author | Dan Williams <[email protected]> | 2023-06-14 18:30:43 -0700 |
|---|---|---|
| committer | Dan Williams <[email protected]> | 2023-06-25 14:31:33 -0700 |
| commit | 516b300c4ca86aa7953b75ce79b5c5eea5779b22 (patch) | |
| tree | 904fab8243e1b30d6aa89fba09207b67dd271208 /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | f3c8a37a432e65dda1384929198dd12c1df3ea38 (diff) | |
cxl/memdev: Formalize endpoint port linkage
Move the endpoint port that the cxl_mem driver establishes from drvdata
to a first class attribute. This is in preparation for device-memory
drivers reusing the CXL core for memory region management. Those drivers
need a type-safe method to retrieve their CXL port linkage. Leave
drvdata for private usage of the cxl_mem driver not external consumers
of a 'struct cxl_memdev' object.
Reviewed-by: Fan Ni <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Dave Jiang <[email protected]>
Link: https://lore.kernel.org/r/168679264292.3436160.3901392135863405807.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions