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author | Jisheng Zhang <[email protected]> | 2023-09-12 15:20:15 +0800 |
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committer | Palmer Dabbelt <[email protected]> | 2023-11-05 14:15:14 -0800 |
commit | 8f8c1ff879fab60f80f3a7aec3000f47e5b03ba9 (patch) | |
tree | c44022bf9b87705a8a3cacd8a135d72ac400a38a /tools/perf/scripts/python/task-analyzer.py | |
parent | 49cfbdc21faf5fffbdaa8fd31e1451a4432cfdaa (diff) |
riscv: vdso.lds.S: remove hardcoded 0x800 .text start addr
I believe the hardcoded 0x800 and related comments come from the long
history VDSO_TEXT_OFFSET in x86 vdso code, but commit 5b9304933730
("x86 vDSO: generate vdso-syms.lds") and commit f6b46ebf904f ("x86
vDSO: new layout") removes the comment and hard coding for x86.
Similar as x86 and other arch, riscv doesn't need the rigid layout
using VDSO_TEXT_OFFSET since it "no longer matters to the kernel".
so we could remove the hard coding now, and removing it brings a
small vdso.so and aligns with other architectures.
Also, having enough separation between data and text is important for
I-cache, so similar as x86, move .note, .eh_frame_hdr, and .eh_frame
between .rodata and .text.
Signed-off-by: Jisheng Zhang <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Tested-by: Emil Renner Berthing <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/task-analyzer.py')
0 files changed, 0 insertions, 0 deletions