diff options
| author | Manasi Navare <[email protected]> | 2019-12-27 19:12:03 -0800 |
|---|---|---|
| committer | Manasi Navare <[email protected]> | 2019-12-30 00:15:48 -0800 |
| commit | aee40639cdc315c0bd7618f84577eeb2ff0ef9b1 (patch) | |
| tree | 9e86954e9f3b3f4b6781f87d0d50a93c987e73a4 /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | a603f5bd1691f975d036718ff176e10332d2bc64 (diff) | |
drm/i915/dp: Make port sync mode assignments only if all tiles present
Add an extra check before making master slave assignments for tiled
displays to make sure we make these assignments only if all tiled
connectors are present. If not then initialize the state to defaults
so it does a normal non tiled modeset without transcoder port sync.
v4:
deafulat port sync values in prepare_cleared_state (Ville)
v3:
* Default master trans to INVALID to avoid pipe mismatch
v2:
* Rename icl_add_sync_mode_crtcs
* Move this function just before .compute_config hook
* Check if DP before master slave assignments (Ville)
Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
Cc: Ville Syrjälä <[email protected]>
Signed-off-by: Manasi Navare <[email protected]>
Acked-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions