diff options
| author | Mark Zhang <[email protected]> | 2012-10-16 16:31:49 +0800 |
|---|---|---|
| committer | Stephen Warren <[email protected]> | 2012-10-16 11:14:34 -0600 |
| commit | 786621308cfbb9421a54773e57dbdbe504c417cc (patch) | |
| tree | 19ae13afa378872be16f842edcdb4761f1159d8b /tools/perf/scripts/python/syscall-counts-by-pid.py | |
| parent | ddffeb8c4d0331609ef2581d84de4d763607bd37 (diff) | |
ARM: tegra30: clk: Fix output_rate overflow
Change the type of variable from "unsigned long" to "u64".
This avoids the overflow while clock rate calculating.
Signed-off-by: Mark Zhang <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/syscall-counts-by-pid.py')
0 files changed, 0 insertions, 0 deletions