spi: bcm2835aux: set up spi-mode before asserting cs-gpio

When using reverse polarity for clock (spi-cpol) on a device
the clock line gets altered after chip-select has been asserted
resulting in an additional clock beat, which confuses hardware.

This happens due to the fact, the the hardware was initialized
and reset at the begin and end of each transfer which results
in default state for all lines except chip-select which is
handled by the spi-subsystem as gpio-cs is used.

To avoid this situation this patch moves the setup of polarity
(spi-cpol and spi-cpha) outside of the chip-select into
prepare_message, which is run prior to asserting chip-select.

Signed-off-by: Stephan Olbrich <[email protected]>
Reviewed-by: Martin Sperl <[email protected]>
Tested-by: Martin Sperl <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Signed-off-by: Mark Brown <[email protected]>

0 files changed, 0 insertions, 0 deletions