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authorImre Deak <[email protected]>2017-11-29 19:51:37 +0200
committerImre Deak <[email protected]>2017-11-30 14:21:43 +0200
commit5643205c6340b565a3be0fe0e7305dc4aa551c74 (patch)
tree4f572b84e166988f777c068f2b3a806ed5a9e9a8 /tools/perf/scripts/python/stackcollapse.py
parentecf73eb2d27d43b2153bb80671768a06d35521f1 (diff)
drm/i915: Avoid PPS HW/SW state mismatch due to rounding
We store a SW state of the t11_t12 timing in 100usec units but have to program it in 100msec as required by HW. The rounding used during programming means there will be a mismatch between the SW and HW states of this value triggering a "PPS state mismatch" error. Avoid this by storing the already rounded-up value in the SW state. Note that we still calculate panel_power_cycle_delay with the finer 100usec granularity to avoid any needless waits using that version of the delay. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103903 Cc: joks <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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