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| author | Julien CHAUVEAU <[email protected]> | 2014-11-21 11:08:47 +0100 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2014-11-23 01:55:14 +0100 |
| commit | 12c0a0e81e2f9c03404a3e095517c022991aad43 (patch) | |
| tree | 33305edb4c4b0b41169216e012066443f4d99420 /tools/perf/scripts/python/stackcollapse.py | |
| parent | b7bdb7f45e7b848dc2eb50c2d5c5106af68562c4 (diff) | |
clk: rockchip: fix rk3188 USB HSIC PHY clock divider
The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11).
Signed-off-by: Julien CHAUVEAU <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions