diff options
| author | Chaotian Jing <[email protected]> | 2018-09-29 10:29:54 +0800 |
|---|---|---|
| committer | Ulf Hansson <[email protected]> | 2018-10-08 12:53:24 +0200 |
| commit | 716b717ac07de239c6ad7bd3c38f2ef979280595 (patch) | |
| tree | 06989cadaf021efe6449c60471ffcc37e2b6721e /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 32b64b0397b440877c4707f3cc3f5b4494f0be3e (diff) | |
mmc: dt-bindings: add "bus-clk" for MT2712
On MT2712 MSDC0/3, HCLK/bus-clk need gate/ungate together,
or will hang when access MSDC register.
Signed-off-by: Chaotian Jing <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions