diff options
| author | Chaotian Jing <[email protected]> | 2018-09-29 10:29:55 +0800 |
|---|---|---|
| committer | Ulf Hansson <[email protected]> | 2018-10-08 12:53:24 +0200 |
| commit | 258bac4a61af9c4e7bc045ce2a17c9eb8c5fd9a5 (patch) | |
| tree | 88bbce0cd7ca588b83c2f2d16b9fc84ff7bd1810 /tools/perf/scripts/python/mem-phys-addr.py | |
| parent | 716b717ac07de239c6ad7bd3c38f2ef979280595 (diff) | |
mmc: mediatek: add bus_clk control
when gate MSDC0_HCLK, access register will hang, even the MSDC driver
will never accessing register after HCLK was gated, but for safety, need
gate the bus_clk(which used to access register) too.
Signed-off-by: Chaotian Jing <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/mem-phys-addr.py')
0 files changed, 0 insertions, 0 deletions