diff options
| author | Maxime Chevallier <[email protected]> | 2022-09-02 10:32:04 +0200 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2022-09-05 10:16:53 +0100 |
| commit | fef2998203e17e4298843afb2056fbed44611734 (patch) | |
| tree | e0d940703332e6d75ec40061b1f858bc05275c6f /tools/perf/scripts/python/libxed.py | |
| parent | 4a502cf4d77e12119e7061a05d5789cd3129d185 (diff) | |
net: altera: tse: convert to phylink
Convert the Altera Triple Speed Ethernet Controller to phylink.
This controller supports MII, GMII and RGMII with its MAC, and
SGMII + 1000BaseX through a small embedded PCS.
The PCS itself has a register set very similar to what is found in a
typical 802.3 ethernet PHY, but this register set memory-mapped instead
of lying on an mdio bus.
Signed-off-by: Maxime Chevallier <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/libxed.py')
0 files changed, 0 insertions, 0 deletions