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authorMaxime Chevallier <[email protected]>2022-09-02 10:32:05 +0200
committerDavid S. Miller <[email protected]>2022-09-05 10:16:53 +0100
commit565f02fc1e5dc18a577545aaef3c1191cd011849 (patch)
tree566380cce9c6fe7c68afcab001fe77482e028f7a /tools/perf/scripts/python/libxed.py
parentfef2998203e17e4298843afb2056fbed44611734 (diff)
dt-bindings: net: altera: tse: add an optional pcs register range
Some implementations of the TSE have their PCS as an external bloc, exposed at its own register range. Document this, and add a new example showing a case using the pcs and the new phylink conversion to connect an sfp port to a TSE mac. Signed-off-by: Maxime Chevallier <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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