diff options
| author | Claudiu Beznea <[email protected]> | 2020-11-19 17:43:14 +0200 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2020-12-19 11:50:56 -0800 |
| commit | f803858af84e1e6916edfbc5ae0fac403c02ee46 (patch) | |
| tree | dd747b0edde826b9d7a33d7d983169e1ee4f7e8a /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 4011f03ee4756df3091ad0c2cfb0593bee8ecdf1 (diff) | |
clk: at91: sama7g5: decrease lower limit for MCK0 rate
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and
CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is
also changed by DVFS to avoid over/under clocking of MCK0 consumers.
The lower limit is changed to be able to set MCK0 accordingly by
DVFS.
Signed-off-by: Claudiu Beznea <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions