drm/i915/gen9: Clear residual context state on context switch

Intel ID: PSIRT-TA-201910-001
CVEID: CVE-2019-14615

Intel GPU Hardware prior to Gen11 does not clear EU state
during a context switch. This can result in information
leakage between contexts.

For Gen8 and Gen9, hardware provides a mechanism for
fast cleardown of the EU state, by issuing a PIPE_CONTROL
with bit 27 set. We can use this in a context batch buffer
to explicitly cleardown the state on every context switch.

As this workaround is already in place for gen8, we can borrow
the code verbatim for Gen9.

Signed-off-by: Mika Kuoppala <[email protected]>
Signed-off-by: Akeem G Abodunrin <[email protected]>
Cc: Kumar Valsan Prathap <[email protected]>
Cc: Chris Wilson <[email protected]>
Cc: Balestrieri Francesco <[email protected]>
Cc: Bloomfield Jon <[email protected]>
Cc: Dutt Sudeep <[email protected]>

0 files changed, 0 insertions, 0 deletions