clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data

1. pcwibits: The integer bits of pcw for PLLs is extend to 8 bits,
   add a variable to indicate this change and
   backward-compatible.

2. fmin: The PLL frequency lower-bound is vary from 1GHz to
   1.5GHz, add a variable to indicate platform-dependent.

Signed-off-by: Owen Chen <[email protected]>
Signed-off-by: Weiyi Lu <[email protected]>
Acked-by: Sean Wang <[email protected]>
Reviewed-by: James Liao <[email protected]>
Reviewed-by: Nicolas Boichat <[email protected]>
Tested-by: Nicolas Boichat <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

0 files changed, 0 insertions, 0 deletions