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| author | Peng Fan <[email protected]> | 2020-08-26 15:14:07 +0800 |
|---|---|---|
| committer | Shawn Guo <[email protected]> | 2020-09-07 11:08:50 +0800 |
| commit | 936c383673b9e3007432f17140ac62de53d87db9 (patch) | |
| tree | a130a30d156df59bbdf73d91fd7b8a94622266af /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | f1859198509e4ddc93a24049f814fa0fcee0bfd8 (diff) | |
clk: imx: fix composite peripheral flags
According to RM, for peripheral clock slice,
"IP clock slices must be stopped to change the clock source.".
So we must have CLK_SET_PARENT_GATE flag to avoid glitch.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions