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| author | Laurent Pinchart <[email protected]> | 2019-03-03 22:29:21 +0200 |
|---|---|---|
| committer | Laurent Pinchart <[email protected]> | 2019-03-28 06:12:38 +0200 |
| commit | 871370308675e477abd57a69ce66ca4730a4249c (patch) | |
| tree | 6fbd2e830e7d43745a1a02cdf515631aa304af5b /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | b764f2f66ed48c7f0df2c4b1350c7973109a1d14 (diff) | |
drm: rcar-du: lvds: Adjust operating frequency for D3 and E3
The D3 and E3 SoCs have different pixel clock frequency limits for the
LVDS encoder than the other SoCs in the Gen3 family. Adjust the mode
fixup implementation accordingly.
Signed-off-by: Laurent Pinchart <[email protected]>
Reviewed-by: Jacopo Mondi <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions