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| author | Paul Cercueil <[email protected]> | 2019-05-08 00:17:55 +0200 |
|---|---|---|
| committer | Paul Burton <[email protected]> | 2019-05-09 16:39:27 -0700 |
| commit | 8041edb5920902adc9b28f2fcd9ccce395434ead (patch) | |
| tree | 4de1eb98bc34c11954423c7cd176023a68e70a07 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 1b1f01b653b408ebe58fec78c566d1075d285c64 (diff) | |
MIPS: Fix Ingenic SoCs sometimes reporting wrong ISA
The config0 register in the Xburst CPUs with a processor ID of
PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
but they don't actually support this ISA.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: Ralf Baechle <[email protected]>
Cc: James Hogan <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions