diff options
| author | Terry Zhou <[email protected]> | 2020-11-06 11:00:39 +0100 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2020-12-19 15:51:18 -0800 |
| commit | 6f37689cf6b38fff96de52e7f0d3e78f22803ba0 (patch) | |
| tree | 0242978f543481ee98806961a1ef2ed70d678225 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 3650b228f83adda7e5ee532e2b90429c03f7b9ec (diff) | |
clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9
There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.
Signed-off-by: Terry Zhou <[email protected]>
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár <[email protected]>
Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Reviewed-by: Marek Behún <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions