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| author | Peng Fan <[email protected]> | 2020-08-28 15:18:50 +0800 |
|---|---|---|
| committer | Shawn Guo <[email protected]> | 2020-09-07 11:08:50 +0800 |
| commit | 4757d2a3a32126be8bf5acb6eb293d0a1310dc1b (patch) | |
| tree | 68c7119935d64a835cfe94d1a55881177f559bc5 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 936c383673b9e3007432f17140ac62de53d87db9 (diff) | |
clk: imx: fix i.MX7D peripheral clk mux flags
According to RM, Page 574, Chapter 5.2.6.4.3 Peripheral clock slice,
"IP clock slices must be stopped to change the clock source.".
So we must have CLK_SET_PARENT_GATE flag to avoid glitch.
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions