clk: at91: Fix division by zero in PLL recalc_rate()

Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL
and DIV values") removed a check that prevents a division by zero. This
now causes a stacktrace when booting the kernel on a at91 platform if
the PLL DIV register contains zero. This commit reintroduces this check.

Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...")
Cc: <[email protected]>
Signed-off-by: Ronald Wahl <[email protected]>
Acked-by: Ludovic Desroches <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>

0 files changed, 0 insertions, 0 deletions