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author | Andre Przywara <[email protected]> | 2020-02-28 13:51:03 +0000 |
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committer | Arnd Bergmann <[email protected]> | 2020-03-26 10:52:19 +0100 |
commit | 0f1321172e0cab2c8ce85656ab6f531feb540715 (patch) | |
tree | 99e749098896ea56d87671d6b40f0489c17fd634 /tools/perf/scripts/python/exported-sql-viewer.py | |
parent | 28c05e422305c17ce3db7290d997b2a4f1ebee64 (diff) |
arm: dts: calxeda: Provide UART clock
The PL011 UART binding requires two clocks to be named in a node.
Add the second clock, which is the bus gate, that just gets enabled.
Since this is a fixed clock anyway, it doesn't make any difference.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions