diff options
| author | Swapnil Jakhade <[email protected]> | 2021-12-23 07:01:29 +0100 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2021-12-27 16:35:09 +0530 |
| commit | fa10517211f72f9480677796b97cbe5a8f3a298f (patch) | |
| tree | db89745fbb7a5229ff7920841527120f7dacbc56 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 8c95e1722689f1b1e63a6206acba2b6200ed7864 (diff) | |
phy: cadence: Sierra: Add PHY PCS common register configurations
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade <[email protected]>
Reviewed-by: Aswath Govindraju <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions