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authorEric Yang <[email protected]>2024-01-16 14:50:55 -0500
committerAlex Deucher <[email protected]>2024-01-29 15:42:52 -0500
commitf2a905b01c6dcca8ce298316eac4e42f766ce766 (patch)
treec0176c0626d597d98ba6855a3e24fc43f3663a15 /tools/perf/scripts/python/export-to-sqlite.py
parent7fc0d111baad0a65f8341b904937ad2b10cc4f1e (diff)
drm/amd/display: fix invalid reg access on DCN35 FPGA
[Why] Unguarded SMU and CLK IP access cause issue on FPGA [How] Guard them for FPGA environment Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Eric Yang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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