diff options
| author | Andre Przywara <[email protected]> | 2019-01-23 00:59:11 +0000 |
|---|---|---|
| committer | Maxime Ripard <[email protected]> | 2019-01-28 09:26:32 +0100 |
| commit | ee0b27a3a4da0b0ed2318aa092f8856896e9450b (patch) | |
| tree | 37dac0f2b5e3a838c099b1efe1d02f75e986f6bb /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 5c59801f7018acba11b12de59017a3fcdcf7421d (diff) | |
clk: sunxi: A31: Fix wrong AHB gate number
According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.
Fix the gate bit definitions in the clock driver.
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions