diff options
| author | Swapnil Jakhade <[email protected]> | 2021-12-23 07:01:33 +0100 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2021-12-27 16:35:09 +0530 |
| commit | da08aab940092a050a4fb2857ed9479d2b0e03c4 (patch) | |
| tree | e3316629dfc80c3b8219ede73d9ffdcf85206a17 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 7a5ad9b4b98cd95f02ec12c895e80bc521fbf9ec (diff) | |
phy: cadence: Sierra: Fix to get correct parent for mux clocks
Fix get_parent() callback to return the correct index of the parent for
PLL_CMNLC1 clock. Add a separate table of register values corresponding
to the parent index for PLL_CMNLC1. Update set_parent() callback
accordingly.
Fixes: 28081b72859f ("phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)")
Signed-off-by: Swapnil Jakhade <[email protected]>
Reviewed-by: Aswath Govindraju <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions