diff options
| author | Lad Prabhakar <[email protected]> | 2021-07-19 15:38:10 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2021-07-26 14:15:23 +0200 |
| commit | d28b1e03dc8d1070538ca3ea3f4e6732109ddf42 (patch) | |
| tree | 6f764e15316cb08aebfae30348766a06c9029f87 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 9800190881cd5bc9e98c69710f04be8ae120cd38 (diff) | |
clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK
to R9A07G044_CLK_P0_DIV2.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions