diff options
| author | Yuantian Tang <[email protected]> | 2019-04-22 17:15:09 +0800 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2019-04-25 11:22:46 -0700 |
| commit | cc61ab9ba2da6587d2b8acfa9d3cf3900456d3b6 (patch) | |
| tree | 0d057a93a236c40d8d8256c062f31b56b15de628 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | f34b2c26fc7d120b26cb181b8d4115675ec58244 (diff) | |
clk: qoriq: add more PLL divider clocks support
More PLL divider clocks are needed by clock consumer IP. So enlarge
the PLL divider array to accommodate more divider clocks.
Signed-off-by: Yuantian Tang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions