diff options
| author | Nicholas Susanto <[email protected]> | 2024-05-14 11:38:39 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2024-06-05 11:06:12 -0400 |
| commit | cc4d6ea0f21e782d8f1c8feeb6bb3133579570dd (patch) | |
| tree | 74be75829db732f8c7b17783a087e43029e34a6d /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | c5afb313e7e623a06cd3428f0a651b2235211430 (diff) | |
drm/amd/display: Fix DML2 logic to set clk state to min
[Why]
When an eDP with high clock states is going into s0i3, stream_count is
0. This causes DML to not update the clks to the lowest state and
blocking us to enter s0i3 since eDP is out of vmin.
[How]
When stream_count is 0, set all the clocks to the lowest state.
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Zaeem Mohamed <[email protected]>
Signed-off-by: Nicholas Susanto <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions