diff options
| author | Peng Fan <[email protected]> | 2019-10-24 01:58:37 +0000 |
|---|---|---|
| committer | Shawn Guo <[email protected]> | 2019-10-25 17:06:47 +0800 |
| commit | c332481f62fa2f29af234bf85846268a5a0b173e (patch) | |
| tree | c0b6c85f16bb4757c76d3ecde9a7c1b1dead7a65 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | e8688fe8df7d01f43586b4bb74b2fa92f56c5ee8 (diff) | |
clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
According Architecture definition guide, SYS_PLL1 is fixed at
800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed
to register the clocks and drop code that could change the rate.
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions