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authorEnric Balletbo i Serra <[email protected]>2020-04-01 22:17:35 +0200
committerMatthias Brugger <[email protected]>2020-05-20 12:47:02 +0200
commitc292b133b58b49d9c5d6a838a8de7831fd97f58d (patch)
tree7e762e87b26efa8aba1e263dd1dc7e5e562cf2b1 /tools/perf/scripts/python/export-to-sqlite.py
parent9c5a0a3a8f0403c911ed4f02d4f4a81fe3c22889 (diff)
clk / soc: mediatek: Bind clock and gpu driver for mt2701
Now that the mmsys driver is the top-level entry point for the multimedia subsystem, we could bind the clock and the gpu driver on those devices that is expected to work, so the drm driver is intantiated by the mmsys driver and display, hopefully, working again. Signed-off-by: Enric Balletbo i Serra <[email protected]> Reviewed-by: Chun-Kuang Hu <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matthias Brugger <[email protected]>
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