diff options
| author | Manasi Navare <[email protected]> | 2021-01-22 15:26:39 -0800 |
|---|---|---|
| committer | Manasi Navare <[email protected]> | 2021-01-25 15:23:17 -0800 |
| commit | aa52b39dc554de07ef7a9eb5c80b487ebbde7e7c (patch) | |
| tree | 68f629c4750ac13208aa9190f20c367e49681ed2 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | dc89bb86facfe82e7f9cc3f8230afad24ec6b538 (diff) | |
drm/i915/display/vrr: Configure and enable VRR in modeset enable
This patch computes the VRR parameters from VRR crtc states
and configures them in VRR registers during CRTC enable in
the modeset enable sequence.
v2:
* Remove initialization to 0 (Jani N)
* Use correct pipe %c (Jani N)
v3:
* Remove debug prints (Ville)
* Use cpu_trans instead of pipe for TRANS_VRR regs (Ville)
Cc: Ville Syrjälä <[email protected]>
Signed-off-by: Manasi Navare <[email protected]>
Reviewed-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions