diff options
| author | Clark Wang <[email protected]> | 2019-01-07 07:47:43 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2019-01-07 15:18:13 +0000 |
| commit | a15dc3d657fa2df08d1adbed926050314b5f4ba7 (patch) | |
| tree | 1e9f4dc40afbfc1c8de635d1b80137c70b60dc6f /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 6a130448498c151d31f1fb6f3003f5cf37b829e0 (diff) | |
spi: lpspi: Fix CLK pin becomes low before one transfer
Remove Reset operation in fsl_lpspi_config(). This RST may cause both CLK
and CS pins go from high to low level under cs-gpio mode.
Add fsl_lpspi_reset() function after one message transfer to clear all
flags in use.
Signed-off-by: Clark Wang <[email protected]>
Reviewed-by: Fugang Duan <[email protected]>
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions