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authorNicholas Kazlauskas <[email protected]>2021-12-09 13:53:36 -0500
committerAlex Deucher <[email protected]>2021-12-28 16:51:24 -0500
commita07f8b9983543d465b50870ab4f845d4d710ed3f (patch)
treedc939d682f0e7eb4f429d2268a58d00b81be6ca0 /tools/perf/scripts/python/export-to-sqlite.py
parentd97e631af2db84c8c9d63abf68d487d0bb559e4c (diff)
drm/amd/display: Send s0i2_rdy in stream_count == 0 optimization
[Why] Otherwise SMU won't mark Display as idle when trying to perform s2idle. [How] Mark the bit in the dcn31 codepath, doesn't apply to older ASIC. It needed to be split from phy refclk off to prevent entering s2idle when PSR was engaged but driver was not ready. Fixes: 118a33151658 ("drm/amd/display: Add DCN3.1 clock manager support") Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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