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authorJoseph Lo <[email protected]>2019-01-04 11:06:53 +0800
committerThierry Reding <[email protected]>2019-02-06 14:30:11 +0100
commit9f5ed5fe60605cadbfeb929565c02fa55e4016ba (patch)
tree24c07b4805a50da5735d207301e832582d9910a2 /tools/perf/scripts/python/export-to-sqlite.py
parentbfeffd155283772bbe78c6a05dec7c0128ee500c (diff)
cpufreq: tegra124: do not handle the CPU rail
The Tegra124 cpufreq driver has no information to handle the Vdd-CPU rail. So this driver shouldn't handle for the CPU clock switching from DFLL to other PLL clocks. It was designed to work on DFLL clock only, which handle the frequency/voltage scaling in the background. This patch removes the driver dependency of the CPU rail, as well as not allow it to be built as a module and remove the removal function. So it can keep working on DFLL clock. Cc: Viresh Kumar <[email protected]> Cc: [email protected] Signed-off-by: Joseph Lo <[email protected]> Acked-by: Jon Hunter <[email protected]> Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
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