diff options
| author | Lubomir Rintel <[email protected]> | 2019-12-18 20:04:54 +0100 |
|---|---|---|
| committer | Olof Johansson <[email protected]> | 2020-01-06 09:19:07 -0800 |
| commit | 8bea5ac0fbc5b2103f8779ddff216122e3c2e1ad (patch) | |
| tree | fa4a74132c0336e62607cc432695b86f06765e78 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 0bd0f30bbf060891f58866a46083a9931f71787c (diff) | |
clk: mmp2: Fix the order of timer mux parents
Determined empirically, no documentation is available.
The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
what is going on, ended up just dividing the rate as of
commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Lubomir Rintel <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions