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author | Swapnil Jakhade <[email protected]> | 2021-12-23 07:01:32 +0100 |
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committer | Vinod Koul <[email protected]> | 2021-12-27 16:35:09 +0530 |
commit | 7a5ad9b4b98cd95f02ec12c895e80bc521fbf9ec (patch) | |
tree | 55d97e785c13ad680ad237c7e414ad558dafa281 /tools/perf/scripts/python/export-to-sqlite.py | |
parent | 36ce416330da5b27d84af519f61e94b73596a297 (diff) |
phy: cadence: Sierra: Update single link PCIe register configuration
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade <[email protected]>
Reviewed-by: Aswath Govindraju <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions