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authorKan Liang <[email protected]>2019-04-10 11:57:09 -0700
committerIngo Molnar <[email protected]>2019-04-16 12:26:19 +0200
commit6daeb8737f8a93c6d3a3ae57e23dd3dbe8b239da (patch)
tree634b6fd7a0cbae516c3d1086f0ca7576143957ae /tools/perf/scripts/python/export-to-sqlite.py
parent6e394376ee89233508fa21d006546357f8efee31 (diff)
perf/x86/intel: Add Tremont core PMU support
Add perf core PMU support for Intel Tremont CPU. The init code is based on Goldmont plus. The generic purpose counter 0 and fixed counter 0 have less skid. Force :ppp events on generic purpose counter 0. Force instruction:ppp on generic purpose counter 0 and fixed counter 0. Updates LLC cache event table and OFFCORE_RESPONSE mask. Adaptive PEBS, which is already enabled on ICL, is also supported on Tremont. No extra code required. Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: Vince Weaver <[email protected]> Cc: [email protected] Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
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